Pyramid micro led pixel point ga n matrix structure and preparation method thereof

Abstract

The application discloses a kind of pyramidal Micro LED pixel point GaN matrix structure and preparation method thereof, including semiconductor layer;GaN pixel point matrix integrated in the front of semiconductor layer, including six HEMT devices are configured to form GaN pixel point circuit by series-parallel connection mode;And Micro LED integrated in the back of semiconductor layer;The GaN pixel point circuit is electrically connected with Micro LED by at least one through hole extending through semiconductor layer, and the GaN pixel point matrix is configured to accurately provide voltage and current for the Micro LED according to external signal.The application effectively reduces product cost by fusing Micro LED and GaN pixel point matrix on the front and back of a wafer, improves the integration of product, and the preparation method of the application uses gold-free process to manufacture HEMT device, only needs to be annealed at low temperature, effectively avoids the damage caused by high-temperature annealing to Micro LED, improves the performance and yield of device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and more specifically, to a pixel GaN matrix structure for a pyramid Micro LED and its fabrication method. Background Technology

[0002] In the field of Micro LED display technology, traditional solutions typically employ mass transfer technology to transfer Micro LED chips from a growth substrate (such as sapphire or silicon) onto a silicon-based driving backplane (such as TFT or CMOS circuits). However, this technology suffers from problems such as low transfer accuracy, insufficient yield, and high cost, making it difficult to meet the demands of high-resolution displays (e.g., above 5000 PPI). Furthermore, heterogeneous integration (such as GaN Micro LEDs and silicon-based driving circuits) also presents challenges such as mismatched coefficients of thermal expansion and low driving efficiency.

[0003] In recent years, monolithic integration technology has become a research hotspot, which involves simultaneously fabricating Micro LED light-emitting units and GaN-based high electron mobility transistor (HEMT) driving circuits on the same GaN substrate, and achieving pixel-level integration through three-dimensional vertical interconnects. Existing technologies mainly include the following approaches:

[0004] ① Homoenomic growth and selective etching: HEMT channel layer (AlGaN / GaN) and Micro LED light-emitting layer are epitaxially grown sequentially on GaN substrate, and the device area is defined by photolithography and etching processes.

[0005] ② Through-hole interconnect technology: Through-holes are fabricated on GaN wafers using deep reactive ion etching (DRIE) or laser drilling, and then filled with metal (Cu / W) to achieve vertical interconnection between Micro LEDs and HEMTs.

[0006] ③ Wafer bonding and back-side alignment technology: First, a Micro LED array is fabricated on the front side of the GaN wafer. Then, the HEMT layer is processed through temporary bonding, back-side thinning and photolithography. Finally, through-hole interconnection is performed.

[0007] ④ Multifunctional epitaxial layer design: The epitaxial structure is optimized through strain engineering to achieve compatibility between the high electron mobility of HEMT and the luminous efficiency of Micro LED on the same wafer.

[0008] All of the above-mentioned processes have certain drawbacks or shortcomings, such as poor material and process compatibility, through-hole reliability issues, miniaturization bottlenecks in drive circuits, and high costs. Summary of the Invention

[0009] To address the aforementioned problems in the prior art, this invention provides a pyramid-shaped Micro LED pixel GaN matrix structure and its fabrication method. By fusing the Micro LED and GaN pixel matrix on both sides of a single wafer, product costs are effectively reduced, product integration is improved, and the GaN pixel matrix can precisely provide the corresponding voltage and current to the Micro LED, thereby achieving display effects with different brightness levels.

[0010] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0011] A pyramid-shaped micro LED pixel GaN matrix structure includes:

[0012] A semiconductor layer with a front and a back side;

[0013] A GaN pixel matrix integrated on the front side of the semiconductor layer, the GaN pixel matrix comprising six HEMT devices configured in series and parallel to form a GaN pixel circuit; and

[0014] A Micro LED integrated on the back side of the semiconductor layer;

[0015] The GaN pixel circuit is electrically connected to the Micro LED through at least one via extending through the semiconductor layer, and the GaN pixel matrix is ​​configured to precisely provide voltage and current to the Micro LED according to external signals to achieve display effects with different brightness.

[0016] Specifically, the six HEMT devices include:

[0017] A first HEMT device and a fourth HEMT device form a switching module;

[0018] A third HEMT device is configured as an enable transistor to control the shutdown of the Micro LED;

[0019] A second HEMT device, connected to the Micro LED, is configured to rapidly release parasitic capacitance to eliminate image retention; and

[0020] A fifth HEMT device and a sixth HEMT device form a current mirror structure, wherein the fifth HEMT device is used as a constant current drive source to control the brightness of the Micro LED.

[0021] Specifically, the first HEMT device, the second HEMT device, and the third HEMT device have a gate width-to-length ratio of 1:50, and the fourth HEMT device, the fifth HEMT device, and the sixth HEMT device have a gate width-to-length ratio of 1:100.

[0022] Specifically, the GaN pixel matrix includes a channel layer with a thickness of 50-55nm, a barrier layer with a thickness of 25-30nm, and a capping layer with a thickness of 80-100nm, which are stacked sequentially on the front side of the semiconductor layer. The channel layer and the barrier layer are configured with an isolation layer consisting of six isolation trenches, five of which are located at adjacent positions of the six HEMT devices, and the remaining isolation trench is located outside the sixth HEMT device.

[0023] Specifically, a gate dielectric layer, multiple passivation layers, and corresponding interconnect metal layers are sequentially disposed on the GaN pixel matrix to form a corresponding HEMT electrode structure.

[0024] Specifically, the Micro LED is a pyramid-shaped GaN Micro LED, comprising an N-type semiconductor layer, a SiO2 passivation layer, an N-type GaN pyramid structure, a pre-strained layer, a multi-quantum-well light-emitting layer, a p-type electron blocking layer, and a p-type semiconductor layer, which are sequentially stacked on the back side of the semiconductor layer. A regular hexagonal groove is formed on the SiO2 passivation layer by etching, and the N-type GaN pyramid structure is formed in the regular hexagonal groove.

[0025] Specifically, the thickness of the N-type semiconductor layer is 1-5 μm, the thickness of the SiO2 passivation layer is 50-100 nm, the height of the N-type GaN pyramid structure is 4-10 μm and the length is 100-120 μm, the thickness of the pre-strained layer is 50-80 nm, the multi-quantum-well light-emitting layer is a periodically overlapping InGaN / GaN layer with an InGaN layer thickness of 2 nm and a GaN layer thickness of 8 nm, the thickness of the p-type electron blocking layer is 10 nm-20 nm, and the thickness of the p-type semiconductor layer is 200 nm-300 nm.

[0026] On the other hand, the present invention also provides a method for fabricating the pixel GaN matrix structure of the pyramid Micro LED, comprising the following steps:

[0027] Prepare the semiconductor layer;

[0028] A GaN HEMT device epitaxial layer is formed on the front side of the semiconductor layer, including a channel layer, a barrier layer and a P-GaN layer;

[0029] A Micro LED structure is formed on the back side of the semiconductor layer;

[0030] A GaN pixel matrix comprising six HEMT devices is fabricated on the epitaxial layer of the GaN HEMT device, including the formation of source, drain and gate electrodes, as well as a multilayer interconnect metal layer;

[0031] Fabricating the Micro LED structure includes forming N-type and P-type contact electrodes;

[0032] At least one via is formed to electrically connect the GaN pixel matrix and the Micro LED structure.

[0033] Specifically, the method for fabricating the pixel GaN matrix structure of the pyramid Micro LED further includes the following steps:

[0034] A P-GaN capping layer is formed by etching a P-GaN layer on the epitaxial layer of a GaN HEMT device.

[0035] ICP etching is performed to form isolation trenches in the barrier layer and channel layer, followed by PECVD deposition of SiN isolation layer;

[0036] Multilayer passivation and interconnect metal layers are deposited through photolithography, etching, and metal deposition processes.

[0037] Furthermore, when fabricating the pyramid-shaped Micro LED structure, the method further includes:

[0038] After depositing a P-GaN layer in the epitaxial layer formation step of GaN HEMT device, a SiN passivation layer with a thickness of 50-100 nm is deposited on its surface.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] This invention effectively reduces product costs and improves product integration by integrating Micro LED and GaN pixel matrix on both sides of a wafer. The GaN pixel circuit is connected to the Micro LED through vias, which can accurately provide the Micro LED with the corresponding voltage and current, thereby achieving display effects with different brightness levels. In addition, HEMT devices made using gold-free processes only need to be annealed at low temperatures, effectively avoiding the damage to Micro LED caused by high-temperature annealing, and improving device performance and yield. Attached Figure Description

[0041] Figure 1 This is a basic circuit diagram of an embodiment of the present invention.

[0042] Figure 2 This is a top view of the pixel matrix structure in an embodiment of the present invention.

[0043] Figure 3This is a schematic diagram of the left cross-section of the pixel matrix structure in an embodiment of the present invention.

[0044] Figure 4 This is a schematic diagram of the left cross-section of the HEMT electrode structure of the pixel matrix in an embodiment of the present invention.

[0045] Figure 5 This is a top view of the surface of the second passivation layer in an embodiment of the present invention.

[0046] Figure 6 This is a top view of the surface of the third passivation layer in an embodiment of the present invention.

[0047] Figure 7 This is a top view of the surface of the fourth passivation layer in an embodiment of the present invention.

[0048] Figure 8 This is a top view of the surface of the fifth passivation layer in an embodiment of the present invention.

[0049] Figure 9 This is a top view of the surface of the sixth passivation layer in an embodiment of the present invention.

[0050] Figure 10 This is a schematic diagram of the left cross-section of the pixel GaN matrix structure of a rectangular Micro LED in an embodiment of the present invention.

[0051] Figure 11 for Figure 10 A cross-sectional schematic diagram of the rectangular Micro LED section.

[0052] Figure 12 This is a schematic diagram of the left cross-section of the pixel GaN matrix structure of the pyramid Micro LED in an embodiment of the present invention.

[0053] Figure 13 for Figure 12 A cross-sectional schematic diagram of the Micro LED section of the central pyramid. Detailed Implementation

[0054] The present invention will be further described below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments. Example

[0055] like Figures 1 to 13As shown, the pyramid-shaped Micro LED pixel GaN matrix structure includes: a semiconductor layer with a front and a back side; a GaN pixel matrix integrated on the front side of the semiconductor layer, the GaN pixel matrix including six HEMT devices, the six HEMT devices being configured in series and parallel to form a GaN pixel circuit; and a Micro LED integrated on the back side of the semiconductor layer; wherein the GaN pixel circuit is electrically connected to the Micro LED through at least one via extending through the semiconductor layer, and the GaN pixel matrix is ​​configured to precisely provide voltage and current to the Micro LED according to external signals to achieve display effects with different brightness levels.

[0056] Figure 1 The basic circuit diagram of the GaN pixel matrix structure is shown, which is divided into two parts: the Micro LED in the upper right corner and the GaN pixel circuit in the lower right corner. The GaN pixel circuit consists of six HEMT devices: HEMT device 1, HEMT device 2, HEMT device 3, HEMT device 4, HEMT device 5, and HEMT device 6. Among them, HEMT device 1 and HEMT device 4 form the switching module of the GaN pixel circuit. When an external current is input, HEMT device 1 and HEMT device 4 can pre-set the Vg voltage to the target value. HEMT device 3 is configured as an enable transistor, which mainly controls the turn-off of the Micro LED. Therefore, under normal circumstances, HEMT device 1 and HEMT device 4 are turned on first to set the target Vg voltage, and then HEMT device 3 is turned on to light up the Micro LED.

[0057] Similarly, the second HEMT device 2 is also connected to the Micro LED and mainly affects the voltage setting before and after the Micro LED is turned on. That is, when the Micro LED is working normally, it is very easy to generate parasitic capacitance. Through the second HEMT device 2, after the Micro LED is turned off, the parasitic current in the parasitic capacitance can be effectively and quickly discharged, eliminating the afterimage of the Micro LED and achieving the purpose of rapid turn-off.

[0058] The fifth HEMT device 5 and the sixth HEMT device 6 form a current mirror structure; the fifth HEMT device 5 is equivalent to a constant current drive source, which can achieve a constant current output by controlling the gate voltage Vg, thereby controlling the brightness of the Micro LED; the sixth HEMT device 6 is a reference tube, which can generate an accurate gate voltage Vg when current is input to the first HEMT device 1.

[0059] Furthermore, the aspect ratio (W / L) of the fifth HEMT device 5 and the sixth HEMT device 6 has a certain proportional relationship. Different ratios generate different currents and different gate voltages Vg. Considering the overall circuit, this invention sets up two types of HEMT devices with different aspect ratios: one is a 1:100 aspect ratio HEMT device, mainly including the fourth HEMT device 4, the fifth HEMT device 5, and the sixth HEMT device 6; the other is a 1:50 aspect ratio HEMT device, mainly including the first HEMT device 1, the second HEMT device 2, and the third HEMT device 3. These two types of HEMT devices constitute the GaN pixel matrix. In the aspect ratio (W / L), L refers to the trench length, and W refers to the trench width. For example, in this invention, W is 1µm, L1 is 50µm, and L2 is 100µm. Figure 2 As shown.

[0060] Figure 2 This shows a top view of six HEMT devices in a GaN pixel matrix. The six HEMT devices are arranged sequentially according to their numbers. Figure 1 The basic circuit diagram layout shown is different; from the top view, it can be seen that the width relationship of the six HEMT devices is that the width of the fourth HEMT device 4, the fifth HEMT device 5 and the sixth HEMT device 6 is twice that of the first HEMT device 1, the second HEMT device 2 and the third HEMT device 3.

[0061] The pixel GaN matrix structure of a pyramid-shaped Micro LED mainly consists of three parts: the semiconductor part, the GaN pixel matrix part, and the Micro LED part. Figure 3 The diagram shows a left-side cross-sectional view of the semiconductor portion and the GaN pixel matrix portion; the Micro LED portion is not shown. The semiconductor portion includes a semiconductor layer 10, a channel layer 11, and a barrier layer 12; the semiconductor layer 10 includes a substrate and a buffer layer (…). Figure 3 (Not clearly marked in the text); the substrate material is Al2O3 / Si based, with a thickness of 500-1000um; the buffer layer material is AlN / AlGaN, with a thickness of 1um-5um.

[0062] The channel layer is made of GaN and has a thickness of approximately 50-55 nm; the barrier layer 12 is made of AlGaN and has a thickness of approximately 25-30 nm; a two-dimensional electron gas layer is formed between the channel layer 11 and the barrier layer 12. Figure 3 (Not shown). The GaN pixel circuitry is located directly above barrier layer 12 and mainly consists of six HEMT devices, interconnecting circuits, and various film layers, such as... Figure 3 As shown.

[0063] Six isolation trenches exist in the barrier layer 12 and the channel layer 11, namely A1, A2, A3, A4, A5, and A6. A1 is located between the first HEMT device 1 and the second HEMT device 2; A2 is located between the second HEMT device 2 and the third HEMT device 3; A3 is located between the third HEMT device 3 and the fourth HEMT device 4; A4 is located between the fourth HEMT device 4 and the fifth HEMT device 5; A5 is located between the fifth HEMT device 5 and the sixth HEMT device 6; and A6 is located to the right of the sixth HEMT device 6. A1, A2, A3, A4, A5, and A6 are 100 μm long and 1-10 μm wide (A6 is wider), with a depth equal to the total thickness of the barrier layer 12 and the channel layer 11. A6 contains a via 25, the width of which is much smaller than the width of A6. SiN is deposited as an isolation layer in the isolation trenches.

[0064] A P-GaN layer with a thickness of approximately 80-100 nm is deposited on the surface of barrier layer 12. The P-GaN layer, excluding the gate region, is etched to form a P-GaN capping layer 15. An isolation layer 13 with a thickness of 80-100 nm is deposited on the surface of the P-GaN capping layer. The source and drain regions are etched to form source and drain trenches, and an ohmic contact metal (Ti / Al / Ti / TiN) is deposited. (20 / 130 / 50 / 50), forming source and drain electrodes, thereby constituting the corresponding HEMT electrode structure, including the source 1-1 of the first HEMT device 1, the source 2-1 of the second HEMT device 2, the source 3-1 of the third HEMT device 3, the source 4-1 of the fourth HEMT device 4, the source 5-1 of the fifth HEMT device 5, and the source 6-1 of the sixth HEMT device 6, as well as the drain 1-3 of the first HEMT device 1, the drain 2-3 of the second HEMT device 2, the drain 3-3 of the third HEMT device 3, the drain 4-3 of the fourth HEMT device 4, the drain 5-3 of the fifth HEMT device 5, and the drain 6-3 of the sixth HEMT device 6. Figure 4 As shown.

[0065] The gate dielectric layer 14 is located directly above the source electrode, drain electrode, and P-GaN capping layer 15. The material is Al2O3 / AlN, and the thickness is approximately 5-10 nm. The first passivation layer 16 is located on the surface of the gate dielectric layer 14, with a thickness of 100-150 nm. The first passivation layer 16 is etched to form a gate trench, and Schottky metal (Ni / Au or Ti / TiN 50 / 50 nm) is deposited to form a T-type gate electrode, such as... Figure 4As shown, there are 6 gate electrodes, namely the gate 1-2 of the first HEMT device, the gate 2-2 of the second HEMT device, the gate 3-2 of the third HEMT device, the gate 4-2 of the fourth HEMT device, the gate 5-2 of the fifth HEMT device, and the gate 6-2 of the sixth HEMT device. The gate electrodes are located directly above the P-GaN capping layer and are separated by the gate dielectric layer 14. The width of the gate electrodes is smaller than the width of the P-GaN capping layer.

[0066] The second passivation layer 17 is located above the T-type gate electrode and has a thickness of 100-150 nm; the first trench 34, the second trench 35, the third trench 36, the fourth trench 37, the fifth trench 38, the sixth trench 39, the seventh trench 40, and the eighth trench 41 are etched to form interconnect metal, as shown below. Figure 5 As shown, the etching depth is equal to the sum of the second passivation layer 17, the first passivation layer 16, and the gate dielectric layer 14, approximately 205-310 nm, and directly contacts the source and drain electrodes, namely the source 1-1 of the first HEMT device 1, the source 2-1 of the second HEMT device 2, the source 3-1 and drain 3-3 of the third HEMT device 3, the source 5-1 and drain 5-3 of the fifth HEMT device 5, and the source 6-1 and drain 6-3 of the sixth HEMT device 6. Interconnect metal (Ti / TiN 120 / 200 nm) is deposited to connect the source 1-1 of the first HEMT device 1 and the drain 6-3 of the sixth HEMT device 6, the source 2-1 of the second HEMT device 2 and the drain 3-3 of the third HEMT device 3, the source 3-1 of the third HEMT device 3 and the drain 5-3 of the fifth HEMT device 5, and the source 5-1 of the fifth HEMT device 5 and the source 6-1 of the sixth HEMT device 6.

[0067] The third passivation layer 18 is located directly above the second passivation layer 17, with a thickness of 100-150 nm; the ninth, tenth, and eleventh grooves 42, 43, and 44, which form the interconnect metal, are etched together. Figure 6 As shown, the etching depth is equal to the sum of the second passivation layer 17 and the third passivation layer 18, approximately 250-350 nm, and directly contacts the source and drain electrodes, which are the drain 2-3 of the second HEMT device 2, and the source 4-1 and drain 4-3 of the fourth HEMT device 4, respectively. Interconnect metal (Ti / TiN 150 / 200 nm) is deposited to connect the drain 2-3 of the second HEMT device 2 and the drain 4-3 of the fourth HEMT device 4. The source 4-1 of the fourth HEMT device 4 forms a contact metal electrode on the surface of the third passivation layer 18.

[0068] The fourth passivation layer 19 is located directly above the third passivation layer 18, with a thickness of 100-150 nm; the twelfth groove 45, thirteenth groove 46, fourteenth groove 47, fifteenth groove 48, sixteenth groove 49, seventeenth groove 62, and eighteenth groove 63 are etched to form the interconnect metal, as shown. Figure 7 As shown, the etching depth is approximately 300-450nm and directly contacts the gate electrode, namely the gate 1-2 of the first HEMT device, the gate 4-2 of the fourth HEMT device, the gate 5-2 of the fifth HEMT device, and the gate 6-2 of the sixth HEMT device. The twelfth groove 45 contacts the contact metal electrode formed on the surface of the third passivation layer 18 with the source 4-1 of the fourth HEMT device 4. The seventeenth groove 62 contacts the interconnect metal formed by the seventh groove 40 and the eighth groove 41. The eighteenth groove 63 contacts the interconnect metal formed by the third groove 36 and the fourth groove 37. An interconnect metal layer (Ti / TiN 150 / 300nm) is deposited to connect the gate 1-2 of the first HEMT device and the gate 4-2 of the fourth HEMT device. The gate 5-2 of the fifth HEMT device, the gate 6-2 of the sixth HEMT device, and the twelfth recess 45 are connected, with their contact points close to the thirteenth recess 46. The seventeenth recess 62 is connected to the interconnect metal formed by the seventh recess 40 and the eighth recess 41, forming a contact metal electrode. The eighteenth recess 63 is connected to the interconnect metal formed by the third recess 36 and the fourth recess 37, forming a contact metal electrode. Figure 7 As shown.

[0069] The fifth passivation layer 20 is located directly above the fourth passivation layer 19, with a thickness of 100-150 nm. Nineteenth groove 51 and twentieth groove 52 are etched to form interconnect metal. Nineteenth groove 51 contacts the interconnect metal contact point of the twelfth groove 45, thirteenth groove 46, and fourteenth groove 47 from the previous step, and is close to the interconnect metal of the fourteenth groove 47. Twentieth groove 52 connects to the contact metal electrode of the eighteenth groove 63 and is close to the fourth groove 37. Figure 8 As shown, interconnect metal (Ti / TiN 150 / 300nm) is deposited, and a first contact metal electrode 50 is formed to the left and a second contact metal electrode 53 is formed to the right, wherein the first contact metal electrode 50 is connected to the nineteenth groove 51, and the second contact metal electrode 53 is connected to the twentieth groove 52.

[0070] The sixth passivation layer 21 is located directly above the fifth passivation layer 20, with a thickness of 100-150 nm. A twenty-first groove 23 is etched to form it, contacting the metal electrode of the seventeenth groove 62, with a depth of approximately 200-300 nm. Interconnect metal (Ti / TiN 50 / 100 nm) is deposited, and a third contact metal electrode 24 is formed on the surface of the sixth passivation layer 21. The third contact metal electrode 24 is connected to the via electrode of the twenty-first groove 23. Figure 9 As shown.

[0071] The pixel GaN matrix structure of the pyramid Micro LED described in this invention is mainly applied to pyramid-shaped Micro LEDs, but can also be applied to traditional rectangular Micro LEDs, thus forming the following two schemes for Micro LED configuration:

[0072] Option 1: As Figure 10 and Figure 11 As shown, this pixel GaN matrix structure is applied to a traditional rectangular Micro LED. From its cross-sectional diagram, it can be seen that a SiN passivation layer 26 is deposited outside the substrate (not explicitly shown in the figure) in semiconductor layer 10 to prevent substrate conductivity from damaging the rectangular Micro LED. A P-type semiconductor layer 27, made of P-GaN, with a thickness of approximately 1-5 μm, is located directly above the SiN passivation layer 26. A quantum well layer 28, with a thickness of approximately 150-160 nm, is located directly above the P-type semiconductor layer 27. An N-type semiconductor layer 29, made of N-GaN, with a thickness of approximately 1-5 μm, is located directly above the quantum well layer 28. A current spreading layer 31, with a thickness of approximately 150-200 nm, is located directly above the N-type semiconductor layer 29. The Micro LED material on the left and right sides is etched, as shown... Figure 11 As shown, the left side is etched down to the P-type semiconductor layer 27, and the right side is etched down to the SiN passivation layer. An isolation layer 32 is deposited, made of SiN with a thickness of 300-350 nm. The left and right isolation layers 32 are etched to form vias, and metal (Ti / TiN or Al / Cu) is deposited to form N-type contact electrodes 30 and P-type contact electrodes 33. The N-type contact electrodes 30 interconnect the current spreading layer 31 and the vias 25. The P-type contact electrodes 33 are connected to the P-type semiconductor layer 27.

[0073] Option 2: Figure 12 and Figure 13As shown, this pixel GaN matrix structure is applied to a pyramid Micro LED. From its cross-sectional diagram, it can be seen that an N-type semiconductor layer 54, made of n-GaN and with a thickness of 1-5 μm, is deposited outside the substrate (not explicitly shown) in semiconductor layer 10. A SiO2 passivation layer 55, made of SiO2 and with a thickness of 50-100 nm, is located directly above the N-type semiconductor layer 54. A regular hexagonal mask with periodic holes and a side length of 18-20 μm is used to etch the SiO2 passivation layer 55, forming a regular hexagonal groove. An N-type GaN pyramid structure 56 (doped with Si) is deposited in the regular hexagonal groove, with a height of 4-10 μm and a length of 100-120 μm. An InGaN pre-strained layer 57, with a thickness of 50-80 nm and an In composition of 10%-15%, is located on the N-type GaN pyramid structure 56. An InGaN / GaN multi-quantum-well light-emitting layer 58 is grown on the InGaN pre-strained layer 57. Different In and Ga compositions correspond to different colors: In 0.12 Ga 0.88 N / GaN corresponds to blue light, In 0.25 Ga 0.75 N / GaN corresponds to green, In 0.35 Ga 0.65 N corresponds to red; the InGaN / GaN multi-quantum-well light-emitting layer 58 is a periodically overlapping InGaN / GaN layer, where the InGaN thickness is 2nm and the GaN thickness is 8nm. The AlGaN p-type electron blocking layer 59 is located on the InGaN / GaN multi-quantum-well light-emitting layer 58, with an Al composition of 0.25 and a thickness of approximately 10nm-20nm. The p-type semiconductor layer 60 is located on the AlGaN p-type electron blocking layer 59, and the material is P-GaN (doped with Mg), with a thickness of 200nm-300nm. The SiO2 passivation layer 55 is etched to form an etched groove, which contacts the N-type semiconductor layer 54. Metal (Ti / TiN 50 / 100 or Al, Cu 150nm) is deposited to form an N-type metal contact electrode 61; the N-type metal contact electrode 61 is connected to the through-hole 25.

[0074] The pixel GaN matrix structure of the pyramid Micro LED of the present invention is as follows: Figure 12 As shown, this pixel GaN matrix structure can also be applied to the construction of traditional rectangular Micro LEDs. Figure 10 The structure shown is different from the other two in that the semiconductor part of the Micro LED is the same as the GaN pixel matrix part. The following describes the fabrication method in detail based on the above structure.

[0075] Step 1: PECVD growth of SiN passivation layer;

[0076] A SiN passivation layer is deposited on one side of a substrate (sapphire or Si-based) in semiconductor layer 10 using plasma-enhanced chemical vapor deposition (PECVD).

[0077] Step 2: MOCVD deposition of GaN HEMT device epitaxial layer;

[0078] GaN epitaxial layers were deposited using a chemical vapor deposition (MOCVD) apparatus, consisting of a semiconductor layer 10, a channel layer 11, a barrier layer 12, and a P-GaN layer from bottom to top. The semiconductor layer 10 includes a substrate and a buffer layer.

[0079] Step 3: MOCVD deposition of Micro LED structure;

[0080] Option 1 (for conventional rectangular Micro LEDs, the same below): On the other side of the GaN epitaxial layer, i.e., on the SiN passivation layer, a P-type semiconductor layer 27, a quantum well layer 28, an N-type semiconductor layer 29 and a current spreading layer 31 are deposited sequentially from bottom to top using a chemical vapor deposition (MOCVD) apparatus; an isolation layer 32 is deposited on the surface of the current spreading layer 31 using a plasma-enhanced chemical vapor deposition (PECVD) apparatus.

[0081] Option 2 (for pyramid Micro LED, the same below): An N-type semiconductor layer 54 of N-GaN is deposited on the SiN passivation layer using a chemical vapor deposition (MOCVD) apparatus; a SiO2 passivation layer 55 is then deposited on the N-type semiconductor layer 54 using a plasma-enhanced chemical vapor deposition (PECVD) apparatus; then, based on a regular hexagonal mask with periodic holes, the SiO2 passivation layer 55 is etched using an inductively coupled plasma (RIE-ICP) apparatus to form a regular hexagonal groove; a pyramid-shaped N-type GaN pyramid structure 56 is deposited in the regular hexagonal groove using a chemical vapor deposition (MOCVD) apparatus, and an InGaN pre-strained layer 57, an InGaN / GaN multiple quantum well light-emitting layer 58, an AlGaN p-type electron blocking layer 59, and a p-type semiconductor layer 60 of p-GaN are deposited sequentially from bottom to top on its surface.

[0082] When using scheme 2, due to the etching in the intermediate steps, some adjustments need to be made to the preceding steps: First, the order of the third and second steps is interchanged to prevent damage to the P-GaN layer in the GaN epitaxial layer when etching the SiO2 passivation layer 55; Second, in the second step, after depositing the P-GaN layer, a plasma-enhanced chemical vapor deposition (PECVD) device is added to deposit a SiN passivation layer with a thickness of 50-100nm on its surface to protect the P-GaN layer from being etched, while keeping the order of steps unchanged.

[0083] Step 4: ICP etching of the P-GaN layer to form the P-GaN capping layer 15;

[0084] After defining the gate photolithography region using negative resist, the P-GaN layer is etched using inductively coupled plasma (ICP) to form a P-GaN capping layer 15 in the gate region.

[0085] Step 5: Device isolation;

[0086] After defining the photolithographic region of the isolation trench using negative resist, the barrier layer 12 and the channel layer 11 are etched using inductively coupled plasma (ICP) to form isolation channels A1, A2, A3, A4, A5 and A6. The width of isolation channel A6 is larger than the other isolation channels. SiN isolation layers are deposited in isolation channels A1, A2, A3, A4, A5 and A6 using plasma-enhanced chemical vapor deposition (PECVD) to form the device isolation effect.

[0087] Step 6: Deposit the source and drain electrodes;

[0088] After defining the source, drain, and P-GaN capping layer 15 photolithographic regions using positive photoresist, the SiN isolation layer on the surface of the source, drain, and P-GaN capping layer 15 is etched using inductively coupled plasma (ICP). Then, the source and drain photolithographic regions are defined again using positive photoresist. After development, the source and drain metals (Ti / Al / Ni / AuTi / Al / Ni / TiN) are deposited using a metal evaporation device or a magnetron sputtering device. (20 / 130 / 50 / 50), after metal stripping, source and drain electrodes are formed, constituting the corresponding HEMT electrode structure, including the source 1-1 of the first HEMT device 1, the source 2-1 of the second HEMT device 2, the source 3-1 of the third HEMT device 3, the source 4-1 of the fourth HEMT device 4, the source 5-1 of the fifth HEMT device 5 and the source 6-1 of the sixth HEMT device 6, as well as the drain 1-3 of the first HEMT device 1, the drain 2-3 of the second HEMT device 2, the drain 3-3 of the third HEMT device 3, the drain 4-3 of the fourth HEMT device 4, the drain 5-3 of the fifth HEMT device 5 and the drain 6-3 of the sixth HEMT device 6.

[0089] Step 7: Deposit the gate dielectric layer 14 and the first passivation layer 16;

[0090] After depositing a gate dielectric layer 14 (Al2O3 / AlN) on the source, drain and P-GaN capping layer 15 using atomic layer deposition (ALD), a first SiN passivation layer 16 is deposited on its surface using plasma enhanced chemical vapor deposition (PECVD).

[0091] Step 8: Deposit the gate electrode;

[0092] The gate electrode photolithography region is defined using negative resist. This region is smaller than the P-GaN capping layer 15 region and is located directly above it. The first passivation layer 16 (SiN) is etched using inductively coupled plasma (ICP) to form the gate trench. Then, the gate metal (Ni / Au Ti / TiN 50 / 50nm) is deposited using a metal deposition equipment or a magnetron sputtering equipment. After the metal is removed, a T-shaped gate electrode is formed, including the gate 1-2 of the first HEMT device, the gate 2-2 of the second HEMT device, the gate 3-2 of the third HEMT device, the gate 4-2 of the fourth HEMT device, the gate 5-2 of the fifth HEMT device, and the gate 6-2 of the sixth HEMT device.

[0093] Step 9: Deposit the second passivation layer 17;

[0094] A second SiN passivation layer 17 was deposited on the surface of the first SiN passivation layer 16 using a plasma-enhanced chemical vapor deposition (PECVD) apparatus.

[0095] Step 10: First interconnect metal layer;

[0096] Photolithographic regions of the first interconnect metal layer are defined on the surface of the second passivation layer 17 of SiN using positive photoresist. These regions include the source 1-1 of the first HEMT device 1, the source 2-1 of the second HEMT device 2, the source 3-1 and drain 3-3 of the third HEMT device 3, the source 5-1 and drain 5-3 of the fifth HEMT device 5, and the source 6-1 and drain 6-3 of the sixth HEMT device 6. After development, these defined regions are etched using inductively coupled plasma (ICP) to form the first groove 34, the second groove 35, the third groove 36, the fourth groove 37, the fifth groove 38, the sixth groove 39, the seventh groove 40, and the eighth groove 41 of the first interconnect metal layer. Then, interconnect metal (Ni / Au) is deposited using a metal deposition apparatus or a magnetron sputtering apparatus. After metal stripping (Ti / TiN 120 / 200nm), interconnect metals are formed between the source 1-1 of the first HEMT device 1 and the drain 6-3 of the sixth HEMT device 6, between the source 2-1 of the second HEMT device 2 and the drain 3-3 of the third HEMT device 3, between the source 3-1 of the third HEMT device 3 and the drain 5-3 of the fifth HEMT device 5, and between the source 5-1 of the fifth HEMT device 5 and the source 6-1 of the sixth HEMT device 6.

[0097] Step 11: Deposit the third passivation layer 18;

[0098] A third SiN passivation layer 18 was deposited on the surface of the second SiN passivation layer 17 using a plasma-enhanced chemical vapor deposition (PECVD) apparatus.

[0099] Step 12: Second interconnect metal layer;

[0100] Photolithographic regions of the second interconnect metal layer are defined on the surface of the third passivation layer 18 using positive photoresist. These regions include the drain 2-3 of the second HEMT device 2, and the source 4-1 and drain 4-3 of the fourth HEMT device 4. After development, these defined regions are etched using inductively coupled plasma (ICP) to form the ninth groove 42, the tenth groove 43, and the eleventh groove 44 of the second interconnect metal layer. Then, interconnect metal (Ni / Au Ti / TiN 150 / 200nm) is deposited using a metal deposition apparatus or a magnetron sputtering apparatus. After metal stripping, interconnect metal is formed between the drain 2-3 of the second HEMT device 2 and the drain 4-3 of the fourth HEMT device 4. The source 4-1 of the fourth HEMT device 4 forms interconnect metal in the eleventh groove 44 on the surface of the third passivation layer 18.

[0101] Step 13: Deposit the fourth passivation layer 19;

[0102] A fourth passivation layer 19 of SiN was deposited on the surface of the third passivation layer 18 of SiN using a plasma-enhanced chemical vapor deposition (PECVD) apparatus.

[0103] Step 14: Third Interconnect Metal Layer

[0104] Photolithographic regions of the third interconnect metal layer are defined on the surface of the fourth passivation layer 19 of SiN using positive resist. These regions include the gates 1-2 of the first HEMT device, the gates 4-2 of the fourth HEMT device, the gates 5-2 of the fifth HEMT device, and the gates 6-2 of the sixth HEMT device. After development, these defined regions are etched using inductively coupled plasma (ICP) to form the second interconnect metal layer recesses: the thirteenth recess 46, the fourteenth recess 47, the fifteenth recess 48, and the sixteenth recess 49. Photolithographic regions of the third interconnect metal layer are defined again on the surface of the fourth passivation layer 19 of SiN using positive resist, and the twelfth recess 45 is etched. Then, photolithographic regions of the third interconnect metal layer are defined again on the surface of the fourth passivation layer 19 of SiN using positive resist, and the seventeenth recess 62 and the eighteenth recess 63 are etched. Interconnect metal (Ni / AuTi / TiN 150 / 300nm) is deposited using a metal deposition apparatus or a magnetron sputtering apparatus.

[0105] After metal stripping, interconnect metal is formed between the gate 1-2 of the first HEMT device and the gate 4-2 of the fourth HEMT device, between the gate 5-2 of the fifth HEMT device, between the gate 6-2 of the sixth HEMT device and the twelfth groove 45, and between the seventeenth groove 62 and the interconnect metal of the seventh groove 40 and the eighth groove 41.

[0106] Step 15: Deposit the fifth passivation layer 20;

[0107] A fifth passivation layer 20 of SiN was deposited on the surface of the fourth passivation layer 19 using a plasma-enhanced chemical vapor deposition (PECVD) apparatus.

[0108] Step 16: Fourth Interconnect Metal Layer;

[0109] Photolithographic regions of the fourth interconnect metal layer are defined on the surface of the fifth passivation layer 20 of SiN using positive resist. The defined regions are etched using inductively coupled plasma (ICP) to form the nineteenth trench 51 and the twentieth trench 52. Interconnect metal (Ni / Au Ti / TiN 150 / 300nm) is deposited using a metal deposition apparatus or a magnetron sputtering apparatus. After metal stripping, interconnect metal is formed between the nineteenth trench 51 and the gate 5-2 of the fifth HEMT device, the gate 6-2 of the sixth HEMT device and the interconnect metal of the twelfth trench 45, and between the twentieth trench 52 and the contact metal electrodes of the eighteenth trench 63.

[0110] Step 17: Deposit the sixth passivation layer 21;

[0111] A sixth passivation layer 21 of SiN was deposited on the surface of the fifth passivation layer 20 of SiN using a plasma-enhanced chemical vapor deposition (PECVD) apparatus.

[0112] Step 18: Deposit through-hole metal;

[0113] The photolithographic region of via 25 is defined on the surface of the sixth passivation layer 21 of SiN using positive resist (thick resist). The entire GaN HEMT device is etched using inductively coupled plasma (ICP) or wet etching equipment. The via 25 passes through the isolation groove A6 region and extends to the lower surface of the semiconductor layer 10. The via metal (Al / Cu) is deposited using magnetron sputtering equipment, and the third contact metal electrode 24 is formed on the surface of the sixth passivation layer 21.

[0114] Step 19: Fifth Interconnect Metal Layer;

[0115] Photolithographic regions of the fifth interconnect metal layer are defined on the surface of the sixth passivation layer 21 of SiN using positive resist. Inductively coupled plasma (ICP) is used to etch the defined regions to form the twenty-first groove 23, which contacts the metal electrode of the seventeenth groove 62. Then, interconnect metal (Ni / Au Ti / TiN 150 / 300nm) is deposited using a metal deposition apparatus or a magnetron sputtering apparatus. After metal stripping, interconnect metal is formed between the third contact metal electrode 24 and the via electrode of the twenty-first groove 23.

[0116] Step 20: Micro LED area processing;

[0117] Option 1: Use positive adhesive to define the leftmost and rightmost photolithographic regions of the Micro LED structure, and use inductively coupled plasma (ICP) to etch these two regions to form grooves; use plasma-enhanced chemical vapor deposition (PECVD) to deposit a SiN isolation layer, which, together with the SiN isolation layer 32 in step 3, is collectively referred to as SiN isolation layer 32; use positive adhesive to define the N-type and P-type etched regions in the Micro LED structure, and etch to form N-type grooves and P-type grooves, with the N-type grooves contacting the N-type semiconductor material and the P-type grooves contacting the P-type semiconductor material; use metal deposition equipment or magnetron sputtering equipment to deposit interconnect metal (Ti / TiN or Al / Cu) to form P-type contact electrodes 33 and N-type contact metal.

[0118] Option 2: Use positive adhesive to define the SiO2 passivation layer 55 of the Micro LED near the surface of the via 25 to define the photolithography area. Use inductively coupled plasma (ICP) to etch this area to form an N-type groove, which contacts the N-type semiconductor layer 54. Use a metal deposition equipment or magnetron sputtering equipment to deposit interconnect metal (Ti / TiN or Al / Cu) to form an N-type contact metal 61.

[0119] Step 21: Etching the through-holes;

[0120] Option 1: Use positive adhesive (thick adhesive) to define the photolithographic area on the left side of the N-type contact electrode, and use inductively coupled plasma (ICP) or wet etching equipment to etch the entire Micro LED to a depth of semiconductor layer 10 and contact the via 25 in the GaNHEMT device; use magnetron sputtering equipment to deposit interconnect metal (Al / Cu); after metal stripping, form the metal electrode of via 25; the metal electrode of via 25 is connected to the N-type contact electrode 30 to form an interconnect metal electrode.

[0121] Option 2: Use positive adhesive (thick adhesive) to define the photolithographic area on the right side of the N-type contact metal 61, and use inductively coupled plasma (ICP) or wet etching equipment to etch the entire GaN Micro LED pixel matrix structure, etching through the entire device structure; use magnetron sputtering equipment to deposit interconnect metal (Al / Cu); after metal stripping, form the metal electrode of the through hole 25; the metal electrode of the through hole 25 is connected to the N-type contact metal 61 to form the interconnect metal electrode.

[0122] The above embodiments are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any changes made based on the design principles of the present invention, or any non-creative modifications made thereon, shall fall within the scope of protection of the present invention.

Claims

1. A pixel point GaN matrix structure of a pyramid Micro LED, characterized in that, The application relates to a semiconductor structure, comprising: a semiconductor layer having a front surface and a back surface; a GaN pixel point matrix integrated on the front surface of the semiconductor layer, the GaN pixel point matrix comprising six HEMT devices, and the six HEMT devices being configured in a series-parallel mode to form a GaN pixel point circuit; and a Micro LED integrated on the back surface of the semiconductor layer; wherein the GaN pixel point circuit is electrically connected with the Micro LED through at least one via hole extending through the semiconductor layer, and the GaN pixel point matrix is configured to accurately provide voltage and current for the Micro LED according to an external signal to realize a display effect with different brightness; the six HEMT devices comprising: a first HEMT device and a fourth HEMT device forming a switch module; a third HEMT device configured as an enable tube to control the turn-off of the Micro LED; a second HEMT device connected with the Micro LED and configured to quickly release a parasitic capacitor to eliminate residual images; and a fifth HEMT device and a sixth HEMT device forming a current mirror structure, wherein the fifth HEMT device is used as a constant current driving source to control the brightness of the Micro LED; the source electrode of the first HEMT device is connected with the drain electrode of the sixth HEMT device, the source electrode of the second HEMT device is connected with the drain electrode of the third HEMT device and the Micro LED, the source electrode of the third HEMT device is connected with the drain electrode of the fifth HEMT device, the source electrode of the fifth HEMT device is connected with the source electrode of the sixth HEMT device and grounded, the drain electrode of the second HEMT device is connected with the drain electrode of the fourth HEMT device, the gate electrode of the first HEMT device is connected with the gate electrode of the fourth HEMT device, and the gate electrode of the fifth HEMT device is connected with the gate electrode of the sixth HEMT device and the source electrode of the fourth HEMT device; the first HEMT device, the second HEMT device and the third HEMT device have a gate width-length ratio of 1:50, and the fourth HEMT device, the fifth HEMT device and the sixth HEMT device have a gate width-length ratio of 1:

100.

2. The pyramid Micro LED pixel point GaN matrix structure according to claim 1, characterized in that, The GaN pixel point matrix comprises, in sequence from the front surface of the semiconductor layer, a channel layer with a thickness of 50-55 nm, a barrier layer with a thickness of 25-30 nm and a cap layer with a thickness of 80-100 nm, and the channel layer and the barrier layer are configured with an isolation layer formed by six isolation grooves, wherein five of the six isolation grooves are located at the adjacent positions of the six HEMT devices, and the remaining one isolation groove is located outside the sixth HEMT device.

3. The pyramid Micro LED pixel point GaN matrix structure according to claim 2, characterized in that, A gate dielectric layer, a multi-layer passivation layer and a corresponding interconnection metal layer are further configured in sequence on the GaN pixel point matrix to form a corresponding HEMT electrode structure.

4. The pyramid Micro LED pixel point GaN matrix structure of claim 3, characterized in that, The Micro LED is a pyramid-shaped GaN Micro LED, comprising an N-type semiconductor layer, a SiO2 passivation layer, an N-type GaN pyramid structure, a pre-strain layer, a multi-quantum well light-emitting layer, a p-type electron blocking layer and a p-type semiconductor layer which are sequentially stacked on the back of a semiconductor layer, wherein a regular hexagonal groove is formed on the SiO2 passivation layer by etching, and the N-type GaN pyramid structure is formed in the regular hexagonal groove.

5. The pyramid Micro LED pixel point GaN matrix structure according to claim 4, characterized in that, The thickness of the N-type semiconductor layer is 1-5 um, the thickness of the SiO2 passivation layer is 50-100 nm, the height of the N-type GaN pyramid structure is 4-10 um and the length is 100-120 um, the thickness of the pre-strain layer is 50-80 nm, the multi-quantum well light-emitting layer is a periodically overlapped InGaN / GaN layer, the thickness of the InGaN layer is 2 nm, the thickness of the GaN layer is 8 nm, the thickness of the p-type electron blocking layer is 10-20 nm, and the thickness of the p-type semiconductor layer is 200-300 nm.

6. The preparation method of the pyramid Micro LED pixel point GaN matrix structure according to any one of claims 1-5, characterized in that, The method comprises the following steps: preparing a semiconductor layer; forming a GaN HEMT device epitaxial layer on the front surface of the semiconductor layer, comprising a channel layer, a barrier layer and a P-GaN layer; forming a Micro LED structure on the back surface of the semiconductor layer; manufacturing a GaN pixel point matrix comprising six HEMT devices on the GaN HEMT device epitaxial layer, including forming source, drain and gate electrodes, and a multi-layer interconnection metal layer; manufacturing the Micro LED structure, including forming N-type and P-type contact electrodes; forming at least one via to electrically connect the GaN pixel point matrix and the Micro LED structure.

7. The preparation method of the pyramid Micro LED pixel point GaN matrix structure according to claim 6, characterized in that, The method further comprises the following steps: etching the P-GaN layer on the GaN HEMT device epitaxial layer to form a P-GaN cap layer; performing ICP etching to form an isolation trench in the barrier layer and the channel layer, and then depositing a SiN isolation layer by PECVD; depositing a multi-layer passivation layer and interconnection metal layer by photolithography, etching and metal deposition processes.

8. The preparation method of the pyramid Micro LED pixel point GaN matrix structure according to claim 6, characterized in that, When preparing a pyramid Micro LED structure, the method further comprises: after depositing the P-GaN layer in the step of forming the GaN HEMT device epitaxial layer, depositing a SiN passivation layer with a thickness of 50-100 nm on the surface thereof.

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