Apparatus for moving qubits for semiconductor spin qubit quantum computer

Abstract

A shuttle element for a quantum computer includes a plurality of gate electrodes arranged on a semiconductor heterostructure. The plurality of gate electrodes includes a shield gate for defining at least one path in the semiconductor heterostructure. The plurality of gate electrodes includes a transfer gate disposed at the at least one path. The transfer gate includes a subset of electrodes electrically disconnected from each other. The transfer gates of any one of the electrode subsets are electrically connected to each other. The finger gate is configured to be provided with at least one voltage V to move at least one qubit along at least one path.

Description

Technical Field

[0001] The present disclosure relates to the field of operation of quantum processors. Background Art

[0002] Quantum processor architectures must take scalability into account in order to achieve a sufficiently high number of logical qubits to implement quantum computer chips, which enable quantum computing in the NISQ (noisy intermediate-scale quantum) era or universal quantum computing. In the case of quantum computing based on spin qubits, the qubits are arranged in a two-dimensional plane. A disadvantage of this two-dimensional architecture is the so-called "fan-out problem," which refers to the space required for routing the control circuits of the quantum processor between the quantum processor and the traditional control circuits. These space requirements scale faster with the number of qubits than the size of the spin qubit-based quantum processor architectures proposed so far can scale.

[0003] Recently, a spin qubit architecture based on direct electron shuttling in Si / SiGe semiconductor heterostructures has been proposed. This architecture includes shuttle paths along which qubits can theoretically be transported over arbitrary distances, for example, up to approximately 50 μm. These shuttle paths allow components of a quantum processor (such as the loading, readout, and manipulation regions) to be spaced apart from one another, resulting in lower crosstalk. The provision of shuttle paths also enables operating modes that require relatively low operating frequencies and reduce local magnetic field gradients.

[0004] In these shuttle-based architectures, high-fidelity shuttling is crucial for reliable computation. This high fidelity can be compromised by, for example, charge defects or valley splitting on the shuttle path. Valley splitting can lead to leakage of the computational basis (e.g., two spin states) used for computation.

[0005] There is a need to identify points in a quantum processor (e.g., a shuttle path or other component of the quantum processor) at which the reliability of qubit processing decreases, which ultimately affects the performance of the quantum processor. Summary of the Invention

[0006] A shuttling element for a quantum computer includes a plurality of gate electrodes disposed on a semiconductor heterostructure, wherein the plurality of gate electrodes include a shield gate configured to define at least one path in the semiconductor heterostructure. The plurality of gate electrodes include a transfer gate disposed along the at least one path. The transfer gate includes a subset of electrodes electrically disconnected from one another. The transfer gates of any of the electrode subsets are electrically connected to one another. The finger gates are configured to be supplied with at least one voltage V to move at least one qubit along the at least one path.

[0007] Subsets of the plurality of electrode subsets may have dielectric or insulating layers disposed between each other.

[0008] The transfer gate may be disposed on a planarized dielectric or insulating layer.

[0009] The plurality of gate electrodes may be arranged on at least one surface of the semiconductor heterostructure.

[0010] The handling region may further include a top gate disposed above the transfer gate.

[0011] A system includes a shuttle element according to the present disclosure and a magnet providing an external magnetic field B0.

[0012] A method for moving at least one quantum bit along at least one path in a semiconductor heterostructure is disclosed, wherein the semiconductor heterostructure includes a plurality of gate electrodes disposed thereon. The method comprises providing an external magnetic field B0. The method further comprises applying at least one voltage to the plurality of gate electrodes to generate at least one traveling potential well disposed along the at least one path for moving the at least one quantum bit.

[0013] Generating the at least one traveling potential well may include applying at least one AC voltage to a transfer gate among the plurality of gate electrodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A schematic top view of a quantum processor is shown.

[0015] Figure 2 Show Figure 2 Schematic top view of the unit cell of the quantum processor shown in FIG.

[0016] Figure 3A Shown is a top view of one aspect of the shuttle channel.

[0017] Figure 3B A longitudinal cross-section showing another aspect of the shuttle channel.

[0018] Figure 3C A grayscale-coded panorama of the valley splitting of the shuttle channel is shown, along with examples of possible trajectories of qubits along the shuttle channel, which bypass a series of sites of reduced fidelity as the valley splitting decreases.

[0019] Figure 3D-3F Results are shown that simulate the effect of disorder in a semiconductor heterostructure on trajectory splitting of one or more qubits moving along at least one path of a shuttling element.

[0020] Figure 4 A pair of path-defining gates are shown arranged at the path of the qubit.

[0021] Figure 5 A longitudinal cross-section showing another aspect of the shuttle channel. DETAILED DESCRIPTION

[0022] The present disclosure relates to a method of operating a quantum processor and a method of manufacturing a quantum processor.

[0023] Quantum processors can operate based on spin qubits. Spin qubits are two-level quantum systems with a spin degree of freedom. An example of a spin qubit is a two-level quantum system of electron spins confined in a quantum dot, and another example is a hole spin qubit. Furthermore, a group of electrons (e.g., two or three electrons) can be used to realize a spin qubit, such as the S-T0 singlet-triplet system of two electrons in a double quantum dot.

[0024] The method of the present disclosure is applicable to any type of electrically controllable spin qubit implemented in the semiconductor heterostructure 12. Using an electron-based spin qubit involves placing the electron spin in a known state. To this end, the electron state is initialized. In one aspect, the selected qubit is associated with the same electron throughout the execution of the quantum algorithm. On the other hand, a qubit implemented by a first electron can be initialized and subsequently operated on, and the qubit can be implemented by a second electron. On the other hand, without affecting the execution of the quantum algorithm, there is a situation where it is impossible to distinguish whether the qubit is implemented by the first electron or the second electron. Similarly, the method of the present disclosure can be applied to any type of hole spin qubit.

[0025] The use of semiconductor materials to form the semiconductor heterostructure 12 for implementing quantum processors is advantageous in manufacturing because the materials are easy to process and are inexpensive (e.g., in the case of silicon). The use of silicon in computing hardware has established technology. A two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG) can be confined within the semiconductor heterostructure 12 formed of semiconductor materials in quantum wells 69 (see below and Figure 5 ). Quantum well 69 is only Figure 5 However, the quantum well 69 will also be present in Figure 3A 、 Figure 3BIn the semiconductor heterostructure 12 shown in . 2DEG or 2DHG can be further confined based on an electric potential. The electric potential can be a static electric potential or a non-static electric potential. The electric potential can form at least one quantum dot, wherein at least one electron or hole in the 2DEG or 2DHG is trappable or confined. The spin of the at least one trapped (confined) electron or hole can be used to realize a spin qubit. Moving the electric potential causes moving at least one quantum dot. The movement of at least one quantum dot enables the movement of at least one trapped (confined) electron / hole and the qubit associated with the at least one trapped (confined) electron / hole. Changing the strength of the electric potential changes the degree of confinement of the at least one trapped (confined) electron or hole.

[0026] The quantum processor may include a plurality of unit cells. A unit cell in the plurality of unit cells includes a component that performs at least one action or operation on one or more qubits located in the unit cell. The at least one action on the one or more qubits includes: loading one or more qubits into the unit cell; unloading one or more qubits from the unit cell; moving (shuttling) one or more qubits into or out of the unit cell (i.e., to another unit cell of the quantum processor); manipulating the quantum state of one or more qubits; and reading out the quantum state of one or more qubits. Manipulating one or more qubits may include: manipulating a single qubit or manipulating two qubits. Manipulating a single qubit includes: rotating the spin of a single qubit, for example, to drive a transition between multiple spin states. The multiple spin states may include, for example, an up spin state and a down spin state. Manipulating two qubits includes implementing a CPHASE gate, a CNOT gate, and / or a SWAP gate.

[0027] In one aspect, several actions performed by components of a unit cell on one or more qubits can be performed one after another as a sequence of actions. For example, two actions can be performed one after another. In another aspect, several actions performed by components of a unit cell on one or more qubits can be performed in parallel. For example, two actions can be performed in parallel.

[0028] In one aspect, several actions on one or more qubits may be performed within a single unit cell of a plurality of unit cells or across several unit cells of the plurality of unit cells.

[0029] In one aspect, several actions may be performed as part of determining gate fidelity (see below for more details). For example, determining gate fidelity may include performing a sequence of actions on one or more qubits.

[0030] In another aspect, several actions may be performed as part of executing an algorithm. For example, executing an algorithm may include performing a sequence of actions on one or more qubits.

[0031] Components are arranged within the unit cells. Some of the components are connected to one another. The components and their connections together constitute the layout or structure of the unit cell. Unit cells within a plurality of unit cells may have substantially the same structure, wherein the same components are arranged and connected to one another in substantially the same manner. Other units within the plurality of unit cells may have different structures, wherein the components and / or connections of the components are different.

[0032] Aspects of the quantum processor are disclosed in International Patent Application No. WO 2021 / 052541 A1, the entire contents of which are incorporated herein by reference. Figure 1 and Figure 2 As shown, the quantum processor 10 includes a semiconductor heterostructure 12. The semiconductor heterostructure 12 includes several layers of different material compositions. The semiconductor heterostructure 12 can be a Si / SiGe or GaAs / AlGaAs heterostructure, however, it is possible to use other materials in which a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG) can be formed, such as Si-MOS or Ge / SiGe. The semiconductor heterostructure can be undoped and / or strained. The semiconductor heterostructure 12 can serve as a substrate for the quantum processor 10. The semiconductor heterostructure 12 can include a 2DEG. The 2DEG or 2DHG can be arranged or located in a quantum well 69 (see Figure 5 ). One or more qubits may be arranged in quantum well 69. One or more qubits may be arranged in at least one quantum dot formed in quantum well 69. One or more qubits may be generated from a 2DEG.

[0033] In one aspect, the semiconductor heterostructure 12 may further include a silicon capping layer 64 having a dielectric or insulating layer 66 disposed thereon (see Figure 5 ). The gate electrodes 50a, 50b may be arranged on top of the dielectric or insulating layer 66.

[0034] On the other hand, the semiconductor heterostructure 12 may further include a strained silicon layer 63 (see Figure 5 In yet another aspect, the semiconductor heterostructure 12 may further include a silicon dioxide layer 62 (see Figure 5 ).

[0035] exist Figure 1 and Figure 2 In the aspect of the quantum processor 10 shown, the components 16, 18, 20, 22, 24 are disposed on at least one surface 14 of the semiconductor heterostructure 12. Figure 1As shown, the illustrated aspect of quantum processor 10 includes one or more of each of components 16, 18, 20, 22, 24. In another aspect, quantum processor 10 may include one or more of only some of components 16, 18, 20, 22, 24.

[0036] Figure 1 and Figure 2 The illustrated quantum processor 10 is a substantially two-dimensional device defined by at least one surface 14. The third dimension of the quantum processor 10 is defined by the thickness of the semiconductor structure 12 and the thicknesses of the components 16, 18, 20, 22, 24.

[0037] The plurality of unit cells of the quantum processor 10 includes a plurality of unit cells 26 (e.g. Figure 2 shown). Figure 2 In the illustrated aspect, unit cell 26 includes components 16, 18, 20, 22, 24. In another aspect of the present disclosure, unit cell 26 includes only some of components 16, 18, 20, 22, 24. In yet another aspect, unit cell 26 may include more than one of at least one of components 16, 18, 20, 22, 24.

[0038] The components 16, 18, 20, 22, 24 include a plurality of gate electrodes 50 arranged on at least one surface 14 of the semiconductor heterostructure 12 (see Figure 3A and Figure 3B ). The plurality of gate electrodes 50 may be arranged to define at least one path 45 within the quantum well 69 of an associated one of the components 16, 18, 20, 22, 24 (see Figure 1 、 Figure 2 、 Figure 3A 、 Figure 3C 、 Figure 4 、 Figure 5 ), one or more qubits can move (shuttle) along these paths.

[0039] exist Figure 1 and Figure 2 , at least one path 45 is shown as being oriented substantially in two directions on the surface 14, the two directions being substantially perpendicular to each other, forming a grid-like structure of a plurality of paths 45. The plurality of paths 45 connect the components 16, 18, 20, 22, 24.

[0040] The plurality of gate electrodes 50 may also be arranged to move (shuttle) one or more qubits along the at least one path 45. The movement (shuttling) may occur in either of two directions (forward and backward) along the at least one path 45. The plurality of gate electrodes 50 may also be arranged to perform at least one action performed by the components 16, 18, 20, 22, 24 on the one or more qubits.

[0041] Multiple gate electrodes 50 can be provided with a voltage. Multiple gate electrodes 50 can be made of metal. Multiple gate electrodes 50 can be superconducting. The voltage can be used for one or more purposes, such as defining at least one path 45, moving (shuttling) one or more qubits, and / or performing at least one action on one or more qubits. The voltage can include a DC (direct current) voltage and an AC (alternating current) voltage. The voltage can include one or more static voltages and one or more non-static voltages. The voltage can be applied via a DC line, an AC line, and / or a biasing device.

[0042] One or more of the components 16, 18, 20, 22, 24 may also include a magnet, such as a micromagnet. The micromagnet may be placed on top of the components 16, 18, 20, 22, 24. The micromagnet provides a magnetic field. The magnetic field may have a zero gradient or a non-zero gradient.

[0043] The external magnetic field splits the multiple spin states (e.g., up spin and down spin) used as the basis for computation of one or more qubits into separate energy levels (Zeeman splitting). The external magnetic field B0 can be provided by an external magnet (e.g., an electromagnet (not shown)) located near the quantum processor 10. The quantum processor 10 can be at least partially placed in the external magnetic field B0 provided by the external magnet.

[0044] One or more components 16, 18, 20, 22, 24 may further include a device for providing electromagnetic radiation (e.g., microwaves) for manipulating the quantum state of one or more qubits (e.g., rotating the spin of one or more qubits between multiple spin states). By electromagnetic radiation based on electron spin resonance (ESR), the spin of one or more qubits can be switched between, for example, an up spin state and a down spin state, or vice versa. The frequency of the electromagnetic radiation can be equal to the energy difference between the separated energy levels. ESR provides another way to manipulate the quantum state of one or more qubits. Microwaves can have a frequency in the range of hundreds of MHz to hundreds of GHz. In one aspect, the frequency is in the range of 9-10 GHz, but is not limited thereto.

[0045] Providing a non-uniform magnetic field, i.e., having a non-zero gradient, enables driving the transition between multiple spin states by the displacement of one or more qubits in a non-uniform magnetic field based on, for example, an AC electric field. This effect is called electric dipole spin resonance (EDSR). The displacement causes one or more qubits to oscillate between multiple spin states (e.g., spin states that form the basis of computing, such as an up spin state and a down spin state). For example, the one or more qubits can oscillate so that the up spin state can be switched to the down spin state, and vice versa. Alternatively, EDSR can be implemented in a semiconductor heterostructure 12 in which spin-orbit coupling exists.

[0046] The plurality of gate electrodes 50 may be provided as one or more gate electrode assemblies 50a, 50b, 50c, 50d. The plurality of gate electrodes 50 may include one or more laterally positioned gate electrodes 50a (also referred to as "shielding gates") (see Figure 3A ), which is arranged to define and / or modify a trajectory 80 in the quantum well 69 and / or at at least one path 45 (see Figure 3C ) to move (shuttle) one or more qubits within or outside the unit cell. Trajectory 80 can be the trajectory of one or more potential wells (described further below) in which one or more qubits can be arranged. The one or more potential wells can therefore be one or more traveling potential wells. The trajectory 80 of the one or more potential wells can therefore correspond to the trajectory of the one or more qubits arranged on at least one path 45. Therefore, the lateral position of trajectory 80 can correspond to the lateral position of the one or more potential wells and / or one or more qubits. Arranging one or more qubits on at least one path 45 should be understood to mean that the one or more qubits are arranged within quantum well 69.

[0047] The plurality of gate electrodes 50 may further include one or more shuttle gate electrodes 50b (also referred to as "transfer gates" or "finger gates" or "keyboard gates") (see Figure 3A ) which is arranged to move (shuttle) one or more qubits along at least one path 45 to move (shuttle) one or more qubits within a unit cell or outside a unit cell.

[0048] The plurality of gate electrodes 50 may further include at least one pitch-enhancing gate electrode 50d (also referred to as a "top gate") arranged so as to enhance the transfer gate pitch or gap of the transfer gates 50b.

[0049] The plurality of gate electrodes 50 may further include at least one vertically positioned gate electrode 50c (also referred to as a "back gate") arranged to define and / or modify a trajectory 80 in the quantum well 69 and / or at at least one path 45 (see Figure 5 ) to move (shuttle) one or more qubits within or outside the unit cell. The vertical position of trajectory 80 can correspond to the vertical position of one or more potential wells and / or one or more qubits.

[0050] The plurality of gate electrodes 50 may further include a qubit processing gate electrode (not shown) configured to perform at least one action on one or more qubits. The qubit processing electrodes include a plunger gate and a barrier gate. The plunger gate may be used to control the occupancy of a quantum dot, control detuning in a double quantum dot, and / or perform an interchanging of two qubits. The barrier gate may be used to form a double potential well and / or control a tunneling barrier in a double quantum dot.

[0051] A plurality of gate electrodes 50 may be arranged on at least one surface 14 of the semiconductor heterostructure 12. The plurality of gate electrodes 50 may be arranged in layers separated by an insulating or dielectric layer 60 and an insulating or dielectric layer 66 (see Figure 3B and Figure 5 In one aspect, the layers can be arranged in a direction substantially perpendicular to the direction of at least one path 45.

[0052] One or more of the insulating or dielectric layer 60, the insulating and dielectric layer 66, and / or the insulating or dielectric layer 67 may be planarized. One method of manufacturing the shuttle element 16 may include the step of planarizing one or more of the insulating or dielectric layer 60, the insulating and dielectric layer 66, and / or the insulating or dielectric layer 67. The insulating or dielectric layer 60 may be planarized during manufacturing before the transfer gate 50b is disposed on the insulating or dielectric layer 60. Planarization facilitates the use of processes such as electron beam epitaxy, deep ultraviolet, and / or spacer lithography.

[0053] Component 16 is used to move (shuttle) one or more quantum dots in semiconductor heterostructure 12 to move (shuttle) one or more qubits within or outside the unit cell. Component 16 is also referred to as a "shuttle channel." Various aspects of shuttle channel 16 are disclosed in International Patent Application No. WO 2021 / 052531A1, the entire disclosure of which is incorporated herein by reference.

[0054] Component 18 provides a junction at which one or more quantum dots can be diverted into at least one branch (at least one second path in at least one path 45) branching out from at least one path 45 for moving (shuttling) one or more quantum bits within or outside the unit cell. Component 18 is also referred to as a "T-junction". The at least one path 45 and at least one branch of the T-junction 18 can be arranged perpendicularly or non-perpendicularly to each other. In one aspect, the at least one path 45 and at least one branch of the T-junction 18 can substantially form a T-shape. Various aspects of the T-junction 16 are disclosed in International Patent Application No. WO 2021 / 052539 A1, the entire disclosure of which is incorporated herein by reference.

[0055] Component 20 is provided for manipulating qubits in quantum dots. Component 20 is also referred to as a "manipulation zone." Manipulation zone 20 enables manipulation of one or more current spin states of one or more qubits. Any qubit has a current spin state. In one aspect, multiple spin states may include the current spin state. In another aspect, the current spin state may be a linear combination of multiple spin states. During manipulation, one or more current spin states may change. Aspects of manipulation zone 20 are disclosed in WO 2021 / 052537 A1, the entire disclosure of which is incorporated herein by reference.

[0056] Component 22 is used to initialize one or more spin states of one or more quantum bits. When one or more spin states have been initialized, any one of the one or more current spin states is equal to one spin state in the plurality of spin states. After initialization, one or more current spin states may remain unchanged during the relaxation time. The relaxation time describes the transition between the upper spin state and the lower spin state due to interaction with the environment (such as the lattice of the semiconductor heterostructure 12). Component 22 is also referred to as an "initialization zone". Various aspects of the initialization zone 22 are disclosed in WO 2021 / 052538 A1, the entire disclosure of which is incorporated herein by reference.

[0057] Component 24 is used to read out one or more current spin states of one or more qubits. When one or more spin states have been read out, any one of the one or more current spin states before the readout is known. Component 24 is also referred to as the "readout region." Various aspects of readout region 24 are disclosed in WO 2021 / 052536 A1, the entire disclosure of which is incorporated herein by reference.

[0058] The quantum processor 10 is operated to execute an algorithm, such as a quantum algorithm. As described above, executing the algorithm includes performing a sequence of actions on one or more qubits. The at least one action is performed by the components 16, 18, 20, 22, 24 of the unit cell 26.

[0059] Operating quantum processor 10 involves controlling at least one action performed by components 16, 18, 20, 22, and 24. In one aspect of the present disclosure, the at least one action is controlled by applying voltages to a plurality of gate electrodes 50. The voltages can be set and / or adjusted to improve the fidelity F of the at least one action and / or sequence of actions. Fidelity F is a measure of how reliably the at least one action or sequence of actions produces the expected result based on the design of quantum processor 10 and the voltages applied to the plurality of gate electrodes 50. To determine fidelity F, at least one action or sequence of actions is repeated; the proportion of repetitions in which the actual result equals the expected result is then determined. The actual result includes one or more current spin states that have been read out at readout region 24 after the at least one action or sequence of actions. The expected result includes one or more current spin states that are expected to be read out at readout region 24 after the at least one action or sequence of actions based on the known fidelity of components 16, 18, 20, 22, and 24 and / or the relaxation time of one or more qubits.

[0060] For example, at least one action may include moving (shuttling) one or more qubits along at least one path 45 of the shuttling channel 16. In this case, the fidelity F is the shuttling fidelity. Shuttling fidelity is understood as the probability that one or more current spin states of one or more qubits are preserved during the shuttling process. For example, the shuttling fidelity can be determined by repeatedly performing a sequence of actions: initializing one or more qubits, moving (shuttling) one or more qubits, and reading out one or more qubits; then determining whether the initialized spin state of the one or more qubits is equal to the one or more current spin states after the shuttling and before the readout; and finally calculating the proportion of repetitions in which the one or more current spin states are unchanged.

[0061] Fidelity F may also be gate fidelity. Gate fidelity F is a measure of how well the results of a gate operation (i.e., a sequence of actions performed by components 16, 18, 20, 22, 24 on one or more qubits associated with the gate that quantum processor 10 is designed to implement) match expected results (e.g., theoretical results) based on the design of quantum processor 10 and components 16, 18, 20, 22, 24. Gate fidelity F can be determined through randomized benchmark testing.

[0062] As an example, improving the shuttling fidelity F of a single qubit along the shuttling channel 16 will be described. Figure 3A 1 shows aspects of a shuttle channel 16. The shuttle channel 16 includes a shield gate 50a and a transfer gate 50b disposed on at least one surface 14 of the semiconductor heterostructure 12. Figure 3A In the illustrated aspect, the at least one surface 14 comprises a top surface 141 of the semiconductor heterostructure 12. Figure 3B In the aspect shown, top surface 141 may be the top surface of dielectric or insulating layer 66 (described further below).

[0063] The shield 50a is arranged to extend on either side of at least one path 45 as shields 50a-1 and 50a-2 (see also Figure 4 ). In one aspect, as Figure 3A-Figure 3B As shown, shield gates 50a-1 and 50a-2 can extend continuously along at least one path 45. Shield gates 50a-1 and 50a-2 can be spaced approximately 200 nm apart. Shield gate 50a can be made of metal and can be fabricated by embedding the metal into semiconductor heterostructure 12 or by locally implanting the metal into semiconductor heterostructure 12. Shield gate 50a can be embedded in dielectric or insulating layer 66 and / or dielectric or insulating layer 60.

[0064] The dielectric or insulating layer 66 and / or the dielectric or insulating layer 60 can be structured in the lateral direction D3. In one aspect, the dielectric or insulating layer 66 and / or the dielectric or insulating layer 60 can be provided as two separate portions (not shown) that surround the two shield gates 50a-1 and 50a-2, and the semiconductor heterostructure 12 extends into the gap (not shown) between the two portions along the lateral direction D3. Thus, the semiconductor heterostructure 12 can form a ridge (not shown) in the gap between the two portions of the dielectric or insulating layer 66 and / or the dielectric or insulating layer 60.

[0065] The transfer gate or finger gate 50b is arranged to extend laterally across at least one path 45 (e.g. Figure 3A For example, the transfer gate 50b may extend in the lateral direction D3. The transfer gate or finger gate 50b is arranged along at least one path 45.

[0066] exist Figure 3A In the aspect shown, transfer gates 50b are provided in the electrode subsets 50b-1, 50b-2, 50b-3, 50b-4 (in Figure 3A and Figure 3B The transfer gates in the transfer gate 50b belonging to one of the electrode subsets 50b-1, 50b-2, 50b-3, 50b-4 are indicated by indices 1, 2, 3, 4. Figure 3A The tops of the columns are marked with the same index, either 1, 2, 3, or 4. Figure 3AThe number of electrode subsets 50b-1, 50b-2, 50b-3, 50b-4 shown in the figure is four. However, the number of electrode subsets of the transfer gate 50b can be different from this example, for example, it can be three or five. Any number of electrode subsets of the transfer gate 50b can be selected, as long as one or more traveling potential wells for moving (shuttling) the quantum bit or one or more quantum bits (see below) can be generated. The one or more traveling potential wells provide confinement for capturing electrons or holes, whose strength is strong enough to overcome the disorder during movement (shuttling) in the quantum well 69, and whose height provides a potential barrier between adjacent potential wells to suppress tunneling. The trapped one or more electrons or holes adiabatically follow the sufficiently slow translation of the electric potential.

[0067] In one aspect, the transfer gates 50b may be arranged at at least one path 45 in such a manner that juxtaposed ones of the transfer gates 50b extend different distances in the lateral (or transverse) direction D3 (eg, Figure 3A In another aspect, transfer gate 50b may extend equally far in lateral direction (or transverse direction) D3.

[0068] The transfer gates 50b can be arranged in a substantially equidistant manner with a substantially constant transfer gate gap between any two adjacent transfer gates 50b. Furthermore, if the transfer gate width of the transfer gates 50b (i.e., the extension of the transfer gates 50b in the longitudinal direction D3) is substantially constant, the transfer gate pitch (the sum of the transfer gate gap and the transfer gate width) is also substantially constant. In one aspect of the present disclosure, the transfer gate pitch can be approximately 80 nm. The transfer gates 50b can be arranged in a periodic manner. In one aspect, the transfer gates 50b of any one of the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 can be arranged in a substantially equidistant manner from one another based on the spatial period of the periodically arranged transfer gates. In another aspect, any two transfer gates 50b belonging to any one of the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 have one transfer gate of each of the other unselected electrode subsets arranged therebetween. The periodic arrangement of the transfer gates 50b facilitates industrial manufacturing of the shuttle channel 16.

[0069] like Figure 3AAs shown, the transfer gates 50b belonging to one of the four electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 are electrically connected to each other by electrical connections (not shown). The transfer gates of any electrode subset selected from the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 are electrically disconnected (or not electrically connected) from the transfer gates of the corresponding unselected electrode subsets. In one aspect of the present disclosure, the electrical connection can be provided by metal strips (not shown) arranged parallel to the shielding grid 50a. The metal strips can be arranged outside the shielding grid 50a in the lateral direction D3. For example, the metal strips connecting the electrode subsets 50b-1 and 50b-3 can be arranged Figure 3A The metal strips connecting the electrode subsets 50b-2 and 50b-4 may be arranged on top of Figure 3A The electrode subsets of the transfer gates 50b indexed 1 and 3 may be on one side of at least one path 45 (e.g. Figure 3A The subset of electrodes of the transfer gates 50b indexed 2 and 4 may have an electrical connection on the other side of at least one path 45 (as shown). Figure 3A As shown, below at least one path 45). In one aspect of the present disclosure, the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 can be arranged at different levels in the stacking direction D1. For example, the metal strips connecting the transfer gates of the electrode subset 50b-1 can be arranged on one side of at least one path 45, which is arranged at a higher level in the stacking direction D1 than the metal strips connecting the transfer gates of the electrode subset 50b-3; and the metal strips connecting the transfer gates of the electrode subset 50b-2 can be arranged on the other side of the at least one path 45, which is arranged at a higher level in the stacking direction D1 than the metal strips connecting the transfer gates of the electrode subset 50b-4. However, on the other hand, all of the metal strips can be arranged on one side of at least one path 45. In a further aspect, the metal strips in the metal strips connecting the transfer gates of the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 can be connected to the transfer gates through through holes; and the transfer gates of the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 can be basically arranged on one level in the stacking direction D1.

[0070] The electrical connection of the transfer grid of any of the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 enables a single voltage to be supplied to the corresponding electrode subset. In other words, the number of voltage signals applied to the transfer grid 50b is given by the number of electrode subsets selected. Thus, the number of voltage signals applied to the shield grid 50a and the transfer grid 50b is independent of the length of the shuttle element 16. Figure 3A and Figure 3BIn the example shown, the number of electrode subsets is four. However, this number can be smaller or larger than four. For example, using three electrode subsets can enable moving one or more qubits through a traveling potential well.

[0071] In a further aspect of the present disclosure, the shuttle channel 16 can include a top grid 50d (see FIG7 ). The top grid 50d can extend in the lateral (transverse) direction D3. The top grid can extend in the shuttle direction (or longitudinal direction) D2. The top grid 50d can cover at least a portion of the first path 451 and / or the second path 452. In one aspect, the top grid 50d completely covers the first path 451 and / or the second path 452, at least in the lateral (transverse) direction D3.

[0072] In another aspect of the present disclosure, a top gate electrode 50d may be disposed on top of the transfer gate 50b with a dielectric layer 67 disposed therebetween. The dielectric or insulating layer 67 may be partially disposed on the dielectric or insulating layer 60 (see FIG. Figure 5 ). Portions of the dielectric or insulating layer 67 disposed between the electrodes of the transfer gate 50b may be disposed on the dielectric or insulating layer 60. The dielectric or insulating layer 67 may be structured in the shuttle direction D2, for example segmented or profiled (see Figure 5 ). Dielectric or insulating layer 67 insulates transfer gates 50b belonging to different subsets of subsets 50b-1, 50b-2, 50b-3, 50b-4 from each other. In one aspect of the present disclosure, dielectric or insulating layers 60 and 67 are a single dielectric or insulating layer 60, 67 in which transfer gates 50b are embedded.

[0073] A constant voltage can be applied to the top gate 50d. In a further aspect, the voltage applied to the top gate 50d can be modified to be used for one or more actions on one or more qubits. For example, the voltage applied to the top gate 50d can be modified to be used to shuttle one or more qubits, to initialize one or more qubits, to read out one or more qubits, or to manipulate one or more qubits. In another example, the voltage applied to the top gate 50d can be modified based on a sequence of actions on one or more qubits, for example as part of executing an algorithm. In a further aspect, the voltage applied to the top gate 50d can be modified periodically or non-periodically. Periodically modifying and / or non-periodically modifying the voltage applied to the top gate 50d can depend on the actions performed on the one or more qubits. Periodically modifying the voltage applied to the top gate 50d includes adding a superposition of a square wave, a sawtooth wave, or a sine wave. Periodically modifying the voltage applied to the top gate 50d includes adding stepwise increments to the voltage applied to the top gate 50d. The step increment may depend on one or more actions performed on one or more qubits.

[0074] In one aspect, the top gate 50d can have a flat top surface (not shown). In another aspect of the present disclosure, the top gate 50d can be structured. An example of a structured top gate 50d is a segmented top gate 50d. Another example of a structured top gate 50d is a top gate with a surface profile (or a shaped top gate), such as Figure 5 In one aspect, the top grid 50d can be a segmented and profiled top grid. In addition to or in lieu of a longitudinal configuration, the top grid 50d can be configured along the lateral direction (or transverse direction) D3, such as segmented and / or profiled.

[0075] Top gate 50d enables increasing the transfer gate spacing between transfer gates 50b while maintaining the ability to shuttle one or more qubits along at least one path 45 .

[0076] In aspects of the present disclosure, at least one surface 14 may further include a back surface 142. At least one back gate 50c may be disposed on the back surface 142 of the semiconductor heterostructure 12 opposite to the top surface 141 (see FIG. Figure 5 ).exist Figure 5 In the illustrated aspect, the back surface 142 is disposed at the bottom of the semiconductor heterostructure. The back surface 142 is disposed opposite the top surface 141. The back surface 142 may be a surface of the silicon dioxide layer 62 (described above).

[0077] exist Figure 5 In the illustrated aspect, the at least one back gate 50c extends along the shuttling direction or longitudinal direction D2 of the shuttle channel 16. The at least one back gate 50c can also extend laterally (or transversely to the at least one path 45). For example, the at least one back gate 50c can also extend along a lateral (or transverse) direction D3 of the shuttle channel 16 that is transverse to the at least one path 45. The at least one back gate 50c can overlap or intersect the shield gate 50a in the lateral direction D3. The at least one back gate 50c can be arranged opposite the shield gate 50a. A voltage can be applied to the at least one back gate 50c to provide an electric potential to modify the confinement at the quantum well 69.

[0078] In one aspect of the present disclosure, at least one back gate 50c can be configured along the shuttling direction (or longitudinal direction) D2, e.g., segmented and / or profiled. In another aspect of the present disclosure, at least one back gate 50c can be configured along the lateral direction D3 (i.e., transverse to at least one path 45), e.g., segmented and / or profiled. In a further aspect of the present disclosure, at least one back gate can be configured along the shuttling direction (or longitudinal direction) D2 and the lateral direction D3, e.g., segmented and / or profiled.

[0079] like Figure 3BAs shown, shield gate 50a and transfer gate 50b are separated by an insulating or dielectric layer 60. As explained above, the insulating or dielectric layer 60 may be planarized during fabrication before transfer gate 50b is disposed on the insulating or dielectric layer 60. The four electrode subsets of transfer gate 50b may be separated by additional insulating or dielectric material (not shown). In addition, a dielectric or insulating layer 66 may be disposed on semiconductor heterostructure 12 (see FIG. Figure 3B The shield gate 50a is separated from the semiconductor heterostructure 12 by an insulating or dielectric layer 66. The shield gate 50a may be disposed on the insulating layer 66.

[0080] The shuttle channel 16 is configured to move (shuttle) one or more qubits along at least one path 45. During operation of the quantum processor 10, the shuttle channel 16 will be used to move one or more qubits, for example, from the initialization region 22 to the manipulation region 20 and then to the readout region 24. During this sequence of actions on one or more qubits, in one aspect of the present disclosure, two shielding grids (or "gates") 50a-1, 50a-2 (see FIG. 1 ) of the shielding grids 50a of the shuttle channel 16 may be moved. Figure 3A and Figure 4 ) provide the same voltage, such as 0V. When a voltage of 0V is applied to the two shield gates 50a-1, 50a-2, the dielectric or insulating layer 66 can be omitted. An AC voltage is provided to the transfer gate 50b to provide one or more traveling potential wells in which one or more qubits can be moved (shuttled). The AC voltage provided to the transfer gate 50b can be a sinusoidal voltage. On the other hand, the AC voltage provided to the transfer gate 50b can be a non-sinusoidal voltage. The non-sinusoidal voltage makes it possible to reduce the varying orbital energy level splitting (see Figure 3D-3F (See also and below) The AC voltage supplied to transfer gate 50b can be phase-shifted between subsets of electrodes of transfer gates 50b-1, 50b-2, 50b-3, and 50b-4. The phase shifts of transfer gates 50b-2, 50b-3, and 50b-4 relative to transfer gate 50b-1 can be set to π / 2, π, and 3π / 2, respectively. However, other settings for the phase shift are possible. The phase shift can deviate from being set to a multiple of π / 2.

[0081] One or more qubits are transmitted along at least one path 45 (along Figure 3C The x-axis extension of the trajectory 80 (see Figure 3C ) in the lateral direction D3 is determined by applying the two gate electrodes 50a-1, 50a-2 in the shielding grid 50a (see, for example, Figure 4). If the voltage applied to gate 50a-1 is substantially equal to the voltage applied to gate 50a-2, the lateral position or positions of the one or more potential wells generated (i.e., the one or more minima of the one or more potential wells) will be substantially in the middle of the two gates 50a-1, 50a-2. On the other hand, if the voltage applied to gate 50a-1 is different from the voltage applied to gate 50a-2, the lateral position or positions of the one or more potential wells generated (i.e., the one or more minima of the one or more potential wells) will deviate from the middle of the two gates 50a-1, 50a-2. The different voltages on gates 50a-1, 50a-2 may be the result of changing the voltage applied to gate 50a-1 or the voltage applied to gate 50a-2 by adding an adjustment voltage ΔV. In other words, the voltage applied to gate 50a-1 or gate 50a becomes V+ΔV. For example, in the case where heterostructure 12 is an undoped Si / SiGe heterostructure, if the voltage applied to gate 50a-1 is reduced relative to the voltage applied to the other gate 50a-2, one or more locations of the generated one or more potential wells (i.e., one or more minima of the one or more potential wells) will shift toward the other gate 50a-2. In the case where heterostructure 12 is doped, such as when GaAs / AlGaAs is used, increasing the voltage applied to gate 50a-1 will shift the one or more potential wells toward the other gate 50a-2. In this way, the trajectory 80 of one or more qubits along at least one path 45 can be shifted laterally (i.e., in a lateral or transverse direction D3 relative to the at least one path 45).

[0082] In one aspect of the present disclosure, the lateral shift of the trajectory 80 of one or more qubits may be transient (at Figure 3C The transient lateral shift is the result of a time-varying adjustment voltage ΔV(t) being applied to the voltage applied to gate 50a-1 or to the voltage applied to gate 50a-2. In other words, track 80 only temporarily deviates from the lateral position initially set during calibration (i.e., at Figure 3C In the example shown, a y position of 0 nm). The temporary lateral displacement results in, for example, Figure 3C Trajectory 80-1 is shown.

[0083] In one aspect, the time-varying adjustment voltage ΔV(t) can be an AC voltage, such as a square pulse or square wave. Figure 3CIf the qubits (e.g., the x-axis in FIG4 ) are spaced an average distance of 1000 nm (or 1 μm) from each other, and the shuttle speed of one or more qubits along at least one path 45 is 10 nm / ns (or 10 m / s), then, on average, it takes one or more qubits 100 ns to travel a distance equal to the average distance. Therefore, the time-varying modulation voltage ΔV(t) can last for 100 ns. For example, half a period of the square wave can be selected to be equal to 100 ns. In other words, the square wave can be selected to have a frequency of 5 MHz.

[0084] In a further aspect of the present disclosure, the tuning voltage comprises a DC voltage added to an AC voltage applied to the transfer gate 50b. This DC voltage may be applied to the transfer gate 50b in addition to or in lieu of the tuning voltage ΔV(t) applied to the shield gate 50a. The further tuning voltage may provide a change in the confinement provided by the transfer gate 50b, for example, to enhance confinement when one or more qubits are near a fidelity degradation site 70 (see below).

[0085] The lateral shifting of the lateral position of trajectory 80-1 enables bypassing of reduced fidelity sites 70 in shuttle channel 16. When one or more qubits pass through reduced fidelity sites 70 in shuttle channel 16, the shuttling fidelity F is reduced. The reduced shuttling fidelity F results in less reliable shuttling of the one or more qubits along shuttle channel 16. Reduced fidelity sites 70 can be the result of, for example, manufacturing impurities, manufacturing defects, charge defects, crystal defects, and / or locally reduced valley splitting. Figure 3C A grayscale-coded valley splitting distribution plot is shown for valley splitting energies between 0 μeV and 300 μeV (lighter shaded areas correspond to higher valley splitting energies; darker shaded areas correspond to lower valley splitting energies). Fidelity reduction sites 70 are located at valley splitting energies between 0 μeV and approximately 30-50 μeV (indicated by the gray-white shaded areas within the dark shaded areas). Figure 3C In the example shown, the trajectory 80-1 bypasses several fidelity degradation sites 70 located at a y position of 0 nm. The fidelity degradation sites 70-1, 70-2, 70-3, ..., 70-10 are indicated by arrows and, in some cases, by white dashed elliptical markers. In the example shown, the peak of the deviation Δy from the lateral position of the trajectory 80 initially set during calibration (i.e., the y position set to 0 nm during the calibration step described below) is along the lateral direction D3. Figure 3C The positive y-axis is about 20 nm in the direction of the lateral direction D3. Figure 3CIn another case, the maximum values ​​of the deviation Δy in the two lateral directions (along the positive and negative y axes, respectively) may be different from 20 nm and -20 nm, respectively.

[0086] The lateral shift of the lateral position y of the track 80 - 1 further enables continuous adjustment of the lateral position y of the track 80 - 1 by a time-varying adjustment voltage ΔV(t). The time-varying adjustment voltage ΔV(t) results in a time-varying deviation Δy(t). Continuous adjustment may be required in the event of fluctuations in the voltages applied to the plurality of gate electrodes 50 .

[0087] In one aspect of the present disclosure, similar to the lateral shift described above, one or more vertical positions of one or more potential wells can be vertically shifted, i.e., in the stacking direction D1 (as described below). As a result, the vertical position of the track 80-3 (the position along the stacking direction D1) can be changed. When the voltage applied to at least one back gate 50c is changed, the confinement of the one or more potential wells will also change. The voltage applied to at least one back gate 50c can be changed relative to the voltage applied to the shield gate 50a. According to at least one fidelity reduction site 70 (at Figure 5 The vertical position of the track 80 can be changed upward or downward in the stacking direction D1 by the position indicated by the asterisk in the figure. As a result, at least one fidelity reduction point 70 can be bypassed and the reliability (ie, fidelity) of the shuttle channel 16 can be improved.

[0088] Figure 3D-3F Results are shown for simulating the effect of disorder in the semiconductor heterostructure 12 on the trajectory splitting of one or more qubits moving along at least one path 45 of the shuttle element 20. The disorder is caused by one or more of defects at the boundaries of the layers of the semiconductor heterostructure 12, defects within the layers of the heterostructure 12, and / or defects within the dielectric layers 60, 66, and / or 67. The defects at the boundaries of the layers of the semiconductor heterostructure 12 include charge defects at the interface between the layer made of semiconductor material and the dielectric or insulating layer 60 and / or 66. These charge defects are randomly distributed, for example at the interface. The density of the charge defects is set to 5E10 / cm 2 Transitions to excited orbital states of electrons confined in one or more traveling potential wells are disorder-induced. Quasi-static fluctuations of disorder in the moving frame of one or more traveling potential wells transform into dynamic noise that couples to the orbital / valley levels. Setting the shuttle velocity to v = 10 m / s results in a reduction in the orbital / valley excitation rate and a subthreshold phase error.

[0089] exist Figure 3D-3FIn FIG, the x-axis shows the distance that one or more qubits are simulated to move. The distance is measured with a spatial period T and has a length of 10T. The spatial period T is four times the spacing of the transmission gates because the same voltage is applied to every four transmission gates 50b. Figure 3D-3F In Figure 5, the y-axis indicates the orbital splitting in meV (millielectron volts) due to the effects of material properties (including or excluding defects) on the orbital splitting. The orbital splitting is caused by the confinement of one or more qubits due to the voltage applied to the gate electrode 50. The wavy horizontal line represents the ideal case of a semiconductor heterostructure 12 without any defects and illustrates the orbital splitting due solely to the confinement caused by the gate. The jagged lines illustrate the effects of defects in the semiconductor heterostructure 12 and / or dielectric layers 60, 66, and / or 67 on the orbital splitting. It can be seen that the orbital splitting decreases or increases depending on the spatially fluctuating material properties of the semiconductor heterostructure 12 and / or the spatially fluctuating material properties of the dielectric layers 60, 66, and / or 67. When the orbital splitting is only slightly reduced along at least one path 45, the confinement of the quantum dot carrying one or more qubits along the at least one path 45 increases, resulting in an increase in the shuttling fidelity F. In one aspect of the present disclosure, the orbital splitting consistently exceeds 1 meV, in which case the shuttling velocity is set to 10 m / s.

[0090] The reduction in thickness of one or more of the insulating or dielectric layers 60, 66, 67 enables shielding of charge defects at the interface by the plurality of gate electrodes 50. Planarization reduces the thickness of one or more of the dielectric or insulating layers 60, 66, 67. For example, before fabricating the transfer gate 50b, the insulating or dielectric layers 66 and / or 60 may be planarized to reduce the thickness of the insulating or dielectric layers 66 and / or 60, respectively.

[0091] After planarization, insulating or dielectric layer 66 and / or 60 is placed closely on semiconductor heterostructure 12. Planarizing insulating or dielectric layer 66 and / or 60 results in a reduction in the thickness of insulating or dielectric layer 66 and / or 60 between at least one path 45 and transfer gate 50b. In one aspect, the thickness of insulating or dielectric layer 60 is required to cover the top and side surfaces of shield gate 50a.

[0092] exist Figure 3D , dielectric or insulating layers 60 and 66 are simulated to have a thickness of 10 nm, shield gates 50a-1 and 50a-2 are simulated to be 210 nm apart, the AC voltage applied to the transfer gates in a phase-shifted manner is simulated to have an amplitude of 100 mV, and the voltage applied to the top gate 50d is simulated to be 170 mV.

[0093] exist Figure 3E, dielectric or insulating layers 60 and 66 are simulated to have a thickness of 7 nm, shield gates 50a-1 and 50a-2 are simulated to be 205 nm apart, the AC voltage applied to the transfer gates in a phase-shifted manner is simulated to have an amplitude of 100 mV, and the voltage applied to the top gate 50d is simulated to be 150 mV.

[0094] exist Figure 3F , the dielectric or insulating layers 60 and 66 are simulated to have a thickness of 5 nm, the shield gates 50a-1 and 50a-2 are simulated to be 200 nm apart, the AC voltage applied to the transfer gates in a phase-shifted manner is simulated to have an amplitude of 100 mV, and the voltage applied to the top gate 50d is simulated to be 140 mV.

[0095] from Figure 3D-3F It can be seen that in Figure 3F The conditions simulated in achieve a minimum standard deviation of track splitting along at least one path 45 .

[0096] Determining the shuttle fidelity F enables identification of the location of the fidelity degradation site 70 at the track 80-1 or 80-3 (e.g., along the track 80-1 or 80-3 and / or near the track 80-1 or 80-3). During identification of the location of the fidelity degradation site 70, the applied voltage V is iteratively adjusted. Thus, the lateral position of the track 80-1 and / or the vertical position of the track 80-3 are iteratively adjusted. Identification of the location of the fidelity degradation site 70 results in a method for controlling the shuttle channel 16.

[0097] In the calibration step, the voltage V applied to the plurality of gate electrodes 50 is calibrated. The calibration of the plurality of voltages V takes into account a target range for the plurality of voltages V. The target range may be predefined based on data previously collected from measurements and experiments. While calibrating the voltage V, the voltage V is maintained within the target range.

[0098] When calibrating multiple voltages V, at least one interaction between some of the multiple voltages is considered. The at least one interaction can be expressed as a boundary condition or a functional relationship. The functional relationship can take into account a target range.

[0099] For example, in Figure 3A and Figure 3BIn the case of the illustrated shuttle channel 16, the voltages applied to the shield gate 50a and the transfer gate 50b generate electric fields (in the case where the voltage V is a DC voltage) and / or electromagnetic fields (in the case where the voltage V is an AC voltage). The generated fields superimpose on each other, for example at the trajectory 80, and result in a composite electric field and / or composite electromagnetic field. The effects of this superposition, or interaction, need to take into account the material composition of the shuttle channel 16 and the target behavior. Other interactions between the voltages applied to the gate electrodes 50 will exist and may depend on the actual design of the quantum processor 10.

Claims

1. A shuttle element (16) for a quantum computer (10), comprising a plurality of gate electrodes (50) arranged on a semiconductor heterostructure (12), wherein The plurality of gate electrodes (50) include shielding gates (50a-1, 50a-2), the shielding gates (50a-1, 50a-2) being used to define at least one path (45) in the semiconductor heterostructure (12); The plurality of gate electrodes (50) include a transfer gate (50b) arranged at the at least one path (45), The transfer gate (50b) includes electrode subsets (50b-1, 50b-2, 50b-3, 50b-4) electrically disconnected from each other, and the transfer gates (50b) of any one of the electrode subsets (50b-1, 50b-2, 50b-3, 50b-4) are electrically connected to each other; The finger gate (50b) is configured to be provided with at least one voltage V to move at least one quantum bit along the at least one path (45).

2. The shuttle element (16) of claim 1, wherein a subset of electrodes in the plurality of electrode subsets (50b-1, 50b-2, 50b-3, 50b-4) have a dielectric or insulating layer (67) disposed between each other.

3. The shuttle element (16) according to claim 1 or 2, wherein the transfer gate (50b) is arranged on a planarized dielectric or insulating layer (60).

4. The steering region (20) according to any one of claims 1 to 3, wherein the plurality of gate electrodes (50) are arranged on at least one surface (14) of the semiconductor heterostructure (12).

5. The manipulation region (20) according to any one of claims 1 to 4, further comprising a top gate (50d) arranged above the transfer gate (50b).

6. A system comprising a shuttle element (16) according to any one of claims 1 to 5 and a magnet providing an external magnetic field B0.

7. A method of moving at least one quantum bit along at least one path (45) in a semiconductor heterostructure (12), the semiconductor heterostructure (12) comprising a plurality of gate electrodes (50) disposed thereon, the plurality of gates: Provide an external magnetic field B0; At least one traveling potential well for moving the at least one quantum bit is generated by applying at least one voltage to the plurality of gate electrodes (50) and arranged at the at least one path (45).

8. The method of claim 7, wherein generating the at least one traveling potential well comprises: At least one AC voltage is applied to a transfer gate (50b) among the plurality of gate electrodes (50).

9. The method of claim 8, wherein generating the at least one traveling potential well comprises: Phase-shifted AC voltages are applied to electrode subsets (50b-1, 50b-2, 50b-3, 50b-4) of the transfer gate (50b), the electrode subsets (50b-1, 50b-2, 50b-3, 50b-4) are electrically disconnected from each other, and the transfer gates (50b) of any one of the electrode subsets (50b-1, 50b-2, 50b-3, 50b-4) are electrically connected to each other.

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