Non-linear channel

Abstract

The present invention provides a finFET including a non-linear channel. The non-linear channel includes one or more arcuate, curved, segmented, etc. sidewalls defining a channel width and a channel length. The non-linear channel provides a relatively increased channel length compared to a linear fin oriented orthogonal to the gate width. Therefore, the channel length of the non-linear channel can be relatively increased in the range of the gate. In other words, short channel effects may be limited due to a decrease in the electric field along the non-linear channel due to a relatively increased channel or fin length within the gate's footprint.

Description

Background Art

[0001] The present invention relates to methods for fabricating semiconductor devices and the resulting structures. More particularly, the present disclosure relates to methods for fabricating integrated circuit (IC) devices, such as wafers, dies, processors, etc., that include transistors having nonlinear channels, such as fin field-effect transistors (finFETs), and the resulting structures.

[0002] Semiconductor devices and IC devices have become ubiquitous in many products, especially as they continue to decrease in cost and size. It has always been desirable to reduce the size of structural features and / or provide a larger number of structural features for a given device size. Generally, miniaturization allows for improved performance at lower power levels and lower costs. Current technology is at or near the atomic scale of certain micro devices, such as logic gates, field effect transistors (FETs), capacitors, etc.

[0003] For example, when the width of the fin of a finFET is scaled down or reaches 5 nanometers (nm) (near the 3nm node), the contact-to-poly pitch (CPP) reaches a CPP limit of approximately 45nm with a metal pitch of 22nm. The CPP is the distance separating the respective centers of adjacent gate contacts. The CPP limit may be caused by the desire to minimize or eliminate short channel effects, by the desire to minimize the increase in parasitic capacitance caused by smaller gate spacing widths, and / or by shrinking the space for source and / or drain contacts.

[0004] To achieve the desired finFET functionality, the gate electric field should generally dominate the channel, and the drain electric field should have a smaller effect on the channel. Otherwise, the finFET will exhibit a set of undesirable effects known as short channel effects. One way to reduce the tendency toward short channel effects is to increase the gate length (Lg). Summary of the Invention

[0005] In an embodiment of the present disclosure, a finFET is provided. The finFET includes a nonlinear channel beneath a gate. The nonlinear channel includes a first nonlinear sidewall. The first nonlinear sidewall is nonlinear (i.e., not straight), resulting in a relatively increased channel length within the confines of the gate footprint. This increased channel length is greater than that of a related linear fin that spans the length of the gate. In other words, the electric field along the nonlinear channel is reduced due to the relatively increased channel length, thereby limiting short channel effects.

[0006] In an example, the nonlinear channel may further include a second nonlinear sidewall opposite the first nonlinear sidewall. In an example, the first nonlinear sidewall is a first curved nonlinear sidewall and / or the second nonlinear sidewall is a second curved nonlinear sidewall. In one example, the first curved nonlinear sidewall and the second curved nonlinear sidewall are parallel. In one example, the first curved nonlinear sidewall and the second curved nonlinear sidewall share the same central axis of curvature.

[0007] In an example, the finFET further includes a source electrode in physical contact with a first end surface of the nonlinear channel and a drain electrode in physical contact with an opposite second end surface of the nonlinear channel. In an example, the finFET further includes a gate spacer surrounding the gate. In an example, a channel length of the nonlinear channel is greater than a gate length of the gate.

[0008] In an example, the first nonlinear channel includes a first nonlinear sidewall and a second nonlinear sidewall opposite the first nonlinear sidewall. In an example, the first nonlinear sidewall is a first curved sidewall, and the second nonlinear sidewall is a second curved sidewall.

[0009] In an example, the second nonlinear channel includes a third nonlinear sidewall and a fourth nonlinear sidewall opposite the first nonlinear sidewall. In an example, the third nonlinear sidewall is a third curved sidewall, and the fourth nonlinear sidewall is a fourth curved sidewall.

[0010] In an example, the first curved sidewall and the second curved sidewall are parallel, and the third curved sidewall and the fourth curved sidewall are parallel. In an example, the first curved sidewall, the second curved sidewall, the third curved sidewall, and the fourth curved sidewall share a same central axis of curvature.

[0011] In an example, the finFET further includes a gate spacer surrounding the gate. In an example, a channel length of the first nonlinear channel is greater than a gate length of the gate. In another example, a channel length of the second nonlinear channel is greater than the gate length.

[0012] In another embodiment of the present disclosure, a finFET fabrication method is provided. The method includes forming a nonlinear fin above a semiconductor substrate, forming a sacrificial gate above the nonlinear fin, forming gate spacers on respective sidewalls of the sacrificial gate, forming a source electrode in physical contact with a first end surface of the nonlinear fin, forming a drain electrode in physical contact with a second end surface of the nonlinear fin, removing the sacrificial gate between the gate spacers, and forming a replacement gate between the gate spacers. The nonlinear fin is a nonlinear channel of the finFET, and the nonlinear channel has a channel length greater than a length of the replacement gate.

[0013] Compared to the linear fin, the nonlinear channel length is relatively large. Therefore, the nonlinear channel length can be relatively increased within the limits of the replacement gate's footprint (e.g., gate length (Lg) multiplied by gate width). In other words, the short channel effect can be limited due to the reduced electric field along the nonlinear channel, which is caused by the relatively increased channel or fin length within the replacement gate's footprint.

[0014] The above summary is not intended to describe each illustrated embodiment or every implementation of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings included in this application are incorporated into and form a part of the specification. They illustrate embodiments of the present disclosure and, together with the specification, explain the principles of the present disclosure. The accompanying drawings only illustrate certain embodiments and do not limit the present disclosure.

[0016] Figure 1 Depicted are cross-sectional and top views of a semiconductor device including a nonlinear channel according to an embodiment of the present invention.

[0017] Figures 2 to 9 Depicted are cross-sectional views of a semiconductor device including a nonlinear channel at various fabrication stages of a fabrication process according to an embodiment of the present disclosure.

[0018] Figure 10 A method of fabricating a semiconductor device including a nonlinear channel according to an embodiment of the present invention is described.

[0019] Figures 11 to 13 Depicted are cross-sectional views of a semiconductor device including a nonlinear channel at various fabrication stages of a fabrication process according to an embodiment of the present disclosure.

[0020] Figure 14 A method of fabricating a semiconductor device including a nonlinear channel according to an embodiment of the present invention is described. DETAILED DESCRIPTION

[0021] To reduce the tendency of short channel effects, the gate length (Lg) is usually increased. However, as CPP is scaled down, there is less room to increase the size of the gate.

[0022] Aspects of the present disclosure can limit short channel effects within finFETs and can allow further scaling of finFETs. More specifically, a finFET including a nonlinear fin is provided. The nonlinear fin has a greater channel length relative to a related linear fin (e.g., a conventional finFET having a vertical straight fin or channel that spans the gate length (Lg)). The channel length of the nonlinear fin can be obtained without increasing the geometry of other finFET features, such as gate length (Lg), gate spacer width, etc. Therefore, the geometry of the finFET including the nonlinear fin can be further scaled while obtaining the benefits of the relatively increased channel length of the nonlinear fin. Increasing the channel length reduces the short channel effect because the electric field decreases along the longer channel length.

[0023] The flowcharts and cross-sectional views in the accompanying drawings illustrate methods for fabricating an IC device including nonlinear fins according to various embodiments of the present disclosure. In some alternative implementations, the fabrication steps may occur in a different order than noted in the drawings, and certain additional fabrication steps may be performed between the steps noted in the drawings. Furthermore, any layered structures depicted in the drawings may include multiple sub-layers.

[0024] Various embodiments of the present disclosure are described herein with reference to the relevant drawings. Without departing from the scope of the present disclosure, alternative embodiments may be designed. Note that various connections and positional relationships (e.g., above, below, adjacent, etc.) are described between the elements in the following description and the accompanying drawings. Unless otherwise indicated, these connections and / or positional relationships may be direct or indirect, and the present disclosure is not intended to be limited in this respect. Therefore, the coupling of entities may refer to direct or indirect coupling, and the positional relationship between entities may be direct or indirect positional relationship. As an example of an indirect positional relationship, the formation of layer "A" on layer "B" mentioned in this specification includes a case where one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B", as long as the relevant properties and functions of layer "A" and layer "B" are not substantially changed by one or more intermediate layers.

[0025] The following definitions and abbreviations are used to interpret the claims and description. As used herein, the terms "comprises," "includes," "has," "contains," or any other variations thereof are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0026] For the purposes of the description below, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom" and their derivatives shall refer to the structures and methods being described as oriented in the accompanying drawings. The terms "overlying", "on top", "positioned on" or "positioned on top" indicate that a first element, e.g., a first structure, is present on a second element, e.g., a second structure, wherein intermediate elements, e.g., an interface structure, may be present between the first element and the second element. The term "direct contact" refers to that a first element (e.g., a first structure) and a second element (e.g., a second structure) are connected without any intermediate conductive, insulating or semiconducting layer at the interface of the two elements. It should be noted that the term "selective", e.g., "a first element is selective to a second element", means that the first element can be etched and the second element can act as an etch stop layer.

[0027] For the sake of brevity, conventional techniques related to semiconductor device and / or IC fabrication may or may not be described in detail herein. In addition, the various tasks and process steps described herein may be incorporated into a more comprehensive program or process having additional steps or functionality not described in detail herein. The various steps in the fabrication of semiconductor devices and semiconductor-based ICs are well known, and therefore, for the sake of brevity, many conventional steps will be mentioned only briefly or omitted entirely without providing well-known process details.

[0028] Typically, the various processes used to form semiconductor devices (e.g., microchips) to be packaged into ICs fall into four general categories: material deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). Removal / etching is any process that removes material from a wafer. Examples include etching processes (wet or dry) and chemical mechanical planarization (CMP). Conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate other wiring or device components. Semiconductor lithography is the process of forming a three-dimensional relief image or pattern in one or more underlying materials for subsequent transfer of the pattern to one or more materials. In semiconductor lithography, the pattern is formed from a photosensitive polymer called a photoresist.

[0029] Referring now to the drawings, wherein like numerals represent the same or similar elements, and first to Figure 1, which depicts a cross-sectional view and a top view of a semiconductor device 100 including a nonlinear channel 110 according to an embodiment of the present disclosure. The term "nonlinear channel" is defined herein as a channel including opposing sidewalls (i.e., opposing sidewalls) that define a nonlinear fin length that is not parallel to an X cross-section, which, as described, is generally orthogonal to the associated gate width. The term "nonlinear" is defined herein as not straight. As such, the nonlinear fin length will include at least one non-straight sidewall in the opposing sidewalls that define the fin length. For example, the nonlinear fin length may include one or more curved sidewalls that define the fin length. For example, the nonlinear channel may include one or more curved sidewalls that define the fin length, the nonlinear channel may include a first set of straight segmented sidewalls and a second set of straight segmented sidewalls that are angled relative to the first set of segmented signed walls (e.g., a V-shaped nonlinear channel, etc.).

[0030] The semiconductor device 100 may further include a semiconductor substrate 102 , one or more isolation regions 112 , one or more source / drain regions 150 , one or more replacement gates 190 , one or more gate spacers 180 , and one or more interlayer dielectrics 195 .

[0031] The nonlinear channel 110 can include one or more sidewalls that are curved, bent, segmented, etc., that define a fin or channel width 181 and / or a fin or channel length 185. Specifically, as depicted, the nonlinear channel 110 can include curved or bent sidewalls that define a channel or fin length 185. Compared to a typical linear fin (i.e., a fin parallel to the X-plane, as depicted), the nonlinear channel 110 typically has a longer channel or fin length 185. As a result, the channel or fin length 185 of the nonlinear channel 110 can be relatively increased within the confines of the footprint or replacement gate structure (e.g., gate length (Lg) of the replacement gate 190 × gate width). In other words, the fin or channel length 185 of the nonlinear channel 110 can be relatively increased without increasing the gate length (Lg) 183 of the replacement gate 190. Although shown as having curved or bent sidewalls, the nonlinear channel 110 can include V-shaped sidewalls, hexagonal sidewalls, or other segmented sidewalls that define the fin length.

[0032] Figure 2 A top view of a semiconductor device 100 including a nonlinear channel 110 is shown at another stage of the fabrication process according to an embodiment of the present disclosure. At the current fabrication stage, a hard mask (not shown) and one or more fin mandrels 104 are formed on a semiconductor substrate 102 .

[0033] The semiconductor substrate 102 includes a semiconductor material, including but not limited to silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), Si:C (carbon-doped silicon), silicon germanium carbide (SiGeC), carbon-doped silicon germanium (SiGe:C), III-V, II-V compound semiconductors, or other similar semiconductors. Furthermore, multiple layers of semiconductor materials may be used as the semiconductor material of the substrate. The semiconductor substrate 102 may be a bulk substrate, as depicted in this example, or a semiconductor-on-insulator substrate, such as, but not limited to, silicon-on-insulator (SOI), silicon-germanium-on-insulator (SGOI), or a III-V-on-insulator substrate including a buried insulating layer (e.g., a buried oxide or nitride layer).

[0034] A hard mask (not shown) may be formed on substrate 102 and may include, for example, a nitride material such as, but not necessarily limited to, silicon nitride (SiN) or titanium nitride (TiN). The hard mask may be deposited using deposition techniques including, but not necessarily limited to, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), radio frequency CVD (RFCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), molecular layer deposition (MLD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source mist chemical deposition (LSMCD), and / or sputtering. In some embodiments, a planarization process such as chemical mechanical planarization (CMP) may be used to remove excess hard mask material. The hard mask may have a height in the range of 20 nm to 100 nm, but is not necessarily limited thereto.

[0035] One or more fin mandrels 104 include (but are not necessarily limited to) amorphous silicon (a-Si), amorphous carbon, polycrystalline silicon, polycrystalline silicon germanium, amorphous silicon germanium, polycrystalline germanium, and / or amorphous germanium, and are formed on a hard mask and spaced apart from each other. The formation of the fin mandrels 104 can be accomplished by various patterning techniques, including but not necessarily limited to, for example, photolithographic patterning followed by directional etching and / or sidewall image transfer (SIT) processes. In some embodiments, the process includes using photolithography followed by directional etching (e.g., reactive ion etching (ME)) to form the one or more fin mandrels 104.

[0036] In an example, the fin mandrel 104 can be a cylinder and have circular sidewalls with a central axis located in and outside the page. In this example, the nonlinear channel 110 manufactured in association therewith can also have circular sidewalls that define the fin width. The sidewalls associated with the nonlinear channel can have the same central axis as the fin mandrel. In another example, as depicted, each fin mandrel 104 can be an oblong column and have curved sidewalls with two focal axes located in and outside the page. In this example, the nonlinear channel 110 manufactured in association therewith can also have elliptical curved sidewalls that define the fin length. In another example, each mandrel 104 can be a diamond pillar and have segmented sidewalls. In this example, the nonlinear channel 110 manufactured in association therewith can also have V-shaped segmented sidewalls that define the fin width. In another example, each mandrel 104 can be a diamond pillar and have segmented sidewalls. In this example, the nonlinear channel 110 fabricated in association therewith may also have V-shaped segmented sidewalls defining the fin width. In another example, each mandrel 104 may be a polygonal column (e.g., a hexagonal column, etc.) having a central bisector axis that enters and exits the page and has associated segmented sidewalls. In this example, the nonlinear channel 110 fabricated in association therewith may also have polygonal segmented sidewalls defining the fin width.

[0037] Figure 3 A top view of a semiconductor device 100 including a nonlinear channel 110 is shown at another stage of the fabrication process according to an embodiment of the present disclosure. At the current fabrication stage, sidewall image transfer (SIT) spacers 106 are formed on one or more nonlinear sidewalls of the fin mandrels 104 and on the top surface of the hard mask.

[0038] The SIT spacers 106 may be a conformal film and may be deposited and then subjected to an etch-back process (e.g., ME). The deposition of material on the mandrels 104 may also be referred to as spacer formation around the vertical sides of each mandrel 104. The SIT spacer 106 material may include, but is not limited to, oxides such as silicon oxide (SiO x)(wherein x is 2, or 1.99 or 2.01 in the case of silicon dioxide (SiO2), which is formed by low pressure chemical vapor deposition (LPCVD), PECVD, sub-atmospheric pressure chemical vapor deposition (SACVD), rapid thermal chemical vapor deposition (RTCVD), in-situ radical assisted deposition, high temperature oxide (HTO) deposition, low temperature oxide (LTO) deposition, ozone / TEOS deposition, limited reaction process CVD (LRPCVD). Alternatively, some other dielectric materials, such as SiOCN, SiCN, SiOC, can be used as the material of the SIT spacer layer 106. The height of the fin mandrel 104 and the corresponding SIT spacer 106 can be in the range of 30nm to 100nm, but is not necessarily limited thereto.

[0039] Figure 4 A top view and a cross-sectional view of a semiconductor device 100 including a nonlinear channel 110 are depicted at another stage of the fabrication process according to an embodiment of the present invention. At the current fabrication stage, one or more fin mandrels 104 are removed, one or more nonlinear channels 110 are formed, and one or more isolation regions 112 are formed.

[0040] The nonlinear channel 110 may be formed by patterning a portion of the semiconductor substrate 102 into the nonlinear channel 110. The nonlinear channel 110 may be formed by removing the mandrel 104 to form an opening. The opening exposes a portion of the top surface of the hard mask and is formed using an etching process such as plasma dry etching.

[0041] The nonlinear channel 110 is formed by patterning a portion of the semiconductor substrate 102 into the nonlinear channel 110. The selective removal of the fin mandrels 104 leaves the SIT spacers 106 on the hard mask. The hard mask is patterned into a plurality of patterned hard mask portions 107 corresponding to the locations covering the SIT spacers 106, such that the underlying patterned hard mask portions 107 have the same shape as the overlying SIT spacers 106. More specifically, the exposed portions of the hard mask not under the SIT spacers 106 (e.g., not masked by the SIT spacers 106) are removed using, for example, a directional etching process including RIE using CF8, CH2F2, or other chemistries, such as those known to etch silicon nitride that is selective to other materials. Patterning the hard mask into the plurality of patterned hard mask portions 107 spaced apart from each other can be performed using, for example, SAMP techniques, which include, but are not necessarily limited to, SADP, SAQP, and SAOP.

[0042] After removing the SIT spacers 106, exposed portions of the semiconductor substrate 102 not covered by the hard mask portion 107 are removed using the patterned hard mask portion 107 as a mask to a specific depth d1 (depending on the design) using a substrate etch. The substrate etch transfers the pattern of the hard mask portion 107 to the semiconductor substrate 102 to form a nonlinear channel 110 having the same shape as the overlying hard mask portion 107. According to embodiments, the semiconductor substrate 102 including a semiconductor material such as Si, SiGe, SiC, Si:C, SiGeC, SiGe:C, III-V, II-V compound semiconductors, or other similar semiconductors can be selectively etched relative to the hard mask portion 107 using, for example, a silicon RIE process.

[0043] Although the embodiments of the present disclosure describe channels as fins, the embodiments are not necessarily limited to fin channels and may include nanowire channels, etc. In addition, although a limited number of nonlinear channels 110 are shown in the figure for ease of explanation, more or fewer nonlinear channels 110 may be formed.

[0044] After forming the nonlinear channels 110, the hard mask portion 107 can be removed and / or isolation regions 112 (e.g., shallow trench isolation (STI) regions) can be formed. After selectively removing portions of the semiconductor substrate 102 to a depth D1, a plurality of trenches or patterns are formed in the semiconductor substrate 102 by, for example, a wet or dry etching process. A dielectric material is deposited in the trenches or patterns, including but not necessarily limited to SiOx, LTO, HTO, flowable oxide (FOX), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), or some other dielectric. The dielectric material can be deposited using deposition techniques including, but not necessarily limited to, CVD, plasma-enhanced CVD, PECVD, RFCVD, PVD, ALD, MLD, MBD, PLD, LSMCD, and / or sputtering to define the isolation regions 112. As depicted, the top surface of the isolation regions 112 is below the top surface of the one or more nonlinear channels 110.

[0045] Figure 5 Depicted are top and cross-sectional views of a semiconductor device 100 including a nonlinear channel 110 at another stage of the fabrication process according to an embodiment of the present disclosure. At the current fabrication stage, one or more sacrificial gate structures are formed.

[0046] One or more sacrificial gate structures may be formed on and around the one or more non-linear channels 110 and on the isolation region 112. The sacrificial gate structure may include a gate liner (not shown), a sacrificial gate 113, and a sacrificial gate cap 114.

[0047] The sacrificial gate structure can be formed by initially forming a gate liner layer (e.g., a dielectric, an oxide, etc.) on the isolation region 112 and on and around the one or more nonlinear channels 110. For example, the gate liner layer can be deposited on the upper surface of the isolation region 112, the sidewalls of the one or more nonlinear channels 110, the upper surface of the one or more nonlinear channels 110, etc. The sacrificial gate structure can also be formed by subsequently forming a sacrificial gate layer (e.g., a dielectric, amorphous silicon, etc.) on the gate liner. The thickness of the sacrificial gate layer can be greater than the height of the one or more nonlinear channels 110.

[0048] A sacrificial gate structure 160 may be further formed by subsequently forming a gate cap layer on the sacrificial gate layer. The gate cap may be formed by depositing a mask material, such as a hard mask material. The gate cap may be composed of one or more layers of mask material to protect the sacrificial gate layer and / or other underlying materials during subsequent processing of the device 100. The gate cap layer may be formed of a gate mask material, such as silicon nitride, silicon oxide, combinations thereof, and the like.

[0049] The gate cap, sacrificial gate layer, and gate liner can be patterned using photolithography and etching processes to remove undesirable portions and retain one or more desired portions, respectively. The remaining desired portions of the gate cap, sacrificial gate layer, and gate liner layer can form the gate liner, sacrificial gate 113, and sacrificial gate cap 114 of each of the one or more sacrificial gate structures, respectively.

[0050] Each sacrificial gate structure can be formed on a target region or area of ​​semiconductor device 100 to define the length of one or more transistors and provide sacrificial material to produce one or more target transistor structures in subsequent processing. According to an example, each sacrificial gate structure can have a height between about 50 nm and about 200 nm and a length between about 15 nm and about 200 nm.

[0051] Figure 6 Depicted are top and cross-sectional views of a semiconductor device 100 including a nonlinear channel 110 at another stage of the fabrication process according to an embodiment of the present disclosure. At the current fabrication stage, one or more gate spacers 180 are formed.

[0052] One or more gate spacers 180 may be formed on at least corresponding side surfaces of the one or more sacrificial gate structures, on and around one or more exposed portions of the nonlinear channel 110, and on the isolation region 112. One or more gate spacers 180 may further be formed on one or more end surfaces of one or more associated one or more sacrificial gate structures. One or more gate spacers 180 may be formed by conformal deposition of a dielectric material such as silicon nitride, SiBCN, SiNC, SiN, SiCO, SiNOC, or a combination thereof. One or more undesirable portions of the dielectric material may be removed by an anisotropic etching process. One or more desired portions of the dielectric material may remain on the sidewalls of the one or more sacrificial gate structures.

[0053] Figure 7 A top view and a cross-sectional view of a semiconductor device 100 including a nonlinear channel 110 at another stage of the fabrication process according to an embodiment of the present disclosure are depicted. At the current fabrication stage, one or more portions of the nonlinear channel 110 not covered by one or more gate spacers 180 may be recessed or otherwise removed.

[0054] The nonlinear channel 110 can be recessed by directional etching, etc., to remove portions of the one or more nonlinear channels 110 not covered by the one or more gate spacers 180. The top surface of the isolation region 112 can serve as an etch stop layer, and the one or more gate spacers 180 can remain. Subsequently, the corresponding end surfaces 125 of the nonlinear channel 110 can be coplanar with the side surfaces 123 of the gate spacers 180. The trimming or removal of one or more portions of the one or more nonlinear channels 110 can form one or more source / drain (S / D) openings 111. The one or more S / D openings 111 can be defined or bounded by the top surfaces of the plurality of isolation regions 112 and at least one or more opposing and facing end surfaces 125 of adjacent nonlinear channels 110. The one or more S / D openings 111 can be further defined or bounded by opposing and facing portions of the side surfaces 123 of the gate spacers 180.

[0055] For clarity, there may be two different patterned nonlinear channels 310 fabricated from a fin structure around a common central axis. For example, as shown in the top view, the upper FET includes a first channel and a second channel that share the same central axis of curvature.

[0056] Figure 8 A top view and a cross-sectional view of a semiconductor device 100 including a nonlinear channel 110 at another stage of the fabrication process are depicted according to an embodiment of the present disclosure. At the current fabrication stage, S / D regions 150 are formed in one or more S / D openings 111 , respectively.

[0057] The S / D regions 150 can be formed by epitaxially growing source / drain regions in the S / D openings 111, for example, from one or more exposed end surfaces 125 of the one or more nonlinear channels 110. In some embodiments, the S / D regions 150 are formed by in-situ doping epitaxial growth. In some embodiments, the epitaxial growth and / or deposition process can be selectively formed on semiconductor surfaces and may not deposit material on dielectric surfaces, such as silicon dioxide or silicon nitride surfaces.

[0058] Suitable n-type dopants include, but are not limited to, phosphorus (P), and suitable p-type dopants include, but are not limited to, boron (B). The use of an in-situ doping process is merely one example. For example, a non-in-situ process may alternatively be employed to introduce dopants into the source and drain. Other doping techniques may be used to incorporate dopants into the bottom source / drain region. Doping techniques include, but are not limited to, ion implantation, vapor phase doping, plasma immersion ion implantation, cluster doping, injection doping, liquid phase doping, solid phase doping, in-situ epitaxial growth, or any suitable combination of these techniques. In a preferred embodiment, the S / D epitaxial growth conditions promote in-situ boron doping of SiGe for p-type transistors and phosphorus or arsenic doping of silicon or Si:C for n-type transistors. The doping concentration of the S / D region 150 may be between 1×1019 cm-3 and 2×1021 cm-3, or preferably between 2×1020 cm-3 and 7×1020 cm-3.

[0059] In some implementations, the S / D regions 150 can be grown such that the bottom surface contacts the isolation region 112 and the upper surface of the S / D regions 150 is higher than the upper surface of the nonlinear channel 110. For clarity, as shown in the X-sectional view, the first S / D region 150 can be the source region of the nonlinear channel 110 and the second S / D region 150 can be the drain region of the nonlinear channel 110. Furthermore, as depicted in the top-down view, two different S / D regions 150 grown from different nonlinear channels 110 can effectively merge and form a single S / D region 150, which can serve as the source or drain of the different nonlinear channels 110.

[0060] Figure 9 A top view and a cross-sectional view of a semiconductor device 100 including a nonlinear channel 110 at another stage of the fabrication process according to an embodiment of the present disclosure are depicted. At the current fabrication stage, an interlayer dielectric 195 is formed over the isolation region 112 and the S / D region 150, the sacrificial gate 113 is removed, and a replacement gate 190 is formed in its place.

[0061] An interlayer dielectric 195 may be formed on one or more S / D regions 150 and on the top surface of the isolation region 112. The interlayer dielectric 195 may be formed by depositing a dielectric material such as silicon oxide, silicon nitride, SiBCN, SiNC, SiN, SiCO, SiNOC, or a combination thereof as a blanket layer on the isolation region 112, the S / D region 150, and the gate spacer 180. In an embodiment, the interlayer dielectric 195 may be formed to a thickness above the top surface of the semiconductor device 100 and then planarized by chemical mechanical polishing (CMP) or etching such that the top surface of the sacrificial gate 113 is exposed (e.g., the sacrificial gate cap 114 is removed by CMP) and is coplanar with the top surface of the sacrificial interlayer dielectric 195 and the top surface of the gate spacer 180.

[0062] The sacrificial gate 113 is removed by etching while a portion of the sacrificial gate 113 is exposed. The removal of the sacrificial gate 113 may expose the nonlinear channel 110 between the gate spacers 180 previously associated therewith, may expose the gate dielectric thereunder, and the like.

[0063] A replacement gate structure is then formed between the gate spacers 180 and over and around the nonlinear channel 110 to replace the removed sacrificial gate 113. The replacement gate structure may include a gate dielectric (not shown) and a replacement gate 190. The gate dielectric is the gate dielectric associated with the replacement gate structure, or if removed, a subsequent gate dielectric that may include any suitable dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, high-k material, or any combination of these materials. The gate dielectric may be formed by any suitable deposition process, etc. In some embodiments, the gate dielectric has a thickness ranging from 1 nm to 5 nm, although lesser and greater thicknesses are also contemplated.

[0064] The replacement gate 190 may include any suitable conductive material, including but not limited to doped polycrystalline or amorphous silicon, germanium, silicon germanium, metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), hafnium (Hf), zirconium (Zr), cobalt (Co), nickel (Ni), copper (Cu), aluminum (Al), platinum (Pt), tin (Sn), silver (Ag), gold (Au), conductive metal compound materials (e.g., tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaC), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tungsten silicide (WSi), tungsten nitride (WN), ruthenium oxide (RuO2), cobalt silicide (CoSi), nickel silicide (NiSi)), transition metal aluminides (e.g., Ti3Al, ZrAl), TaC, TaMgC), carbon nanotubes, conductive carbon, graphene, or any suitable combination of these materials.

[0065] The replacement gate 190 may further include dopants incorporated during or after deposition. In some embodiments, the replacement gate 190 may further include a work function setting layer (not shown) between the gate dielectric and the replacement gate 190. The work function setting layer may be a work function metal (WFM). The replacement gate 190 and the WFM may be formed by any suitable process or any suitable combination of processes, including but not limited to atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, plating, evaporation, ion beam deposition, electron beam deposition, laser assisted deposition, chemical solution deposition, and the like.

[0066] The replacement gate structure can be formed by initially forming a gate dielectric layer between gate spacers around the nonlinear channel 110 and on the top surface of the isolation region. The replacement gate structure can also be formed by subsequently forming a gate conductor layer on the gate dielectric layer. The gate conductor layer and the gate dielectric layer can be patterned using photolithography and etching processes to remove undesired portions and retain one or more desired portions, respectively. The one or more retained desired portions of the gate conductor layer and the gate dielectric layer can form a replacement gate dielectric layer and a replacement gate 190, respectively. CMP, an etching process, or another subtractive removal technique can remove the undesired portions of the replacement gate structure so that the top surface of the replacement gate structure is coplanar with the top surfaces of the gate spacers 180, the interlayer dielectric 195, etc. In some implementations, the replacement gate 190 can be recessed below the top surface of the semiconductor device 100, and a dielectric gate cap (not shown) can be formed on the recessed replacement gate 190.

[0067] For clarity, to achieve the intended finFET functionality, the replacement gate 190 electric field of the semiconductor device 100 generally controls the nonlinear channel 110, and the drain (e.g., one of the S / D regions 150) electric field has a smaller effect on the nonlinear channel 110. The nonlinear channel 110 includes one or more sidewalls that are curved, bent, segmented, etc., defining a nonlinear channel or fin width 181. As depicted, the nonlinear channel or fin width 181 can be constant over a channel or fin length 185 beneath the replacement gate 190. The nonlinearity of the nonlinear channel 110 results in a relative increase in the channel or fin length 185 compared to a linear fin having the same fin width. Consequently, the channel or fin length 185 of the nonlinear channel 110 can be relatively increased within the confines of the replacement gate 190 footprint (e.g., gate length (Lg) 183 multiplied by the gate width). In other words, short channel effects may be limited due to the reduced electric field along the nonlinear channel 110 , which is caused by the relatively increased channel or fin length 185 within the footprint of the replacement gate 190 .

[0068] Figure 10A method 200 of fabricating a semiconductor device 100 including a nonlinear channel 110 according to an embodiment of the present invention is depicted. The method 200 begins at block 202 by forming one or more fin mandrels 104 and one or more SIT spacers 106 on a substrate 102. The method 200 continues at block 204 by removing the one or more fin mandrels 104, patterning a fin including nonlinear sidewalls to effectively form the nonlinear channel 110, and forming an isolation region 112. At block 206, the method 200 continues by removing the one or more SIT spacers 106, forming one or more sacrificial gate structures, and forming gate spacers 108 on the sidewalls of the corresponding one or more sacrificial gate structures.

[0069] The method 200 continues at block 208 by recessing one or more portions of the one or more fins not protected by the sacrificial gate structure and / or not protected by the gate spacers 108. The method 200 continues at block 210 by forming respective S / D regions 150 on or in physical contact with opposing end surfaces of the one or more non-linear channels 110. The method 200 may continue by removing the sacrificial gate structure between the gate spacers 108, forming a replacement gate structure around the non-linear channels 110 and between the gate spacers 108, and forming an interlayer dielectric 195.

[0070] Now refer to Figure 11 , which depicts a cross-sectional view and a top-down view of a semiconductor device 300 including a nonlinear channel 310 according to an embodiment of the present disclosure. The semiconductor device 300 may further include a semiconductor substrate 302, one or more isolation regions 312, one or more source / drain (S / D) 350 (e.g., at Figure 12 ), one or more replacement gates 390 (e.g., in Figure 12 and Figure 13 ), one or more gate spacers 380 (e.g., in Figure 12 ) and one or more interlayer dielectrics 395 (e.g., in Figure 12 (depicted in).

[0071] The non-linear channel 310 may include one or more sidewalls that are generally arcuate, curved, segmented, etc., forming the non-linear channel and defining the fin width 181 and the channel length 185, such as Figure 14 , specifically, as shown, the nonlinear channel 310 can include curved or curved sidewalls that define a fin or channel width 181. Relative to channels that include linear sidewalls (i.e., sidewalls parallel to the X-plane, as depicted) of a typical fin, the nonlinear channel typically has a longer fin or channel length 185. Thus, the channel length 185 of the nonlinear channel 310 can be within the confines of the replacement gate footprint (e.g., within the Figure 14183 of the replacement gate 390 is relatively increased. In other words, the channel length 185 of the nonlinear channel 310 can be relatively increased without increasing the gate length (Lg) 183 of the replacement gate 390. Although shown as having curved or bent sidewalls, the nonlinear channel 310 can include V-shaped sidewalls, hexagonal sidewalls, etc. that define the fin or channel width 181 and the fin or channel length 185.

[0072] Figure 11 A top view and a cross-sectional view of a semiconductor device 300 including a nonlinear channel 310 after a fabrication process according to an embodiment of the present disclosure are shown. At this fabrication stage, one or more fin mandrels 304 may be formed over a semiconductor substrate 302, nonlinear channels 310 may be formed on one or more sidewalls of the one or more fin mandrels 304, the one or more nonlinear channels 310 may be patterned, and one or more isolation regions 320 may be formed.

[0073] The semiconductor substrate 302 includes one or more semiconductor materials and / or structures that are the same or similar to the semiconductor substrate 102. One or more fin mandrels 304 include, but are not necessarily limited to, amorphous silicon (a-Si), amorphous carbon, polycrystalline silicon, polycrystalline silicon germanium, amorphous silicon germanium, polycrystalline germanium, and / or amorphous germanium formed on the substrate 302. In one embodiment, the one or more fin mandrels 304 are formed by depositing or epitaxially growing one or more suitable materials as an overlying core layer on the substrate 302, depositing a mandrel mask layer (not shown) on the overlying core layer, and patterning the mandrel mask layer and the underlying overlying core layer using photolithography and etching techniques. Portions of the blanket mandrel layer and the mandrel hardmask layer are removed while desired portions of the blanket mandrel layer and the mandrel hardmask layer remain, thereby forming one or more fin mandrels 304 having hardmask portions 307 thereon, as depicted.

[0074] One or more fin mandrels 304 may be spaced apart from one another. In an example, the fin mandrel 304 may be cylindrical and have a circular sidewall having a Figure 11 In this example, the nonlinear channel 310 fabricated in association therewith may also have circular sidewalls defining the fin width 181. In another example, as depicted, each fin core axis 304 may be an oblong elliptical cylinder having curved sidewalls with a radius located at Figure 11 In this example, the nonlinear channel 310 fabricated in association therewith may also have elliptical curved sidewalls defining the fin width 181. In another example, each fin core axis 304 may be a diamond cylinder and have a relative Figure 11In this example, the nonlinear channel 310 fabricated in association therewith may also have a V-shaped segmented sidewall defining the fin width 181. In another example, each fin mandrel 304 may be a polygonal cylinder (e.g., a hexagonal cylinder, etc.) having a central bisector axis that enters and exits the fin mandrel. Figure 11 1 and has associated segmented sidewalls. In this example, the nonlinear channel 310 fabricated in association therewith may also have polygonal segmented sidewalls defining the fin width 181.

[0075] After forming the fin mandrels 304 using the fin mandrels 304 and / or the hard mask portion 307 as a mask, exposed portions of the semiconductor substrate 302 not covered by the one or more fin mandrels 304 and the hard mask portion 307 are removed to a specific depth D1 (depending on the design) using a substrate etch. The substrate etch transfers the pattern of the fin mandrels 304 and the hard mask portion 307 to the semiconductor substrate 302. According to an embodiment, the semiconductor substrate 302 including a semiconductor material such as Si, SiGe, SiC, Si:C, SiGeC, SiGe:C, III-V, II-V compound semiconductors, or other similar semiconductors can be selectively etched relative to the hard mask portion 307 and the fin mandrels 304 using, for example, a silicon RIE process.

[0076] After the hard mask portion 307 and the fin mandrel 304 are formed, an isolation region 312 (e.g., a shallow trench isolation (STI) region) may be formed. After selectively removing a portion of the semiconductor substrate 302 to a depth D1, a plurality of trenches or patterns are formed in the semiconductor substrate 302 by, for example, a wet or dry etching process. Dielectric materials, including but not necessarily limited to SiO, are deposited in the trenches or patterns. x , LTO, HTO, flowable oxide (FOX), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), or some other dielectric. The dielectric material may be deposited using deposition techniques including, but not necessarily limited to, CVD, plasma-enhanced CVD, PECVD, RFCVD, PVD, ALD, MLD, MBD, PLD, LSMCD, and / or sputtering to define isolation region 312. As depicted, the top surface of isolation region 312 may be coplanar with the top surface of substrate 302.

[0077] One or more nonlinear channels 310 may be formed by epitaxially growing a semiconductor material (e.g., silicon, silicon germanium, etc.) from one or more sidewalls of one or more fin mandrels 304. In some embodiments, the epitaxial growth and / or deposition process may be selectively formed on semiconductor surfaces and may not deposit material on dielectric surfaces, such as silicon dioxide or silicon nitride surfaces. For example, the epitaxially grown semiconductor material may grow from exposed sidewalls of the fin mandrels 104, but not from exposed surfaces of the isolation regions 312, from exposed surfaces of the hard mask portion 307, etc.

[0078] Although the embodiments of the present disclosure describe the nonlinear channels 310 as fins, the embodiments are not necessarily limited to fin channels and may include nanowire channels, etc. In addition, although a limited number of nonlinear channels 310 are shown in the figure for ease of explanation, more or fewer nonlinear channels 310 may be formed.

[0079] In an example, one or more fin mandrels 304 and corresponding one or more nonlinear channels 310 formed therearound can be patterned. For example, as depicted in the top view, a first portion of the fin mandrel 304 and corresponding one or more nonlinear channels 310 formed therearound can be removed, while a second portion of the fin mandrel 304 and corresponding one or more nonlinear channels 310 formed therearound can be retained. The plurality of fin mandrels 304 and corresponding one or more nonlinear channels 310 formed therearound can be patterned using photolithography and etching processes to remove undesirable portions and retain one or more desired portions, respectively. Subsequently, the one or more fin mandrels 304 and corresponding multiple hard mask portions 307 can be removed, while the one or more nonlinear channels 310 formed therearound can be retained on the top surface of the plurality of isolation regions 312.

[0080] In subsequent manufacturing stages, one or more sacrificial gate structures may be formed. One or more sacrificial gate structures may be formed on and around the one or more nonlinear channels 310, on the substrate 302, and on the isolation region 312. The sacrificial gate structure may include a gate liner (not shown), a sacrificial gate (not shown), and a sacrificial gate cap (not shown). The sacrificial gate structure may be formed by initially forming a gate liner layer (e.g., a dielectric, an oxide, etc.) on the isolation region 312, on the semiconductor substrate 302, and on and around the one or more nonlinear channels 310. For example, the gate liner layer may be deposited on the upper surface of the isolation region 312, the upper surface of the semiconductor substrate 302, the sidewalls of the one or more nonlinear channels 310, the upper surface of the one or more nonlinear channels 310, etc. The sacrificial gate structure may also be formed by subsequently forming a sacrificial gate layer (e.g., a dielectric, amorphous silicon, etc.) on the gate liner. The thickness of the sacrificial gate layer may be greater than the height of the one or more nonlinear channels 310.

[0081] A sacrificial gate structure can be further formed by subsequently forming a gate cap layer on the sacrificial gate layer. The gate cap layer can be formed by depositing a mask material, such as a hard mask material. The gate cap layer can be composed of one or more layers of mask material to protect the sacrificial gate layer and / or other underlying materials during subsequent processing of the device 300. The gate cap layer can be formed of a gate mask material, such as silicon nitride, silicon oxide, combinations thereof, and the like.

[0082] The gate cap layer, the sacrificial gate layer, and the gate liner can be patterned using photolithography and etching processes to remove undesirable portions and retain one or more desired portions, respectively. The retained desired portions of the gate cap layer, the sacrificial gate layer, and the gate liner layer can form the gate liner, the sacrificial gate, and the sacrificial gate cap of each of the one or more sacrificial gate structures, respectively.

[0083] Each sacrificial gate structure can be formed on a target region or area of ​​semiconductor device 300 to define the length of one or more transistors and provide sacrificial material to produce one or more target transistor structures in subsequent processing. According to an example, each sacrificial gate structure can have a height between about 50 nm and about 200 nm and a length between about 15 nm and about 200 nm.

[0084] In another stage, one or more gate spacers 380 are formed, such as Figure 12 As shown in . One or more gate spacers 380 can be formed on at least the corresponding side surfaces of the one or more sacrificial gate structures, on and around the one or more exposed portions of the nonlinear channel 310, on the semiconductor substrate 302, and on the isolation region 312. One or more gate spacers 380 can also be formed on one or more end surfaces of the associated one or more sacrificial gate structures. One or more gate spacers 380 can be formed by conformal deposition of a dielectric material (e.g., silicon nitride, SiBCN, SiNC, SiN, SiCO, SiNOC, or a combination thereof). One or more undesirable portions of the dielectric material can be removed by an anisotropic etching process. One or more desired portions of the dielectric material can be retained on multiple sidewalls of the one or more sacrificial gate structures.

[0085] At another manufacturing stage, one or more portions of the nonlinear channel 310 not covered by the one or more gate spacers 380 can be recessed or otherwise removed. These portions of the nonlinear channel 310 can be recessed by, for example, directional etching to remove portions of the one or more nonlinear channels 310 not covered by the one or more gate spacers 380. The top surface of the isolation region 312 can serve as an etch stop, and the one or more gate spacers 380 can remain. Subsequently, the corresponding end surfaces of the nonlinear channel 110 can be coplanar with the outer side surfaces of the gate spacers 380. The trimming or removal of one or more portions of the one or more nonlinear channels 310 can form one or more source / drain (S / D) openings. The one or more S / D openings can be defined or bounded by the top surface of the isolation region 312 and at least one or more opposing and facing end surfaces of adjacent nonlinear channels 310. The one or more S / D openings can be further defined or bounded by opposing and facing corresponding portions of the side surfaces of the gate spacers 380.

[0086] Figure 12 Depicted are top and cross-sectional views of a semiconductor device 300 including a nonlinear channel 310 after a fabrication process according to an embodiment of the present disclosure. Figure 13 A top view and a cross-sectional view of a semiconductor device 300 including a nonlinear channel 310 after the manufacturing process are depicted according to an embodiment of the present disclosure. At the current manufacturing stage, S / D regions 350 are formed in one or more S / D openings, an interlayer dielectric 395 is formed on the isolation region 312 and on the S / D regions 350, and the sacrificial gate is removed and replaced by a replacement gate 390.

[0087] The S / D regions 350 can be formed by epitaxially growing source / drain regions in the S / D openings, for example, from exposed one or more end surfaces of the one or more nonlinear channels 310. In some embodiments, the S / D regions 350 are formed by in-situ doping epitaxial growth. In some embodiments, the epitaxial growth and / or deposition process can selectively form on semiconductor surfaces and may not deposit material on dielectric surfaces, such as silicon dioxide or silicon nitride surfaces.

[0088] Suitable n-type dopants include, but are not limited to, phosphorus (P), and suitable p-type dopants include, but are not limited to, boron (B). The use of an in-situ doping process is merely one example. For example, a non-in-situ process may alternatively be employed to introduce dopants into the source and drain. Other doping techniques may be used to incorporate dopants into the bottom source / drain region. Doping techniques include, but are not limited to, ion implantation, vapor phase doping, plasma immersion ion implantation, cluster doping, injection doping, liquid phase doping, solid phase doping, in-situ epitaxial growth, or any suitable combination of these techniques. In a preferred embodiment, the S / D epitaxial growth conditions promote in-situ boron doping of SiGe for p-type transistors and phosphorus or arsenic doping of silicon or Si:C for n-type transistors. The doping concentration of the S / D region 350 may be between 1×1019 cm-3 and 2×1021 cm-3, or preferably between 2×1020 cm-3 and 7×1020 cm-3.

[0089] In some implementations, the S / D region 350 may be grown such that the bottom surface contacts the isolation region 312 and the upper surface of the S / D region 350 is higher than the upper surface of the nonlinear channel 310. Figure 12 As shown in the X-sectional view of FIG, the first S / D region 350 can be the source region of the nonlinear channel 310, and the second S / D region 350 can be the drain region of the nonlinear channel 310. For clarity, two different S / D regions 350 grown from different nonlinear channels 310 can effectively merge and form a single S / D region 350, which can serve as the source or drain of the different nonlinear channels 310.

[0090] In another manufacturing stage, an interlayer dielectric 395 is formed over the isolation region 312 and the S / D region 350 , the sacrificial gate is removed, and a replacement gate 390 is formed in its place.

[0091] An interlayer dielectric 395 may be formed on one or more S / D regions 350 and on the top surface of the isolation region 312. The interlayer dielectric 395 may be formed by depositing a dielectric material such as silicon oxide, silicon nitride, SiBCN, SiNC, SiN, SiCO, SiNOC, or a combination thereof as a blanket layer on the isolation region 312, the S / D region 350, and the gate spacer 380. In an embodiment, the interlayer dielectric 395 may be formed to a thickness above the top surface of the semiconductor device 300 and then planarized by chemical mechanical polishing (CMP) or etching such that the top surface of the sacrificial gate is exposed (e.g., the sacrificial gate cap is removed by CMP) and is coplanar with the top surface of the sacrificial interlayer dielectric 395 and the top surface of the gate spacer 380.

[0092] The sacrificial gate is removed by etching while a portion of the sacrificial gate is exposed. Removal of the sacrificial gate may expose the nonlinear channel 310 between the gate spacers 380 previously associated therewith, may expose the gate dielectric thereunder, and the like.

[0093] A replacement gate structure is then formed between the gate spacers 380 and over and around the nonlinear channel 310 to replace the removed sacrificial gate. The replacement gate structure may include a gate dielectric (not shown) and a replacement gate 390. The gate dielectric is the gate dielectric associated with the replacement gate structure, or if removed, a subsequent gate dielectric that may include any suitable dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, high-k material, or any combination of these materials. The gate dielectric may be formed by any suitable deposition process, etc. In some embodiments, the gate dielectric has a thickness ranging from 1 nm to 5 nm, although lesser and greater thicknesses are also contemplated.

[0094] The replacement gate 390 may include any suitable conductive material, including but not limited to doped polycrystalline or amorphous silicon, germanium, silicon germanium, metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), hafnium (Hf), zirconium (Zr), cobalt (Co), nickel (Ni), copper (Cu), aluminum (Al), platinum (Pt), tin (Sn), silver (Ag), gold (Au), conductive metal compound materials (e.g., tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaC), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tungsten silicide (WSi), tungsten nitride (WN), ruthenium oxide (RuO2), cobalt silicide (CoSi), nickel silicide (NiSi)), transition metal aluminides (e.g., Ti3Al, ZrAl), TaC, TaMgC), carbon nanotubes, conductive carbon, graphene, or any suitable combination of these materials.

[0095] The replacement gate 390 may also include dopants incorporated during or after deposition. In some embodiments, the replacement gate 390 may also include a work function setting layer (not shown) between the gate dielectric and the replacement gate 390. The work function setting layer may be a work function metal (WFM). The replacement gate 390 and the WFM may be formed by any suitable process or any suitable combination of processes, including but not limited to atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, plating, evaporation, ion beam deposition, electron beam deposition, laser assisted deposition, chemical solution deposition, and the like.

[0096] The replacement gate structure can be formed by initially forming a gate dielectric layer between gate spacers around the nonlinear channel 310 and on the top surface of the isolation region 312. The replacement gate structure can also be formed by subsequently forming a gate conductor layer on the gate dielectric layer. The gate conductor layer and the gate dielectric layer can be patterned using photolithography and etching processes to remove undesirable portions and retain one or more desired portions, respectively. The retained desired portions of the gate conductor layer and the gate dielectric layer can form a replacement gate dielectric layer and a replacement gate 390, respectively. CMP, an etching process, or another subtractive removal technique can remove the undesirable portions of the replacement gate structure so that the top surface of the replacement gate structure is coplanar with the top surfaces of the gate spacers 380, the interlayer dielectric 395, etc. In some embodiments, the replacement gate 390 can be recessed below the top surface of the semiconductor device 300, and a dielectric gate cap (not shown) can be formed on the recessed replacement gate 390.

[0097] For the sake of clarity, Figure 13 As depicted in the cross-sectional view of FIG, nonlinear channel 310 can be formed above isolation region 312, and a replacement gate structure can be formed on the semiconductor substrate below and directly adjacent to the footprint of nonlinear channel 310. Furthermore, side surface 381 of nonlinear channel 310 can be coplanar with an opposing side surface 383 of substrate 302. Typically, surface 381 is an opposing surface relative to surface 383.

[0098] For further clarity, to achieve desired finFET functionality, the replacement gate 390 electric field of the semiconductor device 300 generally controls the nonlinear channel 310, and the drain (e.g., one of the S / D regions 350) electric field has less influence on the nonlinear channel 310. The nonlinear channel 310 includes one or more sidewalls that are curved, bent, segmented, etc., which define a nonlinear fin or channel width 181 and a fin or channel length 185. As depicted, the nonlinear fin or channel width 181 can be constant over the fin or channel length 185 beneath the replacement gate 390. The nonlinearity of the nonlinear channel 310 results in a relatively increased channel or fin length 185 compared to a linear fin having the same fin width. Consequently, the channel or fin length 185 of the nonlinear channel 310 can be relatively increased within the confines of the footprint of the replacement gate 390. In other words, short channel effects may be limited due to the reduced electric field along the nonlinear channel 310 , which is caused by the relatively increased channel or fin length 185 within the footprint of the replacement gate 390 .

[0099] Figure 14A method 400 of fabricating a semiconductor device 300 including a nonlinear channel 310 according to an embodiment of the present disclosure is depicted. The method 400 begins at block 402 by forming one or more fin mandrels 304 on a substrate 302, patterning or opening portions of the underlying semiconductor substrate 302, and forming isolation regions 312 within the patterns or openings within the semiconductor substrate 302.

[0100] The method 400 continues at block 404 by forming a nonlinear fin (thereby forming a nonlinear channel 310) on one or more sidewalls of the one or more fin mandrels 304 to form the one or more nonlinear channels 310. In an example, one or more of the nonlinear channels 310 may be patterned. The method 400 continues at block 406 by removing the one or more fin mandrels 304, forming one or more sacrificial gate structures, and forming gate spacers 308 on the sidewalls of the corresponding one or more sacrificial gate structures.

[0101] The method 400 continues at block 408 by recessing one or more portions of the nonlinear channel 310 that are not protected by the sacrificial gate structure and / or not protected by the gate spacers 308. The method 400 continues at block 410 by forming respective S / D regions 350 on or in physical contact with opposing end surfaces of the one or more nonlinear channels 310. The method 400 may continue by removing the sacrificial gate structure between the gate spacers 308, forming a replacement gate structure around the nonlinear channel 310 and between the gate spacers 308, and forming an interlayer dielectric 395.

[0102] The description of various embodiments of the present disclosure has been presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications, or improvements over existing technologies in the market, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A finFET comprising: A nonlinear channel is formed below the gate, the nonlinear channel including a first nonlinear sidewall. 2 . The finFET of claim 1 , wherein the nonlinear channel comprises a second nonlinear sidewall opposite the first nonlinear sidewall. 3 . The finFET of claim 2 , wherein the first nonlinear sidewall is a first curved nonlinear sidewall. 4 . The finFET of claim 3 , wherein the second nonlinear sidewall is a second curved nonlinear sidewall. 5 . The finFET of claim 4 , wherein the first curved nonlinear sidewall and the second curved nonlinear sidewall are parallel. 6 . The finFET of claim 4 , wherein the first curved nonlinear sidewall and the second curved nonlinear sidewall share a same central axis of curvature. 7 . The finFET of claim 1 , wherein the finFET further comprises a source in physical contact with a first end surface of the nonlinear channel and a drain in physical contact with an opposing second end surface of the nonlinear channel.

8. The finFET of claim 7, wherein the finFET further comprises a gate spacer around the gate.

9. The finFET of claim 1, wherein a channel length of the nonlinear channel is greater than a gate length of the gate.

10. A finFET comprising: a first nonlinear channel below the gate; a second nonlinear channel below the gate; a source electrode in physical contact with respective end surfaces of the first nonlinear channel and the second nonlinear channel; as well as A drain is in physical contact with respective opposite end surfaces of the first nonlinear channel and the second nonlinear channel. 11 . The finFET of claim 10 , wherein the first nonlinear channel comprises a first nonlinear sidewall and a second nonlinear sidewall opposite the first nonlinear sidewall.

12. The finFET of claim 11, wherein the first nonlinear sidewall is a first curved sidewall and the second nonlinear sidewall is a second curved sidewall.

13. The finFET of claim 12, wherein the second nonlinear channel comprises a third nonlinear sidewall and a fourth nonlinear sidewall opposite the third nonlinear sidewall.

14. The finFET of claim 13, wherein the third nonlinear sidewall is a third curved sidewall and the fourth nonlinear sidewall is a fourth curved sidewall.

15. The finFET of claim 14, wherein the first curved sidewall is parallel to the second curved sidewall, and wherein the third curved sidewall is parallel to the fourth curved sidewall.

16. The finFET of claim 15, wherein the first curved sidewall, the second curved sidewall, the third curved sidewall, and the fourth curved sidewall share a same central axis of curvature.

17. The finFET of claim 16 further comprising a gate spacer surrounding the gate.

18. The finFET of claim 10, wherein a channel length of the first nonlinear channel is greater than a gate length of the gate. The finFET of claim 18 , wherein the second nonlinear channel has a channel length greater than the gate length.

20. A method for manufacturing a finFET, comprising: forming a nonlinear fin over a semiconductor substrate; forming a sacrificial gate over the nonlinear fin; forming gate spacers on respective sidewalls of the sacrificial gate; forming a source electrode in physical contact with the first end surface of the nonlinear fin; forming a drain electrode in physical contact with the second end surface of the nonlinear fin; removing the sacrificial gate between the gate spacers; as well as forming a replacement gate between the gate spacers, The nonlinear fin is a nonlinear channel for the finFET, and wherein a channel length of the nonlinear channel is greater than a length of the replacement gate.

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