Signal monitoring device, signal monitoring method, electronic equipment and storage medium

Abstract

The invention discloses a signal monitoring device, a signal monitoring method, electronic equipment and a storage medium. The signal monitoring device comprises a monitoring module which is configured to obtain a pulse width threshold value, receive a monitored signal and perform burr monitoring on the monitored signal based on the pulse width threshold value, and the monitoring module comprises an edge monitoring sub-module and a burr judgment sub-module, the edge monitoring sub-module is configured to record the occurrence time of each level flipping of a monitored signal and send the occurrence time of each level flipping to the burr judgment sub-module; and the burr judgment sub-module is configured to determine whether the monitored signal generates burrs or not based on the relationship between the difference between the occurrence moments of two adjacent level flipping of the monitored signal and the pulse width threshold. According to the signal monitoring device, the flexibility of burr monitoring on the monitored signal can be improved, an additional sampling clock is not needed, and the circuit cost and power consumption can be effectively reduced.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a signal monitoring device, a signal monitoring method, an electronic device, and a storage medium. Background Art

[0002] In logic circuits, a signal glitch is a brief, unexpected spike or oscillation that occurs during a signal transition. A glitch can be mistakenly identified as a valid signal, causing errors in the logic circuit's output. For example, in a counter circuit, a glitch on the clock signal can cause the counter to count incorrectly, disrupting the entire system. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a signal monitoring device, comprising: a monitoring module, configured to obtain a pulse width threshold and receive a monitored signal, and perform glitch monitoring on the monitored signal based on the pulse width threshold, wherein the monitoring module includes an edge monitoring submodule and a glitch determination submodule, the edge monitoring submodule being configured to record the occurrence time of each level flip of the monitored signal and send the occurrence time of each level flip to the glitch determination submodule; the glitch determination submodule being configured to determine whether the monitored signal has generated a glitch based on the relationship between the difference between the occurrence times of two adjacent level flips of the monitored signal and the pulse width threshold.

[0004] For example, in the signal monitoring device provided by at least one embodiment of the present disclosure, the glitch determination submodule determines whether the monitored signal has generated a glitch based on the relationship between the difference between the occurrence moments of two adjacent level flips of the monitored signal and the pulse width threshold, including: in response to the difference between the occurrence moments of two adjacent level flips of the monitored signal being less than the pulse width threshold, determining that the monitored signal has generated a glitch; in response to the difference between the occurrence moments of two adjacent level flips of the monitored signal being greater than or equal to the pulse width threshold, determining that the monitored signal has not generated a glitch.

[0005] For example, in the signal monitoring device provided in at least one embodiment of the present disclosure, the monitored signal includes a fault alarm signal, which is used to report a fault or abnormal condition in the monitored circuit. The signal monitoring device also includes: an identification module coupled to the monitoring module, and the monitoring module is also configured to send a signal segment in the fault alarm signal from the nearest edge before the burr to the nearest edge after the burr to the identification module in response to determining that the fault alarm signal has generated a burr; the identification module is configured to obtain configuration information of the error type and identify the error type of the signal segment based on the configuration information of the error type.

[0006] For example, in the signal monitoring device provided in at least one embodiment of the present disclosure, the identification module includes a mapping submodule, a generation submodule and a matching submodule, the mapping submodule is configured to map the signal segment to a first pattern in units of clock cycles, wherein the glitch in the signal segment is mapped to a first value in the first pattern, and multiple data corresponding to multiple clock cycles in the signal segment except the glitch are mapped to multiple second values ​​in the first pattern, the generation submodule is configured to generate multiple second patterns based on the configuration information of the error type, wherein each of the multiple second patterns is different, and each second pattern specifies a first range of the number of second values ​​before the first value and a second range of the number of second values ​​after the first value, and the matching submodule is configured to determine a target pattern that matches the first pattern from the multiple second patterns, and determine and output the error type of the signal segment based on the target pattern.

[0007] For example, in the signal monitoring device provided in at least one embodiment of the present disclosure, the matching submodule executes determining a target pattern that matches the first pattern from the multiple second patterns, including: in response to a first number of second values ​​before the first value in the first pattern falling within a first range of the target pattern, and a second number of second values ​​after the first value in the first pattern falling within a second range of the target pattern, determining that the first pattern matches the target pattern.

[0008] For example, in the signal monitoring device provided by at least one embodiment of the present disclosure, the number of the second patterns is equal to the square of the number of the error types.

[0009] For example, in the signal monitoring device provided in at least one embodiment of the present disclosure, the error type includes at least one of a cyclic redundancy check error and a parity check error.

[0010] For example, the signal monitoring device provided in at least one embodiment of the present disclosure further includes an alarm module coupled to the monitoring module, and the alarm module is configured to issue an alarm for glitches generated by the monitored signal.

[0011] For example, in the signal monitoring device provided by at least one embodiment of the present disclosure, the monitoring module is further configured to, in response to determining that the monitored signal generates a glitch, send glitch information of the glitch to the alarm module, the alarm module includes an acquisition submodule, an alarm submodule and a feedback submodule, the acquisition submodule is configured to acquire configuration information of the alarm, and in response to determining that the alarm is needed according to the configuration information of the alarm, send the glitch information to the alarm submodule, the configuration information of the alarm includes at least one of whether the alarm is needed after the glitch is monitored and how to alarm, the alarm submodule is configured to generate alarm information according to the glitch information, and send the alarm information to the feedback submodule, and the feedback submodule is configured to output the alarm information according to the configuration information of the alarm.

[0012] For example, the signal monitoring device provided by at least one embodiment of the present disclosure further comprises a glitch broadening module coupled with the monitoring module, and the glitch broadening module is configured to, in response to the monitored signal generating a glitch, perform broadening processing on a pulse of the glitch, so that the broadened glitch can be detected by a sampling edge of a clock signal of an external circuit of the signal monitoring device.

[0013] For example, in the signal monitoring device provided by at least one embodiment of the present disclosure, the monitoring module is further configured to, in response to determining that the monitored signal generates a glitch, send glitch information of the glitch to the glitch broadening module, the glitch broadening module includes an information saving submodule and a glitch broadening submodule, the information saving submodule is configured to acquire configuration information of glitch broadening, and in response to receiving the glitch information, send the configuration information of glitch broadening to the glitch broadening submodule, and the glitch broadening submodule is configured to perform broadening processing on a pulse width of the glitch according to the configuration information of glitch broadening, so that the pulse width of the broadened glitch reaches a target pulse width set in the configuration information of glitch broadening.

[0014] For example, in the signal monitoring device provided by at least one embodiment of the present disclosure, the glitch broadening submodule includes an AND gate, an OR gate, a first D flip-flop and a second D flip-flop, a first end of the AND gate receives a first signal, a second end of the AND gate is connected with a third end of the OR gate, a first output end of the AND gate is connected with a first input end of the first D flip-flop, the third end of the OR gate receives the monitored signal, a fourth end of the OR gate receives a clock signal, a second output end of the OR gate is connected with a first clock end of the first D flip-flop, a third output end of the first D flip-flop is connected with a second input end of the second D flip-flop, a second clock end of the second D flip-flop is connected with the fourth end of the OR gate to receive the clock signal, and a fourth output end of the second D flip-flop outputs a monitored signal after the glitch is broadened.

[0015] For example, the signal monitoring device provided by at least one embodiment of the present disclosure also includes a configuration module coupled to the monitoring module, wherein the configuration module includes a configuration entry and a first configuration sub-module, and the configuration entry is configured to send the setting information provided by the user to the first configuration sub-module; the first configuration sub-module is configured to parse the setting information to obtain a pulse width threshold, and send the pulse width threshold to the monitoring module.

[0016] For example, in the signal monitoring device provided in at least one embodiment of the present disclosure, the setting information further includes at least one of error type configuration information, alarm configuration information, and glitch widening configuration information.

[0017] At least one embodiment of the present disclosure further provides a signal monitoring method, comprising: obtaining a pulse width threshold and receiving a monitored signal; recording the time of occurrence of each level flip of the monitored signal; and determining whether the monitored signal has generated a glitch based on the relationship between the difference between the time of occurrence of two adjacent level flips of the monitored signal and the pulse width threshold.

[0018] For example, in the signal monitoring method provided in at least one embodiment of the present disclosure, determining whether the monitored signal has generated a glitch based on the relationship between the difference between the occurrence moments of two adjacent level flips of the monitored signal and the pulse width threshold includes: determining that the monitored signal has generated a glitch in response to the difference between the occurrence moments of two adjacent level flips of the monitored signal being less than the pulse width threshold; and determining that the monitored signal has not generated a glitch in response to the difference between the occurrence moments of two adjacent level flips of the monitored signal being greater than or equal to the pulse width threshold.

[0019] For example, in the signal monitoring method provided in at least one embodiment of the present disclosure, the monitored signal includes a fault alarm signal, which is used to report a fault or abnormal condition in the monitored circuit. The signal monitoring method further includes: in response to determining that the fault alarm signal generates a burr, obtaining a signal segment in the fault alarm signal from the nearest edge before the burr to the nearest edge after the burr; obtaining configuration information of the error type; and identifying the error type of the signal segment based on the configuration information of the error type.

[0020] For example, in the signal monitoring method provided in at least one embodiment of the present disclosure, the error type of the signal segment is identified based on the configuration information of the error type, including: mapping the signal segment to a first style in units of clock cycles, wherein the glitch in the signal segment is mapped to a first value in the first style, and multiple data corresponding to multiple clock cycles other than the glitch in the signal segment are mapped to multiple second values ​​in the first style; generating multiple second styles based on the configuration information of the error type, wherein each of the multiple second styles is different, and each second style specifies a first range of the number of second values ​​before the first value and a second range of the number of second values ​​after the first value; and determining a target style that matches the first style from the multiple second styles, and determining and outputting the error type of the signal segment based on the target style.

[0021] For example, in the signal monitoring method provided in at least one embodiment of the present disclosure, determining a target pattern that matches the first pattern from the multiple second patterns includes: in response to a first number of second values ​​before the first value in the first pattern falling within a first range of the target pattern, and a second number of second values ​​after the first value in the first pattern falling within a second range of the target pattern, determining that the first pattern matches the target pattern.

[0022] For example, the signal monitoring method provided by at least one embodiment of the present disclosure further includes: obtaining alarm configuration information; in response to determining that the monitored signal has generated a burr and determining that an alarm is required based on the alarm configuration information, generating alarm information based on the burr information, the alarm configuration information including at least one of whether an alarm is required after a burr is detected and how to alarm; and outputting the alarm information based on the alarm configuration information.

[0023] For example, the signal monitoring method provided by at least one embodiment of the present disclosure further includes: obtaining configuration information for glitch widening; in response to determining that a glitch is generated in the monitored signal, performing the widening processing on the pulse width of the glitch according to the configuration information for glitch widening, so that the widened glitch can be detected by the sampling edge of the clock signal of the external circuit of the signal monitoring device.

[0024] For example, the signal monitoring method provided by at least one embodiment of the present disclosure also includes: obtaining setting information provided by the user; parsing the setting information to obtain at least one of the pulse width threshold, error type configuration information, alarm configuration information and glitch widening configuration information.

[0025] At least one embodiment of the present disclosure further provides an electronic device, comprising: at least one memory, which non-transiently stores computer-executable instructions; and at least one processor, which is configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the processor, implement the signal monitoring method described in any of the above embodiments.

[0026] At least one embodiment of the present disclosure further provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by at least one processor, the signal monitoring method described in any of the above embodiments is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0028] Figure 1 It is a structural diagram of a burr detection circuit;

[0029] Figure 2 A schematic diagram of a signal monitoring device provided by at least one embodiment of the present disclosure;

[0030] Figure 3 A schematic diagram of another signal monitoring device provided by at least one embodiment of the present disclosure;

[0031] Figure 4A A schematic diagram of another signal monitoring device provided by at least one embodiment of the present disclosure;

[0032] Figure 4B A schematic diagram of a mapping operation provided in at least one embodiment of the present disclosure;

[0033] Figure 4C A schematic diagram of generating multiple second patterns based on configuration information of an error type provided by at least one embodiment of the present disclosure;

[0034] Figure 5 A schematic diagram of another signal monitoring device provided by at least one embodiment of the present disclosure;

[0035] Figure 6A A schematic diagram of another signal monitoring device provided by at least one embodiment of the present disclosure;

[0036] Figure 6B A schematic structural diagram of a burr widening submodule provided in at least one embodiment of the present disclosure;

[0037] Figure 6CA schematic diagram of a widened burr provided in at least one embodiment of the present disclosure;

[0038] Figure 7 A schematic diagram of another signal monitoring device provided by at least one embodiment of the present disclosure;

[0039] Figure 8 A flow chart of a signal monitoring method provided by at least one embodiment of the present disclosure;

[0040] Figure 9 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure; and

[0041] Figure 10 A schematic structural diagram of an electronic device provided in at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0043] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meanings understood by a person of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and similar terms used in this disclosure do not denote any order, quantity, or importance, but are simply used to distinguish different components. Terms such as "include" or "comprising" mean that the element or object preceding the term includes the elements or objects listed after the term, and their equivalents, without excluding other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly. It should be understood that the various steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, method embodiments may include additional steps and / or omit steps shown. The scope of this disclosure is not limited in this respect.

[0044] The present disclosure is described below using several specific embodiments. To maintain clarity and conciseness in the following description of the embodiments of the present disclosure, detailed descriptions of known functions and components may be omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, that component is represented by the same or similar reference numeral in each drawing.

[0045] Chip circuits contain numerous combinational logic circuits. In these circuits, the multiple input signals make simultaneous changes in these signals prone to contention hazards. Contention refers to the time difference between input signal changes along different paths and their transmission to the same gate-level circuit, resulting in unwanted spikes and interference pulses in the circuit's output. Hazards are transient errors in circuit output caused by contention, manifesting as narrow pulses at the output that were not originally designed, often called glitches.

[0046] When designing complex digital circuit systems, it's extremely difficult to predict the contention and hazards present within them, which can compromise proper circuit functionality. As chip circuits grow in size, monitoring, identifying, and addressing glitches caused by these contention and hazards becomes increasingly important.

[0047] Figure 1 This is a schematic diagram of the structure of a glitch detection circuit. Figure 1 As shown, the glitch detection circuit includes a frequency-locked loop circuit and a glitch detector. The frequency-locked loop circuit includes a counting module, an internal oscillator and a frequency-locked loop filter. The glitch detector includes detection logic.

[0048] In the system clock signal CK SYS When detecting the glitch, the internal oscillator of the frequency-locked loop circuit first generates multiple high-frequency clock signals CK with different phases. FAST The high-frequency clock signal CK generated by the internal oscillator FAST The clock cycle is shorter than the system clock signal CK SYS The clock cycle is shorter, so the high-frequency clock signal CK FAST Can be used to control the system clock signal CK SYS For sampling, the high frequency clock signal CK FAST May also be called the sampling clock.

[0049] For example, when the system clock signal CK SYS When the clock signal CK arrives, the counting module starts working and uses the high-frequency clock signal CK FAST As the sampling clock for counting, the high-frequency clock signal CK is recorded by the counter in the counting module FAST Each rising edge (or falling edge) until the system clock signal CK SYSThe counter stops counting when a pulse cycle ends. The value recorded in the counter is the system clock signal CK SYS The high-frequency clock signal CK within one pulse cycle FAST The number of pulses due to the high-frequency clock signal CK FAST The frequency is known, so the value recorded in the counter and the high-frequency clock signal CK can be used to calculate the frequency of the clock. FAST The frequency of the system clock signal CK is calculated SYS Then, the system clock pulse width value is output to the glitch detector. The detection logic in the glitch detector monitors the changes in the system clock pulse width based on this value. When the system clock pulse width is less than the set threshold, it is identified as a glitch.

[0050] The frequency-locked loop filter in the frequency-locked loop circuit can feed back the frequency information of the monitored system clock to the internal oscillator, so that the internal oscillator can adjust the output sampling clock (high-frequency clock signal CK) in a timely manner. FAST ) frequency.

[0051] The inventors of the present disclosure have discovered that by Figure 1 The glitch detection circuit shown has the following disadvantages when performing glitch detection on a signal:

[0052] (1) Glitch detection based on the sampling clock method is difficult to detect glitches with very narrow pulse widths. For example, when a glitch with very narrow pulse width is not at the sampling edge of the sampling clock, it cannot be detected.

[0053] (2) Using multiple sampling clocks to detect the monitored signal, when the monitored signal changes, the sampling clock also needs to change, which has poor compatibility;

[0054] (3) When the glitch threshold changes, the sampling clock also needs to change, which is not flexible enough;

[0055] (4) An oscillator is required in hardware, resulting in high circuit cost;

[0056] (5) The detection method based on sampling clock will lead to increased power consumption.

[0057] In this regard, at least one embodiment of the present disclosure provides a signal monitoring device. Figure 2 A schematic diagram of a signal monitoring device provided in at least one embodiment of the present disclosure.

[0058] like Figure 2 As shown, the signal monitoring device 200 includes a monitoring module 10. The monitoring module 10 is configured to obtain a pulse width threshold (not shown in the figure) and receive a monitored signal, and perform glitch monitoring on the monitored signal based on the pulse width threshold.

[0059] For example, the monitoring module 10 includes a coupled edge monitoring submodule 11 and a glitch determination submodule 12. The edge monitoring submodule 11 is configured to record the time of occurrence of each level flip of the monitored signal and send the time of occurrence of each level flip to the glitch determination submodule 12. The glitch determination submodule 12 is configured to determine whether the monitored signal has generated a glitch based on the relationship between the difference between the time of occurrence of two adjacent level flips of the monitored signal and a pulse width threshold.

[0060] For example, in an embodiment of the present disclosure, a monitored signal refers to a signal that is monitored to determine whether glitches are generated. For example, the monitored signal may be a system clock signal, a data signal, an address signal, a fault alarm signal, or other digital signal that needs to be monitored. The monitored signal includes a pulse, and the pulse has a rising edge and a falling edge. The rising edge corresponds to the process of the pulse changing from a low level to a high level, and the falling edge corresponds to the process of the pulse changing from a high level to a low level. The pulses in the monitored signal may be periodically repeated or may appear randomly and non-periodically, and the embodiments of the present disclosure are not limited to this.

[0061] For example, in the embodiment of the present disclosure, the pulse width threshold may be understood as a threshold for distinguishing a pulse width of a glitch from a normal signal. The pulse width of a glitch is generally smaller than the normal pulse width of the monitored signal.

[0062] For example, in an embodiment of the present disclosure, the monitoring module 10 may obtain the pulse width threshold value of the system default configuration, or may obtain the pulse width threshold value in the setting information provided by the user, thereby improving the flexibility of the configuration.

[0063] For example, Figure 3 Another signal monitoring device 300 provided by at least one embodiment of the present disclosure is shown. Compared with the signal monitoring device 200, the signal monitoring device 300 also includes a configuration module 20 coupled to the monitoring module 10. The configuration module 20 is used to provide a configuration entry (not shown in the figure) to the user so that the user can flexibly change the setting information according to his or her needs.

[0064] For example, the configuration entry is used to obtain user-provided setting information, which may include user-defined parameter values ​​and some configuration information. The configuration entry can be implemented using hardware or software (e.g., an interactive interface for parameter setting). For example, the configuration entry includes but is not limited to the Joint Test Action Group (JTAG) interface or the In-System Programming (ISP) interface in Field Programmable Gate Array (FPGA) development software.

[0065] like Figure 3 As shown, the configuration module 20 may include a first configuration submodule 21. The configuration entry may send user-provided setting information to the first configuration submodule 21. The first configuration submodule 21 is configured to parse the user-provided setting information to obtain a pulse width threshold and send the pulse width threshold to the monitoring module 10. The configuration entry and the first configuration submodule 21 enable flexible configuration of the pulse width threshold.

[0066] For example, in the embodiments of the present disclosure, in addition to setting the pulse width threshold, other parameters such as the pulse amplitude of the glitch, whether the glitch is a high pulse or a low pulse, etc. can also be set. The first configuration submodule 21 can be configured to save some glitch-related parameters configured by the system default or freely set by the user, such as the pulse width threshold, the glitch pulse amplitude, the high or low pulse of the glitch, etc.

[0067] For example, the monitoring module 10 can obtain glitch-related parameters from the first configuration submodule 21 of the configuration module 20. For example, when the user does not set a pulse width threshold, the monitoring module 10 can use the pulse width threshold configured by default in the system; when the user sets a pulse width threshold, the monitoring module 10 preferentially uses the pulse width threshold set by the user.

[0068] For example, the number of monitoring modules 10 can be configured as one or multiple, and multiple monitoring modules 10 can each receive multiple different monitored signals. Accordingly, the number of first configuration submodules 21 in the configuration module 20 can also be configured as multiple, or the first configuration submodule 21 can store multiple pulse width thresholds corresponding to multiple monitored signals, thereby enabling the monitoring module 10 to simultaneously detect multiple monitored signals, improving detection efficiency and compatibility with the monitored signals. For example, glitches in both an address signal and a fault alarm signal used to detect whether an address signal has an error can be detected simultaneously.

[0069] For example, in an embodiment of the present disclosure, the edge monitoring submodule 11 can record the time when a level flip occurs by detecting a rising edge or a falling edge in the monitored signal. Here, a level flip (toggle) can be understood as a pulse switching between a first level and a second level, where one of the first level and the second level is a low level and the other is a high level. For example, the edge monitoring submodule 11 can be configured to detect the time when each level flip occurs in the monitored signal from the moment the monitored signal is received, and send the time when each level flip occurs to the glitch determination submodule 12. The edge monitoring submodule 11 can be implemented in hardware or software. For example, when the edge monitoring submodule 11 is implemented as hardware, it can include logic gate circuits and triggers, etc. The embodiment of the present disclosure does not limit the specific implementation method of the edge monitoring submodule 11.

[0070] For example, in an embodiment of the present disclosure, the glitch determination submodule 12 can calculate the difference between the occurrence times of two adjacent level flips of the monitored signal and compare it with the pulse width threshold to determine whether the monitored signal has generated a glitch. Here, the difference between the occurrence times of two adjacent level flips refers to the difference between the occurrence times of a first level flip from a first level to a second level and the occurrence times of a second level flip from the second level to the first level, wherein the first level flip and the second level flip are adjacent.

[0071] For example, in one embodiment, the occurrence times sent by the edge monitoring submodule 11 to the glitch determination submodule 12 include: the occurrence time t1 of level flip A, the occurrence time t2 of level flip B, the occurrence time t3 of level flip C, and the occurrence time t4 of level flip D, with t4>t3>t2>t1. The glitch determination submodule 12 calculates the difference d1 between t2 and t1 and compares this difference d1 with the pulse width threshold to determine whether the pulse from t1 to t2 is a glitch. It then calculates the difference d2 between t4 and t3 and compares this difference d2 with the pulse width threshold to determine whether the pulse from t3 to t4 is a glitch.

[0072] For example, in an embodiment of the present disclosure, the glitch determination submodule 12 can be configured to, in response to the difference between the occurrence moments of two adjacent level flips of the monitored signal being less than a pulse width threshold, determine that the monitored signal has generated a glitch, that is, determine that the pulse between the two adjacent level flips is a glitch; in response to the difference between the occurrence moments of two adjacent level flips of the monitored signal being greater than or equal to the pulse width threshold, determine that the monitored signal has not generated a glitch, that is, determine that the pulse between the two adjacent level flips is a normal signal, not a glitch.

[0073] For example, if the user sets a pulse width threshold, the glitch determination submodule 12 may compare the difference between the occurrence times of two adjacent level flips of the monitored signal with the user-set pulse width threshold. If the user does not set a pulse width threshold, the glitch determination submodule 12 may compare the difference between the occurrence times of two adjacent level flips of the monitored signal with the system default pulse width threshold. The glitch determination submodule 12 may be implemented in hardware or software. For example, if the glitch determination submodule 12 is implemented in hardware, it may include a subtractor and a comparator. The embodiments of the present disclosure do not limit the specific implementation of the glitch determination submodule 12.

[0074] The signal monitoring device provided by at least one embodiment of the present disclosure monitors whether glitches have occurred by calculating the difference between the occurrence times of two adjacent level flips of the monitored signal and comparing the difference with a pulse width threshold. The device can not only monitor glitches of any pulse width, but also flexibly switch the monitored signal. Furthermore, the pulse width threshold for glitches of the monitored signal is adjustable, and no additional sampling clock is required, thereby effectively reducing circuit cost and power consumption.

[0075] For example, in embodiments of the present disclosure, the monitored signal may be a fault alarm signal. Fault alarm signals are signals used to report faults or abnormal conditions in the monitored circuit, including but not limited to alert_n signals and uvm_error signals. For ease of description, the following detailed description of embodiments of the present disclosure uses the alert_n signal as an example; however, this is not intended to limit the embodiments of the present disclosure.

[0076] For example, the DDR protocol of Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) defines two types of check errors in signal transmission: cyclic redundancy check (CRC) error and parity check (Parity Check) error. When either of these two check errors occurs, the alert_n signal will be pulled low, thereby issuing an alarm.

[0077] For example, a cyclic redundancy check (CRC) is an error-correcting code. During data transmission, the sender calculates a CRC based on the data to be transmitted and a pre-defined generator polynomial. This code is appended to the original data and sent together. The receiver verifies the received data using the same generator polynomial. If the calculated CRC does not match the received CRC, a cyclic redundancy check error occurs, and the alert_n signal is pulled low, indicating that an error may have occurred during data transmission.

[0078] For example, parity checking adds a parity bit to the data to ensure that the number of 1s in the data is odd (odd parity) or even (even parity). After receiving the data, the receiver checks whether the number of 1s in the data meets the requirements according to the agreed parity check method. If it does not meet the requirements, a parity error is generated and the alert_n signal is pulled low, indicating that an error may have occurred during data transmission.

[0079] In the DDR protocol, the pulse widths of alert_n corresponding to cyclic redundancy check errors and parity check errors can both fluctuate within a certain range, but the pulse widths of alert_n corresponding to the two are different.

[0080] The inventors of the present disclosure discovered that for the alert_n signal (or other fault alarm signals with different pulse widths for different error types), the control module used to process the alert_n signal can only determine whether the error is a cyclic redundancy check error or a parity check error based on the alert_n pulse width. Although the control module may detect extreme system instability and trigger a reset process when a large number of errors occur consecutively (with a low probability), if two errors of the same type or two different types occur consecutively, the alert_n pulse width may merge into a long pulse, exceeding the standard pulse width of a single error. In this case, the control module can only identify the error as an unknown error. If the control module identifies the error as an unknown error, it will choose to ignore it or report the error.

[0081] In this regard, at least one embodiment of the present disclosure can, by adding an identification module to the signal monitoring device, identify whether a small number of combinations of errors have occurred continuously while detecting that a glitch has occurred in the lowered alert_n signal, thereby improving the accuracy of error identification. For example, the alert_n signal can be sent to both the above-mentioned control module and the signal monitoring device, and the allowable range of the pulse width of alert_n corresponding to the two errors can be set in advance in the configuration module 20 in the signal monitoring device. The identification module in the signal monitoring device can determine what combination of error types has occurred based on the allowable range of the pulse width of alert_n corresponding to the two errors. For example, the above-mentioned control module is outside the signal monitoring device and can be connected to or not connected to the signal monitoring device. After the identification module identifies what combination of error types has occurred, it can directly report the error, or it can also feed back the identified error type to the control module and report it together with the information of the control module, so that the system can execute the corresponding processing strategy according to the error type.

[0082] Figure 4A A schematic diagram of another signal monitoring device provided by at least one embodiment of the present disclosure. Figure 4A As shown, the signal monitoring device 400 is relative to the signal monitoring device 300 Figure 3 As shown, the signal monitoring device 300 further comprises an identification module 30 coupled with the monitoring module 10, for detecting the error type of the monitored signal (e.g., the fault alarm signal). Here, the monitored signal that can be identified by the identification module 30 is a signal whose pulse width is different when different types of errors occur. For example, the monitored signal can be alert_n, and when a cyclic redundancy check error occurs, the signal pulse width of alert_n is several cycles, and when a parity error occurs, the signal pulse width of alert_n is several tens or hundreds of cycles.

[0083] For example, in one example of an embodiment of the present disclosure, the monitoring module 10 can send the monitored signal to the identification module 30 after determining that the monitored signal generates a glitch, and identify the error type of the monitored signal through the identification module 30. For example, in another example of an embodiment of the present disclosure, the monitoring module 10 can also continuously send the monitored signal to the identification module 30, so that the identification module 30 can more comprehensively and accurately identify the monitored signal. For example, in yet another example of an embodiment of the present disclosure, the monitoring module 10 can also only send the signal segment containing the glitch in the monitored signal to the identification module 30, so as to reduce the calculation amount of the identification module 30. The signal segment may, for example, include the signal between the nearest edge before the glitch and the nearest edge after the glitch.

[0084] For example, the identification module 30 is configured to obtain configuration information of the error type, and identify the error type of the signal segment based on the configuration information of the error type. Here, the error type can include at least one of a cyclic redundancy check error and a parity error, and the configuration information of the error type may, for example, include the minimum pulse width and the maximum pulse width of the alert_n signal corresponding to the cyclic redundancy check error, and the minimum pulse width and the maximum pulse width of the alert_n signal corresponding to the parity error. For example, if the identified error does not belong to any error set in the configuration information, it can be considered as an unknown error (e.g., the unknown error can be selected to be ignored or reported).

[0085] For example, in an embodiment of the present disclosure, the identification module 30 can obtain the configuration information of the error type configured by the system by default, or obtain the configuration information of the error type in the setting information provided by the user, so as to improve the flexibility of identification.

[0086] For example, in one example of an embodiment of the present disclosure, as shown in Figure 4AAs shown, the configuration module 20 in the signal monitoring device 400 may further include a second configuration submodule 22, which is configured to store configuration information of the error type configured by the system default or freely set by the user. For example, the identification module 30 is coupled to the second configuration submodule 22 of the configuration module 20, and the identification module 30 may obtain the configuration information of the error type from the second configuration submodule 22 of the configuration module 20.

[0087] like Figure 4A As shown, the recognition module 30 may include a mapping submodule 31 , a generating submodule 32 and a matching submodule 33 that are coupled to each other.

[0088] For example, the mapping submodule 31 is configured to sequentially map the monitored signal or a signal segment within the monitored signal into a first pattern consisting of a first value and a plurality of second values, in units of clock cycles. A glitch is mapped to the first value within the first pattern, and a plurality of data corresponding to a plurality of clock cycles other than the glitch is mapped to the plurality of second values ​​within the first pattern. For example, one of the first value and the second value can be 1, and the other can be 0. For example, in a specific example of an embodiment of the present disclosure, the first value is 1, and the second value is 0. The first value and the second value can also take other values, and the embodiments of the present disclosure are not limited thereto.

[0089] Figure 4B A schematic diagram of a mapping operation provided by at least one embodiment of the present disclosure. Figure 4B As shown in (a) in the figure, the glitch in the signal segment 1 of the monitored signal Sig is within the clock cycle (does not fall on the clock edge) and the level is high, so it is mapped to 1. The data corresponding to other clock cycles except this glitch are all low levels within the clock cycle and are mapped to 0. The resulting pattern of the signal segment 1 after mapping is: 00010. Or, as Figure 4B As shown in (b), the glitch in the signal segment 2 of the monitored signal Sig is at a high level at the rising edge of the clock, which is mapped to 1. The data levels corresponding to the rising edges of other clock cycles except this glitch are all low levels, which are mapped to 0. The resulting pattern of the mapped signal segment 2 is: 010000.

[0090] For example, the generation submodule 32 is configured to generate multiple second styles based on the configuration information of the error type, wherein each second style in the multiple second styles is different, and each second style specifies a first range of the number of second values ​​before the first value and a second range of the number of second values ​​after the first value.

[0091] Figure 4C A schematic diagram of generating multiple second styles based on configuration information of error types is provided in at least one embodiment of the present disclosure. Figure 4C As shown, the error types include error A and error B, and the configuration information of the error types includes the minimum pulse width A_min and the maximum pulse width A_max of error A, the minimum pulse width B_min and the maximum pulse width B_max of error B. The generation submodule 32 can generate multiple second styles based on A_min, A_max, B_min and B_max, which are style 1, style 2, style 3 and style 4 respectively.

[0092] For example, the first range of style 1 is that the number of second value 0s before the first value 1 is greater than or equal to A_min and less than or equal to A_max, and the second range of style 1 is that the number of second value 0s after the first value 1 is greater than or equal to B_min and less than or equal to B_max.

[0093] For example, the first range of style 2 is that the number of second value 0s before the first value 1 is greater than or equal to A_min and less than or equal to A_max, and the second range of style 2 is that the number of second value 0s after the first value 1 is greater than or equal to A_min and less than or equal to A_max.

[0094] For example, the first range of style 3 is that the number of second value 0s before the first value 1 is greater than or equal to B_min and less than or equal to B_max, and the second range of style 3 is that the number of second value 0s after the first value 1 is greater than or equal to B_min and less than or equal to B_max.

[0095] For example, the first range of style 4 is that the number of second value 0s before the first value 1 is greater than or equal to B_min and less than or equal to B_max, and the second range of style 4 is that the number of second value 0s after the first value 1 is greater than or equal to A_min and less than or equal to A_max.

[0096] For example, error A in the above embodiment can be a cyclic redundancy check error, the minimum pulse width A_min can be, for example, 12 cycles, and the maximum pulse width A_max can be, for example, 20 cycles; error B can be a parity check error, the minimum pulse width B_min can be, for example, 96 cycles, and the maximum pulse width B_max can be, for example, 192 cycles. Errors A and B in the above embodiment are not limited to cyclic redundancy check errors and parity check errors. The specific error types and the specific values ​​of the pulse width range can be configured according to the actual circuit and the provisions of the relevant protocol, and the embodiments of the present disclosure are not limited to this. For example, in at least one embodiment of the present disclosure, 3, 4 or more error types can be set according to actual needs, and the number of generated second patterns can be equal to the square of the number of error types. Thus, the generation submodule 32 can generate and store as many second patterns as possible by setting the error types and the configuration information of the error types.

[0097] For example, the matching submodule 33 is configured to determine a target pattern that matches the first pattern from the plurality of second patterns, and determine and output an error type of the signal segment based on the target pattern. For example, if a first number of second values ​​preceding a first value in the first pattern falls within a first range of the target pattern, and a second number of second values ​​following the first value in the first pattern falls within a second range of the target pattern, then the first pattern is determined to match the target pattern.

[0098] For example, in a specific example of an embodiment of the present disclosure, if the signal segment of the monitored signal is mapped to a first pattern of "0000000000001000000000000000", then since the number of second-value 0s before the first value 1 in the first pattern is 12 (first number), and the number of second-value 0s after the first value 1 is 15 (second number), that is, the first number and the second number of 0s in the first pattern are both greater than or equal to A_min (for example, 12 cycles) and less than A_max (for example, 20 cycles), and fall within the first range and the second range of pattern 2, it can be determined that the first pattern matches pattern 2, and the error types of the signal segment can be determined to be A and A based on the error type corresponding to pattern 2. Similarly, if the target pattern of the first pattern is pattern 1, the error types of the signal segment can be determined to be A and B based on the error type corresponding to pattern 1.

[0099] The technical solution provided in the above embodiment of the present disclosure for generating multiple second patterns and matching the first pattern with the target pattern is a specific implementation method with strong operability. In addition, the monitored signal can also be counted in bits (for example, the number of clock cycles in which the low level lasts) and compared and matched with the configuration information of the error type to determine the error type of the monitored signal.

[0100] It should be noted that if the first number of second values ​​before the first value in the first style (or the second number of second values ​​after the first value) is not in the first range (or second range) of any second style, it can be determined that the error type corresponding to this part of the signal segment is an unknown error.

[0101] For example, in a specific example of an embodiment of the present disclosure, if the signal segment of the monitored signal is mapped to a first pattern of "00000000001000000000000000", then since the number of second-value 0s before the first value 1 in the first pattern is 10 (first number), and the number of second-value 0s after the first value 1 is 15 (second number), that is, the first number of 0s in the first pattern is not in the first range of any second pattern, but the second number of 0s in the first pattern is greater than A_min (for example, 12 cycles) and less than A_max (for example, 20 cycles), and falls within the allowable range of the pulse width of error type A, it can be determined that the error type of the part before 1 corresponding to the glitch of the signal segment is an unknown error, and the error type of the part after 1 corresponding to the glitch of the signal segment is A.

[0102] At least one embodiment of the present disclosure provides a signal monitoring device including an identification module 30 that can infer the error type of the fault alarm signal based on the level form before and after the glitch of the fault alarm signal, thereby facilitating subsequent targeted error correction.

[0103] Figure 5 A schematic diagram of another signal monitoring device provided by at least one embodiment of the present disclosure. Figure 5 As shown, the signal monitoring device 500 is relative to Figure 3 The signal monitoring device 300 shown further includes an alarm module 40 coupled to the monitoring module 10, configured to generate an alarm for glitches generated by the monitored signal. The alarm module 40 can provide timely feedback of glitches-related information after the glitches are generated in the monitored signal.

[0104] For example, in an embodiment of the present disclosure, the monitoring module 10 is further configured to, in response to determining that a glitch occurs in the monitored signal, send glitch information of the glitch to the alarm module 40. For example, the glitch information may include the occurrence time, pulse amplitude, pulse width, etc. of the glitch.

[0105] like Figure 5 As shown, the alarm module 40 may include a coupled acquisition submodule 41 , an alarm submodule 42 and a feedback submodule 43 .

[0106] For example, the acquisition submodule 41 is configured to acquire alarm configuration information and, in response to determining that an alarm is required based on the alarm configuration information, send the glitch information to the alarm submodule 42. The alarm submodule 42 is configured to generate alarm information based on the glitch information and send the alarm information to the feedback submodule 43. The feedback submodule 43 is configured to output the alarm information based on the alarm configuration information.

[0107] For example, alarm configuration information can include at least one of whether to generate an alarm after a glitch is detected and how to generate an alarm. For example, you can configure an alarm for glitches whose pulse amplitude exceeds a threshold; or you can configure which pin to use for alarm feedback, such as alert_n or uvm_error; and you can also configure what information is included in the output alarm information, such as the glitch's occurrence time, duration, pulse amplitude, and the signal on which the glitch appears.

[0108] For example, the alarm module 40 may obtain the configuration information of the alarm configured by the system by default, or may obtain the configuration information of the alarm in the setting information provided by the user, thereby improving the flexibility of the alarm.

[0109] For example, in one example of the present disclosure, Figure 5 As shown, the configuration module 20 in the signal monitoring device 500 may include, in addition to the first configuration submodule 21, a third configuration submodule 23. The third configuration submodule 23 is configured to store the system default configuration or the alarm configuration information freely set by the user. For example, the alarm module 40 is coupled to the third configuration submodule 23 of the configuration module 20, and the alarm module 40 can obtain the alarm configuration information from the third configuration submodule 23 of the configuration module 20.

[0110] For example, the alarm module 40 may be implemented in hardware or software, for example, it may output alarm information through an alarm signal, or it may provide feedback through an operation register, and the embodiments of the present disclosure are not limited thereto.

[0111] Figure 6A A schematic diagram of another signal monitoring device provided by at least one embodiment of the present disclosure. Figure 6A As shown, Figure 6A As shown, the signal monitoring device 600 is relative to Figure 3 The illustrated signal monitoring device 300 also includes a glitch widening module 50 coupled to the monitoring module 10. The module is configured to, in response to a glitch generated by the monitored signal, widen the pulse of the glitch so that the widened glitch can be detected by the sampling edge of a clock signal in the signal monitoring device's external circuit. Through the widening process performed by the glitch widening module 50, the pulse of a narrow or previously undetectable glitch can be widened, thereby facilitating system detection of the glitch.

[0112] For example, in an embodiment of the present disclosure, the monitoring module 10 is further configured to, in response to determining that a glitch is generated in the monitored signal, send glitch information of the glitch to the glitch widening module 50. For example, the glitch information may include the occurrence time, pulse amplitude, pulse width, etc. of the glitch.

[0113] like Figure 6AAs shown, the glitch widening module 50 may include an information storage submodule 51 and a glitch widening submodule 52 coupled to each other.

[0114] For example, the information storage submodule 51 is configured to obtain configuration information for glitch widening, and in response to receiving the glitch information, send the configuration information for glitch widening to the glitch widening submodule 52. The glitch widening submodule 52 is configured to widen the pulse width of the glitch according to the configuration information for glitch widening, so that the widened pulse width of the glitch reaches the target pulse width set in the configuration information for glitch widening.

[0115] For example, the glitch widening configuration information may include the pulse width after glitch widening (target pulse width). The target pulse width may be equal to the clock period or another value set as needed (e.g., a value greater than the clock period). For example, the glitch widening configuration information may also include whether to widen the glitch. For example, if the glitch pulse width is wide enough to be detected by the sampling edge of the clock signal, then the glitch may not be widened. Otherwise, the glitch may be widened.

[0116] For example, the glitch widening module 50 may obtain the configuration information of the glitch widening configured by the system by default, or may obtain the configuration information of the glitch widening in the setting information provided by the user, thereby improving the flexibility of the glitch widening.

[0117] For example, in one example of the present disclosure, Figure 6A As shown, the configuration module 20 in the signal monitoring device 600 may include, in addition to the first configuration submodule 21, a fourth configuration submodule 24. The fourth configuration submodule 24 is configured to store configuration information for glitch widening configured by the system default or freely set by the user. For example, the glitch widening module 50 is coupled to the fourth configuration submodule 24 of the configuration module 20, and the glitch widening module 50 may obtain the configuration information for glitch widening from the fourth configuration submodule 24 of the configuration module 20.

[0118] Figure 6B This is a structural diagram of a burr widening submodule 52 provided in at least one embodiment of the present disclosure. Figure 6B As shown, the glitch widening submodule 52 includes an AND gate 521 , an OR gate 522 , a first D flip-flop 523 , and a second D flip-flop 524 .

[0119] For example, a first terminal of an AND gate 521 receives a first signal, a second terminal of the AND gate 521 is connected to a third terminal of an OR gate 522 and receives the monitored signal sig, a first output terminal of the AND gate 521 is connected to a first input terminal (D terminal) of a first D-type flip-flop 523, a third terminal of the OR gate 522 receives the monitored signal sig, a fourth terminal of the OR gate 522 receives a clock signal clk (e.g., a system clock), a second output terminal of the OR gate 522 is connected to a first clock terminal of the first D-type flip-flop 523, a third output terminal (Q terminal) of the first D-type flip-flop 523 is connected to a second input terminal (D terminal) of a second D-type flip-flop 524, a second clock terminal of the second D-type flip-flop 524 is connected to a fourth terminal of the OR gate 522 to receive the clock signal clk, and a fourth output terminal (Q terminal) of the second D-type flip-flop 524 outputs the monitored signal sig_out after glitch widening. Since glitch detection is implemented based on edge detection, the glitch widening submodule 52 can widen glitches of any pulse width.

[0120] Figure 6C A schematic diagram of a widened burr provided in at least one embodiment of the present disclosure. Figure 6B and Figure 6C As shown, the first signal is a continuous high-level signal (for example, a logic state of 1). If there is a glitch in the monitored signal sig (for example, manifested as a high-level pulse), the first D flip-flop 523 (when the clock rises) feeds it back to the intermediate signal m_sig, and m_sig is equal to 1. If there is no glitch, m_sig is equal to 0. Then, when the clock rises at the second D flip-flop 524, the value of m_sig is assigned to the Q terminal of the second D flip-flop 524, thereby widening the pulse width of the glitch. The output signal sig_out after the glitch is widened is shown as follows: Figure 6C As shown. After the glitch is widened, the pulse width of the glitch in the signal sig_out is wide enough to be detected by the sampling edge (e.g., rising edge or falling edge) of the clock signal of other circuits, which facilitates subsequent processing of the glitch, such as filtering. For example, Figure 6B and Figure 6C The clock signal clk in the circuit is the same as the clock signals of other circuits, for example, they are all system clocks.

[0121] Figure 7 A schematic diagram of another signal monitoring device provided by at least one embodiment of the present disclosure. Figure 7 As shown, the signal monitoring device 700 includes a monitoring module 10 , a configuration module 20 , an identification module 30 , an alarm module 40 and a burr widening module 50 .

[0122] The structures and detailed descriptions of the monitoring module 10 , the identification module 30 , the alarm module 40 and the burr widening module 50 may refer to the relevant descriptions in the above embodiments and will not be repeated here.

[0123] For example, the configuration module 20 includes a first configuration submodule 21, a second configuration submodule 22, a third configuration submodule 23, and a fourth configuration submodule 24. The first configuration submodule 21 is connected to the monitoring module 10, the second configuration submodule 22 is connected to the identification module 30, the third configuration submodule 23 is connected to the alarm module 40, and the fourth configuration submodule 24 is connected to the burr widening module 50. For detailed descriptions of the first configuration submodule 21, the second configuration submodule 22, the third configuration submodule 23, and the fourth configuration submodule 24, reference can be made to the relevant descriptions in the above embodiments and will not be repeated here.

[0124] The user can set the pulse width threshold, error type configuration information, alarm configuration information, and glitch widening configuration information according to needs, and save them in the first configuration submodule 21, the second configuration submodule 22, the third configuration submodule 23, and the fourth configuration submodule 24 respectively. When the monitoring module 10, the identification module 30, the alarm module 40, and the glitch widening module 50 need to use this information, they can directly obtain it from the configuration module 20, thereby improving the working efficiency of each module.

[0125] It should be noted that in the embodiments of the present disclosure, the signal monitoring device may include more or fewer circuits or modules, and the connection relationship between the various circuits or modules is not limited and can be determined according to actual needs. The specific configuration of each circuit or module is not limited and can be composed of analog devices based on circuit principles, or can be composed of digital chips, or constructed in other applicable ways.

[0126] Figure 8 A flow chart of a signal monitoring method provided in at least one embodiment of the present disclosure is shown as follows: Figure 8 As shown, the signal monitoring method includes the following steps S810 to S830.

[0127] S810: Acquire a pulse width threshold and receive a monitored signal.

[0128] S820: Record the time when each level reversal of the monitored signal occurs.

[0129] S830: Determine whether a glitch occurs in the monitored signal based on a relationship between a difference between two adjacent level flip times of the monitored signal and a pulse width threshold.

[0130] For example, in the signal monitoring method provided in at least one embodiment of the present disclosure, step S830, i.e., determining whether a glitch has occurred in the monitored signal based on the relationship between the difference between the occurrence moments of two adjacent level flips of the monitored signal and the pulse width threshold, a specific example may include: in response to the difference between the occurrence moments of two adjacent level flips of the monitored signal being less than the pulse width threshold, determining that a glitch has occurred in the monitored signal; in response to the difference between the occurrence moments of two adjacent level flips of the monitored signal being greater than or equal to the pulse width threshold, determining that no glitch has occurred in the monitored signal.

[0131] For example, in the signal monitoring method provided in at least one embodiment of the present disclosure, the monitored signal includes a fault alarm signal, which is used to report a fault or abnormality in the monitored circuit.

[0132] For example, the signal monitoring method provided by at least one embodiment of the present disclosure also includes: in response to determining that a glitch is generated in the fault alarm signal, obtaining a signal segment in the fault alarm signal from the nearest edge before the glitch to the nearest edge after the glitch; obtaining configuration information of the error type; and identifying the error type of the signal segment based on the configuration information of the error type.

[0133] For example, in the signal monitoring method provided in at least one embodiment of the present disclosure, the error type of a signal segment is identified based on the configuration information of the error type, and a specific example thereof may include: mapping the signal segment to a first style in units of clock cycles, wherein the glitch in the signal segment is mapped to a first value in the first style, and multiple data corresponding to multiple clock cycles other than the glitch in the signal segment are mapped to multiple second values ​​in the first style; generating multiple second styles based on the configuration information of the error type, wherein each of the multiple second styles is different, and each second style specifies a first range of the number of second values ​​before the first value and a second range of the number of second values ​​after the first value; and determining a target style that matches the first style from the multiple second styles, and determining and outputting the error type of the signal segment based on the target style.

[0134] For example, in the signal monitoring method provided in at least one embodiment of the present disclosure, a target pattern that matches the first pattern is determined from multiple second patterns. A specific example may include: in response to a first number of second values ​​before the first value in the first pattern falling within a first range of the target pattern, and a second number of second values ​​after the first value in the first pattern falling within a second range of the target pattern, determining that the first pattern matches the target pattern.

[0135] For example, the signal monitoring method provided by at least one embodiment of the present disclosure also includes: obtaining alarm configuration information; in response to determining that a burr has been generated in the monitored signal and determining that an alarm is required based on the alarm configuration information, generating alarm information based on the burr information, the alarm configuration information including at least one of whether an alarm is required after a burr is detected and how to alarm; and outputting alarm information based on the alarm configuration information.

[0136] For example, the signal monitoring method provided by at least one embodiment of the present disclosure further includes: obtaining configuration information for glitch widening; in response to determining that a glitch is generated in the monitored signal, widening the pulse width of the glitch according to the configuration information for glitch widening, so that the widened glitch can be detected by the sampling edge of the clock signal of the external circuit of the signal monitoring device.

[0137] For example, the signal monitoring method provided by at least one embodiment of the present disclosure also includes: obtaining setting information provided by the user; parsing the setting information to obtain at least one of the pulse width threshold, error type configuration information, alarm configuration information and glitch widening configuration information.

[0138] The signal monitoring method provided by at least one embodiment of the present disclosure monitors whether a glitch has occurred by calculating the difference between the occurrence times of two adjacent level flips of the monitored signal and comparing it with a pulse width threshold. This method can not only monitor glitches of any pulse width, but also switch or monitor multiple monitored signals. It also increases the flexibility of glitch monitoring and post-processing, making parameters such as the pulse width threshold of the glitch of the monitored signal, error type configuration information, alarm configuration information, and glitch widening configuration information adjustable.

[0139] At least one embodiment of the present disclosure further provides an electronic device comprising a memory and a processor, wherein the memory non-transiently stores computer-executable instructions, and the processor is configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the processor, implement the signal monitoring method according to any of the above embodiments. The technical effects of this electronic device are the same as those of the above-mentioned signal monitoring methods and are not further described here.

[0140] At least one embodiment of the present disclosure also provides a non-transitory computer-readable storage medium. Figure 9 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. Figure 9 As shown, one or more computer-executable instructions 901 can be non-transitory stored on a storage medium 900. For example, when computer-executable instructions 901 are executed by a processor, one or more steps of the signal monitoring method described above can be performed. The technical effects of this non-transitory storage medium are the same as those of the signal monitoring method described above and are not further described here.

[0141] For example, the above non-transitory readable storage medium is implemented as a memory, such as a volatile memory and / or a non-volatile memory. The memory in the above embodiments can be a volatile memory, which can include a random access memory (RAM), a cache, and / or the like. The non-volatile memory can include a read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a compact disc read-only memory (CD-ROM), a USB memory, a flash memory, and / or the like. The memory can also store various application programs (codes, instructions) and data, and various data used and / or generated by the application programs, and the like.

[0142] The above computer readable medium carries one or more programs, which when executed by the electronic device, cause the electronic device to perform the methods of the present disclosure.

[0143] Computer program code for carrying out the methods of the present disclosure can be written in any one or more programming languages, including object oriented programming languages such as Java, Smalltalk, C++ or conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0144] Some embodiments of the present disclosure also provide an electronic device including the signal monitoring apparatus of any of the above embodiments or capable of executing the signal monitoring method of any of the above embodiments.

[0145] Figure 10 A schematic block diagram of an electronic device according to at least one embodiment of the present disclosure is provided. The electronic device in the embodiments of the present disclosure can include, but is not limited to, a mobile terminal such as a mobile phone, a notebook computer, a digital broadcast receiver, a PDA (Personal Digital Assistant), a PAD (Tablet Personal Computer), a PMP (Portable Multimedia Player), a car terminal (for example, a car navigation terminal), and the like, and a stationary terminal such as a digital TV, a desktop computer, and the like. Figure 10 The electronic device 1000 shown is merely an example and should not bring any limitation to the functions and use range of the embodiments of the present disclosure.

[0146] For example, as shown in FIG. 10, the electronic device 1000 can include a communication unit 1010, a user input unit 1020, a user output unit 1030, a storage unit 1040, and a processor 1050. Figure 10 As shown, in some examples, electronic device 1000 includes a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 1001. This processing device 1001 may include the signal monitoring device of any of the above-mentioned embodiments. It can perform various appropriate actions and processes based on programs stored in a read-only memory (ROM) 1002 or programs loaded from a storage device 1008 into a random access memory (RAM) 1003. RAM 1003 also stores various programs and data required for the operation of the computer system. Processing device 1001, ROM 1002, and RAM 1003 are connected to each other via a bus 1004. An input / output (I / O) interface 1005 is also connected to bus 1004.

[0147] For example, the following components may be connected to the I / O interface 1005: an input device 1006 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 1007 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1008 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 1009 may allow the electronic device 1000 to communicate with other devices wirelessly or by wire to exchange data, performing communication processing via a network such as the Internet. A drive 1010 is also connected to the I / O interface 1005 as needed. A removable storage medium 1011, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 1010 as needed, so that a computer program read therefrom is installed into the storage device 1008 as needed. Although Figure 10 The electronic device 1000 is shown to include various devices, but it should be understood that it is not required to implement or include all of the devices shown, and more or fewer devices may be implemented or included instead.

[0148] For example, the electronic device 1000 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 1009 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communications may use any of a variety of communication standards, protocols, and technologies, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0149] For example, the electronic device 1000 can be any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigator, etc., or it can be any combination of data processing devices and hardware, and the embodiments of the present disclosure are not limited to this.

[0150] Although the present disclosure has been described in detail above using general descriptions and specific embodiments, it will be apparent to those skilled in the art that modifications or improvements may be made based on the embodiments of the present disclosure. Therefore, such modifications or improvements, as long as they do not depart from the spirit of the present disclosure, are within the scope of protection claimed by the present disclosure.

[0151] In addition to the above exemplary contents, the following points need to be explained in this disclosure:

[0152] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0153] (2) For the sake of clarity, the thickness of layers or regions in the drawings used to describe the embodiments of the present disclosure are enlarged or reduced, that is, these drawings are not drawn according to the actual scale.

[0154] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0155] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A signal monitoring device, comprising: The monitoring module is configured to obtain a pulse width threshold and receive a monitored signal, and perform glitch monitoring on the monitored signal based on the pulse width threshold. The monitoring module includes an edge monitoring submodule and a burr determination submodule. The edge monitoring submodule is configured to record the occurrence time of each level flip of the monitored signal, and send the occurrence time of each level flip to the glitch determination submodule; The glitch determination submodule is configured to determine whether the monitored signal has a glitch based on a relationship between a difference between two adjacent level flip times of the monitored signal and the pulse width threshold.

2. The signal monitoring device according to claim 1, wherein: The glitch determination submodule determines whether the monitored signal generates a glitch based on the relationship between the difference between the occurrence times of two adjacent level flips of the monitored signal and the pulse width threshold, including: In response to a difference between the occurrence times of two adjacent level flips of the monitored signal being smaller than the pulse width threshold, determining that a glitch has occurred in the monitored signal; In response to the difference between the occurrence times of two adjacent level flips of the monitored signal being greater than or equal to the pulse width threshold, it is determined that the monitored signal does not generate a glitch.

3. The signal monitoring device according to claim 1, wherein: The monitored signal includes a fault alarm signal, which is used to report a fault or abnormality in the monitored circuit. The signal monitoring device further includes: an identification module coupled to the monitoring module, The monitoring module is further configured to, in response to determining that a burr is generated in the fault alarm signal, send a signal segment of the fault alarm signal between a nearest edge before the burr and a nearest edge after the burr to the identification module; The identification module is configured to obtain configuration information of an error type and identify the error type of the signal segment based on the configuration information of the error type.

4. The signal monitoring device according to claim 3, wherein: The recognition module includes a mapping submodule, a generation submodule and a matching submodule. The mapping submodule is configured to map the signal segment into a first pattern in units of clock cycles, wherein the glitch in the signal segment is mapped to a first value in the first pattern, and a plurality of data corresponding to a plurality of clock cycles in the signal segment excluding the glitch is mapped to a plurality of second values ​​in the first pattern. The generating submodule is configured to generate a plurality of second patterns based on the configuration information of the error type, wherein each second pattern in the plurality of second patterns is different and each second pattern specifies a first range of the number of second values ​​before the first value and a second range of the number of second values ​​after the first value, The matching submodule is configured to determine a target pattern matching the first pattern from the plurality of second patterns, and determine and output an error type of the signal segment based on the target pattern.

5. The signal monitoring device according to claim 4, wherein: The matching submodule determines a target pattern matching the first pattern from the plurality of second patterns, including: In response to a first number of second values ​​before the first value in the first pattern falling within a first range of the target pattern, and a second number of second values ​​after the first value in the first pattern falling within a second range of the target pattern, it is determined that the first pattern matches the target pattern.

6. The signal monitoring device according to claim 4, wherein: The number of the second patterns is equal to the square of the number of the error types.

7. The signal monitoring device according to claim 3, wherein: The error type includes at least one of a cyclic redundancy check error and a parity check error. 8 . The signal monitoring device according to claim 1 , further comprising an alarm module coupled to the monitoring module, wherein the alarm module is configured to generate an alarm for a burr generated by the monitored signal.

9. The signal monitoring device according to claim 8, wherein: The monitoring module is further configured to send glitch information of the glitch to the alarm module in response to determining that the monitored signal generates a glitch. The alarm module includes an acquisition submodule, an alarm submodule and a feedback submodule. The acquisition submodule is configured to acquire alarm configuration information, and in response to determining that an alarm is required based on the alarm configuration information, send the burr information to the alarm submodule, wherein the alarm configuration information includes at least one of whether an alarm is required after a burr is detected and how to issue an alarm. The alarm submodule is configured to generate alarm information according to the burr information and send the alarm information to the feedback submodule. The feedback submodule is configured to output the alarm information according to the alarm configuration information.

10. The signal monitoring device according to any one of claims 1 to 7, further comprising a glitch widening module coupled to the monitoring module, wherein the glitch widening module is configured to widen the pulse of the glitch in response to a glitch generated by the monitored signal, so that the widened glitch can be detected by the sampling edge of the clock signal of the external circuit of the signal monitoring device.

11. The signal monitoring device according to claim 10, wherein: The monitoring module is further configured to send glitch information of the glitch to the glitch widening module in response to determining that the monitored signal generates a glitch. The burr widening module includes an information storage submodule and a burr widening submodule. The information storage submodule is configured to obtain configuration information of burr widening, and in response to receiving the burr information, send the configuration information of burr widening to the burr widening submodule, The glitch widening submodule is configured to perform the widening process on the pulse width of the glitch according to the glitch widening configuration information, so that the widened pulse width of the glitch reaches the target pulse width set in the glitch widening configuration information.

12. The signal monitoring device according to claim 11, wherein: The glitch widening submodule includes an AND gate, an OR gate, a first D flip-flop and a second D flip-flop. The first terminal of the AND gate receives a first signal, the second terminal of the AND gate is connected to the third terminal of the OR gate, and the first output terminal of the AND gate is connected to the first input terminal of the first D flip-flop. The third terminal of the OR gate receives the monitored signal, the fourth terminal of the OR gate receives a clock signal, and the second output terminal of the OR gate is connected to the first clock terminal of the first D flip-flop. The third output terminal of the first D flip-flop is connected to the second input terminal of the second D flip-flop, the second clock terminal of the second D flip-flop is connected to the fourth terminal of the OR gate to receive the clock signal, and the fourth output terminal of the second D flip-flop outputs the monitored signal after glitch widening.

13. The signal monitoring device according to any one of claims 1 to 7, further comprising a configuration module coupled to the monitoring module, wherein: The configuration module includes a configuration entry and a first configuration submodule, The configuration entry is configured to send the setting information provided by the user to the first configuration submodule; The first configuration submodule is configured to parse the setting information to obtain a pulse width threshold, and send the pulse width threshold to the monitoring module.

14. The signal monitoring device according to claim 13, wherein: The setting information further includes at least one of error type configuration information, alarm configuration information, and glitch widening configuration information.

15. A signal monitoring method, comprising: Obtaining pulse width thresholds and receiving monitored signals; Recording the occurrence time of each level flip of the monitored signal; as well as Based on the relationship between the difference between the occurrence times of two adjacent level flips of the monitored signal and the pulse width threshold, it is determined whether the monitored signal has a glitch.

16. The signal monitoring method according to claim 15, wherein: The determining whether the monitored signal generates a glitch based on a relationship between a difference between two adjacent level flipping moments of the monitored signal and the pulse width threshold comprises: In response to a difference between the occurrence times of two adjacent level flips of the monitored signal being smaller than the pulse width threshold, determining that a glitch has occurred in the monitored signal; In response to the difference between the occurrence times of two adjacent level flips of the monitored signal being greater than or equal to the pulse width threshold, it is determined that the monitored signal does not generate a glitch.

17. The signal monitoring method according to claim 16, wherein: The monitored signal includes a fault alarm signal, which is used to report a fault or abnormality in the monitored circuit. The signal monitoring method further includes: In response to determining that a burr is generated in the fault alarm signal, obtaining a signal segment from a nearest edge before the burr to a nearest edge after the burr in the fault alarm signal; Get configuration information for the error type; and An error type of the signal segment is identified based on the configuration information of the error type.

18. The signal monitoring method according to claim 17, wherein: The identifying the error type of the signal segment based on the configuration information of the error type includes: Mapping the signal segment into a first pattern in units of clock cycles, wherein the glitch in the signal segment is mapped to a first value in the first pattern, and a plurality of data corresponding to a plurality of clock cycles in the signal segment excluding the glitch is mapped to a plurality of second values ​​in the first pattern; generating a plurality of second patterns based on the configuration information of the error type, wherein each second pattern of the plurality of second patterns is different and each second pattern specifies a first range of the number of second values ​​before the first value and a second range of the number of second values ​​after the first value; and A target pattern matching the first pattern is determined from the plurality of second patterns, and an error type of the signal segment is determined and output based on the target pattern.

19. The signal monitoring method according to claim 18, wherein: The determining a target pattern matching the first pattern from the plurality of second patterns includes: In response to a first number of second values ​​before the first value in the first pattern falling within a first range of the target pattern, and a second number of second values ​​after the first value in the first pattern falling within a second range of the target pattern, it is determined that the first pattern matches the target pattern.

20. The signal monitoring method according to any one of claims 15 to 19, further comprising: Get the alarm configuration information; In response to determining that a glitch has occurred in the monitored signal and determining that an alarm is required based on the alarm configuration information, generating alarm information based on the glitch information, the alarm configuration information including at least one of whether an alarm is required and how to issue an alarm after the glitch is detected; and The alarm information is output according to the configuration information of the alarm.

21. The signal monitoring method according to any one of claims 15 to 19, further comprising: Get the configuration information of glitch widening; In response to determining that a glitch is generated in the monitored signal, the pulse width of the glitch is widened according to the glitch widening configuration information so that the widened glitch can be detected by a sampling edge of a clock signal of an external circuit of the signal monitoring device.

22. The signal monitoring method according to any one of claims 15 to 19, further comprising: Get the settings information provided by the user; The setting information is parsed to obtain at least one of a pulse width threshold, configuration information of an error type, configuration information of an alarm, and configuration information of a glitch widening.

23. An electronic device comprising: at least one memory non-transitorily storing computer-executable instructions; at least one processor configured to execute the computer-executable instructions, Wherein, when the computer executable instructions are executed by the processor, the signal monitoring method according to any one of claims 15-22 is implemented.

24. A non-transitory computer-readable storage medium, wherein: The non-transitory computer-readable storage medium stores computer-executable instructions, When the computer-executable instructions are executed by at least one processor, the signal monitoring method according to any one of claims 15 to 22 is implemented.

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