Method and system for realizing chip test

Abstract

The invention discloses a method and system for realizing chip testing, and relates to the technical field of chip testing, and the method comprises the steps: assembling a chip testing daughter board, loading a plurality of chips to be tested in a chip loading area, configuring a switch matrix, a decoder and an activation control unit, and generating a chip mapping matrix; selecting a single chip to carry out a high-temperature operation lifetime test, monitoring the power consumption stability of the chip in real time, and calculating the power consumption deviation of the chip; executing a logic function test, a time sequence test and a multi-channel voltage output test, evaluating output consistency, and generating chip function test data; based on the chip power consumption deviation and the chip function test data, the entropy-based risk assessment method is adopted to calculate the failure probability of the chip to be tested, the failure probability distribution is analyzed by constructing a failure mechanism decision model, and the power consumption stability test and the function test of the chip to be tested are optimized. According to the method, the chip mapping matrix is generated through three-dimensional matrix operation, so that the test configuration time is shortened, and the test configuration complexity is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a method and system for implementing chip testing. Background Art

[0002] In recent years, chip test platforms have gradually evolved toward high-density, multi-channel, and high-frequency signal transmission to meet the testing needs of complex chips (such as BGA packages and SoC chips) in fields such as high-performance computing, artificial intelligence, and 5G communications. Conventional testing methods typically use automatic test equipment (ATE) combined with specialized test fixtures to verify the chip's logical functionality, timing performance, and power stability through fixed pin mapping and single-channel selection. In addition, some advanced test systems have introduced switch matrices and decoders to support parallel testing of multiple chips, thereby improving test efficiency. These technologies have demonstrated high reliability within standardized test processes.

[0003] However, existing chip testing technology still has significant deficiencies when dealing with multi-chip parallel testing. First, traditional test systems usually rely on fixed pin mapping and channel configurations, which makes it difficult to flexibly adapt to the pin layout and functional unit requirements of different chips, resulting in complex test configurations and poor versatility. Secondly, in tests under extreme conditions such as high temperature and high voltage, the existing system has limited monitoring capabilities for chip power consumption stability and multi-channel output consistency, and is easily affected by signal routing impedance mismatch or channel selection errors. Test accuracy is affected. These deficiencies not only reduce test efficiency, but may also lead to missed detection of potentially failed chips, thereby affecting chip reliability verification. Therefore, there is an urgent need for a method that can flexibly configure test channels and improve the accuracy of multi-chip parallel testing to meet the diverse needs of complex chip testing. Summary of the Invention

[0004] In view of the above existing problems, the present invention is proposed.

[0005] Therefore, the present invention provides a method for implementing chip testing to solve the problems of low test efficiency and insufficient precision caused by fixed pin mapping and insufficient channel configuration flexibility in multi-chip parallel testing.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions: In a first aspect, the present invention provides a method for implementing chip testing, comprising assembling a chip test sub-board, the chip test sub-board comprising a chip loading area, a test connection area, a signal routing area, a channel selection area, and an activation control area; loading multiple chips to be tested into the chip loading area; configuring a switch matrix, a decoder, and an activation control unit; and generating a chip mapping matrix. Insert the chip test daughter board into the mainboard array of the high-temperature test platform, select a single chip for high-temperature operation life test, monitor the chip power consumption stability in real time, and calculate the chip power consumption deviation; By aligning and applying pressure using an automated press jig, we perform logic function testing, timing testing, and multi-channel voltage output testing to evaluate output consistency and generate chip functional test data. Based on the chip power consumption deviation and chip functional test data, the entropy-based risk assessment method is used to calculate the failure probability of the chip under test. By constructing a failure mechanism decision model to analyze the failure probability distribution, the power consumption stability test and functional test of the chip under test are optimized.

[0007] As a preferred solution of the method for implementing chip testing of the present invention, the specific steps of generating the chip mapping matrix are as follows: According to the pin index of each chip under test, the state of the switch matrix is ​​set, and the mapping relationship between the pin index of each chip under test and the signal routing area is generated; Set the decoder's selection signal, connect the chip test daughter board's channel selection area to the decoder, and generate a mapping relationship between the channel index and the decoder's output signal; According to the FPGA logic of the activation control area, the activation instruction is preset, the signal transmission path of the activation instruction is matched with the chip under test, and the mapping relationship between the activation instruction and the shared signal line of each chip under test is generated; According to the mapping relationship between the pin index of each chip under test and the signal routing area, the mapping relationship between the channel index and the decoder output signal, and the mapping relationship between the activation instruction of each chip under test and the shared signal line, a chip mapping matrix is ​​generated through three-dimensional matrix operation.

[0008] As a preferred solution of the method for implementing chip testing of the present invention, wherein: the mapping relationship between the pin index of each chip to be tested and the routing of the signal routing area refers to the connection and disconnection between the pin of the chip to be tested and the routing of the signal routing area; The mapping relationship between the channel index and the decoder output signal refers to whether the channel is enabled and, if enabled, whether it is valid; The mapping relationship between the activation instruction of each chip under test and the shared signal line indicates whether the chip under test receives the activation instruction and is activated.

[0009] As a preferred solution of the method for implementing chip testing according to the present invention, the specific steps of calculating the chip power consumption deviation are as follows: The logic device in the activation control area selects each chip under test one by one according to the activation instruction, starts the high-temperature test chamber, and performs the high-temperature operation life test; The absolute deviation between the total power consumption and the average power consumption of the chip under test is calculated by integration to obtain the chip power consumption deviation.

[0010] As a preferred scheme of the method for implementing chip testing, the chip function test data is generated, and the specific steps are as follows, The signal port of the performance test mainboard transmits the test vector, the output response of each channel is recorded, the output signal is captured by using a logic analyzer, and the logic function coverage rate of each chip to be tested is calculated by comparing the expected output signal. All channels are gated by the decoder, a high-frequency clock signal is input, the clock frequency and signal delay of the chip are measured, the absolute deviation of the measured actual clock frequency and the target clock frequency is calculated, and the timing error is obtained. The output voltage of each channel is measured by using an analog-to-digital converter, the absolute average deviation of the multi-channel output voltage of the multiple chips to be tested and the target voltage is calculated, and the output voltage deviation is obtained. The logic function coverage rate, the timing error and the output voltage deviation are output as the chip function test data.

[0011] As a preferred scheme of the method for implementing chip testing, the chip function test data is generated, and the specific steps are as follows, The chip power consumption deviation and the chip function test data are normalized, and the state vector of the chip to be tested is constructed by taking the chip to be tested as an index. The state vector of the chip to be tested is discretized into a state interval for each chip to be tested. The state vector of the chip to be tested is discretized into a state interval for each chip to be tested. The state vector of the chip to be tested is discretized into a state interval for each chip to be tested. The state vector of the chip to be tested is discretized into a state interval for each chip to be tested. The state vector of the chip to be tested is discretized into a state interval for each chip to be tested. According to the failure score and the normalized state entropy of the chip to be tested, an exponential weighting function is used to calculate the failure probability of the chip to be tested.

[0012] As a preferred scheme of the method for implementing chip testing, the chip test subboard adopts a multi-layer printed circuit board, the surface is coated with a high-temperature resistant coating, the pin array of the chip loading area supports multiple chip packaging types, and the activation control area is dynamically configured with preset activation instructions by a programmable logic device.

[0013] In a second aspect, the present application provides a system for implementing chip testing, comprising, A mapping matrix module is used to assemble a chip test sub-board, which includes a chip loading area, a test connection area, a signal routing area, a channel selection area, and an activation control area. Multiple chips to be tested are loaded into the chip loading area, and a switch matrix, a decoder, and an activation control unit are configured to generate a chip mapping matrix. The power consumption deviation module is used to insert the chip test daughter board into the mainboard array of the high-temperature test platform, select a single chip for high-temperature operation life cycle testing, monitor the chip power consumption stability in real time, and calculate the chip power consumption deviation; Functional test module, used to perform logic function test, timing test and multi-channel voltage output test through automated pressing fixture alignment and pressure application, evaluate output consistency, and generate chip functional test data; The failure product evaluation module is used to calculate the failure probability of the chip under test based on the chip power consumption deviation and chip functional test data, using the entropy-based risk assessment method. By building a failure mechanism decision model to analyze the failure probability distribution, the power consumption stability test and functional test of the chip under test are optimized.

[0014] In a third aspect, the present invention provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: when the computer program is executed by the processor, any step of the method for implementing chip testing as described in the first aspect of the present invention is implemented.

[0015] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein: when the computer program is executed by a processor, it implements any step of the method for implementing chip testing as described in the first aspect of the present invention.

[0016] The beneficial effects of the present invention are as follows: the present invention dynamically generates the mapping relationship between the pin index, channel selection weight and activation signal of each chip to be tested through three-dimensional matrix operations, realizes the flexible configuration of the test channel, adapts to the pin layout and functional requirements of different chips, reduces the time and complexity of the test configuration, and based on the activation control unit of the programmable logic device (such as FPGA), sends the preset activation instruction through the shared control signal line, supports the parallel testing of multiple chips, and improves the test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1The present invention is a flowchart of a method for implementing chip testing.

[0019] Figure 2 Flowchart for generating the chip mapping matrix.

[0020] Figure 3 Generate chip functional test data flow chart.

[0021] Figure 4 This is the flow chart of the entropy-based risk assessment method. DETAILED DESCRIPTION

[0022] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0023] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0024] Secondly, the term "one embodiment" or "embodiment" herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in various places throughout this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive of other embodiments.

[0025] Reference Figures 1 to 4 , is an embodiment of the present invention, which provides a method for implementing chip testing, including the following steps: S1. Assemble a chip test sub-board, which includes a chip loading area, a test connection area, a signal routing area, a channel selection area, and an activation control area. Load multiple chips to be tested in the chip loading area, configure a switch matrix, a decoder, and an activation control unit, and generate a chip mapping matrix. The specific steps are as follows: The chip test daughter board uses a multi-layer high-frequency printed circuit board (PCB), such as a 10-layer structure, with a typical size of 150mm×150mm and a thickness of about 2.0mm to support high-frequency signal transmission. The frequency range can be as high as 20GHz. The chip test daughter board includes the following functional areas: a chip loading area, located in the center, with a size of 30mm×30mm, with a general pin array, such as a 16×16 grid, and a pin spacing of about 0.3mm; a test connection area, surrounding the chip loading area, for example, with a width of 15mm, with a high-density spring pin array reserved for installation The mounting position is as follows: for example, the spacing is about 0.6mm, with a total of 512 spring pins; the signal routing area is configured with impedance matching traces, the impedance is, for example, 50Ω, and the trace length does not exceed 70mm; the channel selection area reserves the installation space for decoders and switches, and supports multi-channel output selection, for example, 16 channels; the activation control area reserves the installation space for programmable logic devices, supports multi-chip parallel testing, for example, 16 chips, and sends preset activation instructions through shared control signal lines, chip select signal lines and address signal lines. The surface is coated with a high-temperature resistant coating, such as a polyimide coating; Conduct electrical connectivity tests on multi-layer high-frequency printed circuit boards, using a flying probe tester to verify the connectivity and insulation between pins to ensure there are no short circuits or open circuit defects; Using an automatic placement machine, such as a Yamaha YSM20, electronic components of a switch matrix, a decoder, and an activation control area are mounted on a multi-layer high-frequency printed circuit board of a chip test daughter board. For example, a switch matrix chip, such as an ADG1408, having 8 channels, is soldered in the signal routing area. The soldering temperature is controlled between 255° C. and 270° C., the soldering time does not exceed 5 seconds, and the soldering strength is not less than 15 MPa. A decoder chip, such as an SN74HC138, and an NMOS switch, such as a BSS138, are soldered in the channel selection area. A programmable logic device, such as an FPGA, is soldered in the activation control area. The soldering quality is inspected using X-ray inspection equipment to ensure that there are no cold solder joints or short circuits, thereby obtaining an electronic component assembly. Use reflow soldering technology to secure the spring pin array in the test connection area of ​​the electronic component assembly. Use conductive glue to secure the pins in the universal pin array position in the chip loading area to ensure stable electrical connection between the pins and the printed circuit board. Use a high-precision microscope to inspect the installation flatness of the spring pin array and the bonding quality of the universal pin array. Use an automatic placement machine to accurately place multiple chips under test on the universal pin array. For example, 16 BGA packaged chips, each with 144 pins and 16 functional units, are secured using micro-soldering technology. Use a multimeter to test the electrical connectivity between each chip under test and the universal pin array to ensure that all pins are correctly connected. Generate a chip test daughter board. Use programming software, such as LabVIEW, to set the state of the switch matrix according to the pin index of each chip under test. For example, connect the pins to the traces in the signal routing area to obtain the mapping relationship between the pin index of each chip under test, such as 1 to 144, and the traces in the signal routing area. Set the state value to 0 or 1, where 0 indicates disconnected and 1 indicates connected. Use a digital oscilloscope to verify the signal integrity of the pin connection. According to the number of functional units of the chip to be tested, use LabVIEW's digital I / O to connect to the channel selection area of ​​the chip test daughter board, communicate with the decoder through the USB or PCIe interface, configure the decoder of the chip test daughter board, set the decoder's selection signal, support multi-channel output selection, such as 16 channels, generate a mapping relationship between the channel index and the decoder output signal, set the selection signal value to 0 or 1, where 0 indicates that the channel is not selected and 1 indicates that the channel is selected, and set the channel's selection weight, which indicates the selection validity status, with a value of 0 or 1, where 0 indicates that the selection is invalid and 1 indicates that the selection is valid. Use a logic analyzer to verify the selection function of the decoder; Use the IP Integrator tool in Vivado (a programming software) to set the FPGA logic in the activation control area and preset activation instructions. The activation instructions include format bits and status bits. Use Vivado's I / O Planning function to allocate shared control signal lines, chip select signal lines, and address signal lines for the FPGA logic pins to ensure that the signal transmission path matches the chip under test. Generate a mapping relationship between the activation instructions and shared signal lines for each chip under test, and set the activation signal value to 0 or 1, where 0 indicates that the chip under test is not activated and 1 indicates that the chip under test is activated. Use MATLAB scripts to load the mapping relationship between the pin index of each chip under test and the signal routing area, the mapping relationship between the channel index and the decoder output signal, and the mapping relationship between the activation instruction of each chip under test and the shared signal line. Through three-dimensional matrix operations, generate the chip mapping matrix. The calculation formula is as follows: ; in, It is the chip mapping matrix, which indicates the total number of pins of all chips under test on the chip test daughter board that are correctly connected to the activated chip through valid channels. The value range is , reflects the integrity of the chip test daughter board connection configuration, for example, when When , it means that the 144 pins of the 16 chips under test are correctly connected. is the total number of pins of the chip to be tested, is the index variable of the pin of the chip to be tested, is the number of channels, is the index variable of the channel, is the number of chips to be tested, is the index variable of the chip to be tested, Indicates the chip test sub-board The first chip to be tested Is the first pin connected to the second pin through the signal routing area? Channel, the value is 0 or 1, where 0 means disconnected and 1 means correctly connected, for example Indicates that pin 1 of chip 1 under test is connected to channel 1. Indicates the The gating weight of each channel, For the The selection signal value of each channel, For the The activation signal value of the chip under test.

[0026] S2. Insert the chip test daughter board into the mainboard array of the high-temperature test platform, select a single chip for high-temperature operation life test, monitor the chip power consumption stability in real time, and calculate the chip power consumption deviation.

[0027] Parse the chip mapping matrix to extract the mapping relationship between the pin index, channel index, and activation signal of each chip under test, ensuring that all pins of each chip under test are effectively connected to the channel; Use an automatic insertion device to align the pogo pin array of the chip test daughter board with the pogo pin interface of the main board array of the high-temperature test platform via a robotic arm. Apply a contact pressure of, for example, 2N, and insert the chip test daughter board into the main board array of the high-temperature test platform. Use a multimeter to test the electrical connectivity between the main board array and the chip test daughter board to confirm that all pogo pins are correctly connected. The preset activation instructions are transmitted to the chip under test through shared control signals, chip select signals, and address signal lines. The control software of the high-temperature test platform, such as the ESPEC control interface, is used to set the high-temperature operation life test conditions, including the temperature, humidity, power supply, and test duration of the high-temperature test chamber. The stability of the test conditions is verified using temperature and humidity sensors and voltmeters to ensure that the temperature, humidity, and voltage are within the preset ranges. For example, the temperature is set to 150°C with an error of ±0.5°C, and the humidity is set to 50% with an error of ±5% to meet the specific temperature and humidity requirements of the high-temperature operation life test. This ensures the stability of the entire test environment and minimizes the impact of objective factors on the high-temperature operation life test. The power supply is provided by the Keysight E36300, and 1.3 times the nominal voltage is applied to each chip under test with a voltage error of ±0.01 volt. The test duration is 256 hours. Activate the logic devices in the control area. According to the activation instructions, select each chip under test one by one, start the high-temperature test chamber, and perform high-temperature operation life test. Based on the real-time monitoring of the voltage and current of the chip under test, calculate the real-time power consumption of the chip under test. By integrating the absolute deviation between the total power consumption and the average power consumption of the chip under test, evaluate the power consumption consistency of multiple chips under high temperature and high voltage conditions, and obtain the chip power consumption deviation. The calculation formula is as follows: ; ; in, Indicates time The deviation between the total power consumption and the average power consumption of multiple chips under test reflects the power consumption stability of the chip under test under high temperature and high voltage conditions. is the power consumption test time point, and The upper and lower limits of the sampling time window for voltage and current are typically Second, For all chips under test at time The total power consumption, For the The chip under test is Power consumption, To be applied in The voltage of the chip under test, For the The chip under test is of current.

[0028] S3. Use automated pressing fixtures to align and apply pressure to perform logic function testing, timing testing, and multi-channel voltage output testing to evaluate output consistency and generate chip functional test data.

[0029] Parse the chip mapping matrix to extract the mapping relationship between the pin index, channel index, and activation signal of each chip under test, ensuring that all pins of each chip under test are effectively connected to the channel; An automated pressing fixture is used to place the chip test daughter board on the performance test main board. Specifically, the chip test daughter board's alignment mark, such as the optical mark located in the test connection area, is identified by the automated pressing fixture's high-precision camera. The pressing assembly applies pressure to the chip test daughter board via a servo motor. The uniformity of the applied pressure is verified via a pressure sensor to ensure a stable electrical connection between the 512 spring pin arrays on the chip test daughter board and the signal terminals of the performance test main board. A multimeter is used to test the electrical connectivity between the performance test main board and the chip test daughter board to confirm that all 512 spring pins are correctly connected. Use performance test board test software, such as Keysight PathWave Test, to perform a logic function test. The specific steps are as follows: Select a single chip under test (DUT), select 16 channels through the decoder, input test vectors, and verify the logical operation function of the DUT. The test vectors are predefined binary input sequences that cover the 16 processing units of the DUT (each unit corresponds to a channel). The test vectors are transmitted through the signal ports of the performance test motherboard, and the output response of each channel is recorded. The output signal is captured using a logic analyzer, such as the Keysight U4154A, and compared with the expected output signal to calculate the logic function coverage of each DUT. The expected output signal is based on the DUT specifications. The test vectors are created according to the DUT specifications using the test software of the performance test motherboard. The expected output corresponding to each test vector is calculated based on the truth table of the DUT specifications. For the gating and logic function tests, the same chip under test is tested by gating all channels through the decoder and inputting a high-frequency clock signal, such as 100MHz. The chip's clock frequency and signal delay are measured, and the absolute deviation between the measured actual clock frequency and the target clock frequency is calculated. The absolute deviation is converted into a time deviation using the first-order error propagation approximation through frequency-to-time domain equivalent conversion. The time deviation is then summed with the signal delay to obtain the timing error. For the same chip under test, select all channels through the decoder, set the target output voltage, such as 1.2V, apply a standard input signal, such as 1V, and use an analog-to-digital converter (such as Texas Instruments ADS127L01, with a sampling rate of 1MS / s) to measure the output voltage of each channel. Calculate the absolute average deviation between the output voltage of multiple channels of the multiple chips under test and the target voltage, evaluate the multi-channel output accuracy, and obtain the output voltage deviation. The calculation formula is as follows: ; in, For in time The average deviation between the multi-chip multi-channel output voltage and the target voltage is For the The chip under test is Channels at time The voltage measurement value at For the The chip under test is Target voltage for each channel; The logic function coverage, timing error and output voltage deviation are output as chip functional test data.

[0030] S4. Based on the chip power consumption deviation and chip functional test data, the entropy-based risk assessment method is used to calculate the failure probability of the chip under test. By building a failure mechanism decision model to analyze the failure probability distribution, the power consumption stability test and functional test of the chip under test are optimized.

[0031] Normalize the chip power consumption deviation and chip function test data, and use the chip under test as an index to construct the state vector of the chip under test; For each chip under test, the state vector of the chip under test is discretized into state intervals, for example, 10 intervals of equal width. The histogram method is used to calculate the probability of the state vector of the chip under test being in each state interval by counting the distribution frequency of the state vector of each chip under test in the state interval. Aggregate the probability of the state vector of the chip under test in each state interval and calculate the state entropy of the chip under test. The calculation formula is as follows: ; in, For the The state entropy of the chip under test, is the number of state intervals, is the index variable of the state interval, For the The state vector of the chip under test is The probability of a state interval; By performing weighted normalization on the chip power consumption deviation and chip function test data, the degree to which the chip under test deviates from the expected performance is measured, and the failure score of the chip under test is obtained; Normalize the state entropy of the chip under test based on the number of state intervals; According to the failure score and normalized state entropy of the chip under test, the exponential weighting function is used to calculate the failure probability of the chip under test. The calculation formula is as follows: ; in, For the The failure probability of the chip under test, Indicates the The normalized state entropy of the chips under test, is the base of natural logarithms, is the failure amplification factor, which adjusts the impact of the failure score on the failure probability. The recommended value is 1. For the The failure score of the chip under test; Based on the failure probabilities of all chips under test, a failure probability histogram is drawn to statistically analyze the distribution of the failure probabilities of all chips under test, where the horizontal axis is the failure probability of the chip under test and the vertical axis is the number of chips under test. Based on the distribution of failure probabilities, a failure probability threshold is set; When the failure probability of the chip under test is greater than the failure probability threshold, it is marked as a potential failure chip; otherwise, it is marked as a non-failure chip; According to the standard distribution of chip power consumption deviation and chip function test data of non-failed chips, thresholds for chip power consumption deviation, logic function coverage, timing error, and output voltage deviation are set. For example, the power consumption deviation threshold is 1.5W, the logic function coverage threshold is 96%, the timing error threshold is 0.5ns, and the output voltage deviation threshold is 0.04V. The chip power consumption deviation and chip function test data of potential failed chips are summarized. For each potential failed chip, the failure mechanism of the potential failed chip is defined. Specifically, when the power consumption deviation is greater than the power consumption deviation threshold, the main mechanism is oxide layer rupture. When the logic function coverage is less than the logic function coverage threshold, the main mechanism is logic unit manufacturing defects. When the timing error is greater than the timing error threshold, the main mechanism is clock path delay. When the output voltage deviation is greater than the output voltage deviation threshold, the main mechanism is ion contamination. Create a training set based on the state vector, binary failure labels (potential failure and non-failure), and failure mechanism labels of the chip under test. The training set is in matrix form, with rows representing the chip under test and columns representing the state vector, binary failure label, and failure mechanism. Based on the classification and regression tree algorithm, a failure mechanism decision model for potential failure chips is constructed. The maximum depth and minimum number of leaf node samples of the failure mechanism classification model are initialized. The Gini index is calculated to evaluate the contribution of chip power consumption deviation, logic function coverage, timing error, and output voltage deviation to failure mechanism classification. This is used as a segmentation criterion to obtain the failure mechanism distribution of potential failure chips. The training set is input into the failure mechanism decision model, and the failure mechanism decision model is cross-validated and trained using the leave-one-out method. Taking 16 chips to be tested as an example, the training set of the 16 chips to be tested is divided into a training set of 15 chips and a validation set of 1 chip. 16 iterations are performed, and the state vector and failure mechanism label of the training set are extracted as input. The Gini index of the root node of the failure mechanism decision model is calculated, and the state and split point with the largest information gain are selected. The training set is divided into two subsets based on the split point. The Gini index is recursively calculated for each subset, and the best features and split points of the next layer are selected. The split process is repeated until the stopping condition is met (reaching the maximum depth of 4, the number of subset samples ≤ 2, or the Gini index is 0). The validation set is input into the single chip state vector test subtree to obtain the predicted failure mechanism label. The predicted failure mechanism label is compared with the true failure mechanism label, and the prediction accuracy is recorded. A different validation chip is selected in each iteration to generate 16 subtrees. The failure mechanism decision model training is completed by majority voting. The above failure mechanism decision model training is prior art and will not be described in detail. Based on the failure mechanism distribution of potential failure chips, the power consumption stability test and functional test of the chip under test are optimized. The specific contents are as follows: For logic unit manufacturing defects, which indicate manufacturing defects in the logic units of the chip under test due to lithography errors or uneven doping, we increase the coverage of test vectors and focus on verifying the boundary conditions of the logic units by generating more binary sequences. We also adjust the switch matrix configuration of the chip test daughterboard and optimize the routing of the signal routing area. In subsequent tests, we prioritize additional functional verification of chips under test whose logic function coverage is below the logic function coverage threshold. We use a logic analyzer to capture detailed output responses and identify the defect location. Clock path delay indicates that there is a delay in the internal clock path of the chip under test due to uneven wiring or capacitance effects. This can be solved by reducing the input clock frequency, adjusting the signal routing area of ​​the chip test daughterboard, shortening the length of the clock signal trace, and lowering the test temperature during high-temperature operation life testing to reduce the impact of thermal stress on the clock path. Regarding ion contamination, it indicates that the chip channel output voltage deviation is large. This may be caused by ion contamination (such as sodium ions) during the manufacturing process, which affects the electrical performance. You can choose to increase the pressure between the chip test daughter board and the performance test main board. During high-temperature operation life testing, reduce the test humidity to reduce the risk of ion migration. Regarding the rupture of the oxide layer, it indicates that the leakage current of the chip increases under high temperature and high voltage. Due to the rupture of the oxide layer, the voltage of the high-temperature operation life test can be reduced, the electrical stress can be reduced, the high-temperature operation life test time can be extended, and the thickness of the high-temperature resistant coating can be increased to ensure contact reliability.

[0032] This embodiment also provides a system for implementing chip testing, including: a mapping matrix module, which is used to assemble a chip test sub-board, wherein the chip test sub-board includes a chip loading area, a test connection area, a signal routing area, a channel selection area and an activation control area, multiple chips to be tested are loaded into the chip loading area, a switch matrix, a decoder and an activation control unit are configured, and a chip mapping matrix is ​​generated; a power consumption deviation module, which is used to insert the chip test sub-board into the mainboard array of the high-temperature test platform, select a single chip for high-temperature operation life test, monitor the chip power consumption stability in real time, and calculate the chip power consumption deviation; a functional test module, which is used to align and apply pressure through an automated pressing fixture, perform logic function testing, timing testing and multi-channel voltage output testing, evaluate output consistency, and generate chip functional test data; a failure product evaluation module, which is used to calculate the failure probability of the chip to be tested based on the chip power consumption deviation and chip functional test data, using an entropy-based risk assessment method, analyze the failure probability distribution by constructing a failure mechanism decision model, and optimize the power consumption stability test and functional test of the chip to be tested.

[0033] This embodiment also provides a computer device suitable for implementing a chip testing method, comprising: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute computer-executable instructions to implement the chip testing method proposed in the above embodiment.

[0034] The computer device may be a terminal, comprising a processor, memory, a communication interface, a display, and an input device connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores an operating system and computer programs. The internal memory provides an environment for the operating system and computer programs stored in the non-volatile storage media. The communication interface of the computer device is used to communicate with external terminals via wired or wireless communication. Wireless communication may be achieved via Wi-Fi, a carrier network, NFC (near-field communication), or other technologies. The display of the computer device may be a liquid crystal display or an electronic ink display. The input device may be a touchscreen overlay on the display, buttons, a trackball, or a touchpad on the computer device housing, or an external keyboard, touchpad, or mouse.

[0035] This embodiment also provides a storage medium having a computer program stored thereon, which, when executed by a processor, implements the chip testing method proposed in the above embodiment; the storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0036] In summary, the present invention dynamically generates the mapping relationship between the pin index, channel selection weight and activation signal of each chip to be tested through three-dimensional matrix operations through the chip mapping matrix, thereby realizing flexible configuration of the test channel, adapting to the pin layout and functional requirements of different chips, reducing the time and complexity of the test configuration, and based on the activation control unit of the programmable logic device (such as FPGA), sending preset activation instructions through the shared control signal line, supporting parallel testing of multiple chips, and improving test efficiency.

[0037] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A method for implementing chip testing, characterized in that: include, Assemble a chip test sub-board, load multiple chips to be tested into the chip loading area, configure a switch matrix, a decoder, and an activation control unit, and generate a chip mapping matrix; the chip test sub-board includes a chip loading area, a test connection area, a signal routing area, a channel selection area, and an activation control area; Insert the chip test daughter board into the mainboard array of the high-temperature test platform, select a single chip for high-temperature operation life test, monitor the chip power consumption stability in real time, and calculate the chip power consumption deviation; By aligning and applying pressure using an automated press jig, we perform logic function testing, timing testing, and multi-channel voltage output testing to evaluate output consistency and generate chip functional test data. Based on the chip power consumption deviation and chip functional test data, the entropy-based risk assessment method is used to calculate the failure probability of the chip under test. By constructing a failure mechanism decision model to analyze the failure probability distribution, the power consumption stability test and functional test of the chip under test are optimized.

2. The method for implementing chip testing according to claim 1, wherein: The specific steps of generating the chip mapping matrix are as follows: According to the pin index of each chip under test, the state of the switch matrix is ​​set, and the mapping relationship between the pin index of each chip under test and the signal routing area is generated; Set the decoder's selection signal, connect the chip test daughter board's channel selection area to the decoder, and generate a mapping relationship between the channel index and the decoder's output signal; According to the FPGA logic of the activation control area, the activation instruction is preset, the signal transmission path of the activation instruction is matched with the chip under test, and the mapping relationship between the activation instruction and the shared signal line of each chip under test is generated; According to the mapping relationship between the pin index of each chip under test and the signal routing area, the mapping relationship between the channel index and the decoder output signal, and the mapping relationship between the activation instruction of each chip under test and the shared signal line, a chip mapping matrix is ​​generated through three-dimensional matrix operation.

3. The method for implementing chip testing according to claim 2, wherein: The mapping relationship between the pin index of each chip under test and the routing of the signal routing area refers to the connection and disconnection between the pin of the chip under test and the routing of the signal routing area; The mapping relationship between the channel index and the decoder output signal refers to whether the channel is enabled and, if enabled, whether it is valid; The mapping relationship between the activation instruction of each chip under test and the shared signal line indicates whether the chip under test receives the activation instruction and is activated.

4. The method for implementing chip testing according to claim 1, wherein: The specific steps for calculating chip power consumption deviation are as follows: The logic device in the activation control area selects each chip under test one by one according to the activation instruction, starts the high-temperature test chamber, and performs the high-temperature operation life test; The absolute deviation between the total power consumption and the average power consumption of the chip under test is calculated by integration to obtain the chip power consumption deviation.

5. The method for implementing chip testing according to claim 1, wherein: The specific steps of generating chip functional test data are as follows: Transmit test vectors through the signal ports of the performance test motherboard, record the output response of each channel, use a logic analyzer to capture the output signal, compare it with the expected output signal, and calculate the logic function coverage of each chip under test; By selecting all channels through the decoder and inputting a high-frequency clock signal, the clock frequency and signal delay of the chip are measured, and the absolute deviation between the measured actual clock frequency and the target clock frequency is calculated to obtain the timing error; Use an analog-to-digital converter to measure the output voltage of each channel, calculate the absolute average deviation between the output voltage of multiple channels of multiple chips under test and the target voltage, and obtain the output voltage deviation; The logic function coverage, timing error and output voltage deviation are output as chip functional test data.

6. The method for implementing chip testing according to claim 1, wherein: The entropy-based risk assessment method is used to calculate the failure probability of the chip under test. The specific steps are as follows: Normalize the chip power consumption deviation and chip function test data, and use the chip under test as an index to construct the state vector of the chip under test; For each chip under test, the state vector of the chip under test is discretized into state intervals; The histogram method is used to calculate the probability of the state vector of each chip under test in each state interval by counting the distribution frequency of the state vector of each chip under test in the state interval; Aggregate the probability of the state vector of the chip under test in each state interval and calculate the state entropy of the chip under test; By performing weighted normalization on the chip power consumption deviation and chip function test data, the degree to which the chip under test deviates from the expected performance is measured, and the failure score of the chip under test is obtained; Normalize the state entropy of the chip under test based on the number of state intervals; According to the failure score and normalized state entropy of the chip under test, the failure probability of the chip under test is calculated using an exponential weighting function.

7. The method for implementing chip testing according to claim 1, wherein: The chip test sub-board adopts a multi-layer printed circuit board with a high-temperature resistant coating on the surface. The pin array of the chip loading area supports multiple chip packaging types. The activation control area dynamically configures preset activation instructions through a programmable logic device.

8. A system for implementing chip testing, based on the method for implementing chip testing according to any one of claims 1 to 7, characterized in that: include, A mapping matrix module is used to assemble a chip test sub-board, which includes a chip loading area, a test connection area, a signal routing area, a channel selection area, and an activation control area. Multiple chips to be tested are loaded into the chip loading area, and a switch matrix, a decoder, and an activation control unit are configured to generate a chip mapping matrix. The power consumption deviation module is used to insert the chip test daughter board into the mainboard array of the high-temperature test platform, select a single chip for high-temperature operation life cycle testing, monitor the chip power consumption stability in real time, and calculate the chip power consumption deviation; Functional test module, used to perform logic function test, timing test and multi-channel voltage output test through automated pressing fixture alignment and pressure application, evaluate output consistency, and generate chip functional test data; The failure product evaluation module is used to calculate the failure probability of the chip under test based on the chip power consumption deviation and chip functional test data, using the entropy-based risk assessment method. By building a failure mechanism decision model to analyze the failure probability distribution, the power consumption stability test and functional test of the chip under test are optimized.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method for implementing chip testing according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method for implementing chip testing according to any one of claims 1 to 7 are implemented.

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