An instruction processing apparatus, method and related device

Abstract

The embodiment of the present application provides an instruction processing device, method and related equipment, wherein the instruction processing device comprises: an instruction fetching unit configured to read an instruction to be executed; a decoding unit configured to decode the instruction to be executed to generate a decoded instruction; an instruction dispatching unit configured to dispatch the decoded instruction to an instruction execution unit based on a disorderly dispatching rule; the disorderly dispatching rule at least comprises determining a dispatching sequence of the decoded instruction according to a busy state of the instruction execution unit; and the instruction execution unit is configured to execute the decoded instruction and generate an instruction execution result. The present application scheme can make the instruction execution unit obtain the instruction more timely, reduce the waiting time of the instruction in the front end of the pipeline, and improve the instruction processing efficiency.

Description

Technical Field

[0001] This application relates to the field of computer technology, specifically to an instruction processing apparatus, method, and related equipment. Background Technology

[0002] Processors process instructions in a pipelined manner. A typical pipeline usually includes stages such as instruction fetch, instruction decode, instruction dispatch, instruction execution, and instruction release. Currently, in the instruction decode stage, multiple instructions can be sequentially decoded within the same clock cycle. Then, in the instruction dispatch stage, the sequentially decoded instructions are sent sequentially to the respective instruction execution stages, allowing multiple instructions to be executed simultaneously during the instruction execution stage. Finally, in the instruction release stage, the executed instructions are sequentially released, thus completing the instruction execution process within the processor.

[0003] However, the current instruction processing efficiency still needs to be improved. Summary of the Invention

[0004] In view of this, embodiments of this application provide an instruction processing apparatus, method, and related devices to improve instruction processing efficiency.

[0005] To achieve the above objectives, the embodiments of this application provide the following technical solutions.

[0006] In a first aspect, embodiments of this application provide an instruction processing apparatus, including:

[0007] The instruction fetch unit is used to read the instruction to be executed;

[0008] The decoding unit is used to decode the instruction to be executed and generate a decoded instruction;

[0009] An instruction dispatch unit is used to dispatch the decoded instructions to the instruction execution unit based on an out-of-order dispatch rule; the out-of-order dispatch rule includes at least determining the dispatch order of the decoded instructions based on the busy state of the instruction execution unit;

[0010] The instruction execution unit is used to execute the decoding instructions and generate the instruction execution result.

[0011] Optionally, the instruction execution unit includes multiple execution subunits, and each execution subunit is used to execute an instruction of a certain type;

[0012] Determining the dispatch order of the decoded instructions based on the busy state of the instruction execution unit includes: prioritizing the dispatch of instructions that match the type of idle execution subunits based on the busy state of the instruction execution unit's execution subunits.

[0013] Optionally, the out-of-order distribution rule further includes determining the dispatch order of the decoded instructions based on the dependency relationship between the instructions.

[0014] Optionally, the instruction fetching unit is used to read multiple instructions to be executed in parallel and to reorder the multiple instructions to be executed during the step of reading the instructions to be executed;

[0015] The decoding unit is used to decode the instruction to be executed, and in the step of generating the decoded instruction, the reordered instruction to be executed is decoded;

[0016] Determining the dispatch order of the decoding instructions based on instruction dependencies includes: determining the instruction execution order of the decoding instructions; and dispatching the decoding instructions based on the determined instruction execution order.

[0017] Optionally, there are multiple instruction dispatch units. Each instruction dispatch unit is used to dispatch the decoded instructions to the instruction execution unit based on an out-of-order dispatch rule, including:

[0018] Determine the status of each instruction dispatch unit;

[0019] The instruction dispatch order of the decoded instructions is determined based on the state of the instruction dispatch unit.

[0020] Optionally, the state of the instruction dispatch unit includes:

[0021] The first state is used to indicate that the current instruction dispatching unit has the execution authority over the execution subunit in the instruction execution unit for a preset time period;

[0022] The second state is used to indicate that there is no physical connection between the current instruction dispatch unit and the execution subunit in the instruction execution unit;

[0023] The third state is used to indicate that the current instruction dispatching unit is allowed to receive instructions from the instruction dispatching unit in the second state;

[0024] The fourth state is used to indicate that the current instruction dispatch unit has the same execution authority as other instruction dispatch units for the execution subunits in the instruction execution unit;

[0025] The instruction dispatch unit is configured to determine the instruction dispatch order of the decoded instructions based on the state of the instruction dispatch unit, including:

[0026] For the same execution subunit in the instruction execution unit, if there is an instruction dispatch unit in the first state among the states of each instruction dispatch unit, then the highest priority is assigned to that instruction dispatch unit so that the instruction dispatch unit will preferentially dispatch the decoded instructions to that execution subunit.

[0027] For the same execution subunit in the instruction execution unit, if there is an instruction dispatch unit in the second state and an instruction dispatch unit in the third state, then the instruction dispatch unit in the third state is assigned a high weight so that the instruction dispatch unit in the third state will preferentially dispatch the decoded instruction to the execution subunit.

[0028] For the same execution subunit in the instruction execution unit, if the state of each instruction dispatch unit is the fourth state, then each instruction dispatch unit dispatches the decoded instructions to the execution subunit in a preset order.

[0029] Optionally, it also includes: a reordering buffer, which is used to store instruction information in the instruction dispatch process, and the instruction information in the instruction dispatch process is used as the information basis for the out-of-order distribution rule.

[0030] Optionally, the instruction execution unit is further configured to generate an instruction clear signal and send the instruction clear signal to the instruction fetch unit, the decoding unit, and the instruction dispatch unit to clear the instructions in the instruction fetch unit, the decoding unit, and the instruction dispatch unit.

[0031] Optionally, clearing the instructions in the instruction fetch unit, decoding unit, and instruction dispatch unit includes:

[0032] Check the age of each instruction;

[0033] If the age of the instruction is greater than the age of the instruction clearing signal, the instruction will be executed normally.

[0034] If the age of the instruction is less than or equal to the age of the instruction clearing signal, then the instruction is cleared.

[0035] Optionally, the decoding unit is further configured to generate an instruction clear signal and send the instruction clear signal to the instruction fetch unit to clear the instruction in the instruction fetch unit; wherein, when there are multiple instruction clear signals, the instruction clear signal with the oldest instruction age is selected as the target instruction clear signal.

[0036] Optionally, the decoding unit and the instruction dispatching unit are configured to correspond to each other. The instruction dispatching unit is used to dispatch the decoded instructions generated by the corresponding decoding unit to the instruction execution unit based on the out-of-order dispatching rules.

[0037] The configuration relationship between the decoding unit and the instruction dispatch unit is one-to-one, or multiple decoding units are configured to correspond to one instruction dispatch unit.

[0038] When a decoding instruction cache unit exists, the decoding instruction cache unit is configured as the decoding unit in conjunction with the instruction dispatch unit.

[0039] Secondly, embodiments of this application provide an instruction processing method applied to an instruction processing apparatus, the instruction processing apparatus including at least an instruction execution unit, the method comprising:

[0040] Read the instruction to be executed;

[0041] The instruction to be executed is decoded to generate a decoded instruction;

[0042] The decoding instructions are dispatched to the instruction execution unit based on the out-of-order dispatch rule, so that the instruction execution unit executes the decoding instructions and generates the instruction execution result; the out-of-order dispatch rule includes at least determining the dispatch order of the decoding instructions based on the busy state of the instruction execution unit.

[0043] Optionally, the instruction execution unit includes multiple execution subunits, and each execution subunit is used to execute an instruction of a certain type;

[0044] Determining the dispatch order of the decoding instructions based on the busy state of the instruction execution unit includes:

[0045] Based on the busy status of the execution subunits of the instruction execution unit, instructions that match the type of the idle execution subunit are selected for dispatch first.

[0046] Optionally, the out-of-order distribution rule may further include determining the dispatch order of the decoded instructions based on the dependency relationship between the instructions.

[0047] Optionally, in the step of reading the instructions to be executed, multiple instructions to be executed are read in parallel and the multiple instructions to be executed are reordered;

[0048] In the step of decoding the instruction to be executed and generating a decoded instruction, the reordered instruction to be executed is decoded.

[0049] Determining the dispatch order of the decoding instructions based on instruction dependencies includes: determining the instruction execution order of the decoding instructions; and dispatching the decoding instructions based on the determined instruction execution order.

[0050] Optionally, the instruction processing device further includes multiple instruction dispatch units, which are used to dispatch the decoded instructions to the instruction execution unit based on out-of-order dispatch rules;

[0051] The step of dispatching the decoded instructions to the instruction execution unit based on the out-of-order distribution rule includes:

[0052] Determine the status of each instruction dispatch unit;

[0053] The instruction dispatch order of the decoded instructions is determined based on the state of the instruction dispatch unit.

[0054] Optionally, the state of the instruction dispatching unit includes: a first state, indicating that the current instruction dispatching unit has execution authority over the execution subunit in the instruction execution unit for a preset time period; a second state, indicating that there is no physical connection between the current instruction dispatching unit and the execution subunit in the instruction execution unit; a third state, indicating that the current instruction dispatching unit is allowed to receive instructions from the instruction dispatching unit in the second state; and a fourth state, indicating that the current instruction dispatching unit has the same execution authority over the execution subunit in the instruction execution unit as other instruction dispatching units.

[0055] The method of determining the instruction dispatch order of the decoded instructions based on the state of the instruction dispatch unit includes:

[0056] For the same execution subunit in the instruction execution unit, if there is an instruction dispatch unit in the first state among the states of each instruction dispatch unit, then the highest priority is assigned to that instruction dispatch unit so that the instruction dispatch unit will preferentially dispatch the decoded instructions to that execution subunit.

[0057] For the same execution subunit in the instruction execution unit, if there is an instruction dispatch unit in the second state and an instruction dispatch unit in the third state, then the instruction dispatch unit in the third state is assigned a high weight so that the instruction dispatch unit in the third state will preferentially dispatch the decoded instruction to the execution subunit.

[0058] For the same execution subunit in the instruction execution unit, if the state of each instruction dispatch unit is the fourth state, then each instruction dispatch unit dispatches the decoded instructions to the execution subunit in a preset order.

[0059] Thirdly, embodiments of this application provide a processor including the instruction processing apparatus as described in the first aspect above.

[0060] Fourthly, embodiments of this application provide a computer device including a processor as described in the third aspect above.

[0061] Compared with the prior art, the technical solution of this application has the following advantages:

[0062] This application provides an instruction processing apparatus, method, and related devices. The instruction processing apparatus includes: an instruction fetching unit for reading an instruction to be executed; a decoding unit for decoding the instruction to be executed to generate a decoded instruction; an instruction dispatching unit for dispatching the decoded instruction to an instruction execution unit based on an out-of-order dispatching rule; the out-of-order dispatching rule at least includes determining the dispatching order of the decoded instructions based on the busy state of the instruction execution unit; and an instruction execution unit for executing the decoded instruction and generating an instruction execution result.

[0063] As can be seen, the instruction processing apparatus provided in this application dispatch unit dispatches the decoded instructions to the instruction execution unit based on out-of-order dispatch rules. The out-of-order dispatch rules include at least determining the dispatch order of the decoded instructions according to the busy state of the instruction execution unit, thereby enabling the instruction execution unit to obtain instructions more promptly, reducing the waiting time of instructions at the front end of the pipeline, and thus improving instruction processing efficiency. Attached Figure Description

[0064] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0065] Figure 1 This is a schematic diagram of a first optional structure of the instruction processing apparatus provided in the embodiments of this application;

[0066] Figure 2 This is a schematic diagram of a second optional structure of the instruction processing apparatus provided in the embodiments of this application;

[0067] Figure 3 This is a schematic diagram of a third optional structure of the instruction processing apparatus provided in the embodiments of this application;

[0068] Figure 4 This is a schematic diagram of a fourth optional structure of the instruction processing apparatus provided in the embodiments of this application;

[0069] Figure 5 This is a schematic diagram of a fifth optional structure of the instruction processing apparatus provided in the embodiments of this application;

[0070] Figure 6 This is a schematic diagram of the first optional allocation structure for instruction execution unit resources provided in an embodiment of this application;

[0071] Figure 7 This is a schematic diagram of a second optional allocation structure for instruction execution unit resources provided in an embodiment of this application;

[0072] Figure 8 This is a schematic diagram of a third optional allocation structure for instruction execution unit resources provided in an embodiment of this application;

[0073] Figure 9 This is a schematic diagram of the fourth optional allocation structure for instruction execution unit resources provided in the embodiments of this application;

[0074] Figure 10 This is a schematic diagram of the fifth optional allocation structure for instruction execution unit resources provided in an embodiment of this application;

[0075] Figure 11 This is a schematic diagram of the sixth optional allocation structure for instruction execution unit resources provided in the embodiments of this application;

[0076] Figure 12 This is a schematic diagram of the states of each instruction dispatching unit and different implementation units provided in the embodiments of this application;

[0077] Figure 13 This is a schematic diagram of an optional structure of a reordering buffer provided in an embodiment of this application to ensure the order of instruction submission;

[0078] Figure 14 This is a schematic diagram of an optional flowchart of the instruction processing method provided in the embodiments of this application. Detailed Implementation

[0079] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0080] As described in the background section, processors process instructions in a pipelined manner. A typical pipeline usually includes stages such as instruction fetch, instruction decoding, instruction dispatch, instruction execution, and instruction release. Currently, in the instruction decoding stage, multiple instructions can be sequentially decoded within the same clock cycle. Then, in the instruction dispatch stage, the sequentially decoded instructions are sent sequentially to the respective instruction execution stages, allowing multiple instructions to be executed simultaneously during the instruction execution stage. Finally, in the instruction release stage, the completed instructions are released sequentially, thus completing the instruction execution within the processor. However, current instruction processing efficiency still needs improvement.

[0081] The inventors argue that the reason instruction processing efficiency needs improvement lies in the fact that as the types and number of execution units in the processor's back-end pipeline (BD) continue to increase, the execution capability of the back end is continuously enhanced. However, in the existing instruction dispatch model, the front-end pipeline (FD) dispatches sequentially decoded instructions to subsequent instruction execution stages according to the original program sequence. This approach limits the execution capability of the front-end pipeline, preventing it from utilizing the abundant execution unit resources on the back-end pipeline, thus affecting overall instruction processing efficiency.

[0082] In view of this, embodiments of this application provide an instruction processing apparatus, method, and related devices, wherein the instruction processing apparatus includes: an instruction fetching unit for reading an instruction to be executed; a decoding unit for decoding the instruction to be executed to generate a decoded instruction; an instruction dispatching unit for dispatching the decoded instruction to an instruction execution unit based on an out-of-order dispatching rule; the out-of-order dispatching rule at least includes determining the dispatching order of the decoded instructions based on the busy state of the instruction execution unit; and an instruction execution unit for executing the decoded instruction and generating an instruction execution result.

[0083] As can be seen, the instruction processing apparatus provided in this application dispatch unit dispatches the decoded instructions to the instruction execution unit based on out-of-order dispatch rules. The out-of-order dispatch rules include at least determining the dispatch order of the decoded instructions according to the busy state of the instruction execution unit, thereby enabling the instruction execution unit to obtain instructions more promptly, reducing the waiting time of instructions at the front end of the pipeline, and thus improving instruction processing efficiency.

[0084] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0085] refer to Figure 1 , Figure 1 This is a schematic diagram of a first optional structure of the instruction processing apparatus provided in the embodiments of this application. For example... Figure 1 As shown, the instruction processing device may include:

[0086] Instruction fetch unit 32 is used to read the instruction to be executed;

[0087] The instruction fetch unit 32 reads the instructions to be executed to provide a basis for subsequent instruction processing. The instructions to be executed are those read sequentially from the instruction stream, and after being read, they are sent to subsequent hardware units for instruction processing. It is understood that the instructions to be executed in this embodiment can be understood as the currently read instructions.

[0088] In an optional implementation, the instruction processing apparatus may further include a branch prediction unit 31, used to predict the branch prediction result of branch instructions, so that the instruction fetch unit 32 reads the instructions to be executed according to the branch prediction result. In a specific implementation, the branch prediction unit 31 predicts the execution direction of branch instructions (such as conditional jumps, function calls, etc.) in the program, so that the instruction fetch unit 32 can decide in advance from which address to start reading instructions based on the prediction result of the branch prediction unit 31. For example, if the branch prediction unit 31 predicts that a certain conditional jump instruction will "jump", then the instruction fetch unit 32 will start reading instructions from the jump target address. If the prediction is "no jump", then the subsequent instructions are read sequentially.

[0089] In an optional implementation, the instruction fetch unit 32 can retrieve the instruction to be executed from the instruction memory (such as the instruction cache or main memory). The instruction fetch unit 32 generates the instruction address based on the value of the program counter (PC). If the branch prediction is correct, the PC is updated to the predicted target address; otherwise, if the prediction is incorrect, it needs to fall back to the correct execution path. To improve efficiency, the instruction fetch unit 32 typically prioritizes reading instructions from the instruction cache. If a cache miss occurs, the instruction needs to be read from main memory. After reading the instruction, the instruction fetch unit 32 can sequentially distribute the read instructions to the decoding unit. In an optional implementation, the instruction fetch unit 32 can also distribute the read instructions out of order to the decoding unit so that subsequent instruction execution units can utilize execution resources more efficiently. This out-of-order distribution allows the instruction fetch unit to distribute instructions outside the original program order.

[0090] In the specific implementation, the instructions fetched by the instruction fetch unit 32 are placed into an instruction queue or instruction window. The instruction queue temporarily stores multiple instructions for subsequent decoding units to select from. Furthermore, the instruction fetch unit 32 retrieves instructions from the instruction queue and delivers them to the decoding unit in out-of-order order. Out-of-order delivery avoids pipeline stalls caused by dependencies between instructions (such as data dependencies). The instruction fetch unit 32 can inject new instructions into the queue at a fixed or dynamic pace without waiting for previous instructions to complete execution.

[0091] A decoding unit is used to decode the instruction to be executed and generate decoded instructions. In this application, to improve the decoding efficiency during the decoding stage, two decoding units are used as an example. Figure 1 As shown in the decoding units 331 and 332, by setting two decoding units to work in parallel during the decoding stage, multiple instructions can be decoded simultaneously, which can significantly shorten the total time required for instruction decoding.

[0092] An instruction dispatch unit is used to dispatch the decoded instructions to the instruction execution unit based on an out-of-order dispatch rule; the out-of-order dispatch rule includes at least determining the dispatch order of the decoded instructions based on the busy state of the instruction execution unit.

[0093] This application dispatches the decoded instructions to the instruction execution unit based on an out-of-order dispatch rule through an instruction dispatch unit. The out-of-order dispatch rule includes at least determining the dispatch order of the decoded instructions according to the busy state of the instruction execution unit, thereby enabling the instruction execution unit to obtain instructions more promptly, reducing the waiting time of instructions at the front end of the pipeline, and thus improving instruction processing efficiency.

[0094] In a further optional implementation, the decoding unit and the instruction dispatch unit can be configured to have a corresponding relationship. Accordingly, the instruction dispatch unit can dispatch the decoded instructions generated by the corresponding decoding unit to the instruction execution unit based on out-of-order dispatch rules. The configuration relationship between the decoding unit and the instruction dispatch unit is one-to-one, which can effectively increase the bandwidth of decoding and dispatch. Alternatively, multiple decoding units can be configured to correspond to one instruction dispatch unit, thereby establishing multiple instruction processing channels while avoiding adding extra hardware area.

[0095] In an optional implementation, to buffer data from multiple decoding channels, two instruction dispatch units can be set up during the instruction dispatch stage. For example... Figure 1 As shown in the instruction dispatch unit 341 and instruction dispatch unit 342, by having two instruction dispatch units work in parallel, the speed of instruction dispatch is significantly improved, thereby enabling instructions to enter the execution stage more quickly, thus solving the problem that the execution capability of the front-end pipeline device is limited by the traditional sequential dispatch mechanism.

[0096] The instruction execution unit 350 is used to execute the decoding instructions and generate the instruction execution result.

[0097] The instruction execution unit 350 is one of the core modules in the processor pipeline. It is responsible for receiving instructions from the instruction dispatch unit, executing corresponding operations based on the instruction type, and ultimately generating the instruction execution result. In an optional implementation, the instruction execution unit 350 may include multiple execution subunits, each subunit executing one type of instruction. Specifically, as shown... Figure 1 As shown, the instruction execution unit 350 may include three execution subunits, which are specifically:

[0098] The memory access unit 351 is used to perform memory access operations. In a specific implementation, the memory access unit may include an address generation unit AGU, a loading unit LOAD, and a storage unit STORE.

[0099] The fixed-point arithmetic unit 352 is used to perform integer operations, such as addition, subtraction, multiplication, division, shifting, and logical operations (AND, OR, XOR). In a specific implementation, the fixed-point arithmetic unit may include an arithmetic logic unit (ALU) and a multiplication unit (MUL).

[0100] The floating-point arithmetic unit 353 is used to perform floating-point operations, such as floating-point addition, subtraction, multiplication, division, square root, etc. In a specific implementation, the specific implementation unit of the floating-point arithmetic unit may include a matrix operation unit FMX and a floating-point multiplication unit FMUL.

[0101] The instruction execution unit 350 receives decoded instructions and allocated execution resources from the instruction dispatch unit. The types of instructions may include, but are not limited to, arithmetic operations, logical operations, memory access, and branch jumps. Based on the instruction type, the unit dispatches the instructions to the corresponding execution subunits (such as memory access units, fixed-point arithmetic units, and floating-point arithmetic units). The execution subunits perform specific operations (such as addition, subtraction, multiplication, division, memory read / write, etc.) and generate the instruction execution results.

[0102] In an optional implementation, determining the dispatch order of the decoded instructions based on the busy state of the instruction execution unit may include: prioritizing the dispatch of instructions that match the type of idle execution subunits based on their busy state, thereby maximizing the resource utilization of the instruction execution unit while avoiding pipeline blockage and resource conflicts. By dynamically monitoring the busy state of execution subunits and prioritizing the dispatch of instructions that match the type of idle units, instruction-level parallelism and overall performance can be effectively improved.

[0103] In an optional implementation, the out-of-order dispatch rule further includes determining the dispatch order of the decoded instructions based on instruction dependencies. In a specific implementation, the instruction fetching unit, in its step of reading instructions to be executed, can read multiple instructions to be executed in parallel and reorder them; the decoding unit, in its step of decoding the instructions to be executed and generating decoded instructions, can decode the reordered instructions to be executed; correspondingly, in a specific out-of-order dispatch rule, determining the dispatch order of the decoded instructions based on instruction dependencies may include: determining the instruction execution order of the decoded instructions; and dispatching the decoded instructions based on the determined instruction execution order.

[0104] Understandably, by reordering multiple instructions to be executed based on the instruction fetch unit, out-of-order distribution of instructions can be achieved to speed up decoding. In this scenario, the order of instruction dependencies may be disrupted. Accordingly, the dispatch stage determines the dispatch order of the decoded instructions based on the instruction dependencies, and dispatches the decoded instructions based on the instruction execution order determined by the instruction dependencies, thereby improving instruction processing efficiency.

[0105] In an optional implementation, the instruction processing device may further include an instruction release unit 36, configured to submit the instruction execution results in a preset order, wherein the preset order is the logical order in which the instructions are executed. To ensure correct program execution, the execution results need to be submitted in the logical order of the instructions. The instruction release unit ensures the correctness and consistency of the final result, providing logically consistent execution results even during out-of-order execution.

[0106] In an optional implementation, the instruction processing apparatus may further include: a decoding instruction cache unit, which is used to cache the decoded instructions decoded by the decoding unit. In one optional implementation, refer to... Figure 2 , Figure 2 This is a schematic diagram of a second optional structure of the instruction processing apparatus provided in the embodiments of this application. For example... Figure 2 As shown, the instruction processing device may further include: a decode instruction buffer unit (such as...) Figure 2 As shown in the decoding instruction cache unit 333, the decoding instruction cache unit is used to cache the decoded instructions after the decoding unit decodes them. When these instructions need to be executed later, they can be read directly from the decoding instruction cache unit to avoid repeated decoding.

[0107] In a specific instruction processing path, when it is confirmed that the instruction type is a decoded instruction type, the corresponding instruction is sent to the decode instruction buffer unit, which then generates a corresponding decode instruction. In other words, in a specific instruction processing path, the decode instruction buffer unit can also be understood as a decoding unit.

[0108] In another alternative implementation, multiple decoding instruction buffer units can be configured. (See reference) Figure 3 , Figure 3 This is a schematic diagram of a third optional structure of the instruction processing apparatus provided in the embodiments of this application. For example... Figure 3 As shown, the instruction processing device may further include: multiple decoding instruction buffer units (such as...) Figure 3As shown in the decoding instruction cache unit 333 and decoding instruction cache unit 334, the decoding instruction cache unit is used to cache the instructions decoded by the decoding unit. When these instructions need to be executed later, they can be read directly from the decoding instruction cache unit to avoid repeated decoding.

[0109] It is understood that by using the decoding instruction cache unit as a decoding unit, the decoding instruction cache unit can be configured with the instruction dispatch unit to form a corresponding path. Specifically, one or more decoding instruction cache units can be configured with one instruction dispatch unit, or the decoding instruction cache unit can be configured together with the decoding unit into one instruction dispatch unit.

[0110] exist Figure 1 , Figure 2 and Figure 3 In the example shown, each path is matched with an instruction dispatch unit. This structure can effectively increase the bandwidth of the decoding and instruction dispatch units, but it introduces additional area increase. Therefore, in practical design implementations, for structures with more than two paths, only a small number (e.g., two) of instruction dispatch units are used to implement the out-of-order distribution of decoded instructions to the instruction execution unit. Here, a path refers to a path or pipeline stage within the processor where different instructions can be executed in parallel. In this application, a path refers to the path of parallel execution during the decoding stage. Figure 3 For example, in the decoding stage, the structure includes decoding unit 331, decoding unit 332, decoding instruction cache unit 333, and decoding instruction cache unit 334, which can be executed in parallel. Therefore, the structure can be described as having 4 paths.

[0111] by Figure 3 For example, in a structure with four paths, two instruction dispatch units can be used to distribute the decoded instructions out of order to the instruction execution unit. In one optional implementation, refer to... Figure 4 , Figure 4 This is a schematic diagram of a fourth optional structure of the instruction processing apparatus provided in the embodiments of this application, as shown below. Figure 4 As shown, the structure has four pathways and uses two instruction dispatch units to distribute the decoded instructions out of order to the instruction execution unit. Specifically, the two decoding units (such as...) Figure 4 The decoding units 331 and 332 share a single instruction dispatch unit 441 to distribute the decoded instructions out of order to the instruction execution unit; the two decoding instruction buffer units (such as...) Figure 4 The decoding instruction cache unit 333 and the decoding instruction cache unit 334 share a single instruction dispatch unit 442 to distribute the decoded instructions out of order to the instruction execution unit.

[0112] In another alternative implementation, refer to Figure 5 , Figure 5 This is a schematic diagram of a fifth optional structure of the instruction processing apparatus provided in the embodiments of this application, as shown below. Figure 5 As shown, the structure has four pathways and uses two instruction dispatch units to distribute the decoded instructions out of order to the instruction execution unit. This includes one decoding unit and one decoding instruction buffer unit (e.g., ...). Figure 5 The decoding unit 331 and the decoding instruction cache unit 333 (as shown) share an instruction dispatch unit 541 to distribute the decoded instructions out of order to the instruction execution unit; one decoding unit and one decoding instruction cache unit (as shown) Figure 5 The decoding unit 332 and the decoding instruction cache unit 334 share a single instruction dispatch unit 542 to distribute the decoded instructions out of order to the instruction execution unit.

[0113] In other words, the implementation of this application can improve the bandwidth capability of instruction dispatch by appropriately increasing the number of instruction dispatch units, without necessarily configuring a dedicated instruction dispatch unit for each decoding channel. Specifically, by reasonably expanding the scale of the instruction dispatch units, the efficiency of instruction distribution can be guaranteed while balancing hardware resource consumption and system complexity.

[0114] In the specific implementation, the instruction dispatch phase adopts an out-of-order sending rule. That is, when sending instructions, the order of the instruction stream is not guaranteed. As long as the execution subunit in the instruction execution unit has the execution capability (or receiving capability), the instruction can be sent from the instruction dispatch unit to the execution subunit in the instruction execution unit. Therefore, during the instruction sending process, it is necessary to identify the execution capability of the execution subunit in the backend pipeline instruction execution unit. Consequently, each instruction dispatch unit needs to identify the execution capability of the backend pipeline.

[0115] Therefore, in the case of multiple instruction dispatch units, each instruction dispatch unit needs to understand the execution capabilities of the backend pipeline to dispatch instructions reasonably. This makes it an additional problem to solve how to reasonably allocate backend execution units to different instruction dispatch units.

[0116] The following section, focusing on an architecture with four instruction dispatch units, uses the ALU and AGU implementation units within the instruction execution unit as examples to illustrate how to rationally allocate backend execution units to different instruction dispatch units. Specifically, the ALU performs arithmetic and logical operations, while the AGU generates and manages memory addresses.

[0117] In an alternative implementation, a shared allocation approach can be used, where the ALU and AGU can be dynamically shared by multiple instruction dispatch units, dynamically allocated based on instruction type or workload. For example... Figure 6 The ALU 200 can be dynamically shared by instruction dispatch unit 0, instruction dispatch unit 1, instruction dispatch unit 2 and instruction dispatch unit 3, and the AGU 300 can be dynamically shared by instruction dispatch unit 0, instruction dispatch unit 1, instruction dispatch unit 2 and instruction dispatch unit 3.

[0118] In one alternative implementation, a fixed allocation method can be used, where specific execution units (e.g., ALUs or AGUs) are fixedly assigned to a particular instruction dispatch unit. This means that each ALU is dedicated to handling instructions from its corresponding instruction dispatch unit. For example, Figure 7 ALU 201 is fixedly assigned to instruction dispatch unit 0, ALU 202 is fixedly assigned to instruction dispatch unit 1, ALU 203 is fixedly assigned to instruction dispatch unit 2, and ALU 204 is fixedly assigned to instruction dispatch unit 3.

[0119] In an alternative implementation, a hybrid allocation approach can be used, combining shared and fixed allocation methods. For example... Figure 7 AGU 301 and AGU 302 are allocated using a fixed allocation method, while AGU 303 is allocated using a shared allocation method. For example... Figure 8 ALU 201, ALU 204, AGU 301 and AGU 302 are allocated in a fixed manner, while ALU 202, ALU 203 and AGU 303 are allocated in a shared manner.

[0120] In an alternative implementation, a specific instruction dispatch unit may not be assigned a specific execution unit. That is, the specific instruction dispatch unit does not have the capability to dispatch instructions with specific functions. In this case, the corresponding instruction needs to be sent to another corresponding instruction dispatch unit to complete the instruction dispatch. For example... Figure 9 The instruction dispatch unit 0 does not have the ability to dispatch instructions that require arithmetic logic. Instead, it can send the instruction to the instruction dispatch unit 1 to complete the dispatch of the instruction.

[0121] In some optional embodiments, the execution sub-units in the instruction execution unit can also be allocated. The following describes how to reasonably allocate back-end execution units to different instruction dispatch units, taking the allocation of memory access unit, fixed-point arithmetic unit and floating-point arithmetic unit as an example for an architecture with 4 instruction dispatch units.

[0122] In one alternative implementation, a shared allocation approach can be used, where memory access units, fixed-point arithmetic units, and floating-point arithmetic units can be dynamically shared by multiple instruction dispatch units, dynamically allocated according to instruction type or workload. For example... Figure 10 The memory access unit 100 can be dynamically shared by instruction dispatch units 0, 1, 2, and 3; the fixed-point arithmetic unit 101 can be dynamically shared by instruction dispatch units 0, 1, 2, and 3; and the floating-point arithmetic unit 102 can be dynamically shared by instruction dispatch units 0, 1, 2, and 3. In this structure, each instruction dispatch unit can directly distribute the decoded instructions out of order to the execution subunits in the instruction execution unit.

[0123] In another alternative implementation, a specific instruction dispatch unit may not be assigned a specific execution subunit. That is, the specific instruction dispatch unit does not have the capability to dispatch instructions with specific functions. In this case, the corresponding instruction needs to be sent to another corresponding instruction dispatch unit to complete the instruction dispatch. For example... Figure 11 Instruction dispatch unit 0 does not have the capability to dispatch instructions requiring arithmetic logic; instead, it can send such instructions to instruction dispatch unit 1 to complete the dispatch. In this structure, instruction dispatch unit 0 does not have the capability to dispatch instructions to fixed-point arithmetic unit 101; it can send decoded instructions to other instruction dispatch units (such as...). Figure 11 The instruction dispatching unit 1 in the instruction dispatching unit completes the dispatching of the instruction.

[0124] Furthermore, during the instruction sending process, the instruction dispatching unit cannot blindly dispatch instructions. Instead, it must understand the execution capabilities of each execution subunit in the backend pipeline, such as what types of instructions they can handle and whether they are currently idle. Only in this way can instructions be reasonably dispatched to the appropriate execution units to ensure that instructions can be executed efficiently.

[0125] For ease of understanding, the following description focuses on an architecture with four instruction dispatch units, taking the execution subunits of the instruction execution unit, including the memory access unit, fixed-point arithmetic unit, and floating-point arithmetic unit, as an example.

[0126] In a specific implementation, the memory access unit may include an address generation unit (AGU), a loading unit (LOAD), and a storage unit (STORE). The fixed-point arithmetic unit may include an arithmetic logic unit (ALU) and a multiplication unit (MUL). The floating-point arithmetic unit may include a matrix operation unit (FMX) and a floating-point multiplication unit (FMUL). Therefore, determining the state of each instruction dispatch unit can be equivalent to determining the state of each instruction dispatch unit relative to the specific implementation unit of each execution subunit within the instruction execution unit.

[0127] In other words, it is necessary to determine the state of each instruction dispatch unit and address generation unit (AGU), load unit (LOAD), storage unit (STORE), arithmetic logic unit (ALU), multiplication unit (MUL), matrix operation unit (FMX), and floating-point multiplication unit (FMUL).

[0128] Furthermore, in this application, there are multiple instruction dispatch units. Each instruction dispatch unit is used to dispatch the decoded instructions to the instruction execution unit based on an out-of-order dispatch rule, and may include: determining the state of each instruction dispatch unit; and determining the instruction dispatch order of the decoded instructions based on the state of the instruction dispatch units. (Reference) Figure 12 The exemplary diagram illustrates the states of each instruction dispatch unit and different implementation units. The states of the instruction dispatch units may include:

[0129] The first state indicates that the current instruction dispatching unit has execution authority over the execution subunits in the instruction execution unit within a preset time period; in specific implementations, the state of each instruction dispatching unit over the specific implementation unit of each execution subunit in the instruction execution unit (e.g., ...) can be determined. Figure 12 (As shown in the "LOCK" box). It is worth noting that this type of operation does not specify the instruction dispatch unit; that is, it is performed based on the specific data dispatched by the instruction dispatch unit, or on statistical information regarding branch prediction errors in the instruction dispatch unit.

[0130] In an optional implementation, the first state can be dynamically allocated based on a global arbitration mechanism (such as time-slice polling, priority allocation, etc.). For example, in a processor, the arbitrator determines which instruction dispatch unit obtains LOCK privileges (i.e., the first state) based on the idle state of the instruction execution unit and the request priority of the instruction dispatch unit. This is relevant when multiple instruction dispatch units compete to access the same execution subunit's specific implementation unit (e.g., Figure 12 When the ALU column is shown in the diagram, the first state can be ensured by hardware mechanisms that there is only one instruction dispatch unit (e.g., ALU column) at any given time. Figure 12The instruction dispatch unit 1) in the application can use this specific implementation unit to avoid resource conflicts. The specific LOCK algorithm involved in the first state will not be described in this application.

[0131] The second state indicates that there is no physical connection between the current instruction dispatch unit and the execution subunit in the instruction execution unit. In a specific implementation, the state of each instruction dispatch unit relative to the specific implementation unit of each execution subunit in the instruction execution unit (e.g., ...) can be determined. Figure 12 (As shown in the "X" box). In other words, the instruction dispatch unit in the second state cannot send the corresponding instruction to the specific implementation unit of the execution subunit, such as... Figure 12 As shown, instruction dispatch unit 0 cannot dispatch floating-point related instructions to the specific implementation units FMUL and FMX of the execution subunit.

[0132] The third state indicates that the current instruction dispatch unit is permitted to receive instructions from the instruction dispatch unit in the second state. In a specific implementation, the state of each instruction dispatch unit relative to the specific implementation unit of each execution subunit within the instruction execution unit (e.g., ...) can be determined. Figure 12 (As shown in the "O" box). Figure 12 As shown, instruction dispatch unit 2 and instruction dispatch unit 3 are capable of receiving instructions from instruction dispatch unit 0 in the second state. Specifically, instruction dispatch unit 2 receives the instruction corresponding to FMUL sent by instruction dispatch unit 0, and instruction dispatch unit 3 receives the instruction corresponding to FMX sent by instruction dispatch unit 0.

[0133] The fourth state indicates that the current instruction dispatch unit has the same execution authority as other instruction dispatch units for the execution subunits within the instruction execution unit. In a specific implementation, the state of each instruction dispatch unit for the specific implementation unit of each execution subunit within the instruction execution unit (e.g., ...) can be determined. Figure 12 (as shown in the blank box in the image).

[0134] After determining the state of each instruction dispatch unit, the instruction dispatch order of the decoded instructions can be determined based on the state of the instruction dispatch units. Determining the instruction dispatch order of the decoded instructions based on the state of the instruction dispatch units may, for example, include:

[0135] For the same execution subunit within an instruction execution unit, if any instruction dispatch unit is in the first state among the various instruction dispatch units, then that instruction dispatch unit is assigned the highest priority, ensuring that it prioritizes dispatching decoded instructions to that execution subunit. In specific implementations, this can be applied to the same specific implementation unit within the same execution subunit of the instruction execution unit, such as... Figure 12As shown in the ALU column, instruction dispatch unit 1 is in the first state. In this case, the instruction dispatch unit will be given the highest priority until the instruction dispatch unit releases the LOCK state. Then, each instruction dispatch unit returns to the "blank" state, that is, it returns to the polling state.

[0136] For the same execution subunit within the instruction execution unit, if there are instruction dispatch units in both the second and third states, then the instruction dispatch unit in the third state is assigned a higher weight, so that it preferentially dispatches decoded instructions to that execution subunit. In specific implementations, this can be applied to the same specific implementation unit within the same execution subunit of the instruction execution unit, such as... Figure 12 As shown in the FMUL and FMX columns, instruction dispatch unit 2 is in the third state in the FMUL column, and instruction dispatch unit 3 is in the third state in the FMX column. Therefore, instruction dispatch unit 2 in the third state is assigned a high weight so that it prioritizes dispatching the decoded instructions to the specific implementation unit FMUL of the execution subunit; similarly, instruction dispatch unit 3 in the third state is assigned a high weight so that it prioritizes dispatching the decoded instructions to the specific implementation unit FMX of the execution subunit. Likewise, a round-robin algorithm is used among other instruction dispatch units within the same specific implementation unit of the same execution subunit.

[0137] For the same execution subunit within the instruction execution unit, if all instruction dispatch units are in the fourth state, then each instruction dispatch unit dispatches the decoded instructions to that execution subunit in a preset order. In specific implementations, this can be applied to the same specific implementation unit within the same execution subunit of the instruction execution unit, such as... Figure 12 As shown in the AGU, MUL, LOAD, and STORE columns, each instruction dispatch unit is in the fourth state. In this case, each instruction dispatch unit has fair instruction dispatch authority. Each instruction dispatch unit can distribute the decoded instructions to the specific implementation unit of the execution subunit in a preset order. For example, the dispatch order of instruction dispatch units in the Least Recently Used (LRU) algorithm or the First In First Out (FIFO) algorithm can be used.

[0138] In this embodiment, the instruction processing device further includes a reordering buffer, which stores instruction information from the instruction dispatch process. This instruction information serves as the information basis for the out-of-order distribution rule. Since out-of-order distribution is used in the instruction dispatch stage, the execution of out-of-order distribution relies on the reordering buffer (ROB) to manage the order of instructions, ensuring that the final result is consistent with sequential execution.

[0139] In the specific implementation, refer to Figure 13 The exemplary embodiment of this application provides an optional structure diagram of a reordering buffer for ensuring instruction submission order. In this application, the reordering buffer can be divided into three regions. Region 1 stores branch prediction information, such as "branch prediction direction" and "branch prediction target address"; Region 2 stores instruction dispatch information, such as "instruction decoding information" and "decoding unit redirect information"; Region 3 stores instruction execution process information, such as "branch execution direction". Specifically, the decoding unit redirect information refers to the need to redirect subsequent instruction fetching, decoding, and other operations to a new address or path due to a change in the instruction execution path caused by some reason (such as branch prediction error, exception handling, interrupt handling, etc.).

[0140] Furthermore, the update logic for different regions in the reordering buffer varies depending on functional requirements. The following details this in conjunction with specific scenarios:

[0141] For area 1, which is used to store branch prediction information, when the branch prediction unit generates a new branch prediction result, the corresponding result can be updated to area 1 of the ROB. For example, if the branch prediction unit's prediction condition jump instruction is "jump", then this result is immediately written to area 1 of the ROB.

[0142] For area 2, which is used to store information related to instruction dispatch, it can be updated after the instruction is decoded (i.e., the DECODE stage), or when the instruction dispatch unit sends the instruction (i.e., the DISPATCH stage), or some information can be updated in the DECODE stage and some information can be updated in the DISPATCH stage.

[0143] For region 3, which is used to store instruction execution process information, it can be updated during the execution of the instruction execution unit.

[0144] In this application, if an anomaly is detected in the pipeline (such as branch prediction failure, anomaly occurrence, resource conflict, etc.), an anomaly handling mechanism (such as a Flush operation) can be triggered. The Flush operation is an important mechanism in pipeline processing, mainly used to clear or reset instructions or data in the pipeline under specific circumstances to ensure the correctness and consistency of instruction execution. The Flush operation is described in detail below:

[0145] Scenario 1: A flush operation occurs during the instruction execution phase.

[0146] In practical implementations, when the instruction execution unit detects an exception (such as an illegal instruction or a division-by-zero error), it needs to flush subsequent instructions in the pipeline to prevent the exception from affecting the execution of other instructions. Alternatively, when the branch prediction unit makes a prediction error, the instruction execution unit needs to flush the instructions that entered the pipeline due to the misprediction. Or, when resources needed by the instruction execution unit (such as registers, ALU, etc.) are occupied by other instructions and cannot be released within the expected time, the pipeline needs to be flushed to resolve the conflict.

[0147] Furthermore, when the instruction execution unit detects that an instruction clearing operation needs to be performed, it can generate an instruction clearing signal (such as a Flush signal) and send the instruction clearing signal to the instruction fetch unit, decode unit, and instruction dispatch unit to clear the instructions in the instruction fetch unit, decode unit, and instruction dispatch unit. In other words, the instruction execution unit can generate a Flush operation to clear the instructions in the pipeline's front end.

[0148] Specifically, clearing instructions in the instruction fetch unit, decode unit, and instruction dispatch unit can include: checking the age of each instruction; if the instruction's age is greater than the age of the instruction clear signal, the instruction is executed normally; if the instruction's age is less than or equal to the age of the instruction clear signal, the instruction is cleared. In other words, the instruction execution unit can check the age of each instruction (i.e., the order in which they entered the pipeline) according to the order of instructions in the reorder buffer to determine instruction release. For example, if the instruction's age is greater than the age of the Flush signal, the instruction will be executed normally and released sequentially; if the instruction's age is less than or equal to the age of the Flush signal, the instruction will be cleared and not released.

[0149] Scenario 2: A flush operation occurs during the instruction decoding stage.

[0150] In practical implementations, when the decoding unit or decoding instruction cache unit detects an instruction format error or an invalid opcode, it needs to clear subsequent instructions in the pipeline. Alternatively, when resources needed by the decoding unit or decoding instruction cache unit (such as the decoder, register file, etc.) are occupied by other instructions and cannot be released within the expected time, the pipeline needs to be cleared to resolve the conflict.

[0151] Furthermore, when the decoding unit detects that an instruction clearing operation needs to be performed, it generates an instruction clearing signal and sends the instruction clearing signal to the instruction fetch unit to clear the instructions in the instruction fetch unit. Since this application uses multiple channels in the decoding stage, when an instruction decoding error is detected on one channel and an instruction clearing signal (such as a Flush signal) needs to be sent, the status of other channels needs to be checked (in this application, this status can be read from the reordering buffer). When multiple channels simultaneously generate instruction clearing signals (such as Flush signals), the instruction clearing signal with the oldest instruction age is selected as the target instruction clearing signal.

[0152] Specifically, when a channel detects that a clearing operation needs to be performed, it needs to check the command status of other channels. The actions taken will vary depending on the status of each channel, as categorized below:

[0153] (1) If the age of the instruction in other channels is less than the age of the instruction clear signal, the corresponding instruction decoding / instruction dispatch channel will be blocked to prevent erroneous instructions from continuing to enter the pipeline.

[0154] (2) If the age of the instruction in other channels is greater than the age of the instruction clear signal, then it is necessary to keep comparing each instruction until an instruction with an age less than that of the instruction clear signal is found, and then block the instruction decoding / instruction dispatch channel corresponding to the instruction with an age less than that of the instruction clear signal.

[0155] For example, the decoding stage has three channels: Channel A, Channel B, and Channel C. When Channel A detects a decoding error and triggers a flush operation: if the instruction age in Channel B is less than the instruction clear signal age in Channel A, then Channel B is blocked to prevent the erroneous instruction from continuing into the pipeline. If the instruction age in Channel C is greater than the instruction clear signal age in Channel A, then the comparison of instructions in Channel C continues until an instruction with an age less than the instruction clear signal age is found, and that channel is blocked.

[0156] Next, when multiple channels simultaneously generate instruction clear signals (such as Flush signals), the instruction clear signal with the oldest instruction age is selected as the target instruction clear signal. This target instruction clear signal is then sent to the branch prediction unit and instruction fetch unit located at the front end of the decoding stage. This allows the branch prediction unit to regenerate the instruction fetch address, and the instruction fetch unit to reread the instruction information. For example, when Channel A detects a decoding error and triggers a Flush operation, if Channel C also triggers a Flush operation, and the age of its Flush instruction is greater than that of Channel A's Flush instruction, then Channel C's Flush operation is selected as the target instruction clear signal.

[0157] In a further implementation, when there is an instruction age that is less than the age of the Flush signal, the Flush signal needs to be sent to the instruction release unit so that the instruction release unit will not release the instruction.

[0158] It should be noted that this application does not restrict or specify the specific implementation method of PIPE SWITCH, but rather allows the use of existing PIPE SWITCH technology. For example, PIPESWITCH can be implemented in the following ways:

[0159] Using TAKEN BRANCH (executed branch): When the program executes a branch instruction, it selects the appropriate path to perform a PIPE SWITCH based on the branch prediction result.

[0160] Specific branch types: Select the appropriate PIPE SWITCH strategy based on the type of branch instruction (such as conditional branch, unconditional branch, etc.).

[0161] Using a random correct instruction boundary: In some cases, a correct instruction boundary can be randomly selected for PIPE SWITCH to achieve specific performance or functional goals.

[0162] Train a more suitable instruction boundary: Train a more suitable instruction boundary through machine learning or other optimization algorithms to improve the efficiency and accuracy of PIPE SWITCH.

[0163] In this application, there are no restrictions on the mapping relationship between multiple threads and multiple pipes; it is only necessary to establish the mapping relationship between multiple threads and multiple pipes. Each thread can be allocated a different number of pipes to adapt to different load requirements. For example, thread A is allocated 3 pipes, and thread B is allocated 1 pipe.

[0164] Multi-Pipeline refers to multiple pipelines in a processor that execute in parallel, with each pipeline processing instructions independently. SMT (Simultaneous Multi-Threading) allows a single physical core to execute multiple threads simultaneously, improving efficiency by sharing resources (such as the ALU and registers). In SMT mode, multiple threads share pipeline resources, requiring the establishment of a thread-pipeline mapping. Mapping methods can include static mapping where each thread is allocated a fixed portion of the pipeline, and dynamic mapping where pipeline allocation is dynamically adjusted based on thread load. For example, if the processor has four pipelines and two threads are running, two pipelines can be allocated to thread A and two to thread B; or the allocation can be dynamically adjusted to a 3:1 ratio.

[0165] This application also provides an instruction processing method applied to an instruction processing apparatus, wherein the instruction processing apparatus includes at least an instruction execution unit, see reference. Figure 14 An exemplary flowchart of an instruction processing method is shown, such as... Figure 14 As shown, the method may include the following steps:

[0166] Step S100: Read the instruction to be executed.

[0167] The instruction to be executed refers to the instructions read sequentially from the instruction stream, and after being read, they are sent to subsequent hardware units for instruction processing. It is understood that the instruction to be executed in this embodiment can be understood as the currently read instruction.

[0168] In an optional implementation, after reading the instructions to be executed, the read instructions can be sequentially distributed to the decoding unit. Alternatively, the read instructions can be distributed to the decoding unit out of order, allowing subsequent instruction execution units to utilize execution resources more efficiently. This out-of-order distribution allows the instruction fetching unit to distribute instructions outside the original program order.

[0169] Step S200: Decode the instruction to be executed to generate a decoded instruction.

[0170] Step S300: The decoded instructions are dispatched to the instruction execution unit based on the out-of-order distribution rule, so that the instruction execution unit executes the decoded instructions and generates the instruction execution result.

[0171] The out-of-order dispatch rule includes at least determining the dispatch order of the decoded instructions based on the busy state of the instruction execution unit.

[0172] This application dispatches the decoded instructions to the instruction execution unit based on an out-of-order dispatch rule, which includes at least determining the dispatch order of the decoded instructions according to the busy state of the instruction execution unit. This enables the instruction execution unit to obtain instructions more promptly, reduces the waiting time of instructions at the front end of the pipeline, and thus improves instruction processing efficiency.

[0173] In a specific implementation, the instruction execution unit includes multiple execution subunits, each subunit executing a specific type of instruction. Determining the dispatch order of the decoded instructions based on the busy state of the instruction execution unit can include: prioritizing the dispatch of instructions matching the type of idle execution subunits based on their busy state, thereby maximizing the resource utilization of the instruction execution unit while avoiding pipeline congestion and resource conflicts. By dynamically monitoring the busy state of execution subunits and prioritizing the dispatch of instructions matching the type of idle units, instruction-level parallelism and overall performance can be effectively improved.

[0174] In an optional implementation, the out-of-order dispatch rule further includes determining the dispatch order of the decoded instructions based on instruction dependencies. In a specific implementation, the step of reading the instructions to be executed involves reading multiple instructions to be executed in parallel and reordering them; the step of decoding the instructions to be executed to generate decoded instructions involves decoding the reordered instructions to be executed; and the step of determining the dispatch order of the decoded instructions based on instruction dependencies includes: determining the instruction execution order of the decoded instructions; and dispatching the decoded instructions based on the determined instruction execution order.

[0175] In an optional implementation, the instruction processing apparatus further includes a plurality of instruction dispatch units, which are used to dispatch the decoded instructions to the instruction execution unit based on an out-of-order dispatch rule.

[0176] The step of dispatching the decoded instructions to the instruction execution unit based on the out-of-order distribution rule includes:

[0177] Determine the status of each instruction dispatch unit;

[0178] The instruction dispatch order of the decoded instructions is determined based on the state of the instruction dispatch unit.

[0179] The states of the instruction dispatching unit include: a first state, indicating that the current instruction dispatching unit has execution authority over the execution subunits in the instruction execution unit for a preset time period; a second state, indicating that there is no physical connection between the current instruction dispatching unit and the execution subunits in the instruction execution unit; a third state, indicating that the current instruction dispatching unit is allowed to receive instructions from the instruction dispatching unit in the second state; and a fourth state, indicating that the current instruction dispatching unit has the same execution authority over the execution subunits in the instruction execution unit as other instruction dispatching units.

[0180] Furthermore, determining the instruction dispatch order of the decoded instructions based on the state of the instruction dispatch unit may include:

[0181] For the same execution subunit in the instruction execution unit, if there is an instruction dispatch unit in the first state among the states of each instruction dispatch unit, then the highest priority is assigned to that instruction dispatch unit so that the instruction dispatch unit will preferentially dispatch the decoded instructions to that execution subunit.

[0182] For the same execution subunit in the instruction execution unit, if there is an instruction dispatch unit in the second state and an instruction dispatch unit in the third state, then the instruction dispatch unit in the third state is assigned a high weight so that the instruction dispatch unit in the third state will preferentially dispatch the decoded instruction to the execution subunit.

[0183] For the same execution subunit in the instruction execution unit, if the state of each instruction dispatch unit is the fourth state, then each instruction dispatch unit dispatches the decoded instructions to the execution subunit in a preset order.

[0184] This application also provides a processor, including the instruction processing apparatus as described above.

[0185] This application also provides a computer device including the processor described above.

[0186] The foregoing describes multiple embodiment schemes provided by the embodiments of this application. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and published by the embodiments of this application.

[0187] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. An instruction processing device, characterized in that, include: The instruction fetch unit is used to read the instruction to be executed; The decoding unit is used to decode the instruction to be executed and generate a decoded instruction; An instruction dispatch unit is used to dispatch the decoded instructions to the instruction execution unit based on an out-of-order dispatch rule. The out-of-order dispatch rule at least includes determining the dispatch order of the decoded instructions based on the busy state of the instruction execution unit. There are multiple instruction dispatch units, and each instruction dispatch unit is used to dispatch the decoded instructions to the instruction execution unit based on the out-of-order dispatch rule, including: determining the state of each instruction dispatch unit; and determining the instruction dispatch order of the decoded instructions based on the state of the instruction dispatch unit. The state of each instruction dispatch unit includes: a first state, indicating that the current instruction dispatch unit has execution permission for the execution subunits in the instruction execution unit within a preset time period; a second state, indicating that there is no physical connection between the current instruction dispatch unit and the execution subunits in the instruction execution unit; a third state, indicating that the current instruction dispatch unit is allowed to receive instructions from instruction dispatch units in the second state; and a fourth state, indicating that the current instruction dispatch unit has the same execution permission for the execution subunits in the instruction execution unit as other instruction dispatch units. The instruction execution unit is used to execute the decoding instructions and generate the instruction execution result.

2. The instruction processing apparatus as described in claim 1, characterized in that, The instruction execution unit includes multiple execution subunits, and each execution subunit is used to execute an instruction of a certain type. Determining the dispatch order of the decoded instructions based on the busy state of the instruction execution unit includes: prioritizing the dispatch of instructions that match the type of idle execution subunits based on the busy state of the instruction execution unit's execution subunits.

3. The instruction processing apparatus as described in claim 1, characterized in that, The out-of-order distribution rule also includes determining the dispatch order of the decoded instructions based on the dependency relationship between the instructions.

4. The instruction processing apparatus as described in claim 3, characterized in that, The instruction fetching unit is used to read multiple instructions to be executed in parallel and to reorder the multiple instructions to be executed during the step of reading the instructions to be executed. The decoding unit is used to decode the instruction to be executed, and in the step of generating the decoded instruction, the reordered instruction to be executed is decoded; Determining the dispatch order of the decoding instructions based on the instruction dependencies includes: determining the instruction execution order of the decoding instructions; Based on the determined instruction execution order, the decoding instructions are dispatched.

5. The instruction processing apparatus as described in claim 1, characterized in that, The instruction dispatch unit is configured to determine the instruction dispatch order of the decoded instructions based on the state of the instruction dispatch unit, including: For the same execution subunit in the instruction execution unit, if there is an instruction dispatch unit in the first state among the states of each instruction dispatch unit, then the highest priority is assigned to that instruction dispatch unit so that the instruction dispatch unit will preferentially dispatch the decoded instructions to that execution subunit. For the same execution subunit in the instruction execution unit, if there is an instruction dispatch unit in the second state and an instruction dispatch unit in the third state, then the instruction dispatch unit in the third state is assigned a high weight so that the instruction dispatch unit in the third state will preferentially dispatch the decoded instruction to the execution subunit. For the same execution subunit in the instruction execution unit, if the state of each instruction dispatch unit is the fourth state, then each instruction dispatch unit dispatches the decoded instructions to the execution subunit in a preset order.

6. The instruction processing apparatus as described in claim 1, characterized in that, Also includes: A reordering buffer is used to store instruction information in the instruction dispatch process, which serves as the information basis for the out-of-order distribution rule.

7. The instruction processing apparatus as described in claim 1, characterized in that, The instruction execution unit is further configured to generate an instruction clear signal and send the instruction clear signal to the instruction fetch unit, the decoding unit, and the instruction dispatch unit to clear the instructions in the instruction fetch unit, the decoding unit, and the instruction dispatch unit.

8. The instruction processing apparatus as described in claim 7, characterized in that, The clearing of instructions in the instruction fetching unit, decoding unit, and instruction dispatching unit includes: Check the age of each instruction; If the age of the instruction is greater than the age of the instruction clearing signal, the instruction will be executed normally. If the age of the instruction is less than or equal to the age of the instruction clearing signal, then the instruction is cleared.

9. The instruction processing apparatus as claimed in claim 1, characterized in that, The decoding unit is further configured to generate an instruction clear signal and send the instruction clear signal to the instruction fetch unit to clear the instruction in the instruction fetch unit; wherein, when there are multiple instruction clear signals, the instruction clear signal with the oldest instruction age is selected as the target instruction clear signal.

10. The instruction processing apparatus as claimed in claim 1, characterized in that, The decoding unit and the instruction dispatching unit are configured to correspond to each other. The instruction dispatching unit is used to dispatch the decoding instructions generated by the corresponding decoding unit to the instruction execution unit based on the out-of-order distribution rule. The configuration relationship between the decoding unit and the instruction dispatch unit is one-to-one, or multiple decoding units are configured to correspond to one instruction dispatch unit. When a decoding instruction cache unit exists, the decoding instruction cache unit is configured as the decoding unit in conjunction with the instruction dispatch unit.

11. An instruction processing method, characterized in that, Applied to an instruction processing apparatus, the instruction processing apparatus including at least an instruction execution unit, the method includes: Read the instruction to be executed; The instruction to be executed is decoded to generate a decoded instruction; The decoded instructions are dispatched to the instruction execution unit based on an out-of-order dispatch rule, so that the instruction execution unit executes the decoded instructions and generates an instruction execution result; the out-of-order dispatch rule includes at least determining the dispatch order of the decoded instructions based on the busy state of the instruction execution unit; The instruction processing device further includes multiple instruction dispatch units, which are used to dispatch the decoded instructions to the instruction execution unit based on out-of-order dispatch rules. The step of dispatching the decoded instructions to the instruction execution unit based on the out-of-order distribution rule includes: determining the state of each instruction dispatch unit; determining the instruction dispatch order of the decoded instructions based on the state of the instruction dispatch unit; the state of the instruction dispatch unit includes: a first state, used to indicate that the current instruction dispatch unit has the execution permission for the execution sub-unit in the instruction execution unit for a preset time period; a second state, used to indicate that there is no physical connection between the current instruction dispatch unit and the execution sub-unit in the instruction execution unit; a third state, used to indicate that the current instruction dispatch unit allows receiving instructions from the instruction dispatch unit in the second state; and a fourth state, used to indicate that the current instruction dispatch unit has the same execution permission for the execution sub-unit in the instruction execution unit as other instruction dispatch units.

12. The instruction processing method as described in claim 11, characterized in that, The instruction execution unit includes multiple execution subunits, and each execution subunit is used to execute an instruction of a certain type. Determining the dispatch order of the decoding instructions based on the busy state of the instruction execution unit includes: Based on the busy status of the execution subunits of the instruction execution unit, instructions that match the type of the idle execution subunit are selected for dispatch first.

13. The instruction processing method as described in claim 11, characterized in that, The out-of-order distribution rule also includes determining the dispatch order of the decoded instructions based on the dependency relationship between the instructions.

14. The instruction processing method as described in claim 13, characterized in that, In the step of reading the instructions to be executed, multiple instructions to be executed are read in parallel and the instructions to be executed are reordered. In the step of decoding the instruction to be executed and generating a decoded instruction, the reordered instruction to be executed is decoded. Determining the dispatch order of the decoding instructions based on the instruction dependencies includes: determining the instruction execution order of the decoding instructions; Based on the determined instruction execution order, the decoding instructions are dispatched.

15. The instruction processing method as described in claim 11, characterized in that, in, The method of determining the instruction dispatch order of the decoded instructions based on the state of the instruction dispatch unit includes: For the same execution subunit in the instruction execution unit, if there is an instruction dispatch unit in the first state among the states of each instruction dispatch unit, then the highest priority is assigned to that instruction dispatch unit so that the instruction dispatch unit will preferentially dispatch the decoded instructions to that execution subunit. For the same execution subunit in the instruction execution unit, if there is an instruction dispatch unit in the second state and an instruction dispatch unit in the third state, then the instruction dispatch unit in the third state is assigned a high weight so that the instruction dispatch unit in the third state will preferentially dispatch the decoded instruction to the execution subunit. For the same execution subunit in the instruction execution unit, if the state of each instruction dispatch unit is the fourth state, then each instruction dispatch unit dispatches the decoded instructions to the execution subunit in a preset order.

16. A processor, characterized in that, Includes the instruction processing apparatus as described in any one of claims 1-10.

17. A computer device, characterized in that, Includes the processor as described in claim 16.

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