Multi-CPU (Central Processing Unit) USB (Universal Serial Bus) multiplexing method and device

Abstract

The invention relates to the technical field of data processing, in particular to a multi-CPU USB multiplexing method and device, and the device comprises an interrupt module which comprises a first interrupt unit connected with a master CPU and a second interrupt unit connected with a slave CPU; the USB module is used for outputting interruption information based on the endpoint equipment; the main CPU is used for responding to the received interrupt information of the endpoint equipment and determining the event type of the interrupt information; determining whether to communicate through a second interruption unit based on the event type of the interruption information; the first interruption unit is controlled to enter an enabling state; the slave CPU is used for controlling the second interrupt unit to enter an enabling state; and when the second interrupt unit receives the interrupt information sent by the first interrupt unit, whether information is returned to the main CPU through the first interrupt unit is determined based on the event type of the interrupt information. According to the device, communication among multiple CPUs is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to a USB multiplexing method and device for multiple CPUs in the technical field of data processing. Background Art

[0002] In the world of system-on-chips (SoCs), power consumption is a critical parameter. To reduce SoC power consumption, a Universal Serial Bus (USB) channel typically supports only one central processing unit (CPU). The USB is directly connected to this CPU, notifying the CPU via internal interrupts (INT interrupts). This requires multiple USB channels to meet communication needs, resulting in high costs.

[0003] Based on this, a USB channel is designed in the related technology to support multiple CPUs. The USB provides multiple interrupts connected to each CPU respectively. Although it can meet the needs of communicating with multiple CPUs via USB, if the USB host sends standard protocol commands such as reset, this solution cannot respond normally. The only solution is to reset the entire chip. It takes a long time for the chip to resume normal operation after reset. In addition, reset is not allowed in many business scenarios. In some business scenarios, the chip cannot be restored to the working state before reset after reset, which cannot meet business needs. Summary of the Invention

[0004] The object of the present invention is to provide a multi-CPU USB multiplexing method and device, and the technical solution adopted is as follows: In a first aspect, an embodiment of the present invention provides a multi-CPU USB multiplexing method, the method comprising: Adopt USB module based on endpoint device to output interrupt information; In response to the received interrupt information, determining an event type of the interrupt information using the main CPU; Determining, based on the event type of the interrupt information, whether to communicate through a second interrupt unit connected to the slave CPU; and controlling a first interrupt unit connected to the master CPU to enter an enabled state so as to communicate with the slave CPU based on the first interrupt unit; wherein the first interrupt unit and the second interrupt unit are capable of communicating with each other; Using the slave CPU to control the second interrupt unit to enter an enabled state, so as to communicate with the master CPU based on the second interrupt unit; When the second interrupt unit receives the interrupt information sent by the first interrupt unit, it determines whether to return information to the main CPU through the first interrupt unit based on the event type of the interrupt information.

[0005] In some possible implementations, the main CPU is further used to determine whether it is necessary to receive the processing completion information returned by the slave CPU based on the event type and preset type of the interrupt information; if the event type meets the preset type, upon receiving the processing completion information, it is determined whether it is necessary to operate other endpoint devices used by the main CPU.

[0006] In some possible implementations, the main CPU is further configured to determine whether to return information to the USB host end based on the event type if the event type does not meet the preset type.

[0007] In some possible implementations, the main CPU is further configured to determine a preset interruption with the USB module; control the preset interruption to enter an enabled state, and receive the interruption information based on the preset interruption in the enabled state.

[0008] In some possible implementations, the preset interrupt serves as a common interrupt of the master CPU and the slave CPU, connected to the master CPU and the slave CPU respectively, for notifying the master CPU and the slave CPU of the interrupt information of the endpoint device.

[0009] In some possible implementations, the slave CPU is further configured to disable a preset interruption between the slave CPU and the USB module to shield the interruption information; and receive the interruption information sent by the first interruption unit based on the second interruption unit being in an enabled state.

[0010] In some possible implementations, the slave CPU is also used to determine whether it is necessary to operate the endpoint device corresponding to the slave CPU based on the event type of the interrupt information; if it is necessary to operate the endpoint device corresponding to the slave CPU, when it is detected that the operation is completed, it is determined whether to notify the main CPU through the first interrupt unit based on the event type.

[0011] In some possible implementations, the interrupt module is further used to connect a first interrupt unit corresponding to the master CPU and a second interrupt unit corresponding to the slave CPU based on a common path; and synchronize information between the master CPU and the slave CPU through the first interrupt unit and the second interrupt unit.

[0012] In some possible implementation manners, the main CPU is further configured to determine that the interrupt information is received when a standard protocol command sent by the USB host end is received.

[0013] In a second aspect, an embodiment of the present application provides a multi-CPU USB multiplexing device, which comprises: an interrupt module, comprising a first interrupt unit connected with the main CPU and a second interrupt unit connected with the slave CPU, the first interrupt unit and the second interrupt unit being capable of communicating with each other; a USB module configured to output interrupt information based on an endpoint device; the main CPU is configured to determine an event type of the interrupt information in response to the received interrupt information of the endpoint device, determine whether to communicate through the second interrupt unit based on the event type of the interrupt information, and control the first interrupt unit to enter an enabled state to communicate with the slave CPU based on the first interrupt unit; the slave CPU is configured to control the second interrupt unit to enter an enabled state to communicate with the main CPU based on the second interrupt unit, and determine whether to return information to the main CPU through the first interrupt unit based on the event type of the interrupt information when the second interrupt unit receives interrupt information sent by the first interrupt unit.

[0014] In a third aspect, a computer program product is provided, which comprises computer program code, and when the computer program code is run on a computer, the computer is caused to execute the method of the first aspect.

[0015] In a fourth aspect, a computer readable storage medium is provided, which stores computer program code, and when the computer program code is run on a computer, the computer is caused to execute the method of the first aspect.

[0016] The present invention has the following beneficial effects: In a multi-CPU USB multiplexing device, a first interrupt unit matching the master CPU and a second interrupt unit matching the slave CPU are designed in the interrupt module, and the first interrupt unit and the second interrupt unit are capable of communicating with each other. After the USB module outputs interrupt information based on the endpoint device, the master CPU determines the event type of the interrupt information in response to the received interrupt information; based on the event type of the interrupt information, determines whether to communicate through the second interrupt unit; and controls the first interrupt unit to enter an enabled state to communicate with the slave CPU based on the first interrupt unit. In this way, the master CPU receives information sent by the slave CPU through the first interrupt unit in the interrupt module, and sends the interrupt information to the slave CPU through the second interrupt unit connected to the slave CPU. The slave CPU controls the second interrupt unit to enter an enabled state to communicate with the master CPU based on the second interrupt unit. When the second interrupt unit receives the interrupt information sent by the first interrupt unit, it determines whether to return information to the master CPU through the first interrupt unit based on the event type of the interrupt information. In this way, in a multi-CPU USB multiplexing device, by designing an interrupt module, a separate interrupt unit is provided for each other CPU, so that the current CPU can be notified of the status of other endpoint devices except the corresponding endpoint device through these interrupt units, and each CPU can interrupt each other through the interrupt unit, thereby achieving the purpose of communication between multiple CPUs. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions and advantages of the embodiments of the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 This is a schematic diagram of the structure of a multi-CPU USB multiplexing device provided in the related art; Figure 2 This is a schematic diagram of the structure of a multi-CPU USB multiplexing device provided by an embodiment of the present invention; Figure 3 This is another structural diagram of a multi-CPU USB multiplexing device provided by an embodiment of the present invention; Figure 4 This is a schematic diagram of a multi-CPU USB multiplexing method according to an embodiment of the present invention; Figure 5 It is a structural diagram of a computer device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0019] To further illustrate the technical means and effectiveness of the present invention in achieving its intended objectives, the following, in conjunction with the accompanying drawings and preferred embodiments, describes in detail the specific implementation, structure, features, and effectiveness of a multi-CPU USB multiplexing method proposed in accordance with the present invention. In the following description, references to "one embodiment" or "another embodiment" do not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics of one or more embodiments may be combined in any suitable manner.

[0020] In the description of the embodiments of the present invention, unless otherwise specified, " / " means or, for example, A / B can mean A or B: "and / or" in the text is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present invention, "multiple" refers to two or more than two.

[0021] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to imply or suggest relative importance or implicitly indicate the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features.

[0022] Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

[0023] In the related art, the communication between USB and CPU is as follows Figure 1 As shown, one USB channel usually only supports one CPU. The USB is directly connected to the CPU and notifies the CPU through the INT interrupt. In this way, although the implementation logic is simple, if there are multiple CPUs, multiple USBs are required to meet the communication needs, which is costly.

[0024] Based on this, the embodiment of the present invention provides a multi-CPU USB multiplexing device. The specific solution of the multi-CPU USB multiplexing device provided by the present invention is described in detail below with reference to the accompanying drawings. Figure 2 , which shows a schematic structural diagram of a multi-CPU USB multiplexing device provided by an embodiment of the present invention, the device 200 includes: The interrupt module 201 includes: a first interrupt unit connected to the master CPU, and a second interrupt unit connected to the slave CPU. The first interrupt unit 205 and the second interrupt unit 206 can communicate with each other.

[0025] Here, the interrupt module may be implemented by a plurality of interrupt units capable of communicating with each other, each interrupt unit independently corresponding to a CPU. The first interrupt unit and the second interrupt unit may be internal interrupts (ie, INT interrupts).

[0026] In some possible implementations, the interrupt module is further configured to connect a first interrupt unit corresponding to the master CPU and a second interrupt unit corresponding to the slave CPU based on a common path; and synchronize information between the master CPU and the slave CPU via the first interrupt unit and the second interrupt unit. Figure 3 As shown, the interrupt module includes: CPU_INT(0), CPU_INT(1), ... CPU_INT(n). CPU_INT(0) sends status information of other CPUs to CPU(0), and CPU_INT(n) sends status information of other CPUs to CPU(n). Each CPU has a separate CPU_INT(n) to send to the corresponding CPU(n) to notify the current CPU(n) of the status of the EP endpoints used in addition to EP0. In addition, each CPU can interrupt each other through CPU_INT(n).

[0027] The USB module 202 is configured to output interrupt information based on an endpoint device.

[0028] USB has 16 endpoints (EPs), from EP0 to EP15. When a USB is first connected, enumeration occurs through EP0. During enumeration, a CPU must process the data sent. Only after successful enumeration can the other EPs function properly. During USB operation, actions such as suspend and disconnect are notified to the CPU through EP0, requiring the CPU to perform deinitialization. During this time, the EPs cannot send or receive data normally.

[0029] After USB is suspended / disconnected, it can be restored through actions such as reset / resume / plugging and unplugging the USB interface. These actions are also notified to the CPU through EP0, and the CPU needs to initialize the channels used by each.

[0030] USB may reset at any time. This action is notified to the CPU through EP0. The CPU needs to deinitialize each channel and then re-enumerate it. During this process, the channel is unavailable. All of the above EP0 information processing may involve processing logic for each channel, and there may be requirements for the order in which they are completed.

[0031] In the USB module, interrupt information is generated and output through EP0.

[0032] The main CPU 203 is used to determine the event type of the interrupt information received from the endpoint device in response to the interrupt information; determine whether to communicate through the second interrupt unit based on the event type of the interrupt information; and control the first interrupt unit to enter an enabled state to communicate with the slave CPU based on the first interrupt unit.

[0033] Here, the main CPU can be Figure 3 In CPU(0), the slave CPU can be Figure 3 CPU (1) to CPU (n) in the USB host. When the main CPU receives a standard protocol command sent by the USB host, it determines that the interrupt information has been received. In this way, for standard protocol commands such as reset, the interrupt information output by EP0 is received, and the information status of EP0 is synchronized between the CPUs through the interrupt units corresponding to the CPUs in the interrupt module.

[0034] The main CPU is further configured to determine a preset interruption with the USB module; control the preset interruption to enter an enabled state; and receive the interruption information based on the preset interruption in the enabled state.

[0035] Here, the preset interrupt is used as a common interrupt of the master CPU and the slave CPU, connected to the master CPU and the slave CPU respectively, for notifying the master CPU and the slave CPU of the interrupt information of the endpoint device. Figure 3 As shown, the preset interrupt can be Figure 3 The INT interrupt between the USB and CPU (0) in the USB is given to all CPUs. This interrupt is used to notify the status of EP0.

[0036] The main CPU is also used to determine whether it is necessary to receive the processing completion information returned by the slave CPU based on the event type and preset type of the interrupt information; if the event type meets the preset type, when the processing completion information is received, it is determined whether it is necessary to operate other endpoint devices used by the main CPU.

[0037] Here, if the interrupt message's event type falls within a preset category, then the main CPU determines that it needs to receive a processing completion message from the slave CPU. For example, if the interrupt message's event type requires handshake communication, the main CPU determines that it needs to wait for the processing completion message from the slave CPU. Only after receiving the processing completion message from the slave CPU will the main CPU proceed to the next processing step. Specifically, after receiving the processing completion message from the slave CPU, the main CPU will determine whether it needs to perform any operations on other endpoint devices used by the main CPU, such as disabling / enabling data communication and data backup for other endpoint devices.

[0038] The main CPU is further configured to determine whether to return information to the USB host end based on the event type if the event type does not meet the preset type.

[0039] Here, if the event type does not meet the preset type, that is, there is no need to wait for the processing completion information returned from the CPU. After receiving the interrupt information, by determining the event type of the interrupt information, it is determined whether to return information to the USB host end, and whether it is necessary to operate other endpoint devices used by the main CPU.

[0040] For example, if the event type of the interrupt information indicates that processing of the interrupt information is related to other endpoint devices, it is determined that operations need to be performed on the other endpoint devices used by the main CPU; for example, disabling / enabling data communication and data backup of the other endpoint devices.

[0041] In some possible implementations, such as Figure 3 As shown, the software implementation process of the main CPU (i.e. CPU (0)) is: The first step is to enable INT interrupt so that the interrupt information of USB EP0 can be received; The second step is to enable the CPU_INT(0) interrupt so that the interrupt information of other CPUs can be received. Step 3: When receiving the INT interrupt (i.e., interrupt information), determine whether the following steps 4 and 5 need to be performed based on the received EP0 event type: The fourth step is to determine whether to notify CPU (1) through CPU_INT (1), and according to the EP0 event type, determine whether it is necessary to wait for CPU (1) to return the processing completion information. If waiting is required, the fifth step can be executed only after waiting for the completion information. The fifth step is to determine whether to operate other EP endpoints used by CPU0. If necessary, operate other EP endpoints; this operation includes whether to disable / enable data communication and data backup of other EP endpoints.

[0042] Step 6: After processing steps 4 and 5, determine whether to return information to the USB host based on the received EP0 event type.

[0043] The slave CPU 204 is used to control the second interrupt unit to enter an enabled state so as to communicate with the main CPU based on the second interrupt unit; when the second interrupt unit receives the interrupt information sent by the first interrupt unit, it determines whether to return information to the main CPU through the first interrupt unit based on the event type of the interrupt information.

[0044] Here, the master CPU synchronizes the interrupt information output by EP0 to the slave CPU via the second interrupt unit, thereby synchronizing the states between the master and slave CPUs. The slave CPU is configured to disable the preset interrupt with the USB module to mask the interrupt information; and receives the interrupt information sent by the first interrupt unit based on the second interrupt unit being enabled.

[0045] like Figure 3 As shown, the slave CPU (for example, CPU (1) to CPU (n)) disables INT interrupt to shield the interrupt information output by USB EP0. At the same time, the interrupt unit corresponding to the slave CPU is enabled, as shown in Figure 3 As shown, taking the slave CPU as CPU (1) as an example, CPU_INT (1) is enabled so that the interrupt information sent by CPU (0) can be received.

[0046] In some possible implementations, the slave CPU is also used to determine whether it is necessary to operate the endpoint device corresponding to the slave CPU based on the event type of the interrupt information; if it is necessary to operate the endpoint device corresponding to the slave CPU, when it is detected that the operation is completed, it is determined whether to notify the main CPU through the first interrupt unit based on the event type.

[0047] Here, after receiving an interrupt message via the second interrupt unit, the slave CPU determines the event type of the interrupt message and decides whether to perform an operation on the endpoint device corresponding to the slave CPU. This operation includes whether to disable or enable data communication and data backup for other EP endpoints. After completing the operation, the slave CPU determines whether to notify the master CPU of the completion of the operation via the first interrupt unit based on the event type.

[0048] In some possible implementations, Figure 3 The CPU (1) in the figure is used as an example to illustrate the software processing flow of the CPU (1): The first step is to disable the INT (preset interrupt) interrupt so that the interrupt information of USB EP0 (endpoint device) can be shielded.

[0049] The second step is to enable CPU_INT(1) (i.e. the second interrupt unit) so that it can receive interrupt information from CPU(0) (i.e. the main CPU).

[0050] The third step is to determine whether to operate the EP endpoint used by it according to the event type of the interrupt information sent by CPU (0) when the CPU_INT (1) interrupt is received; this operation includes whether to disable / enable data communication and data backup of other EP endpoints; Step 4. After processing step 3, determine whether it is necessary to notify CPU (0) through CPU_INT (0) based on the type of event received.

[0051] The embodiment of the present invention provides a multi-CPU USB multiplexing method, such as Figure 4 As shown, it can be achieved through Figure 4 The steps shown achieve: 401, using the USB module based on the endpoint device to output interrupt information; 402, in response to the received interrupt information, using the main CPU to determine the event type of the interrupt information; 403, based on the event type of the interrupt information, determining whether to communicate through the second interrupt unit connected to the slave CPU; and controlling the first interrupt unit connected to the master CPU to enter an enabled state, so as to communicate with the slave CPU based on the first interrupt unit; The first interruption unit and the second interruption unit are capable of communicating with each other.

[0052] 404, using the slave CPU to control the second interrupt unit to enter an enabled state, so as to communicate with the master CPU based on the second interrupt unit; 405 : When the second interrupt unit receives the interrupt information sent by the first interrupt unit, determine whether to return information to the main CPU through the first interrupt unit based on the event type of the interrupt information.

[0053] Through steps 401 to 405 above, after the USB module outputs interrupt information based on the endpoint device, the master CPU determines the event type of the interrupt information in response to the received interrupt information; based on the event type of the interrupt information, determines whether to communicate through the second interrupt unit; the master CPU receives the information sent by the slave CPU via the first interrupt unit in the interrupt module, and sends the interrupt information to the slave CPU via the second interrupt unit connected to the slave CPU. The slave CPU controls the second interrupt unit to enter an enabled state to communicate with the master CPU based on the second interrupt unit; when the second interrupt unit receives the interrupt information sent by the first interrupt unit, it determines whether to return information to the master CPU via the first interrupt unit based on the event type of the interrupt information. In this way, in a multi-CPU USB multiplexing device, the interrupt module is designed to provide a separate interrupt unit for each additional CPU, so that these interrupt units can notify the current CPU of the status of endpoint devices other than the corresponding endpoint device. Furthermore, each CPU can interrupt each other through the interrupt units, achieving communication between multiple CPUs. Even in a reset scenario, data communication between the master CPU and the slave CPU can still be relatively simple and accurate, thereby meeting service requirements.

[0054] Optionally, the transmission medium may be a wired link (such as, but not limited to, coaxial cable, optical fiber, and digital subscriber line (DSL)) or a wireless link (such as, but not limited to, wireless Fidelity (WIFI), Bluetooth, and mobile device network). It should be noted that the system provided in the above embodiment is only illustrated by the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the computer device can be divided into different functional modules to complete all or part of the functions described above. In addition, the method embodiments provided in the above embodiments belong to the same concept. The specific implementation process is detailed in the method embodiments and will not be repeated here.

[0055] Figure 5 FIG. 1 is a schematic diagram of the structure of a computer device provided by an embodiment of the present invention. For example, Figure 5 As shown, the computer device 500 includes: a memory 501, a processor 502, and a computer program 503 stored in the memory 501 and running on the processor 502, wherein when the processor 502 executes the computer program 503, the computer device can execute any of the multi-CPU USB multiplexing methods described above.

[0056] In addition, an embodiment of the present invention also protects a system, which may include a memory and a processor, wherein an executable program code is stored in the memory, and the processor is used to call and execute the executable program code to perform a multi-CPU USB multiplexing method provided by an embodiment of the present invention. This embodiment can divide the system into functional modules according to the above method example. For example, it can correspond to each functional module, or two or more functions can be integrated into one processing module, and the above integrated module can be implemented in the form of hardware. It should be noted that the division of modules in this embodiment is schematic, which is only a logical function division, and there may be other division methods in actual implementation. It should be noted that all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module, and will not be repeated here.

[0057] It should be understood that the system provided in this embodiment is used to execute the above-mentioned multi-CPU USB multiplexing method, and therefore can achieve the same effect as the above-mentioned implementation method. In the case of adopting an integrated unit, the system may include a processing module and a storage module. Specifically, when the system is applied to a device, the processing module can be used to control and manage the actions of the device. The storage module can be used to support the device in executing mutual program codes, etc. Specifically, the processing module can be a processor or a controller, which can implement or execute the various exemplary logic blocks, modules and circuits described in conjunction with the disclosure of the present invention. The processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of digital signal processing (DSP) and a microprocessor, etc., and the storage module can be a memory.

[0058] In addition, the system provided by an embodiment of the present invention may be specifically a chip, component, or module. The chip may include a connected processor and memory; the memory is used to store instructions. When the processor calls and executes the instructions, the chip can execute the multi-CPU USB multiplexing method provided in the above embodiment. This embodiment also provides a computer-readable storage medium storing computer program code. When the computer program code is executed on a computer, the computer executes the above-mentioned method steps to implement the multi-CPU USB multiplexing method provided in the above embodiment.

[0059] This embodiment also provides a computer program product. When the computer program product is run on a computer, it causes the computer to execute the above-mentioned steps to implement a multi-CPU USB multiplexing method provided in the above embodiment. The system, computer-readable storage medium, computer program product, or chip provided in this embodiment are all used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects of the corresponding method provided above, and will not be repeated here. Through the description of the above embodiments, those skilled in the art will understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual application, the above-mentioned functions can be distributed to different functional modules as needed, that is, the internal structure of the system is divided into different functional modules to complete all or part of the functions described above. In the embodiments provided by the present invention, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not implemented. On the other hand, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, system or unit, which may be electrical, mechanical or other forms.

[0060] It should be noted that the above-mentioned order of the embodiments of the present invention is for description only and does not represent the advantages and disadvantages of the embodiments. The processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multi-task processing and parallel processing are also possible or may be advantageous. The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referenced to each other. Each embodiment focuses on the differences from other embodiments. The above content is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed by the present invention, which should be covered within the scope of protection of the present invention.

Claims

1. A multi-CPU USB multiplexing device, characterized in that: The multi-CPU USB multiplexing device comprises: The interrupt module includes: a first interrupt unit connected to the master CPU, and a second interrupt unit connected to the slave CPU, wherein the first interrupt unit and the second interrupt unit are capable of communicating with each other; USB module, used to output interrupt information based on endpoint devices; The master CPU is configured to, in response to the received interrupt information from the endpoint device, determine an event type of the interrupt information; determine whether to communicate through the second interrupt unit based on the event type of the interrupt information; and control the first interrupt unit to enter an enabled state to communicate with the slave CPU based on the first interrupt unit; The slave CPU is used to control the second interrupt unit to enter an enabled state so as to communicate with the master CPU based on the second interrupt unit; when the second interrupt unit receives the interrupt information sent by the first interrupt unit, it determines whether to return information to the master CPU through the first interrupt unit based on the event type of the interrupt information.

2. A multi-CPU USB multiplexing device according to claim 1, characterized in that: The main CPU is also used to determine whether it is necessary to receive the processing completion information returned by the slave CPU based on the event type and preset type of the interrupt information; if the event type meets the preset type, when the processing completion information is received, it is determined whether it is necessary to operate other endpoint devices used by the main CPU.

3. A multi-CPU USB multiplexing device according to claim 2, characterized in that: The main CPU is further configured to determine whether to return information to the USB host end based on the event type if the event type does not meet the preset type.

4. A multi-CPU USB multiplexing device according to claim 1, characterized in that: The main CPU is further configured to determine a preset interruption between the main CPU and the USB module; control the preset interruption to enter an enabled state; and receive the interruption information based on the preset interruption in the enabled state.

5. A multi-CPU USB multiplexing device according to claim 4, characterized in that: The preset interrupt serves as a common interrupt of the master CPU and the slave CPU, is connected to the master CPU and the slave CPU respectively, and is used to notify the master CPU and the slave CPU of the interrupt information of the endpoint device.

6. A multi-CPU USB multiplexing device according to claim 1, characterized in that: The slave CPU is further configured to prohibit a preset interruption between the slave CPU and the USB module to shield the interruption information; and receive the interruption information sent by the first interruption unit based on the second interruption unit being in an enabled state.

7. A multi-CPU USB multiplexing device according to claim 6, characterized in that: The slave CPU is also used to determine whether it is necessary to operate the endpoint device corresponding to the slave CPU based on the event type of the interrupt information; if it is necessary to operate the endpoint device corresponding to the slave CPU, when it is detected that the operation is completed, it is determined whether to notify the main CPU through the first interrupt unit based on the event type.

8. The multi-CPU USB multiplexing device according to claim 1, characterized in that: The interrupt module is further configured to connect a first interrupt unit corresponding to the master CPU and a second interrupt unit corresponding to the slave CPU based on a common path; and synchronize information between the master CPU and the slave CPU through the first interrupt unit and the second interrupt unit.

9. The multi-CPU USB multiplexing device according to claim 1, characterized in that: The main CPU is further configured to determine that the interrupt information is received when a standard protocol command sent by the USB host is received.

10. A multi-CPU USB multiplexing method, characterized in that: A USB multiplexing device for multiple CPUs, and a USB multiplexing method for multiple CPUs, comprising: Adopt USB module based on endpoint device to output interrupt information; In response to the received interrupt information, determining an event type of the interrupt information using the main CPU; Determining, based on the event type of the interrupt information, whether to communicate through a second interrupt unit connected to the slave CPU; and controlling a first interrupt unit connected to the master CPU to enter an enabled state so as to communicate with the slave CPU based on the first interrupt unit; wherein the first interrupt unit and the second interrupt unit are capable of communicating with each other; Using the slave CPU to control the second interrupt unit to enter an enabled state, so as to communicate with the master CPU based on the second interrupt unit; When the second interrupt unit receives the interrupt information sent by the first interrupt unit, it determines whether to return information to the main CPU through the first interrupt unit based on the event type of the interrupt information.

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