Industrial controller fast and slow operation cycle full data backup method

Abstract

The invention discloses a full-data backup method for a fast and slow operation period of an industrial controller. The full-data backup method comprises the following steps: detecting whether a main power supply is powered down or a backup command is received by an FPGA (Field Programmable Gate Array); if yes, the FPGA writes the latest fast-cycle integrity data into the power-down nonvolatile storage chip by comparing the integrity marks and the timestamps of the fast-cycle data of the data A area and the data B area of the memory chip; then, the FPGA writes the completeness data of the latest slow period into the power-down nonvolatile storage chip by comparing the completeness marks and the timestamps of the data of the slow period of the data A area and the data B area of the memory chip; according to the data backup method, data does not need to be selected, one cycle of complete data can be recovered under the condition of power failure or no power failure, common memory chips and power failure non-volatile storage chips are used, and cost and implementation complexity are effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of data protection and backup, and in particular to a method for backing up full data of fast and slow operation cycles of an industrial controller. Background Art

[0002] In the field of industrial automation control, the operating environment of the controller is very complex, with strong electromagnetic radiation and harsh ambient temperature, which may cause the controller to work abnormally or crash and restart. During the restart process, the data in the memory is lost, and the configuration and other data need to be reloaded. The reloaded data does not contain the previous calculation data.

[0003] Currently, there are two most commonly used methods to solve this problem on the market: one is to store important data in storage media such as SRAM that can retain data without power failure. However, this type of media not only has a small capacity and requires data selection, but is also expensive and data will still be lost in the event of a power failure. The other is to run both programs and data in magnetic memory media. This type of memory media can also keep data unchanged in the event of a power failure, but the cost of this type of media is extremely high, and there are currently few options available for domestic manufacturers. Obviously, how to achieve data backup and complete data recovery at low cost is a technical problem that urgently needs to be solved in the industry.

[0004] Based on this, the purpose of the present invention is to address the deficiencies of the above-mentioned existing technologies and provide a full data backup method for fast and slow operation cycles of industrial controllers. Not only can the method realize the recovery of complete data of a cycle with or without power failure without selecting data, but the devices used are common memory chips and non-volatile storage chips in the event of power failure, effectively reducing costs and implementation complexity. Summary of the Invention

[0005] In response to the defects in the prior art, the purpose of the present invention is to provide a full data backup method for fast and slow operation cycles of industrial controllers, which not only can achieve the need to select data, but also can restore the complete data of a cycle with or without power failure. The devices used are common memory chips and power-off non-volatile storage chips, which effectively reduces the cost and implementation complexity, so as to solve the problems existing in data backup and data integrity recovery in the prior art.

[0006] Specifically, the technical problem to be solved by the present invention is to address the deficiencies in the above-mentioned prior art. The present invention provides a method for backing up full data of fast and slow operation cycles of an industrial controller, comprising:

[0007] The FPGA detects whether the main power supply has been lost or a backup command has been received;

[0008] If it exists, the FPGA compares the integrity mark and timestamp of the fast cycle data in the data area A and data area B of the memory chip, and writes the latest fast cycle integrity data into the power-off non-volatile storage chip;

[0009] Then, the FPGA compares the integrity mark and timestamp of the slow cycle data in data area A and data area B of the memory chip, and writes the latest slow cycle integrity data into the power-off non-volatile storage chip.

[0010] In one embodiment of the method for full data backup of fast and slow operation cycles of an industrial controller according to the present invention, the FPGA detects whether a main power failure occurs or a backup command is received, including:

[0011] If a main power failure is detected, the FPGA uses the backup power supply and turns off the backup power supply after the slow cycle data is written to the power-down non-volatile memory chip;

[0012] If a backup command is received, after the slow cycle data is written into the power-off non-volatile storage chip, the backup completion is reported.

[0013] In one embodiment of the method for full data backup of fast and slow operation cycles of an industrial controller according to the present invention, the main power supply is used to power the entire board, and the backup power supply is only used to power the FPGA, memory chip, and power-off non-volatile storage chip;

[0014] The CPU is responsible for communication and computing operations, while the FPGA is responsible for data backup and recovery. The CPU and FPGA communicate using a high-speed bus and a low-speed bus. The high-speed bus uses its high bandwidth throughput to transmit data that needs to be saved. The low-speed bus uses its high real-time capability to transmit register data between the CPU and FPGA, and transmit data between the FPGA and memory chips and power-off non-volatile storage chips.

[0015] In one embodiment of the method for full data backup of fast and slow operation cycles of an industrial controller according to the present invention, the high-speed bus includes but is not limited to parallel LVDS or serial Aurora, SRIO, PCIe; the low-speed bus includes but is not limited to SPI, LIO, UART.

[0016] In one embodiment of the method for full data backup of fast and slow operation cycles of an industrial controller according to the present invention, the memory chip is a DDR chip, and the power-off non-volatile storage chip includes but is not limited to a flash and an SD card.

[0017] In one embodiment of the method for full data backup of fast and slow operation cycles of an industrial controller according to the present invention, the memory chip is divided into data area A and data area B. The data distribution in data area A and data area B is the same as the data size and relative position in the CPU memory; the last position of the data in data area A and data area B is the fast cycle and slow cycle data backup completion mark and timestamp. If the data backup is completed, the data backup completion mark will be set and the timestamp of the completion of the backup will be recorded.

[0018] In one embodiment of the full data backup method for fast and slow operation cycles of an industrial controller according to the present invention, the CPU writes commands to corresponding registers through a low-speed bus, and the fast cycle and slow cycle correspond to registers with different addresses respectively; if a fast cycle command is received, the fast cycle command is cached in a fast cycle queue, and if a slow cycle command is received, the slow cycle command is replaced in a slow cycle queue; wherein the depth of the fast cycle queue is not less than the number of fast cycle data areas in the CPU memory, and the depth of the slow cycle queue is not less than the number of slow cycle data areas in the CPU memory; the FPGA reads the command from the cache queue, parses the length of the data to be read and the address of the data in the CPU memory, and reads the data of the corresponding address and length through the high-speed bus.

[0019] In one embodiment of the full data backup method for the fast and slow operation cycles of an industrial controller according to the present invention, each time the CPU completes calculation of a data area, it combines the data length and the memory base address where the data is located into a command and sends it to the corresponding register in the FPGA through a low-speed bus.

[0020] In one embodiment of the method for full data backup of fast and slow operation cycles of an industrial controller according to the present invention, an FPGA cyclically monitors a fast cycle command queue and a slow cycle command queue. When the fast cycle command queue is detected to be not empty, the FPGA reads a fast cycle command, verifies the correctness of the command, and discards it if it is incorrect. If it is correct, the FPGA parses the base address and length of the data in the CPU memory from the command and passes these two parameters to the high-speed bus interface. Upon receiving these two parameters, the high-speed bus interface initiates a read operation command to read the data into the memory chip under the FPGA. After completion, the FPGA continues to check whether the fast cycle command queue is empty. If not, the data read operation continues until the fast cycle command queue is detected to be empty. When the fast cycle command queue is empty, the FPGA checks the slow cycle command queue. If it is empty, the FPGA checks the fast cycle command queue. If not, the FPGA reads a slow cycle command once to verify the correctness of the command, and discards it if it is incorrect. If the data base address and length are correctly parsed, they are passed to the high-speed bus. The high-speed bus reads the data and stores it in the memory chip under the FPGA. After execution, the fast cycle command queue is checked.

[0021] In one embodiment of the method for backing up all data in fast and slow operation cycles of an industrial controller according to the present invention, when the controller is restarted after power failure and the data recovery process is executed, the CPU writes to the register via the low-speed bus to start the FPGA recovery program. The FPGA reads the storage status area of ​​the power-off non-volatile memory chip, reads data starting from the address with the latest timestamp, and writes the read data to the corresponding memory of the CPU, thereby achieving the effect of data recovery.

[0022] When the controller recovers data without power failure, the CPU starts the FPGA recovery program by writing registers through the low-speed bus. The FPGA reads the fast and slow cycle data integrity marks and timestamps of the data areas A and B of the memory chip below it, finds the latest fast and slow cycle integrity data by comparing the integrity marks and timestamps, and writes the data to the CPU memory through the high-speed bus to achieve the effect of data recovery.

[0023] Compared with the prior art, the present invention has the following positive effects:

[0024] 1. The high-speed bus read operation between the FPGA and the CPU proposed in the present invention responds very quickly, and the space size of the memory chip under the FPGA and the power-off non-volatile storage medium (power-off non-volatile storage chip) can be selected according to actual needs. This allows the data in the CPU, including configuration data and operation data, to be saved and restored at startup without the need to select data.

[0025] 2. This invention proposes integrity marking of the fast and slow cycles of Data Areas A and B in the FPGA memory, resolving the issue of double-cycle data caused by incomplete calculation of operation cycles during abnormal operation. The fast and slow cycles can be combined using the integrity markings and timestamps of Data Areas A and B to produce a single, up-to-date data set with both fast and slow cycles calculated, thus preventing incomplete data caused by abnormal CPU downtime.

[0026] 3. Due to the nature of non-volatile storage media that are susceptible to power failure, they have a lifespan issue. The lifespan of the media is positively correlated with the number of writes. Therefore, reducing the number of writes can increase the service life of the media. Therefore, multiple write operations to the same area should be minimized. Therefore, the present invention divides the media storage space so that multiple spaces can be used cyclically. By comparing timestamps, the latest data can be loaded.

[0027] 4. Since the calculation time of the fast cycle is faster than that of the slow cycle, the data that needs to be backed up has high real-time performance. The present invention can achieve the actual demand of giving priority to responding to fast cycle commands and ensure the real-time performance of fast cycle data by optimizing the different detection frequencies of fast and slow cycles.

[0028] 5. The present invention uses a backup power supply, and data can be stored in a non-volatile memory chip even in the event of a power outage. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of the structure of an electronic device for the method for backing up full data in fast and slow operation cycles of an industrial controller according to the present invention;

[0030] Figure 2 Schematic diagram of data distribution in the CPU of the present invention;

[0031] Figure 3 Schematic diagram of data distribution in the memory chip under the FPGA of the present invention;

[0032] Figure 4 Schematic diagram of low-speed bus communication between the CPU and FPGA of the present invention;

[0033] Figure 5 A schematic diagram of a command format consisting of the data length of the data area of ​​the CPU and the memory base address where the data is located in the present invention;

[0034] Figure 6 This is a flow chart of the FPGA cyclic monitoring of the fast cycle command queue and the slow cycle command queue in the present invention;

[0035] Figure 7 Flowchart of the method for full data backup of fast and slow operation cycles of an industrial controller in the present invention;

[0036] Figure 8 Flowchart of the data recovery method of the present invention. DETAILED DESCRIPTION

[0037] Below, the exemplary embodiments according to the present application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application, and it should be understood that the present application is not limited to the exemplary embodiments described herein.

[0038] It is understood that the term "a" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element may be one, while in another embodiment, the number of the element may be multiple, and the term "a" should not be understood as limiting the number. "Multiple" means greater than or equal to two.

[0039] Although ordinal numbers such as "first," "second," and the like will be used to describe various components, these are not intended to limit those components. The terms are used solely to distinguish one component from another. For example, a first component could be referred to as a second component, and similarly, a second component could be referred to as a first component without departing from the teachings of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0040] The terms used herein are for the purpose of describing various embodiments only and are not intended to be limiting. As used herein, the singular is intended to include the plural, unless the context clearly indicates otherwise. It will also be understood that the terms "including" and / or "having" when used in this specification specify the presence of a stated feature, number, operation, component, element, or combination thereof, and do not preclude the presence or addition of one or more other features, numbers, operations, components, elements, or combinations thereof.

[0041] The following combination Figure 1-8 The present invention is further described with specific embodiments.

[0042] like Figure 1 FIG2 is a schematic diagram showing the structure of an electronic device for the method for backing up full data in fast and slow operation cycles of an industrial controller according to the present invention;

[0043] The main power supply powers the entire board, while the backup power supply only powers the FPGA, memory chips, and power-off non-volatile storage chips. The CPU is responsible for communications, computing, and other tasks, while the FPGA is responsible for data backup and recovery. The CPU and FPGA communicate using high-speed and low-speed buses. High-speed buses utilize technologies such as parallel LVDS, serial Aurora, SRIO, and PCIe, while low-speed buses utilize technologies such as SPI, LIO, and UART. The high-bandwidth throughput of the high-speed bus is used for data transmission that requires preservation. The low-speed bus, leveraging its high real-time capabilities, is responsible for register data transmission between the CPU and FPGA, and data transmission between the FPGA and memory chips and power-off non-volatile storage chips.

[0044] like Figure 2 The figure shows a schematic diagram of data distribution in the CPU of the present invention; the figure shows a schematic diagram of the distribution of fast cycle and slow cycle data in the CPU memory.

[0045] Figure 3It is a data distribution schematic diagram in the memory chip under the FPGA of the application; the memory under the FPGA is divided into data A area and data B area, the data distribution is same as the data size in the CPU memory, and the relative position is same. The last position of the data is a fast cycle and a slow cycle data backup completion mark and a time stamp, if the data backup is completed, the data backup completion mark is set, and the time stamp of completing the backup is recorded. For the fast cycle or slow cycle data integrity problem of abnormal reset, the data A area and the data B area in the application are completely same in size and distribution, and are used for alternately saving data, that is, if the data is written into the A area this time, the data is written into the B area next time; if the data is written into the B area this time, the data is written into the A area next time, and the cycle is repeated, because the data A area and the data B area alternately save data, only one area is completed, and the other area is switched, therefore, the data area which is not used at this time is the complete data area, therefore, the scheme provided in the application does not exist the situation that the data A area and the data B area are not completed at the same time, that is, at least the fast cycle data of one area is complete, and at least the slow cycle data of one area is complete. When data needs to be recovered, the data backup completion mark is read first, if the mark of one area is completed and the mark of one area is not completed, the data recovery is selected in the completed area; if the marks of the two areas are both completed, the time stamp is compared, and the data of the latest time stamp is selected for recovery.

[0046] Figure 4 It is a low-speed bus communication schematic diagram of the CPU and the FPGA of the application; the CPU writes the command into the corresponding register through the low-speed bus, and the fast cycle and the slow cycle correspond to the registers of different addresses. If the fast cycle command is received, the fast cycle command is buffered in the fast cycle queue, and if the slow cycle command is received, the slow cycle command is buffered in the slow cycle queue. The depth of the fast cycle queue is not less than the number of the fast cycle data area in the CPU memory, and the depth of the slow cycle queue is not less than the number of the slow cycle data area in the CPU memory. The FPGA reads the command from the buffer queue, analyzes the data length and the address of the data in the CPU memory which need to be read, reads the data of the corresponding length and the corresponding address through the high-speed bus.

[0047] Figure 5 It is a command format schematic diagram of the data length and the memory base address of the data area of the CPU in the application; the CPU forms a command of the data length and the memory base address of the data after completing the calculation of one data area, and sends the command to the corresponding register in the FPGA through the low-speed bus, Figure 5 It is the format of the command.

[0048] Figure 6 It is a flow chart of the FPGA in the application which cyclically monitors the fast cycle command queue and the slow cycle command queue;

[0049] The FPGA cyclically monitors the fast-cycle command queue and the slow-cycle command queue. When it detects that the fast-cycle command queue is not empty, the FPGA reads a fast-cycle command to verify the correctness of the command. If it is incorrect, it discards it. If it is correct, it parses the base address and length of the data in the CPU memory from the command and passes these two parameters to the high-speed bus interface. After receiving these two parameters, the high-speed bus interface will initiate a read operation command to read the data into the memory chip under the FPGA. After completion, it continues to check whether the fast-cycle command queue is empty. If it is not empty, it continues to execute the data read operation until it detects that the fast-cycle command queue is empty. When the fast-cycle command queue is empty, the FPGA checks the slow-cycle command queue. If it is empty, it checks the fast-cycle command queue. If it is not empty, it reads a slow-cycle command once to verify the command is correct. If it is incorrect, it discards it. If the data base address and length are correctly parsed, they are passed to the high-speed bus. The high-speed bus reads the data and puts it into the memory chip under the FPGA. After execution, it checks the fast-cycle command queue.

[0050] Fast cycles have the highest priority, so when a fast-cycle command needs to be executed, the FPGA prioritizes it, increasing the frequency of checking the fast-cycle command queue. After each slow-cycle command is executed, the FPGA starts checking the fast-cycle command queue again. After each fast-cycle command is executed, the FPGA also starts checking the fast-cycle command queue again. This increases the frequency of fast-cycle queue checks and ensures timely response to fast-cycle data reads.

[0051] Figure 7 This is a flow chart of the full data backup method for industrial controllers during both fast and slow operation cycles, according to the present invention. The backup power supply area supplies power to the FPGA, memory chips, and power-off non-volatile storage chips. The backup power supply and main power supply are seamlessly switched. When the FPGA detects a main power outage, it initiates a data backup operation and, upon completion, disconnects the backup power supply. Upon receiving an active backup command, the FPGA also initiates a data backup operation and, upon completion, reports the completion of the data backup.

[0052] Figure 8 This is a flow chart of the data recovery method of the present invention. When the controller is powered off and started, when executing the recovery data, the CPU starts the FPGA recovery program by writing registers via the low-speed bus. The FPGA reads the storage status area of ​​the power-off non-volatile memory chip, reads data starting from the address with the latest timestamp, and writes the read data to the corresponding memory of the CPU to achieve the effect of data recovery.

[0053] When the controller recovers data without power failure, the CPU starts the FPGA recovery program by writing registers through the low-speed bus. The FPGA reads the fast and slow cycle data integrity marks and timestamps of the data areas A and B of the memory chip below it, finds the latest fast and slow cycle integrity data by comparing the integrity marks and timestamps, and writes the data to the CPU memory through the high-speed bus to achieve the effect of data recovery.

[0054] When the controller in the prior art is unstable or crashes, the data in the memory will become unreliable due to reset and restart. If the configuration, algorithm and other data need to be reloaded after startup, the data lost during the operation cannot be restored, which will cause control mutations during operation and may cause major accidents. Therefore, the controller needs to back up all data as much as possible and restore all data when restarted or manually operated. There are two operating states in the controller memory: fast cycle and slow cycle. However, the two are determined in the memory according to the configuration parameters and are not continuous. Moreover, the calculation in each operation cycle is not continuous. Therefore, when an abnormal situation occurs, the operation cycle is not necessarily completed. When the calculation is not completed, there are data points in the memory that have been completed and there are also points that have not been completed. Restoring such data has no practical use. What needs to be restored is the memory data that has completed the calculation of all points. Therefore, what needs to be restored is the data of the previous operation cycle.

[0055] The present invention uses dual data zones to back up data. Each zone is of equal size and contains data for both the fast and slow cycles. Each zone's fast and slow data has a completion mark and a timestamp. When a backup is needed, the completion mark of each zone is read first, and the completed data is used first. If both zones are marked as completed, the data with the larger timestamp is used. The present invention can achieve full data backup for both the fast and slow cycles of the controller, and can also restore the complete data for each fast and slow cycle.

[0056] The present invention adopts two power supplies: the main power supply supplies power to the entire machine, and the backup power supply is a small energy power supply used in the controller, which can supply power to the FPGA, memory and power-off non-volatile storage chip. When the entire machine loses power, the power of the backup power supply can complete the FPGA to store data from the memory to the power-off non-volatile storage chip. When the data backup is completed, the FPGA can actively cut off the power supply of the backup power supply.

[0057] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art will be able to modify the technical solutions described in the aforementioned embodiments or substitute equivalents for some of the technical features. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

[0058] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. For the systems or devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method description.

[0059] It should be understood that in the present invention, "at least one (item)" means one or more, and "more" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or plural.

[0060] It should also be noted that, in the present invention, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0061] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly using hardware, software modules executed by a processor, or a combination of the two. The software modules can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

[0062] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein, but is intended to be embodied in the widest possible manner consistent with the principles and novel features disclosed herein.

Claims

1. A method for backing up all data of industrial controllers in fast and slow operation cycles, characterized in that: include: The FPGA detects whether the main power supply has been lost or a backup command has been received; If it exists, the FPGA compares the integrity mark and timestamp of the fast cycle data in the data area A and data area B of the memory chip, and writes the latest fast cycle integrity data into the power-off non-volatile storage chip; Then, the FPGA compares the integrity mark and timestamp of the slow cycle data in data area A and data area B of the memory chip, and writes the latest slow cycle integrity data into the power-off non-volatile storage chip.

2. The method for backing up full data of industrial controllers in fast and slow operation cycles according to claim 1, characterized in that: The FPGA detects whether the main power supply has been lost or a backup command has been received, including: If a main power failure is detected, the FPGA uses the backup power supply and turns off the backup power supply after the slow cycle data is written to the power-down non-volatile memory chip; If a backup command is received, after the slow cycle data is written into the power-off non-volatile storage chip, the backup completion is reported.

3. A method for backing up full data of fast and slow operation cycles of an industrial controller according to claim 1 or 2, characterized in that: The main power supply provides power to the entire board, while the backup power supply only provides power to the FPGA, memory chips, and power-off non-volatile storage chips. The CPU is responsible for communication and computing operations, the FPGA is responsible for data backup and data recovery, and the CPU and FPGA use high-speed and low-speed buses for communication. The high-speed bus is responsible for transmitting data that needs to be saved, and the low-speed bus is responsible for register data transmission between the CPU and FPGA, and data transmission between the FPGA and memory chips and power-off non-volatile storage chips.

4. The method for backing up full data of industrial controllers in fast and slow operation cycles according to claim 3, characterized in that: High-speed buses include parallel LVDS or serial Aurora, SRIO, and PCIe; Low-speed buses include SPI, LIO, and UART.

5. The method for backing up full data of industrial controllers in fast and slow operation cycles according to claim 3, characterized in that: The memory chip is a DDR chip, and the power-off non-volatile storage chips include flash and SD cards.

6. The method for backing up full data of industrial controllers in fast and slow operation cycles according to claim 3, characterized in that: The memory chip is divided into data area A and data area B. The data distribution in data area A and data area B is the same as the data size and relative position in the CPU memory. The last position of the data in data area A and data area B is the fast cycle and slow cycle data backup completion mark and timestamp. If the data backup is completed, the data backup completion mark will be set and the backup completion timestamp will be recorded.

7. The method for backing up full data of industrial controllers in fast and slow operation cycles according to claim 6, characterized in that: The CPU writes commands to the corresponding registers through the low-speed bus. Fast cycles and slow cycles correspond to registers with different addresses. If a fast cycle command is received, the fast cycle command is cached in the fast cycle queue. If a slow cycle command is received, the slow cycle command is replaced in the slow cycle queue. The depth of the fast cycle queue is not less than the number of data blocks in the fast cycle data area in the CPU memory, and the depth of the slow cycle queue is not less than the number of data blocks in the slow cycle data area in the CPU memory; the FPGA reads the command from the cache queue, parses the data length to be read and the address of the data in the CPU memory, and reads the data of the corresponding address and length through the high-speed bus.

8. The method for backing up full data of a fast and slow operation cycle of an industrial controller according to claim 7, characterized in that: Each time the CPU completes the calculation of a data block, it combines the data length and the memory base address where the data is located into a command and sends it to the corresponding register in the FPGA through the low-speed bus.

9. The method for backing up full data of a fast and slow operation cycle of an industrial controller according to claim 8, characterized in that: The FPGA cyclically monitors the fast-cycle command queue and the slow-cycle command queue. When it detects that the fast-cycle command queue is not empty, the FPGA reads a fast-cycle command and verifies the correctness of the command. If it is incorrect, it is discarded. If correct, the base address and length of the data in the CPU memory are parsed from the command, and these two parameters are passed to the high-speed bus interface. After receiving these two parameters, the high-speed bus interface will initiate a read operation command to read the data into the memory chip under the FPGA. After completion, it will continue to check whether the fast cycle command queue is empty. If not, it will continue to perform data read operations until it detects that the fast cycle command queue is empty. When the fast cycle command queue is empty, the FPGA checks the slow cycle command queue. If it is empty, it checks the fast cycle command queue again. If it is not empty, read the slow cycle command once to verify that the command is correct. If it is wrong, discard it. If the data base address and length are parsed correctly, they are handed over to the high-speed bus, which reads the data and puts it into the memory chip under the FPGA. After execution, the fast-cycle command queue is checked.

10. The method for full data backup of fast and slow operation cycles of an industrial controller according to claim 9, characterized in that: When the controller is powered off and restarted, when executing the recovery data, the CPU starts the FPGA recovery program by writing registers through the low-speed bus. The FPGA reads the storage status area of ​​the power-off non-volatile memory chip, reads data starting from the address with the latest timestamp, and writes the read data to the corresponding memory of the CPU to achieve the effect of data recovery. When the controller recovers data without power failure, the CPU starts the FPGA recovery program by writing registers through the low-speed bus. The FPGA reads the fast and slow cycle data integrity marks and timestamps of the data areas A and B of the memory chip below it, finds the latest fast and slow cycle integrity data by comparing the integrity marks and timestamps, and writes the data to the CPU memory through the high-speed bus to achieve the effect of data recovery.

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