A method, system, chip, computer-readable storage medium, and electronic device for backing up RAM data using cache during the SoC boot phase.

Abstract

This invention belongs to the field of SoC boot technology and discloses a method, system, chip, computer-readable storage medium, and electronic device for backing up RAM data using cache during the SoC boot phase. The method includes: after the SoC powers on and initializes, transferring data from RAM to a cache for temporary storage via a DMA controller or CPU; subsequently loading and executing a secondary bootloader to complete DDR initialization, during which the cache isolates the risk of data overwriting; after DDR initialization is complete, mapping the address space of the backup data to the DDR physical address via a remapping mechanism, and performing a cache refresh operation to persist the data to DDR. This invention effectively solves the problem of DDR initialization code overwriting RAM abnormal situation data without adding hardware costs, providing complete data preservation for system anomaly analysis and significantly improving debugging efficiency.

Description

Technical Field

[0001] This invention belongs to the field of system-on-a-chip (SoC) boot technology, and particularly relates to a method, system, chip, computer-readable storage medium, and electronic device for backing up RAM data using cache during SoC boot phase, which is used to solve the problem of field data being overwritten during abnormal recovery. Background Technology

[0002] Modern mobile SoCs undergo a multi-stage boot process, including loading initial code from ROM into on-chip RAM and initializing DDR. Before the DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) is initialized, the system can only execute boot code using the integrated on-chip RAM (usually SRAM). To optimize chip area cost, this on-chip RAM is time-division multiplexed after system boot, for example, reallocated to data exchange areas between subsystems or dedicated code space. This resource reuse mechanism results in the original RAM contents being overwritten by subsequent programs.

[0003] Highly integrated SoC chips are the brains of various types of smart devices, from smartphones and wearable devices to smart medical devices and self-driving cars; they are ubiquitous. The ultimate goal is to achieve low power consumption. When a SoC experiences a hardware malfunction (such as a crash or unexpected reset), it is necessary to completely save the state data in RAM (including register states, stack information, etc.) to external storage media for offline analysis. However, the existing process has fundamental contradictions: 1. The DDR initialization program itself requires a large amount of on-chip RAM space, and its execution process directly overwrites the malfunction state data to be saved; 2. If a dedicated RAM area is reserved for backup data, it will significantly increase the chip manufacturing cost.

[0004] In response to the above problems, there are currently two main solutions: (1) Dedicated cache-to-RAM design: By modifying the cache controller logic, it enables direct address indexing to store RAM data. The drawback of this solution is that it increases the design complexity of the cache controller and may affect memory access efficiency; (2) Early backup mechanism for external storage: Data is exported through a low-speed interface (such as a serial bus) before DDR initialization. This method is limited by interface bandwidth, has a low data transfer rate, and requires additional hardware pin support.

[0005] In summary, existing technologies lack a mature solution to effectively resolve the contradiction between "initialization code execution and on-site data preservation," leading to the loss of abnormal on-site information and significantly increasing the difficulty of system debugging.

[0006] Based on this, the present invention transforms the cache into a temporary backup medium and combines it with bus remapping technology to achieve seamless transfer of RAM data without increasing hardware costs. Summary of the Invention

[0007] The purpose of this invention is to propose a method, system, chip, computer-readable storage medium, and electronic device for backing up RAM data using cache during the SoC startup phase, in order to resolve the contradiction between RAM space reuse and the destruction of on-site information.

[0008] This invention proposes a method for backing up RAM data using cache during the SoC startup phase. This method includes at least the following steps:

[0009] Step 1: Power on the SoC and perform basic initialization;

[0010] Step 2: Transfer RAM data to the cache, which is done either through the DMA controller or initiated by the CPU; among which,

[0011] The above-mentioned data transfer via the DMA controller includes: first, configuring the DMA; then,

[0012] Initiate DMA transfer and write RAM data to the cache via the consistency bus; wherein configuring DMA specifically includes: setting the source address to the RAM region to be backed up; setting the target address to a preset address window reserved in the SoC memory mapping; configuring the DMA controller so that its initiated data transfer transactions carry a bus signal indicating cacheability, thereby writing data to the cache via the consistency bus.

[0013] The above-mentioned data transfer initiated by the CPU specifically includes: First, the CPU initializes the Memory Management Unit (MMU); second, the CPU executes the memory copy process: copying the RAM data to a virtual address that has been configured as cacheable, and the data will automatically enter the cache.

[0014] Step 3: Secondary boot loading and DDR initialization, specifically including:

[0015] After the RAM data backup is complete, perform the following operations:

[0016] Load the complete secondary bootloader: Load the secondary bootloader containing DDR initialization code from the storage device into the backed-up RAM area;

[0017] The CPU jumps to execute the secondary boot program in RAM to complete DDR initialization;

[0018] Complete DDR controller training and establish a usable physical address space;

[0019] Step 4: Remap and data persistence;

[0020] Step 5: System startup and anomaly analysis.

[0021] As described above, a method for backing up RAM data using cache during the SoC startup phase includes step 1, which specifically includes: after the SoC receives external power, the reset circuit releases the reset signal, and the main control CPU core executes the ROM firmware program.

[0022] As described above, in a method for backing up RAM data using a cache during the SoC startup phase, the coherence bus employs the ACE or CHI protocol.

[0023] As described above, in a method for backing up RAM data using cache during SoC startup, the Remap remapping remaps the source address space used for data backup to the DDR physical address.

[0024] As described above, in the method of using cache to back up RAM data during the SoC startup phase, step 4 further includes performing a cache refresh operation to force the backup data in the cache to be written to the DDR target area.

[0025] As described above, in the method of backing up RAM data using cache during the SoC startup phase, step 5 specifically includes: after transferring the RAM data in the cache to DDR, continuing the operating system boot process; when a system exception is triggered, reading the backup data in DDR through the debug interface; and reconstructing the crash scene by combining register snapshots.

[0026] This invention also proposes a system for backing up RAM data using cache during the SoC startup phase. This system includes a power-on and initialization module, a DMA configuration and data transfer module, a DDR initialization module, a remapping module, and an anomaly analysis module; wherein,

[0027] Power-on and initialization module: used for SoC power-on and basic initialization;

[0028] Data transfer module: used to transfer RAM data to cache;

[0029] DDR initialization module: used to load secondary boot code and initialize DDR;

[0030] Remapping module: used for Remap remapping and data persistence;

[0031] Anomaly analysis module: used for system startup and anomaly analysis;

[0032] During the SoC startup phase, the system performs the aforementioned method of backing up RAM data using the cache during the SoC startup phase.

[0033] The present invention also provides a chip including at least one processor and a communication interface, the communication interface being coupled to the at least one processor, the at least one processor being used to run computer programs or instructions to implement the above-described method of backing up RAM data using cache during the SoC startup phase.

[0034] The present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor of an electronic device, causes the electronic device to perform the above-described method of backing up RAM data using cache during the SoC startup phase.

[0035] The present invention also provides an electronic device, including one or more processors; and a storage device for storing one or more computer programs, which, when executed by the one or more processors, cause the electronic device to implement the above-described method of backing up RAM data using cache during the SoC startup phase.

[0036] This invention provides a method, system, chip, computer-readable storage medium, and electronic device for backing up RAM data using cache during the SoC boot phase. The method includes: after SoC power-on initialization, transferring data from RAM to cache for temporary storage via a DMA controller or CPU; subsequently loading and executing a secondary bootloader to complete DDR initialization, during which the cache isolates the risk of data overwriting; after DDR initialization is complete, mapping the address space of the backup data to the DDR physical address via a remapping mechanism, and performing a cache refresh operation to persist the data to DDR. This invention effectively solves the problem of DDR initialization code overwriting RAM abnormal situation data without adding hardware costs, providing complete data preservation for system anomaly analysis and significantly improving debugging efficiency. Attached Figure Description

[0037] Figure 1 This is a flowchart illustrating the process of backing up RAM data using a cache according to an embodiment of this application.

[0038] Figure 2 This is a flowchart illustrating the use of DMA to back up RAM data to cache according to an embodiment of this application;

[0039] Figure 3 A flowchart illustrating the transfer of backed-up RAM data to DDR according to one embodiment of this application;

[0040] Figure 4 This is a schematic diagram of the structure of a chip according to an embodiment of this application;

[0041] Figure 5 This is a schematic diagram of the structure of a computer-readable storage medium according to an embodiment of this application;

[0042] Figure 6 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0043] The present invention will be described in detail below through embodiments.

[0044] The following description, in conjunction with the accompanying drawings, details a method, system, electronic device, and computer-readable storage medium for backing up RAM data using cache during the SoC startup phase, provided by the present invention.

[0045] Please see Figure 1 This is a flowchart illustrating the process of backing up RAM data using a cache, as provided in an embodiment of this application. Figure 1 As shown, a flowchart illustrates the process of backing up RAM data using cache during the SoC startup phase.

[0046] This embodiment provides a method for backing up RAM data using cache during the SoC startup phase, combined with the attached... Figure 1 The process shown includes the following steps:

[0047] Step 1: Power on the SoC and perform basic initialization;

[0048] It should be noted that after the SoC receives external power, the reset circuit releases the reset signal, and the main control CPU core executes the ROM-based firmware, including:

[0049] Initialize necessary peripherals: Configure the clock controller, power management unit (PMU), and basic communication interfaces (such as UART debug serial port);

[0050] Configure the physical address mapping range of the on-chip RAM (Random Access Memory);

[0051] Define a secure RAM region: Reserve a fixed-size unused RAM region for temporary storage of critical boot code;

[0052] Loading the mini-bootloader: This involves loading minimal boot code containing only DMA configuration functionality into the safe zone. The principle is that this stage initializes only the bare minimum environment required for the backup operation. The size of the safe zone is strictly calculated (typically less than or equal to 5% of the total RAM capacity) to ensure it does not occupy the data area to be backed up.

[0053] Step 2: Transfer RAM data to cache; It should be noted that the above RAM data transfer process can be accomplished in two ways, including data transfer through the DMA controller and data transfer initiated by the CPU.

[0054] Scenario 1: Data transfer via DMA controller

[0055] First, configure DMA, which includes:

[0056] Set the source address to the RAM region to be backed up (containing abnormal situation data);

[0057] Set the target address to a preset address window reserved in the SoC memory mapping; configure the DMA controller so that its initiated data transfer transactions carry a bus signal indicating cacheability, thereby writing data to the cache via the consistency bus.

[0058] Then, DMA transfer is initiated, and RAM data is written to the cache via the Coherent Bus.

[0059] In this step, the cacheable attribute and coherent bus technology are used to implement RAM data backup operations using a cache, wherein:

[0060] Coherent Bus: A coherent bus is a communication mechanism used in multi-core systems to maintain data consistency. It automatically manages cache consistency among multiple cores or master devices through bus protocols, ensuring data synchronization. It is suitable for scenarios such as multi-core CPUs, heterogeneous computing with GPUs and CPUs, and high-speed cache-sharing systems. Compared to non-coherent buses, coherent buses feature hardware consistency, complex protocols, and low-latency access. In hardware design, the coherent bus is a key component for achieving data consistency in multi-core systems. Employing ACE (Advanced Microcontroller Bus Architecture Coherency Extension) or CHI (Coherent Hub Interface) protocols ensures data consistency among multiple cores and prevents backup data from being accidentally lost.

[0061] Scenario 2: Data transfer initiated via CPU

[0062] First, the CPU initializes the Memory Management Unit (MMU): by configuring the MMU page table, the target virtual space is specified as cacheable.

[0063] Secondly, the CPU executes the memory copy process: copying the RAM data to a virtual address that has been configured as cacheable, and the data will automatically enter the cache.

[0064] It is important to note that the two scenarios described above lead to different technical effects: the DMA-based transfer scheme utilizes hardware acceleration and dedicated interfaces, resulting in extremely high data transfer efficiency, extremely low CPU utilization, and no reliance on the MMU, simplifying the initial boot environment; while the CPU-based software transfer scheme offers maximum hardware compatibility and flexibility, requires no specific hardware support, is highly versatile, and has the lowest hardware implementation cost.

[0065] Step 3: Secondary bootloader loading and DDR initialization;

[0066] It should be noted that after the RAM data backup is complete, the following operations should be performed:

[0067] Load the complete secondary bootloader: Load the secondary bootloader containing DDR initialization code from the storage device (such as eMMC) into the backed-up RAM area;

[0068] The CPU jumps to execute the secondary boot program in RAM to complete DDR initialization, including:

[0069] Initialize the MMU and establish a translation table from virtual address to physical address;

[0070] Execute DDR SDRAM initialization code (including timing configuration, impedance calibration, etc.);

[0071] Complete DDR controller training and establish a usable physical address space. Data preservation principle: Because backup data is stored in the cache, the SRAM space occupied by the DDR initialization code is physically isolated from the backup area, avoiding data overwriting.

[0072] It should be noted that the key preservation mechanism of this execution step is: (1) the secondary bootloader is loaded into the on-chip RAM area that has been backed up, and the original data has been stored in the cache in advance via DMA; (2) when the area is overwritten, its data copy has been safely stored in the cache.

[0073] Step 4: Remap and Data Persistence; It should be noted that critical data transfer operations are performed after DDR becomes available:

[0074] Configure the bus Remap logic unit to remap the source address space (such as the 0x9E00_0000 starting region) used for backup data to the DDR physical address (such as 0xC100_0000).

[0075] Perform a cache flush operation to force the backup data in the cache to be written to the DDR target area.

[0076] In this step, Remap and Flush techniques are used to transfer backup data from the cache to DDR.

[0077] In the middle, Remap is a hardware-level address remapping module that dynamically modifies address mapping relationships at the bus interconnect layer; Flush operation clears specified cache lines through cache maintenance instructions (such as DC CISW in ARMv8) to ensure data is written to disk.

[0078] Step 5: System startup and anomaly analysis.

[0079] It should be noted that after transferring the RAM data in the cache to DDR, the operating system boot process will continue: the RAM will be reused as the working area for functional modules (such as the NPU instruction cache).

[0080] When a system exception is triggered, the backup data in DDR is read through the debug interface; the crash scene is reconstructed by combining the register snapshot.

[0081] The present invention provides a method for backing up RAM data using cache during the SoC startup phase, which achieves the following technical effects: under the condition of zero new hardware resources, the contradiction between DDR initialization boot code overwriting RAM data is resolved through the temporary storage mechanism of cache and the dynamic remapping of Remap.

[0082] Please see Figure 2 This is a flowchart illustrating the use of DMA to back up RAM data to the cache, provided in an embodiment of this application. For example... Figure 2 As shown, this is the detailed process of backing up critical data in RAM to cache during the SoC startup phase.

[0083] Because abnormal field data in the on-chip RAM is at risk of being overwritten during the initial startup of the SoC (before DDR initialization), this embodiment utilizes cache as a temporary non-volatile storage medium and achieves lossless backup and seamless data transfer through a hardware-accelerated data transfer mechanism. Its key technical characteristics rely on the following:

[0084] Consistency bus protocol: ensures the consistency of backup data in multi-core systems; DMA hardware acceleration: speeds up the data transfer process. Combined with... Figure 2 As shown, the detailed process of backing up RAM data is as follows:

[0085] Step 2.1: Configure DMA parameters for the micro bootloader;

[0086] It should be noted that this step is performed only after the security initialization in step 1 has been completed (i.e., the micro bootloader has been loaded). The relevant parameters involved include, but are not limited to:

[0087] Set the source address register: Point to the on-chip RAM physical region containing the exception context data (example: 0x8002_0000);

[0088] Set the target address register: a preset address window reserved in the SoC memory mapping (example: 0x9E00_0000); configure the DMA controller so that write transactions to this address carry a bus signal indicating cacheability;

[0089] Set the transfer length register: transfer in segments according to the cache line size (usually 64 bytes).

[0090] During this process, the CPU writes to the DMA control register via the bus; source address: physical address 0x8002_0000 (containing the exception context), destination address: 0x9E00_0000 (cacheable attribute), transfer length: preset exception data area size (example 64KB).

[0091] Key signal: DMA_CTRL[START]=0 (configuration state)

[0092] DMA_SRC_ADDR = 0x8002_0000

[0093] DMA_DST_ADDR = 0x9E00_0000

[0094] Step 2.2: DMA reads RAM data;

[0095] It should be noted that during this stage, the DMA controller sends an AXI ReadNoSnoop request to the RAM controller, with parameters including a specified source address (0x8002_0000) and a burst transfer length (4 transfers). The RAM then responds by: (1) sending a Row Activation (RAS) command to the RAM array after receiving the request; and (2) returning 128 bits of data to the controller. During data transfer, the RAM controller transfers data to the DMA at a rate of 128 bits per cycle, performing 4 consecutive transfers (totaling 64 bytes). This 64-byte data block corresponds to a complete cache line, which will be written to a single storage unit of the L2 cache via the coherence bus in subsequent operations. At the same time, the RAM controller sends an RLAST signal to indicate that the transfer is complete. It is worth mentioning that since this startup stage is essentially a single-core, single-master device environment, ReadNoSnoop is used, and its no-snoop characteristic is well-suited to this scenario.

[0096] Step 2.3: DMA initiates a write operation;

[0097] It should be noted that this stage includes the request submission stage, the protocol encapsulation stage, the bus transmission stage, and the completion confirmation stage.

[0098] During the request commit phase: DMA retrieves 64 bytes of data from the internal buffer; sets the target address to the preset address window (0x9E00_0000); and configures the bus signal for this write transaction, marking it as cacheable.

[0099] During the protocol encapsulation phase: Protocol selection is based on the system type. If it is a single-core system, the AXI CoherentExtensions (ACE) protocol is selected; if it is a multi-core system, the CHI protocol is selected. The corresponding transaction generation includes: WriteUnique transactions for single-core systems and SnpUnique transactions for multi-core systems.

[0100] Add metadata: Add a consistency tag (Axcache=0b1111) and set a system-level consistency domain (AxDOMAIN=0b10).

[0101] During the bus transmission phase: its physical path is DMA → AXI bus → interconnect matrix → L2 cache controller; its timing characteristics are: the address phase has a fixed 3-cycle delay; the data phase requires 2 cycles per 128-bit transmission (including handshake); its bandwidth is 128 bits @ 1GHz = 16GB / s.

[0102] During the completion confirmation phase: the cache controller returns BRESP=OKAY (0b00); at the same time, the DMA updates the status register: TRANS_COUNT+=64 (bytes); if it is the last transfer, STATUS.DONE is set.

[0103] Step 2.4: Cache misses trigger cache line allocation;

[0104] It should be noted that during this phase, the cache controller receives listening requests and then queries the consistency catalog for the status of the requests. It checks for conflicts; if no conflict is found, a new cache row is allocated directly. If a replica exists, a SnpInvalid invalidation request is sent to other cores. For invalidation handling, it waits for ACK confirmations from other cores, and allocates a new row upon receiving confirmation. Finally, the consistency catalog status is updated, the new row's status is set to Exclusive (E), and the system returns to the ready state.

[0105] Step 2.5: Update cache data;

[0106] It should be noted that during this stage, the cache data write phase (L2 cache) is as follows: Data reaches the cache controller, which compares the matching address tag with the Tag RAM content. If a match fails, a replacement line is selected, and the status of the replacement line is checked (if it's in Clean state: it's overwritten directly; if it's in Dirty state: it's written back to memory first). If a match is successful, the existing line data is updated directly. Finally, the data is written to Data RAM, and the Tag RAM status is updated to Modified (M), completing the cache line update.

[0107] In addition, an error handling mechanism is included. This process involves performing ECC verification during data transmission, with the following rules: no errors, write normally to the cache; correctable errors, write after correction; uncorrectable errors trigger an exception. Handling exceptions involves saving the error address to a dedicated register and aborting the current transmission process. This stage also includes recovery attempts, which involve jumping to a safe handler and initiating a retry mechanism (up to 3 times); successful retry continues subsequent operations, while failed retry marks the memory block as bad. Finally, the system error log is updated.

[0108] This invention provides a method for backing up RAM data to a cache, which overcomes the problem of DDR initialization code overwriting abnormal field data during the SoC startup phase without hardware cost.

[0109] Please see Figure 3 This is a flowchart illustrating the process of transferring backed-up RAM data to DDR, provided in an embodiment of this application. For example... Figure 3 As shown, this is the detailed process of transferring the backup data in the cache to the DDR after the DDR is initialized.

[0110] After DDR initialization is complete, the exception data temporarily stored in the cache needs to be persistently stored for long-term analysis. This embodiment effectively combines hardware remapping and cache flushing technologies to achieve seamless data transfer from cache to DDR. Its core technologies are: zero-copy data migration: avoiding secondary data copying through bus-level address remapping; atomic flushing: ensuring cache data is safely written to disk during system operation; and immediate resource release: immediately reclaiming cache space for system use after the transfer.

[0111] Combination Figure 3 As shown, the detailed process of transferring backup data to DDR is as follows:

[0112] Step 4.1: Remap logic configuration;

[0113] It should be noted that this requires DDR initialization to be complete (physical 0xC000_0000 is active). This check for DDR initialization completion is performed by the secondary bootloader. After DDR initialization, the Remap controller configures parameters involving the source address, destination address, and mapping length; the source address is 0x9E00_0000, the destination address is 0x100_0000, and the mapping length is 64KB. The source address corresponds to the source address space of the backup data in the cache, and the destination address corresponds to the DDR physical space.

[0114] The pseudocode for Remap is as follows:

[0115] always_comb begin

[0116] if (addr[31:16] == 16'h9E00) / / 0x9E00_xxxx

[0117] remapped_addr = {8'hC1, addr[23:0]}; / / 0xC100_xxxx

[0118] end

[0119] Step 4.2: Cache Flush operation;

[0120] It should be noted that this cache flush operation is a command-level data flush.

[0121] Its source code is as follows:

[0122] ARMv8 refresh instructions

[0123] mov x0, #0x9E000000; Starting address

[0124] mov x1, #0x10000; Length 64KB 1:

[0126] `dc civac, x0;` clears the cache lines.

[0127] `add x0, x0, #64;` Steps 64 bytes (cache line).

[0128] subs x1, x1, #64; (Length decreases)

[0129] b.gt 1b; loops until completion.

[0130] During the cache flush operation, hardware acceleration mechanisms are utilized: (1) Batch flush engine: Automatically converts to Burst transmission when detecting consecutive addresses; (2) Parallel channel: L2 cache supports 4-way parallel write-back (256 bits / cycle).

[0131] Step 4.3: Write data to DDR;

[0132] It should be noted that after the DDR controller receives the conversion request, it performs physical storage operations, which involve activation commands and column write commands; then, it transmits 128 bits of data in four consecutive transmissions; finally, it performs storage confirmation.

[0133] This invention provides a method for transferring backup data from cache to DDR. The technical effect achieved is as follows: the secondary copying of data is eliminated by hardware remapping, and direct writing from cache to DDR is realized by instruction-level flush operation. Under the condition of zero new hardware and zero system awareness, the hidden migration and persistent storage of critical data are completed.

[0134] This invention also provides a system for backing up RAM data using cache during the SoC startup phase. This system includes a power-on and initialization module, a DMA configuration and data transfer module, a DDR initialization module, a remapping module, and an anomaly analysis module; wherein,

[0135] Power-on and initialization module: used for SoC power-on and basic initialization;

[0136] Data transfer module: used to transfer RAM data to cache;

[0137] DDR initialization module: used to load secondary boot code and initialize DDR;

[0138] Remapping module: used for Remap remapping and data persistence;

[0139] Anomaly analysis module: used for system startup and anomaly analysis;

[0140] During the SoC startup phase, the system executes the method described in any of the above embodiments for backing up RAM data using a cache during the SoC startup phase.

[0141] Please see Figure 4 This is a schematic diagram of a chip structure provided in an embodiment of this application, such as... Figure 4 As shown, chip 4000 includes one or more (including two) processors 4100 and a communication interface 4300. The communication interface 4300 is coupled to the at least one processor 4100, which is used to run computer programs or instructions to implement the method of backing up critical data using cache during the SoC startup phase as described in the above embodiments.

[0142] Preferably, the memory 4400 stores the following elements: executable modules or data structures, or subsets thereof, or extended sets thereof.

[0143] In this embodiment, memory 4400 may include read-only memory and random access memory, and provides instructions and data to processor 4100. A portion of memory 4400 may also include non-volatile random access memory (NVRAM).

[0144] In this embodiment, the memory 4400, the communication interface 4300, and the memory 4400 are coupled together via a bus system 4200. The bus system 4200 includes a data bus, and may also include a power bus, a control bus, and a status signal bus, etc. For ease of description, in... Figure 4 The general labeled all buses as Bus System 4200.

[0145] The methods described in the embodiments of this application can be applied to, or implemented by, processor 4100. Processor 4100 may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above methods can be completed by integrated logic circuits in the hardware of processor 4100 or by instructions in software form. Processor 4100 may be a general-purpose processor (e.g., a microprocessor or conventional processor), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gates, transistor logic devices, or discrete hardware components. Processor 4100 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this invention.

[0146] Please see the appendix Figure 5 This is a schematic diagram of the structure of a computer-readable storage medium provided in an embodiment of the present invention, such as... Figure 5 As shown, a computer-readable storage medium 5000 stores program code 5100 for performing the method steps according to the present invention. When executed by a processor, the program code 5100 for performing the method steps according to the present invention implements the method of backing up critical data using a cache during the SoC startup phase as described above. The method of backing up critical data using a cache during the SoC startup phase has been described in detail above and will not be repeated here.

[0147] The methods described in the above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any combination thereof. The computer-readable medium 5000 may include computer storage media and communication media, and may also include any medium capable of transferring a computer program from one place to another. The storage medium can be any target medium accessible by a computer.

[0148] As one possible design, computer-readable medium 5000 may include compact disc read-only memory (CDROM), RAM, ROM, EEPROM, or other optical disc storage; computer-readable medium may include disk storage or other disk storage devices. Furthermore, any connecting cable may also be appropriately referred to as computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. As used herein, disks and optical discs include optical discs (CD), laser discs, optical discs, digital versatile discs (DVD), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs optically reproduce data using lasers.

[0149] Please see Figure 6 The diagram illustrates a structural schematic of a computer device according to an embodiment of this application, such as... Figure 6 As shown, the computer device 6000 includes a memory 6100, a processor 6200, and a computer program stored in the memory 6100 and executable by the processor, wherein the processor 6200 executes... Figure 5 When the program code 5100 stored in the computer-readable storage medium 5000, which is used to execute the steps of the method according to the present invention, is executed, the system control for backing up critical data using a cache during the SoC startup phase can be realized. The method for backing up critical data using a cache during the SoC startup phase has been described in detail above and will not be repeated here.

[0150] The memory 6100 may be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), EPROM, hard disk, or ROM. The memory 6100 has storage space 6300 for storing program code 6400 for performing the method steps according to the invention. The program code 6400 for performing the method steps according to the invention may be read from or written to one or more computer program products. These computer program products include program code carriers such as hard disks, CDs, memory cards, or floppy disks. The computer device may include multiple processors, each of which may be a single-core processor or a multi-core processor. Here, a processor may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0151] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive), etc.

[0152] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. This program can be stored in a computer-readable storage medium, and when executed, it can include the processes described in the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM or random access memory (RAM), magnetic disks, or optical disks.

[0153] The above are preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made to the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A method for backing up RAM data using cache during the SoC startup phase, characterized in that, This method performs at least the following steps: Step 1: Power on the SoC and perform basic initialization; Step 2: Transfer RAM data to the cache, which is done either through the DMA controller or initiated by the CPU; among which, The above-mentioned data transfer via the DMA controller includes: first, configuring the DMA; then, Initiate DMA transfer and write RAM data to the cache via the consistency bus; wherein configuring DMA specifically includes: setting the source address to the RAM region to be backed up; setting the target address to a preset address window reserved in the SoC memory mapping; configuring the DMA controller so that its initiated data transfer transactions carry a bus signal indicating cacheability, thereby writing data to the cache via the consistency bus. The above-mentioned data transfer initiated by the CPU specifically includes: First, the CPU initializes the Memory Management Unit (MMU); second, the CPU executes the memory copy process: copying the RAM data to a virtual address that has been configured as cacheable, and the data will automatically enter the cache. Step 3: Secondary boot loading and DDR initialization, specifically including: After the RAM data backup is complete, perform the following operations: Load the complete secondary bootloader: Load the secondary bootloader containing DDR initialization code from the storage device into the backed-up RAM area; The CPU jumps to execute the secondary boot program in RAM to complete DDR initialization; Complete DDR controller training and establish a usable physical address space; Step 4: Remap and data persistence; Step 5: System startup and anomaly analysis; The Remap remapping remaps the source address space used for backup data to the DDR physical address. Step 4 also includes performing a cache refresh operation, forcing the backup data in the cache to be written to the DDR target area; Step 5 specifically includes: after transferring the RAM data in the cache to DDR, the operating system boot process will continue to be executed; when a system exception is triggered, the backup data in DDR will be read through the debug interface; and the crash scene will be reconstructed by combining the register snapshot.

2. The method for backing up RAM data using cache during the SoC startup phase according to claim 1, characterized in that, Step 1 specifically includes: after the SoC receives external power, the reset circuit releases the reset signal, and the main control CPU core executes the ROM firmware program.

3. The method for backing up RAM data using cache during the SoC startup phase according to claim 1, characterized in that, The consensus bus uses the ACE or CHI protocol.

4. A system for backing up RAM data using cache during the SoC boot phase, the system comprising a power-on and initialization module, a DMA configuration and data transfer module, a DDR initialization module, a remapping module, and an anomaly analysis module; wherein, Power-on and initialization module: used for SoC power-on and basic initialization; Data transfer module: used to transfer RAM data to cache; DDR initialization module: used to load secondary boot code and initialize DDR; Remapping module: used for Remap remapping and data persistence; Anomaly analysis module: used for system startup and anomaly analysis; During the SoC startup phase, the system performs the method described in any one of claims 1-3 for backing up RAM data using cache during the SoC startup phase.

5. A chip, characterized in that, The chip includes at least one processor and a communication interface, the communication interface being coupled to the at least one processor, the at least one processor being used to run computer programs or instructions to implement the method of backing up RAM data using cache during the SoC startup phase as described in any one of claims 1-3.

6. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by the processor of the electronic device, causes the electronic device to perform the method described in any one of claims 1-3 for backing up RAM data using a cache during the SoC startup phase.

7. An electronic device, characterized in that, The device includes one or more processors; a storage device for storing one or more computer programs; and when the one or more computer programs are executed by the one or more processors, the electronic device causes the electronic device to implement a method for backing up RAM data using a cache during the SoC startup phase according to any one of claims 1-3.

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