Test method and device of storage equipment, storage medium and electronic equipment

Abstract

The invention discloses a test method and device of storage equipment, a storage medium and electronic equipment, and relates to the technical field of computers, and the method comprises the following steps: receiving a test request used for requesting signal performance test on the storage equipment; in response to the test request, positioning a target storage part of which the path interference parameter with the control part meets an interference parameter condition from a plurality of storage parts of the storage equipment; controlling the target storage component to transmit data transmission signals to the control component under a plurality of reference configuration parameters, and detecting stability parameters of the data transmission signals received by the control component under the reference configuration parameters; the target configuration parameters with the corresponding stability parameters meeting the stability parameter conditions are screened out from the multiple reference configuration parameters, the target storage component is controlled to execute the target test item under the target configuration parameters, the target test result is obtained, the technical problems that the test efficiency of the storage device is low and the like are solved, and the test efficiency is improved. The technical effect of improving the test efficiency of the storage device is achieved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and more specifically, to a storage device testing method and apparatus, a storage medium, and an electronic device. Background Art

[0002] Existing storage device testing methods typically assess DDR signal integrity using manual oscilloscope operation. This method relies on multiple manual soldering and disassembly of test points, capturing and analyzing eye diagram waveforms one by one to confirm signal quality. While this testing process provides accurate waveform data, it is inherently manual, isolated, and time-consuming.

[0003] The main problem with existing technologies is their low efficiency and incomplete testing. Due to the large number of parameter configuration combinations, manual testing is extremely time-consuming and difficult to cover all possible parameter combinations, making it impossible to find the optimal universal configuration solution.

[0004] In view of technical problems such as low testing efficiency of storage devices in related technologies, no effective solutions have been proposed yet. Summary of the Invention

[0005] The embodiments of the present application provide a storage device testing method and apparatus, a storage medium, and an electronic device to at least solve technical problems in related technologies such as low storage device testing efficiency.

[0006] According to one embodiment of the present application, a method for testing a storage device is provided, comprising:

[0007] receiving a test request for requesting a signal performance test on a storage device;

[0008] In response to the test request, locating a target storage component from a plurality of storage components of the storage device, wherein a path interference parameter between the storage component and the control component satisfies an interference parameter condition, wherein the path interference parameter indicates a degree of interference of the path between the storage component and the control component on a transmitted data transmission signal;

[0009] controlling the target storage component to transmit data transmission signals to the control component under a plurality of reference configuration parameters, respectively, and detecting a stability parameter of the data transmission signal received by the control component under the reference configuration parameters, wherein the stability parameter is used to indicate signal stability of the data transmission signal;

[0010] Filter out target configuration parameters whose corresponding stability parameters meet stability parameter conditions from multiple reference configuration parameters, and control the target storage component to execute target test items under the target configuration parameters to obtain target test results, wherein the target test items are used to test whether the target storage component allows stable operation in a real deployment scenario, and the target test results are used to indicate the signal performance of the storage device.

[0011] According to another embodiment of the present application, a storage device testing apparatus is provided, including:

[0012] A receiving module, configured to receive a test request for requesting a signal performance test on a storage device;

[0013] a positioning module, configured to, in response to the test request, locate, from the plurality of storage components of the storage device, a target storage component whose path interference parameter with the control component satisfies an interference parameter condition, wherein the path interference parameter indicates a degree of interference of the path between the storage component and the control component on a transmitted data transmission signal;

[0014] a control module, configured to control the target storage component to transmit a data transmission signal to the control component under a plurality of reference configuration parameters, and detect a stability parameter of the data transmission signal received by the control component under the reference configuration parameters, wherein the stability parameter is used to indicate signal stability of the data transmission signal;

[0015] A screening module is used to screen out target configuration parameters whose corresponding stability parameters meet the stability parameter conditions from multiple reference configuration parameters, and control the target storage component to execute target test items under the target configuration parameters to obtain target test results, wherein the target test items are used to test whether the target storage component allows stable operation in a real deployment scenario, and the target test results are used to indicate the signal performance of the storage device.

[0016] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned storage device testing methods when executing the computer program.

[0017] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned storage device testing methods are implemented.

[0018] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned storage device testing methods when executed by a processor.

[0019] This application proposes a storage device testing method. First, a "target storage component" whose path interference parameters meet interference parameter requirements is located from multiple storage components. This method focuses testing efforts on the single point most prone to problems (i.e., the target storage component), avoiding repeated testing of all storage components. Subsequently, the solution performs tests under multiple configuration parameters, enabling rapid initial screening and accurate verification of a large number of parameters, significantly improving the efficiency of finding the optimal configuration (i.e., the target configuration parameters). Finally, the solution executes the target test items under the target configuration parameters whose stability parameters meet the stability parameter requirements, using a single, verified optimal solution to represent all possible scenarios, eliminating the need for time-consuming testing of all possible scenarios. Through this intelligent screening and phased verification strategy, the solution significantly reduces the number of tests and the required manpower and resources, thereby fundamentally addressing the technical challenge of low testing efficiency. Consequently, it addresses the technical issue of low storage device testing efficiency in related technologies, achieving the technical effect of improving storage device testing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] Figure 1 This is a hardware structure block diagram of a computer device for a storage device testing method according to an embodiment of the present application;

[0022] Figure 2 is a flow chart of a method for testing a storage device according to an embodiment of the present application;

[0023] Figure 3 is a schematic diagram of a storage device according to an embodiment of the present application;

[0024] Figure 4 is a schematic diagram of a storage device testing system according to an embodiment of the present application;

[0025] Figure 5 is a schematic diagram of a test process of a storage device according to an embodiment of the present application;

[0026] Figure 6 is a structural block diagram of a storage device testing apparatus according to an embodiment of the present application;

[0027] Figure 7 is a schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0029] It should be noted that, in the description of the present application, the terms “comprise”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0030] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below in combination with the drawings and specific embodiments.

[0031] The method embodiments provided in the embodiments of the present application can be executed in a server device or similar computing device. Taking the case of running on a server device, Figure 1 is a hardware structure block diagram of a computer device for a test method of a storage device. As shown in Figure 1 , the server device can include one or more (only one is shown in Figure 1 ) processor 102 (the processor 102 can include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the above-mentioned server device can further include a transmission device 106 for communication function and an input and output device 108. Those skilled in the art can understand that Figure 1 The structure shown is only schematic, which does not limit the structure of the above-mentioned server device. For example, the server device can further include more or less components than those shown in Figure 1 , or have a different configuration from Figure 1 .

[0032] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the test method of the storage device in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, implementing the above-mentioned method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely located relative to the processor 102, and these remote memories may be connected to a server device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0033] Transmission device 106 is used to receive or transmit data via a network. A specific example of the aforementioned network may include a wireless network provided by a communication provider of the server device. In one embodiment, transmission device 106 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0034] In this embodiment, a method for testing a storage device is provided. Figure 2 is a flow chart of a method for testing a storage device according to an embodiment of the present application. Figure 2 As shown, the process includes the following steps:

[0035] Step S12, receiving a test request for requesting a signal performance test on a storage device;

[0036] Step S14, in response to the test request, locating a target storage component from the plurality of storage components of the storage device, wherein a path interference parameter between the storage component and the control component satisfies an interference parameter condition, wherein the path interference parameter indicates a degree of interference of the path between the storage component and the control component on a transmitted data transmission signal;

[0037] Step S16, controlling the target storage component to transmit data transmission signals to the control component under a plurality of reference configuration parameters respectively, and detecting a stability parameter of the data transmission signal received by the control component under the reference configuration parameters, wherein the stability parameter is used to indicate signal stability of the data transmission signal;

[0038] Step S18, filtering out the target configuration parameters whose corresponding stability parameters meet the stability parameter conditions from the multiple reference configuration parameters, and controlling the target storage component to execute the target test items under the target configuration parameters to obtain the target test results, wherein the target test items are used to test whether the target storage component allows stable operation in a real deployment scenario, and the target test results are used to indicate the signal performance of the storage device.

[0039] This application proposes a storage device testing method. First, a "target storage component" whose path interference parameters meet interference parameter requirements is located from multiple storage components. This method focuses testing efforts on the single point most prone to problems (i.e., the target storage component), avoiding repeated testing of all storage components. Subsequently, the solution performs tests under multiple configuration parameters, enabling rapid initial screening and accurate verification of a large number of parameters, significantly improving the efficiency of finding the optimal configuration (i.e., the target configuration parameters). Finally, the solution executes the target test items under the target configuration parameters whose stability parameters meet the stability parameter requirements, using a single, verified optimal solution to represent all possible scenarios, eliminating the need for time-consuming testing of all possible scenarios. Through this intelligent screening and phased verification strategy, the solution significantly reduces the number of tests and the required manpower and resources, thereby fundamentally addressing the technical challenge of low testing efficiency. Consequently, it addresses the technical issue of low storage device testing efficiency in related technologies, achieving the technical effect of improving storage device testing efficiency.

[0040] Optionally, in this embodiment, the storage device may be, but is not limited to, any device with storage functionality, such as an SSD (Solid State Drive) and an HDD (Hard Disk Drive). The storage component may be, but is not limited to, a core component of the complete device, such as a DDR chip responsible for high-speed data caching. The control component may be, but is not limited to, the system-on-chip (SOC) on the SSD (Solid State Drive).

[0041] Optionally, in this embodiment, Figure 3 is a schematic diagram of a storage device according to an embodiment of the present application, such as Figure 3As shown, the storage device is the entire SSD (solid-state drive). It is a complete hardware product, encompassing all components, including the motherboard and chips, used to store data in a computer or server. Optionally, an SSD includes a PCB (printed circuit board), a main control chip (controller), and DDR. The main control chip and DDR are deployed on the PCB and connected via paths to transmit data transmission signals. The storage component refers to the DDR chips (DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory)) on the SSD board. DDR chips are independent chips used to provide high-speed cache memory. A complete SSD typically integrates multiple DDR chips, which are key components for actual storage and high-speed data processing. The control component refers to the main control chip (SOC) on the SSD board. The SOC (System on Chip) is the "brain" of the SSD, responsible for receiving read and write commands from the computer and managing data transfer between the DDR chips and NAND flash memory (another storage component not specifically mentioned in your document). Data transmission signals refer to the DQ signals (data signals) transmitted between the main control chip and the DDR chips. These DQ signals are electrical signals representing 0s and 1s, and are transmitted at high speeds via traces on the PCB (printed circuit board). Path interference parameters refer to various physical factors that affect the quality of DQ signal transmission. Specifically, when DQ signals are transmitted from the main control chip to the DDR chips on the PCB traces, they are affected by loss (signal energy attenuation due to trace length and material properties) and reflection (signal rebound at impedance mismatches). These factors determine the degree of signal interference. Stability parameters are used to quantify the quality of data transmission signals. In this solution, these specifically refer to the eye width and eye height of the eye diagram. Eye width represents the timing margin of the signal, while eye height represents the voltage margin of the signal. Larger eye width and eye height indicate higher signal stability. The signal performance of the storage device is the ultimate assessment of the signal transmission capabilities of the entire SSD system. By comprehensively considering the stability parameters (eye width and eye height) of the DQ signal under different parameter configurations and extreme environments, it determines whether the entire storage device can operate reliably and stably.

[0042] Optionally, in this embodiment, the control component (main control chip) generates data transmission signals (DQ signals), which are then transmitted to the storage components (DDR chips) via paths on the PCB. During transmission, the signals are affected by path interference parameters (loss and reflection). By monitoring the signal stability parameters (eye width and eye height), it is possible to evaluate and ultimately determine whether the signal performance of the entire storage device meets the requirements.

[0043] Optionally, in this embodiment, the storage device testing method may be implemented, but is not limited to, by a storage device testing system. Figure 4 is a schematic diagram of a storage device testing system according to an embodiment of the present application. Figure 4 As shown in the figure, the storage device test system includes: oscilloscope, host computer, server (general server), probe, SSD and temperature chamber. The specific functions are as follows:

[0044] (1) Oscilloscope: Captures the waveform of the received data at the SSD SOC end, converts the electrical signal into a two-dimensional waveform display, and generates an eye diagram to evaluate the high-speed signal quality.

[0045] (2) Host computer: configure the configuration parameters of DDR and the interface rate of DDR. The configurable parameters include DRAMDic and PhyOdtImpedance. DRAMDic (DRAM Drive Impedance Control) determines the driving strength of the DDR particle (memory chip) when sending data signals to the outside. It adjusts the internal circuit of the DDR particle to change the voltage and current strength when sending DQ (data) signals. If the DRAMDic value is high, the signal sent by the DDR particle will be stronger, which helps to overcome signal loss caused by resistance, capacitance and other factors when the signal is transmitted on a longer PCB trace. If the DRAMDic value is low, the signal will be weaker, which helps to reduce signal crosstalk (interference between signals) and overshoot (voltage exceeding the target value) on shorter traces, so that the signal waveform is cleaner. Therefore, the DRAMDic parameter needs to be finely adjusted according to the distance (trace length) between the DDR particle and the host chip to ensure that the signal has enough strength when it reaches the receiving end and maintains good waveform quality. PhyOdtImpedance (Physical On-Die Termination Impedance) is a termination impedance value on the host chip (SOC). Its main function is to absorb signals. When high-speed signals reach the host chip, if the impedance is not matched, the signal will bounce back like hitting a wall, forming a reflected wave. These reflected waves will superimpose on subsequent signals, causing waveform distortion. The function of PhyOdtImpedance is to match the impedance and "absorb" the energy of the signal at the end point to prevent signal reflection. This is like setting a huge "cushion" at the end of the highway to ensure that the car (signal) stops smoothly and does not bounce back to cause chaos. The relationship between DRAMDic and PhyOdtImpedance is "impedance matching": DRAMDic is responsible for ensuring that the signal is sent out from the source with the appropriate strength. PhyOdtImpedance is responsible for "receiving" and "terminating" the signal at the receiving end with the appropriate impedance. When the values of these two parameters are adjusted to match each other, the impedance of the entire signal transmission channel is continuous. In this way, the signal sent out has enough strength to reach the destination, and can be effectively absorbed at the end point without reflection. This perfect match ensures that the DQ signal is clean and stable in high-speed transmission, forming a wide and clear "eye diagram" to ensure the reliability of data transmission. The configuration parameters of DDR can include but are not limited to 14 configurations, as shown in Table 1 below. If all are tested by an oscilloscope, it will take a lot of time.

[0046] Table 1

[0047]

[0048] (3) Server (General Server) The server plays a core "execution" role in the test. It is not just a power supply; more importantly, it is responsible for running professional business scripts such as FIO (Flexible I / O Tester). These scripts simulate real-world data read and write patterns, thereby generating continuous, high-pressure workloads on the SSD. By establishing communication with the SSD and CPU, the server ensures that data can smoothly interact within the SSD (between the SSD and the onboard DDR) and externally (between the SSD and the CPU), providing a real and reliable data flow for subsequent signal testing.

[0049] (4) A temperature chamber is a device used to simulate extreme environments. Its main function is to perform cycle tests within a temperature range of 0°C to 85°C to verify the SSD's tolerance. This is because in real-world applications, SSDs may operate in high or low temperature environments for long periods of time, and these temperature fluctuations can seriously affect the quality of DDR signals and even cause data errors. Temperature chamber testing ensures that the SSD maintains reliability even under the harshest conditions.

[0050] (5) SSD: The SSD is the ultimate target of this test. It is a complete storage device that integrates DDR chips (for high-speed data caching) and the SOC (main control chip). These two key components frequently transmit data in the SSD's daily operations. All tests, whether eye pattern scanning or high and low temperature cycling, are aimed at evaluating and verifying the signal integrity and performance reliability of the SSD as a whole during data exchange between these core components.

[0051] The test system executes the test method which consists of several stages:

[0052] 1. Preparation and Control Phase: The host computer serves as the command center, issuing all high-level commands. This includes sending DDR initialization and training instructions, configuring various DDR parameters (such as drive strength and impedance), and switching DDR rates. The server, acting as the executor, receives host computer instructions and translates them into specific operations, such as sending SSD read and write patterns that simulate real-world loads and performing fast electronic eye diagram tests.

[0053] 2. Screening and Verification Phase: First, a DDR electronic eye diagram scan is used to quickly identify configurations with sufficient margins for eye width and height. This scan provides a quick preliminary assessment, aiming to quickly identify potential qualified configurations from a large number of configurations. These qualified configurations are then accurately tested using an oscilloscope. The oscilloscope uses a probe to capture the DQ signal waveform and generate a visual eye diagram, resulting in accurate test results. During this process, FIO service testing is performed to simulate real data flows to ensure the validity of the test results.

[0054] 3. Final reliability testing phase: After finding the maximum DDR rate and optimal parameter combination, the SSD under test is placed in an incubator. Under the incubator's high and low temperature cycling environment, the SSD undergoes a 72-hour FIO service test to verify whether DDR signal quality deteriorates under extreme temperature conditions, leading to data errors. After the test, logs are collected and checked for error anomalies to determine whether the test passed. If there are no errors, this proves that the selected parameter and rate combination is appropriate and that the SSD can maintain signal integrity in this harsh environment.

[0055] As an optional solution, locating a target storage component whose path interference parameter with the control component satisfies an interference parameter condition from the multiple storage components of the storage device further includes:

[0056] S21, identifying, from the plurality of storage components based on the path connection relationship between the plurality of storage components and the control component in the storage device, a first storage component whose loss interference parameter satisfies a loss parameter condition, and a second storage component whose reflection interference parameter satisfies a reflection parameter condition, wherein the path interference parameter includes the loss interference parameter and / or the reflection interference parameter, the loss interference parameter indicates the degree of interference caused by signal loss of the path on the transmitted data transmission signal, the reflection interference parameter indicates the degree of interference caused by signal reflection of the path on the transmitted data transmission signal, and the interference parameter condition includes the loss parameter condition and / or the reflection parameter condition;

[0057] S22: Locate the target storage component from the first storage component and the second storage component.

[0058] Optionally, in this embodiment, on an SSD card, the system-on-chip (SOC) connects to multiple DDR chips via PCB traces. The testing method analyzes the PCB design files to identify the connection paths between all DDR chips and the SOC. This analysis determines that the DDR chip farthest from the SOC has the longest signal path, resulting in the greatest energy attenuation during signal transmission due to trace impedance and capacitance. It also determines that the DDR chip closest to the SOC has the shortest signal path, resulting in the strongest reflection when the signal reaches the terminal due to impedance abruptness. The DQ signals of the DDR chips at these two physical locations are identified as the first and second storage components with the largest loss interference parameters and reflection interference parameters, respectively. The target storage components requiring focused testing are then identified. Path interference parameters are concepts that quantify signal integrity issues and specifically include loss interference and reflection interference parameters. The loss interference parameter indicates signal attenuation due to energy consumption during transmission and is positively correlated with path length. The reflection interference parameter indicates signal bounce at the transmission endpoint due to impedance mismatch and is negatively correlated with path length. This solution provides an efficient entry point for subsequent testing by identifying these extreme interference points.

[0059] This embodiment significantly improves test efficiency and targeting. By intelligently identifying and selecting the most representative "worst" test points, this method shifts the focus of testing from all DDR components to a few key points. This avoids repetitive, time-consuming, and potentially useless testing of all components, saving significant time and manpower.

[0060] As an optional solution, the step of identifying, from the plurality of storage components based on the path connection relationship between the plurality of storage components and the control component in the storage device, a first storage component whose loss interference parameter satisfies a loss parameter condition and a second storage component whose reflection interference parameter satisfies a reflection parameter condition, further includes:

[0061] S31, identifying, from the plurality of storage components, a storage component having the longest path to the control component based on the path connection relationship as the first storage component, wherein the length of the path is positively correlated with the loss interference parameter, and a larger loss interference parameter indicates a greater degree of interference caused by signal loss of the path on the transmitted data transmission signal;

[0062] S32, identifying the storage component with the shortest path between the storage component and the control component from the multiple storage components according to the path connection relationship as the second storage component, wherein the length of the path is negatively correlated with the reflection interference parameter, and the larger the loss interference parameter is, the greater the degree of interference of the signal reflection of the path on the transmitted data transmission signal.

[0063] Optionally, in this embodiment, the test method accurately measures the PCB trace length between the main control chip and each DDR particle based on the design drawings of the SSD board. The measurement results show that among all the traces, there is a longest path, whose length is, for example, 100mm, which causes the signal loss interference parameter to be the largest, and the DDR particles connected to this path are identified as the first storage component. At the same time, there is a shortest path, whose length is, for example, 10mm, which causes the signal to produce the strongest reflection at the terminal, and its reflection interference parameter is the largest, and the DDR particles connected to this path are identified as the second storage component. This embodiment defines in detail how to determine the storage component with the largest loss interference parameter and reflection interference parameter. The loss is positively correlated with the path length, that is, the longer the path, the greater the signal energy attenuation, resulting in a decrease in the eye diagram height. The reflection is negatively correlated with the path length, that is, the shorter the path, the more serious the interference of the signal rebounding at the terminal, resulting in a decrease in the eye diagram width.

[0064] This embodiment provides a specific and practical test point selection method. By directly determining key test points based on the physical layout, the positioning process is made more accurate, ensuring the scientific nature of the test, and automating the test process, avoiding errors caused by human judgment.

[0065] As an optional solution, locating the target storage component from the first storage component and the second storage component further includes:

[0066] S41, controlling the first storage component and the second storage component to transmit the data transmission signal to the control component respectively under the same candidate configuration parameters;

[0067] S42, performing an eye scan operation on the first data transmission signal of the first storage component received by the control component to obtain a first stability parameter of the first data transmission signal, and performing the eye scan operation on the second data transmission signal of the second storage component received by the control component to obtain a second stability parameter of the second data transmission signal, wherein the eye scan operation is an operation of detecting the stability parameter by scanning the data transmission signal, and a detection speed of the eye scan operation for detecting the stability parameter is greater than a preset speed;

[0068] S43: if the first stability parameter is greater than the second stability parameter, determine the second storage component as the target storage component;

[0069] S44: When the first stability parameter is smaller than the second stability parameter, determine the first storage component as the target storage component.

[0070] Optionally, in this embodiment, the server's electronic eye scan operation is used to quickly evaluate the first storage component (with the highest loss) and the second storage component (with the highest reflection) identified from multiple DDR chips. Under certain parameter configurations, the server scanned the first storage component to obtain an eye width of 220ps and an eye height of 330mV; the second storage component to obtain an eye width of 200ps and an eye height of 310mV. Because the second storage component's stability parameters (eye width and eye height) are smaller and its signal quality is poorer, it is identified as the only target storage component requiring precise oscilloscope testing in the next step. Eye scan is a high-speed, automated signal detection method that rapidly obtains stability parameters (eye width and eye height) by scanning the data signal, significantly exceeding manual oscilloscope operation. Stability parameters quantify the signal's stability. Eye width represents the signal's timing margin, while eye height represents the signal's voltage margin.

[0071] This embodiment can significantly reduce the number of oscilloscope tests. By using faster but less accurate electronic eye scans for pre-screening, engineers no longer need to perform time-consuming oscilloscope tests on all test points, thereby saving a significant amount of testing time and manpower.

[0072] As an optional solution, controlling the target storage component to transmit data transmission signals to the control component under multiple reference configuration parameters respectively, and detecting stability parameters of the data transmission signals received by the control component under the reference configuration parameters, further comprising:

[0073] S51, obtaining a plurality of reference configuration parameters;

[0074] S52, controlling the target storage component to transmit a data transmission signal to the control component under a plurality of reference configuration parameters respectively, and performing an oscilloscope detection operation on the data transmission signal received by the control component under each reference configuration parameter to obtain a stability parameter corresponding to each reference configuration parameter, wherein the oscilloscope detection operation is an operation of detecting the stability parameter by acquiring the waveform of the data transmission signal by an oscilloscope, and the detection accuracy of the stability parameter detected by the oscilloscope detection operation is greater than a preset accuracy.

[0075] Optionally, in this embodiment, an oscilloscope is used to perform precise eye diagram testing on the target storage components that have undergone preliminary screening. For example, if the host computer configures DRAM Dic = 1.25V and PhyOdt Impedance = 40Ω, the oscilloscope uses a probe to capture the complete waveform of the DQ signal and generate a high-precision eye diagram. Every detail of the eye diagram can be clearly observed, and the eye width and eye height can be accurately measured to determine whether they meet the spec requirements (e.g., eye width ≥ 200ps, eye height ≥ 300mV). Concept Explanation: Oscilloscope detection operation is a high-precision, low-speed measurement method that captures the complete signal waveform, providing the most reliable and detailed signal stability data, and is the "gold standard" for signal integrity testing.

[0076] This embodiment provides high-precision, high-reliability signal quality verification. By introducing an oscilloscope, this solution ensures that the final selected configuration is the optimal solution that truly meets the stringent standards, eliminating the possibility of misjudgment due to insufficient rapid scanning accuracy.

[0077] As an optional solution, obtaining a plurality of the reference configuration parameters further includes:

[0078] S61, obtaining multiple initial configuration parameters;

[0079] S62, controlling the target storage component to transmit data transmission signals to the control component under the multiple initial configuration parameters respectively, and performing an eye pattern scanning operation on the data transmission signal received by the control component under each of the initial configuration parameters to obtain a stability parameter corresponding to each of the multiple initial configuration parameters, wherein the eye pattern scanning operation is an operation of detecting the stability parameter by scanning the data transmission signal, a detection speed of the stability parameter detected by the eye pattern scanning operation is greater than a detection speed of the stability parameter detected by the oscilloscope detection operation, and a detection accuracy of the stability parameter detected by the eye pattern scanning operation is lower than a detection accuracy of the stability parameter detected by the oscilloscope detection operation;

[0080] S63: Eliminate the configuration parameters whose stability parameters are lower than the first stability threshold from the multiple initial configuration parameters to obtain the multiple reference configuration parameters.

[0081] Optionally, in this embodiment, assume that there are 14 initial configuration parameters that need to be tested. This solution does not perform time-consuming oscilloscope testing on all 14 configurations. Instead, it first uses a faster electronic eye scan to directly eliminate configurations whose eye width and eye height fall below a certain first stability threshold (for example, 200ps and 300mV). If only three configurations meet the requirements after the scan, these three configurations serve as reference configuration parameters for the oscilloscope test, significantly narrowing the test scope. This solution details how to obtain the reference configuration parameters. By first performing a high-speed, low-precision eye scan operation and then screening according to the first stability threshold, unqualified initial configuration parameters are eliminated, thereby obtaining reference configuration parameters for subsequent high-precision testing.

[0082] This embodiment achieves a collaborative "coarse screening-fine testing" model, significantly improving overall testing efficiency. Automated, rapid initial screening replaces time-consuming, comprehensive manual testing, allowing the oscilloscope to conduct precise testing on only a few promising solutions, reducing testing time from days to hours.

[0083] As an optional solution, selecting a target configuration parameter whose corresponding stability parameter satisfies a stability parameter condition from a plurality of reference configuration parameters includes one of the following:

[0084] S71, determining the reference configuration parameter whose corresponding stability parameter is greater than a second stability threshold among the plurality of reference configuration parameters as the target configuration parameter;

[0085] S72: Determine the reference configuration parameter having the largest corresponding stability parameter among the plurality of reference configuration parameters as the target configuration parameter.

[0086] Alternatively, in this embodiment, among the three qualified configurations tested by oscilloscope, Configuration A has an eye width of 220ps and an eye height of 330mV; Configuration B has an eye width of 240ps and an eye height of 350mV; and Configuration C has an eye width of 250ps and an eye height of 400mV. Based on this solution, engineers will select Configuration C, which has the largest eye margin, as the final target configuration parameters because it has the most robust signal. The stability threshold is the minimum passing standard for eye width and eye height, and the most stable configuration is the one with the largest eye margin among all qualified configurations.

[0087] This embodiment ensures that the solution ultimately used for high-intensity testing is the most robust, ensuring that even under extreme conditions, the system can meet challenges with the most robust parameters, laying a solid foundation for subsequent verification.

[0088] As an optional solution, controlling the target storage component to execute the target test item under the target configuration parameters to obtain the target test result further includes:

[0089] S81, obtaining a maximum value of the transmission rate of the target storage component under the target configuration parameters to obtain a target transmission rate, wherein the transmission rate refers to the rate at which the target storage component transmits data transmission signals to the control component;

[0090] S82, controlling the target storage component to operate at the target transmission rate under the target configuration parameters, and detecting an operating state of the target storage component during the operation of the target storage component;

[0091] S83, when it is detected that the target storage component is in a normal operating state for a period greater than or equal to a preset period, determining that the target test result indicates that the signal performance of the storage device meets a preset signal performance;

[0092] S84: When it is detected that the target storage component is in a normal operating state for a period of time shorter than the preset period of time, determine that the target test result indicates that the signal performance of the storage device does not meet the preset signal performance.

[0093] Optionally, in this embodiment, after determining the optimal configuration, by changing the DDR rate, the test system finds that the maximum transmission rate that can stably work under this configuration is 4266MHz. Next, the SSD is run under this optimal configuration and 4266MHz rate for 72 hours for the FIO business test. During this period, the Server continuously monitors the logs, and if no errors are recorded, the test is determined to have passed. Concept explanation: The target transmission rate is the maximum stable rate that can be achieved under this configuration; the preset time (such as 72 hours) is used to simulate the pressure of long-term operation. The detection of the operating status refers to judging whether the system has data transmission errors or crashes through logs or other monitoring means.

[0094] This example verifies the performance ceiling of the storage device under optimal configuration, ensuring its long-term stable operation at the highest speed, demonstrating the product's top-level performance and reliability.

[0095] As an optional solution, controlling the target storage component to execute the target test item under the target configuration parameters to obtain the target test result includes:

[0096] S91, obtaining a maximum value of the transmission rate of the target storage component under the target configuration parameters to obtain a target transmission rate, wherein the transmission rate refers to the rate at which the target storage component transmits data transmission signals to the control component;

[0097] S92, controlling the target storage component to operate according to the target configuration parameters and the target transmission rate at multiple ambient temperatures, and detecting an operating state of the target storage component at each of the ambient temperatures;

[0098] S93, when it is detected that the target storage component is in a normal operating state for a period greater than or equal to a preset period under the multiple ambient temperatures, determining that the target test result indicates that the signal performance of the storage device meets a preset signal performance;

[0099] S94: When it is detected that under multiple ambient temperatures, the target storage component is in a normal operating state for a period that is less than the preset period, determining that the target test result indicates that the signal performance of the storage device does not meet the preset signal performance.

[0100] Optionally, in this embodiment, the SSD is placed in an incubator at the optimal configuration and maximum rate, and cycle tests are performed at multiple temperatures, such as 0°C, 25°C, and 85°C. In each temperature range, the SSD runs the FIO business test and records the log. If there are no errors in the tests of all temperature ranges, the test is considered to have passed. Concept explanation: Multiple ambient temperatures are intended to simulate the harsh working environment of the real world. Normal operating status means that no data errors occur during continuous operation.

[0101] This embodiment ensures the reliability of the product in various harsh environments. This high and low temperature cycle test proves the signal integrity and robustness of the product, making it adaptable to a wider range of real-world application scenarios and improving its universality.

[0102] Optionally, in this embodiment, in order to better understand the testing process of the above-mentioned storage device, the testing process of the above-mentioned storage device is described below in combination with an optional embodiment, but it is not used to limit the technical solution of the embodiment of this application.

[0103] In this embodiment, a method for testing a storage device is provided. Figure 5 is a schematic diagram of a test process of a storage device according to an embodiment of the present application, such as Figure 5 As shown, it mainly includes the following steps:

[0104] Step S501: Test starts;

[0105] Step S502: Connect the oscilloscope to the probe and fix the target DQ of the SSD;

[0106] Step S503: The SSD is plugged into the server and powered on. The server recognizes that the target disk is in place.

[0107] Step S504: The host computer establishes communication with the target SSD via the UART interface and configures the DDR rate;

[0108] Step S505: configure DRAMDic parameters and PhyOdtimpedance parameters;

[0109] Step S506: The host computer completes DDR initialization and DDR Training;

[0110] Step S507: The host computer remotely controls the server to execute a complex pattern script (a data pattern or sequence with specific read and write behaviors used for testing. It is not random data but a series of pre-set operation instructions used to simulate real business scenarios).

[0111] Step S508: Output the DDR eye diagram result and analyze the eye width and eye height;

[0112] Step S509: Check whether the eye height and eye width of the eye diagram have a certain margin. If yes, proceed to step S510; if not, proceed to step S505.

[0113] Step S510: Record DRAMDic parameter 1 and PhyOdtImpedance parameter 1 to record the current DDR rate;

[0114] Step S511: The host computer remotely controls the server to execute various FIO business scripts;

[0115] Step S512: The oscilloscope captures the full-screen waveform, including the DQ and DQS signals, with the amplitude occupying 80% of the screen;

[0116] Step S513: The oscilloscope uses an eye diagram analysis tool to analyze the waveform and generate an eye diagram;

[0117] Step S514: Check whether the eye height and eye width of the eye diagram are greater than spec. If yes, proceed to step S515; if not, proceed to step S510.

[0118] Step S515: Record DRAMDic parameter 2 and PhyOdtlmpedance parameter 2 to record the current DDR rate;

[0119] Step S516: By adjusting the temperature of the incubator, the host computer executes various FIO business scripts to enable the SSD to operate in high and low temperature environments;

[0120] Step S517: Collect logs and check whether there are any DDR single or double bit errors. If yes, proceed to step S504; if no, proceed to step S518.

[0121] Step S518: The test ends.

[0122] In summary, the testing process for the above storage devices is divided into the following stages:

[0123] Phase 1: Identify key test points. First, confirm the SSD board's DDR layout. The system-on-chip (SoC) and DDR chips transmit data via inner-layer PCB traces. Based on this, select the DDR chips farthest and closest to the SoC. The farthest chip experiences the greatest loss due to long traces, while the closest chip experiences the greatest interference due to reflections. These two points represent the two worst-case signal conditions, and their corresponding DQ signals (DQ1 and DQ2) will be the primary test targets.

[0124] Phase 2: Configure and conduct preliminary testing. For both DQ1 and DQ2 signals, the host computer must use the same DRAMDic (DQ signal drive strength) and PhyOdtImpedance (PHY ODT impedance) parameter configurations to ensure uniformity and comparability of the tests.

[0125] Phase 3: Rapid eye scan: The host computer sends a command to start the DDR initialization and training process. The server then performs an electronic eye scan, and the host computer prints the eye width and height test results via UART.

[0126] Phase 4: Screening the optimal test target. Both eye width and eye height must maintain a certain margin. The test system compares the eye margin results for DQ1 and DQ2 under the same parameters. Across all parameter configurations, the DQ signal with the smallest margin is selected for the next oscilloscope test. This allows oscilloscope measurement results to be obtained by testing only one set of DQ signals.

[0127] Phase 5: High-precision oscilloscope testing: The selected DQ signal to be tested is soldered and connected to the oscilloscope. The oscilloscope will iterate through all configuration parameters that have passed the initial screening and perform eye diagram testing. Only when the eye width and eye height meet the specification requirements will the current DDR parameter configuration and rate be recorded. If not, the configuration must be changed and the test must be repeated.

[0128] Phase 6: Update the rate and retrain. Using the optimal parameter configuration obtained during oscilloscope testing, the host computer reinitializes and retrains the DDR. The DDR rate is then updated, starting with the lowest rate and gradually stepping up to the maximum rate supported by the DDR. When both the eye width and eye height meet the specifications, the system confirms the parameter configuration and DDR rate and records it as "Parameter Configuration 2."

[0129] Phase 7: High and low temperature cycle stress test: Using the currently optimized parameter configuration (parameter configuration 2) and the maximum DDR rate, the SSD is placed in an incubator and subjected to high and low temperature cycle testing. Simultaneously, the FIO service test is run for 72 hours.

[0130] Phase 8: Results Collection and Verification: After the test is complete, all logs are collected and any errors or exceptions are recorded. If there are no errors in the logs, the test has passed, the selected DDR parameter configuration and rate are reasonable and effective, and DDR signal integrity verification has been successfully achieved.

[0131] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0132] Based on this understanding, the technical solution of this application or the part that contributes to the existing technology can be embodied in the form of a software product. The computer software product is stored in a storage medium (such as ROM / RAM, disk, CD-ROM), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of this application.

[0133] This embodiment also provides a storage device testing device for implementing the above-mentioned embodiments and preferred implementations. Details already described will not be repeated here. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0134] Figure 6 is a structural block diagram of a test device for a storage device according to an embodiment of the present application; Figure 6 Shown, including:

[0135] A receiving module 602 is configured to receive a test request for requesting a signal performance test on a storage device;

[0136] a positioning module 604, configured to, in response to the test request, locate, from the plurality of storage components of the storage device, a target storage component whose path interference parameter with the control component satisfies an interference parameter condition, wherein the path interference parameter indicates a degree of interference of the path between the storage component and the control component on a transmitted data signal;

[0137] a control module 606, configured to control the target storage component to transmit a data transmission signal to the control component under a plurality of reference configuration parameters, and detect a stability parameter of the data transmission signal received by the control component under the reference configuration parameters, wherein the stability parameter is used to indicate signal stability of the data transmission signal;

[0138] The screening module 608 is used to screen out the target configuration parameters whose corresponding stability parameters meet the stability parameter conditions from the multiple reference configuration parameters, and control the target storage component to execute the target test items under the target configuration parameters to obtain the target test results, wherein the target test items are used to test whether the target storage component allows stable operation in a real deployment scenario, and the target test results are used to indicate the signal performance of the storage device.

[0139] In an exemplary embodiment, the positioning module includes:

[0140] an identification unit, configured to identify, from the plurality of storage components, a first storage component whose loss interference parameter satisfies a loss parameter condition, and a second storage component whose reflection interference parameter satisfies a reflection parameter condition, based on a path connection relationship between the plurality of storage components and the control component in the storage device, wherein the path interference parameter includes the loss interference parameter and / or the reflection interference parameter, the loss interference parameter indicates a degree of interference caused by a signal loss of a path on a transmitted data transmission signal, the reflection interference parameter indicates a degree of interference caused by a signal reflection of a path on a transmitted data transmission signal, and the interference parameter condition includes the loss parameter condition and / or the reflection parameter condition;

[0141] A positioning unit is used to locate the target storage component from the first storage component and the second storage component.

[0142] In an exemplary embodiment, the identification unit is further configured to:

[0143] identifying, from the plurality of storage components according to the path connection relationship, a storage component having the longest path to the control component as the first storage component, wherein the length of the path is positively correlated with the loss interference parameter, and a larger loss interference parameter indicates a greater degree of interference of the signal loss of the path on the transmitted data transmission signal;

[0144] According to the path connection relationship, a storage component with the shortest path between the storage component and the control component is identified from the multiple storage components as the second storage component, wherein the length of the path is negatively correlated with the reflection interference parameter, and the larger the loss interference parameter is, the greater the degree of interference of the signal reflection of the path on the transmitted data transmission signal.

[0145] In an exemplary embodiment, the positioning unit is further configured to:

[0146] controlling the first storage component and the second storage component to transmit the data transmission signal to the control component respectively under the same candidate configuration parameters;

[0147] performing an eye scan operation on a first data transmission signal of the first storage component received by the control component to obtain a first stability parameter of the first data transmission signal, and performing the eye scan operation on a second data transmission signal of the second storage component received by the control component to obtain a second stability parameter of the second data transmission signal, wherein the eye scan operation is an operation of detecting the stability parameter by scanning the data transmission signal, and a detection speed of the eye scan operation for detecting the stability parameter is greater than a preset speed;

[0148] When the first stability parameter is greater than the second stability parameter, determining the second storage component as the target storage component;

[0149] In a case where the first stability parameter is smaller than the second stability parameter, the first storage component is determined as the target storage component.

[0150] In an exemplary embodiment, the control module includes:

[0151] A first acquiring unit, configured to acquire a plurality of reference configuration parameters;

[0152] A first control unit is used to control the target storage component to transmit a data transmission signal to the control component under a plurality of reference configuration parameters, and perform an oscilloscope detection operation on the data transmission signal received by the control component under each reference configuration parameter to obtain a stability parameter corresponding to each reference configuration parameter, wherein the oscilloscope detection operation is an operation of detecting the stability parameter by acquiring the waveform of the data transmission signal by an oscilloscope, and the detection accuracy of the stability parameter detected by the oscilloscope detection operation is greater than a preset accuracy.

[0153] In an exemplary embodiment, the first acquiring unit is further configured to:

[0154] Get multiple initial configuration parameters;

[0155] controlling the target storage component to transmit a data transmission signal to the control component under the multiple initial configuration parameters, and performing an eye scan operation on the data transmission signal received by the control component under each of the initial configuration parameters to obtain a stability parameter corresponding to each of the multiple initial configuration parameters, wherein the eye scan operation is an operation of detecting the stability parameter by scanning the data transmission signal, a detection speed of the stability parameter detected by the eye scan operation is greater than a detection speed of the stability parameter detected by the oscilloscope detection operation, and a detection accuracy of the stability parameter detected by the eye scan operation is lower than a detection accuracy of the stability parameter detected by the oscilloscope detection operation;

[0156] Configuration parameters whose stability parameters are lower than a first stability threshold are eliminated from the multiple initial configuration parameters to obtain the multiple reference configuration parameters.

[0157] In an exemplary embodiment, the screening module includes one of the following:

[0158] a first determining unit, configured to determine, among the plurality of reference configuration parameters, the reference configuration parameter corresponding to the stability parameter greater than a second stability threshold as the target configuration parameter;

[0159] The second determining unit is configured to determine the reference configuration parameter having the largest corresponding stability parameter among the plurality of reference configuration parameters as the target configuration parameter.

[0160] In an exemplary embodiment, the screening module includes:

[0161] a second acquiring unit, configured to acquire a maximum value of the transmission rate of the target storage component under the target configuration parameters, to obtain a target transmission rate, wherein the transmission rate refers to a rate at which the target storage component transmits a data transmission signal to the control component;

[0162] a second control unit, configured to control the target storage component to operate at the target transmission rate under the target configuration parameters, and to detect an operating state of the target storage component during its operation;

[0163] a third determining unit, configured to, when detecting that the target storage component is in a normal operating state for a period greater than or equal to a preset period, determine that the target test result indicates that the signal performance of the storage device meets a preset signal performance;

[0164] The fourth determining unit is configured to determine that the target test result is used to indicate that the signal performance of the storage device does not meet the preset signal performance, in a case where it is detected that the duration in which the target storage component is in the normal operation state is less than the preset duration.

[0165] In an example embodiment, the screening module comprises:

[0166] The third obtaining unit is configured to obtain a maximum value of a transmission rate allowed to be reached by the target storage component under the target configuration parameter, to obtain a target transmission rate, wherein the transmission rate refers to a rate at which the target storage component transmits a data transmission signal to the control component.

[0167] The third control unit is configured to control the target storage component to operate according to the target configuration parameter and the target transmission rate at a plurality of environmental temperatures respectively, and to detect an operation state of the target storage component operating at each of the environmental temperatures.

[0168] The fifth determining unit is configured to determine that the target test result is used to indicate that the signal performance of the storage device meets the preset signal performance, in a case where it is detected that the duration in which the target storage component is in the normal operation state is greater than or equal to the preset duration at the plurality of environmental temperatures.

[0169] The sixth determining unit is configured to determine that the target test result is used to indicate that the signal performance of the storage device does not meet the preset signal performance, in a case where it is detected that the duration in which the target storage component is in the normal operation state is less than the preset duration at the plurality of environmental temperatures.

[0170] It should be noted that each of the above modules can be implemented by software or hardware, and for the latter, the following implementation manners can be used, but are not limited thereto: all of the above modules are located in the same processor; or the above modules are located in different processors in any combination.

[0171] The features of the embodiments of the testing device of the storage device can be referred to the related descriptions of the embodiments of the testing method of the storage device, which will not be repeated here.

[0172] The embodiments of the present application also provide an electronic device, Figure 7 is a schematic diagram of the electronic device according to the embodiments of the present application, as Figure 7 shown, the electronic device comprises a memory and a processor, the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the embodiments of the testing method of the storage device described above.

[0173] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0174] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0175] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned storage device testing method embodiments when run.

[0176] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0177] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0178] An embodiment of the present application further provides a computer program product, comprising a computer program, which, when executed by a processor, implements the steps of the method described in each embodiment of the present application; the computer program product further comprises a non-volatile computer-readable storage medium, which stores the computer program, which, when executed by a processor, implements the steps of the storage device testing method described in each embodiment of the present application.

[0179] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0180] The above is a detailed introduction to a storage device testing method provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. It should be pointed out that, for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A method for testing a storage device, characterized in that: include: receiving a test request for requesting a signal performance test on a storage device; In response to the test request, locating a target storage component from a plurality of storage components of the storage device, wherein a path interference parameter between the storage component and the control component satisfies an interference parameter condition, wherein the path interference parameter indicates a degree of interference of the path between the storage component and the control component on a transmitted data transmission signal; controlling the target storage component to transmit data transmission signals to the control component under a plurality of reference configuration parameters, respectively, and detecting a stability parameter of the data transmission signal received by the control component under the reference configuration parameters, wherein the stability parameter is used to indicate signal stability of the data transmission signal; Filter out target configuration parameters whose corresponding stability parameters meet stability parameter conditions from multiple reference configuration parameters, and control the target storage component to execute target test items under the target configuration parameters to obtain target test results, wherein the target test items are used to test whether the target storage component allows stable operation in a real deployment scenario, and the target test results are used to indicate the signal performance of the storage device.

2. The method according to claim 1, characterized in that The step of locating a target storage component from among the plurality of storage components of the storage device, wherein the path interference parameter between the target storage component and the control component satisfies the interference parameter condition, comprises: identifying, from the plurality of storage components according to the path connection relationship between the plurality of storage components and the control component in the storage device, a first storage component whose loss interference parameter satisfies a loss parameter condition, and a second storage component whose reflection interference parameter satisfies a reflection parameter condition, wherein the path interference parameter includes the loss interference parameter and / or the reflection interference parameter, the loss interference parameter indicates the degree of interference of a path signal loss on a transmitted data transmission signal, the reflection interference parameter indicates the degree of interference of a path signal reflection on a transmitted data transmission signal, and the interference parameter condition includes the loss parameter condition and / or the reflection parameter condition; The target storage component is located from the first storage component and the second storage component.

3. The method according to claim 2, characterized in that The method of identifying, from the plurality of storage components according to the path connection relationship between the plurality of storage components and the control component in the storage device, a first storage component whose loss interference parameter satisfies a loss parameter condition and a second storage component whose reflection interference parameter satisfies a reflection parameter condition, comprises: identifying, from the plurality of storage components according to the path connection relationship, a storage component having the longest path to the control component as the first storage component, wherein the length of the path is positively correlated with the loss interference parameter, and a larger loss interference parameter indicates a greater degree of interference of the signal loss of the path on the transmitted data transmission signal; According to the path connection relationship, a storage component with the shortest path between the storage component and the control component is identified from the multiple storage components as the second storage component, wherein the length of the path is negatively correlated with the reflection interference parameter, and the larger the loss interference parameter is, the greater the degree of interference of the signal reflection of the path on the transmitted data transmission signal.

4. The method according to claim 2, characterized in that The locating the target storage component from the first storage component and the second storage component includes: controlling the first storage component and the second storage component to transmit the data transmission signal to the control component respectively under the same candidate configuration parameters; performing an eye scan operation on a first data transmission signal of the first storage component received by the control component to obtain a first stability parameter of the first data transmission signal, and performing the eye scan operation on a second data transmission signal of the second storage component received by the control component to obtain a second stability parameter of the second data transmission signal, wherein the eye scan operation is an operation of detecting the stability parameter by scanning the data transmission signal, and a detection speed of the eye scan operation for detecting the stability parameter is greater than a preset speed; When the first stability parameter is greater than the second stability parameter, determining the second storage component as the target storage component; In a case where the first stability parameter is smaller than the second stability parameter, the first storage component is determined as the target storage component.

5. The method according to claim 1, wherein The controlling the target storage component to transmit data transmission signals to the control component under a plurality of reference configuration parameters, and detecting stability parameters of the data transmission signals received by the control component under the reference configuration parameters, includes: Acquiring a plurality of reference configuration parameters; The target storage component is controlled to transmit a data transmission signal to the control component under a plurality of reference configuration parameters respectively, and an oscilloscope detection operation is performed on the data transmission signal received by the control component under each reference configuration parameter to obtain a stability parameter corresponding to each reference configuration parameter, wherein the oscilloscope detection operation is an operation of detecting the stability parameter by acquiring the waveform of the data transmission signal by an oscilloscope, and the detection accuracy of the stability parameter detected by the oscilloscope detection operation is greater than a preset accuracy.

6. The method according to claim 5, characterized in that The obtaining of the plurality of reference configuration parameters comprises: Get multiple initial configuration parameters; controlling the target storage component to transmit a data transmission signal to the control component under the multiple initial configuration parameters, and performing an eye scan operation on the data transmission signal received by the control component under each of the initial configuration parameters to obtain a stability parameter corresponding to each of the multiple initial configuration parameters, wherein the eye scan operation is an operation of detecting the stability parameter by scanning the data transmission signal, a detection speed of the stability parameter detected by the eye scan operation is greater than a detection speed of the stability parameter detected by the oscilloscope detection operation, and a detection accuracy of the stability parameter detected by the eye scan operation is lower than a detection accuracy of the stability parameter detected by the oscilloscope detection operation; Configuration parameters whose stability parameters are lower than a first stability threshold are eliminated from the multiple initial configuration parameters to obtain the multiple reference configuration parameters.

7. The method according to claim 1, characterized in that The step of selecting a target configuration parameter whose corresponding stability parameter satisfies a stability parameter condition from the plurality of reference configuration parameters includes one of the following: Determining, among the plurality of reference configuration parameters, the reference configuration parameters corresponding to the stability parameters greater than a second stability threshold as the target configuration parameters; The reference configuration parameter having the largest corresponding stability parameter among the plurality of reference configuration parameters is determined as the target configuration parameter.

8. The method according to claim 1, characterized in that The controlling the target storage component to execute the target test item under the target configuration parameters to obtain the target test result includes: Obtaining a maximum value of the transmission rate of the target storage component under the target configuration parameters to obtain a target transmission rate, wherein the transmission rate refers to a rate at which the target storage component transmits a data transmission signal to the control component; controlling the target storage component to operate at the target transmission rate under the target configuration parameters, and detecting an operating state of the target storage component during the operation of the target storage component; In a case where it is detected that the target storage component is in a normal operating state for a period greater than or equal to a preset period, determining that the target test result is used to indicate that the signal performance of the storage device meets a preset signal performance; In a case where it is detected that the target storage component is in a normal operating state for a period of time shorter than the preset period of time, the target test result is determined to indicate that the signal performance of the storage device does not meet the preset signal performance.

9. The method according to claim 1, characterized in that The controlling the target storage component to execute the target test item under the target configuration parameters to obtain the target test result includes: Obtaining a maximum value of the transmission rate of the target storage component under the target configuration parameters to obtain a target transmission rate, wherein the transmission rate refers to a rate at which the target storage component transmits a data transmission signal to the control component; controlling the target storage component to operate at a plurality of ambient temperatures according to the target configuration parameters and the target transmission rate, and detecting an operating state of the target storage component at each of the ambient temperatures; When it is detected that the target storage component is in a normal operating state for a period of time greater than or equal to a preset period of time under the multiple ambient temperatures, determining that the target test result indicates that the signal performance of the storage device meets the preset signal performance; When it is detected that under multiple ambient temperatures, the target storage component is in a normal operating state for a period of time that is less than the preset period of time, the target test result is determined to indicate that the signal performance of the storage device does not meet the preset signal performance.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the storage device testing method according to any one of claims 1 to 9 are implemented.

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