Signal tracing circuit diagram construction method for EDA software

Abstract

The invention discloses a signal tracing circuit diagram construction method for EDA software. The method comprises the following steps: step 1, obtaining a connection relation and a hierarchical relation of elements; step 2, determining a starting element according to a local circuit diagram to be drawn, drawing each stage of parent element according to the hierarchical relationship of the starting element, and enabling the peripheral edge of each stage of parent element to surround the starting element in a visual effect; 3, selecting a signal pin to be traced from the drawn elements, taking the selected element as a source element, taking the element to be connected as a target element, and placing the target element on the corresponding side of the source element; step 4, judging whether other elements located on the same side are overlapped with the target element and the connecting pins are located above or below, and moving the target element towards the opposite direction until the elements are not overlapped; and 5, wiring and returning to the step 3 until all elements in the local circuit diagram are completely wired. According to the method, more efficient and more intuitive construction of the multi-level circuit diagram can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic automation design, and in particular to a circuit diagram construction method for EDA software. Background Art

[0002] The circuit diagram display function plays a crucial role in EDA software design. EDA software is commonly used to design, simulate, and verify large integrated circuit designs, and the circuit diagram display function is one of the primary interfaces for users to interact with circuit design code. As a core component of EDA tools, the circuit diagram is an important medium for designers to understand circuit structure, analyze logical relationships, and debug problems.

[0003] With the significant increase in the scale and complexity of circuit design and the rapid development of EDA technology, the traditional method of constructing circuit diagrams in EDA software has been unable to meet the needs of efficient design and debugging. Moreover, as the scale of circuits expands, the computing resource consumption and time cost of generating and rendering full circuit diagrams increase significantly. In particular, in scenarios with frequent design iterations, the traditional method is less efficient. Therefore, the circuit diagram construction method based on signal tracing has become the key to improving design efficiency. By constructing the local circuits that circuit designers are concerned about through signal tracing, the signal path is intuitively displayed, and the designer is helped to quickly understand the circuit structure. Compared with constructing full circuit diagrams, the computing resource consumption and time cost are reduced. At present, the common method for constructing circuit diagrams is [1]: through the directed acyclic graph generation algorithm and the preset layout rules, the position allocation of the logic circuit is realized, and finally the preset routing rules are followed to automatically route the circuit in the channel manner. In addition, there is [2] to optimize the component layout through topological algorithms and bidirectional bubble sorting, improve the component position relationship by using average value calculation and bubble value adjustment, and achieve efficient routing by sharing the vertical axis space through stretching blank space and greedy algorithm.

[0004] However, the above circuit diagram construction methods are all based on components at the same level, and require the pre-construction of the data structure of all component information within the level. It can be seen that the above methods are more suitable for full circuit diagrams, so there are certain limitations. When there are multiple levels in the circuit design, it is necessary to build a circuit diagram for each level. When the user performs signal tracing, he needs to jump to the corresponding level layer first, and then view the signal flow. This makes it impossible to intuitively see the overall signal flow path. Therefore, the above methods are not suitable for constructing local circuit diagrams based on signal tracing. Summary of the Invention

[0005] In order to solve the problem that the existing technology cannot meet the needs of constructing a local circuit diagram based on signal tracing, the present invention proposes a signal tracing circuit diagram construction method for EDA software.

[0006] The signal tracing circuit diagram construction method for EDA software of the present invention comprises:

[0007] Step 1: Read the design file of the circuit to be analyzed and obtain the connection relationship and hierarchical relationship of all components;

[0008] Step 2: Create the starting component. Based on the desired partial circuit diagram, determine the starting component for the partial circuit diagram. Following the starting component's hierarchy, create child components of the previously created component, starting from top to bottom. Then, adjust the sizes of the corresponding parent components, starting from bottom to top, so that the edges of any child component are visually enclosed by its parent component, wrapping the starting component layer by layer. In particular, module components have internal and external pins to facilitate signal tracing both inward and outward.

[0009] Step 3: Select the signal pin to be traced from the drawn components. Based on the connection relationship of the components, the selected component is used as the source component, and the component to which the signal pin to be traced is connected is used as the target component. First, determine whether the signal is fan-in or fan-out, and then place the target component on the corresponding left or right side of the source component.

[0010] Step 4: Layout the target component. Determine whether other components in the same column as the target component overlap with the target component and whether their connection pins are above or below the target component. Then move the target component in the opposite direction until the components no longer overlap.

[0011] Step 5: Perform wiring to connect the source component and the target component, and return to step 3 until all components of the partial circuit diagram you want to draw are wired.

[0012] When the position of a component at the top level moves up or down, causing it to exceed the four edges of any component at the bottom level, the components at the level below the moved component begin to expand in area until the four edges of any component at the bottom level visually enclose the components at its top level.

[0013] Furthermore, the hierarchical relationship of the starting element is obtained by analyzing the complete path of the starting element.

[0014] Furthermore, when the signal is a fan-in signal, the target component is placed on the left side of the source component; when the signal is a fan-out signal, the target component is placed on the right side of the source component.

[0015] Furthermore, when the signal is a fan-in signal, the target component is placed to the right of the source component; when the signal is a fan-out signal, the target component is placed to the left of the source component.

[0016] Furthermore, when each component is created and adjusted, the coordinate information of the component is recorded or updated, and the size and position of the component are adjusted according to the coordinate information of the component.

[0017] Furthermore, the coordinate information of the component includes the horizontal coordinate and the vertical coordinate of the upper left corner of the component, the length of the component, the width of the component, and the height of the top of the component from each pin.

[0018] Furthermore, the components include module components and basic logic components.

[0019] Furthermore, step 4 includes:

[0020] Based on the generated position of the target component, the position of the target component is adjusted so that the pins connecting the target component and the source component are at the same height, and the target component is at an initial position;

[0021] Determine whether other components connected to the source component and located in the same column as the target component overlap with the target component's original initial position; if so, determine whether the connection pins of the other components to the source component are located above or below the connection pins of the target component to the source component;

[0022] If the connection pins of other components and the source component are located above, move the target component downward; if the connection pins of other components and the source component are located below, move the target component upward;

[0023] Determine whether other components that are not connected to the source component and are in the same column as the target component overlap with the target component's original initial position. If so, determine whether the source component of the other component is above or below the source component of the target component.

[0024] If the source component of the other component is located above, the other component is moved upward; if the source component of the other component is located below, the other component is moved downward.

[0025] The present invention effectively solves the problem that the layout and routing algorithm of the existing technology cannot achieve cross-level tracing when constructing a local circuit diagram based on signal tracing, and its data structure is limited to only applicable to the full circuit diagram. The present invention supports cross-level signal tracing, realizes multi-level layout and routing, supports the display of multi-level modules in the same view, and clearly observes the signal tracing path, thereby improving the efficiency of the circuit design process. Compared with the existing technology, the present invention has the following specific advantages:

[0026] The present invention has the advantage of high efficiency. When faced with complex multi-level circuits, traditional circuit diagram construction methods take a long time to construct, and designers need to manually search layer by layer, which is not only time-consuming and labor-intensive, but also prone to errors. The circuit construction method of the present invention uses cross-level signal tracing and real-time layout technology to achieve rapid construction and display of local circuit diagrams, and the construction efficiency is more efficient. At the same time, designers can intuitively see the flow of signals and the connection relationship between components, so as to quickly locate problems and make modifications. This high efficiency not only improves the work efficiency of designers, but also reduces design costs, making circuit design faster, more accurate and reliable.

[0027] The present invention offers the advantage of flexibility. Circuit designers can flexibly select the signals and components to be traced based on actual needs, quickly constructing a local circuit diagram that meets the requirements. Furthermore, the present invention supports the display of multiple levels of modules and components in the same view, allowing designers to more intuitively observe the flow of signals and the connection relationships between components, thereby more flexibly adjusting and optimizing circuit designs. This flexibility not only increases design freedom but also provides designers with more creative space, making circuit designs more diverse, personalized, and innovative.

[0028] The present invention has the advantage of intuitiveness, which is mainly reflected in the visualization effect of its cross-level signal tracing and real-time layout technology. Through cross-level signal tracing, designers can clearly observe the flow path of signals in multi-level circuits without having to manually search and connect signals layer by layer, thereby greatly improving the intuitiveness of circuit design. At the same time, real-time layout technology enables components to calculate position coordinates based on their relationship with signals when they are created, thereby achieving a reasonable layout of components. This layout method not only makes the circuit diagram more neat and beautiful, but also allows designers to more intuitively observe the connection relationship between components and the flow of signals, making it easier to understand and analyze circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The present invention is described in detail below with reference to the embodiments and accompanying drawings, in which:

[0030] Figure 1 This is a main flow chart of an embodiment of the present invention.

[0031] Figure 2 FIG. 1 is a flowchart of creating hierarchical components according to an embodiment of the present invention.

[0032] Figure 3 This is a flowchart of wiring components with signal connection relationships according to an embodiment of the present invention.

[0033] Figure 4 This is a schematic diagram of a circuit with a hierarchical relationship according to an embodiment of the present invention.

[0034] Figure 5 FIG. 4 is a schematic diagram of moving a target component to an initial position according to an embodiment of the present invention.

[0035] Figure 6 FIG. 1 is a process diagram of moving a target component according to an embodiment of the present invention.

[0036] Figure 7 FIG. 2 is a process diagram of moving a target component according to another embodiment of the present invention.

[0037] Figure 8 This is a schematic diagram of wiring size adjustment according to an embodiment of the present invention. DETAILED DESCRIPTION

[0038] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0039] Thus, a feature indicated in this specification is intended to illustrate one of the features of one embodiment of the present invention, rather than to imply that every embodiment of the present invention must have the described feature. In addition, it should be noted that this specification describes many features. Although certain features can be combined together to illustrate possible system designs, these features can also be used in other, not explicitly described, combinations. Thus, unless otherwise noted, the described combinations are not intended to be limiting.

[0040] The circuit diagram construction method for EDA software of the present invention comprises the following steps.

[0041] Step 1: Read the design file of the circuit to be analyzed and obtain the connection relationship and hierarchical relationship of all components. In the prior art, there are various tools that can obtain the connection relationship and hierarchical relationship of components through the circuit design file, which are all relatively mature prior art.

[0042] Step 2: Create the starting component. Based on the desired partial circuit diagram, determine the starting component for the partial circuit diagram. Create the child components of the previously created component from top to bottom, and then adjust the size of the corresponding parent components from bottom to top, so that the edges of any child component are visually enclosed by its parent component, and there is a certain distance between the edges of the parent component and the edges of its child components. Wrap the starting component layer by layer. In particular, module components have internal and external pins to facilitate signal tracing inward and outward.

[0043] Step 3: Select the signal pin to be traced from the drawn components. Based on the connection relationship of the components, the selected component is used as the source component, and the component to which the signal pin to be traced is connected is used as the target component. First, determine whether the signal is fan-in or fan-out, and then place the target component on the corresponding left or right side of the source component.

[0044] Step 4: Layout the target component. Determine whether other components in the same column as the target component overlap with the target component and whether their connection pins are above or below the target component. Then move the target component in the opposite direction until the components no longer overlap.

[0045] Step 5: Perform wiring to connect the source component and the target component, and return to step 3 until all components of the partial circuit diagram you want to draw are wired.

[0046] When a component at the bottom level (a child component relative to another component) moves up or down, causing it to exceed the four edges of any top-level component (a parent component relative to another component), the components at the level above the moved component begin to expand until the four edges of any component at the top level visually enclose the components at its bottom level.

[0047] The circuit diagram construction method based on signal tracing in this invention is key to improving design efficiency. By using signal tracing to construct the local circuits of interest to circuit designers, it intuitively displays the signal paths and helps designers quickly understand the circuit structure. Compared to building a full circuit diagram, this method reduces computing resource consumption and time costs.

[0048] The present invention pays special attention to the creation of components and the layout of components. In order to achieve cross-level signal tracing, nested creation is used in the creation of components. For example, if the traced component exists inside a module, it is necessary to create the instance component corresponding to the module during creation, and then create the target component within this module component. Similarly, when the target component exists in a multi-layer module, the corresponding components will be created layer by layer until the target component is created. In response to the layout problem of components, the present invention adopts a real-time layout method, but when the component is created, the position coordinates are calculated based on its relationship with the signal whether it is fan-out or fan-in. Through this method, the present invention aims to enable cross-level components to be displayed in the same view at the same time, and to reasonably layout components, thereby improving the simplicity and intuitiveness of operations during signal tracing, and greatly improving the efficiency of the design team in viewing and analyzing problems in local circuits.

[0049] In the process of drawing a circuit diagram, the present invention adjusts the sizes of components in nested levels in real time, so that the positions and layouts of components at different levels are very intuitive.

[0050] In one embodiment, a starting element is confirmed in step 1, and elements are created layer by layer in step 2 until the starting element is created.

[0051] Regarding the positional relationship between the source and target components, in a first embodiment, when the signal is a fan-in signal, a set of predecessor components located at the source component is obtained; when the signal is a fan-out signal, a set of successor components located at the source component is obtained. In a second embodiment, when the signal is a fan-in signal, a set of successor components located at the source component is obtained; when the signal is a fan-out signal, a set of predecessor components located at the source component is obtained.

[0052] In a specific embodiment, the above step 4 includes the following steps.

[0053] Based on the generated position of the target component, the position of the target component is adjusted so that the pins connecting the target component and the source component are at the same height. At this time, the target component is in the initial position;

[0054] Determine whether other components connected to the source component and located in the same column as the target component overlap with the target component's original initial position. If so, determine whether the connection pins of the other components to the source component are located above or below the connection pins of the target component to the source component.

[0055] If the connection pins of other components and the source component are located above, move the target component downward; if the connection pins of other components and the source component are located below, move the target component upward;

[0056] Determine whether other components that are not connected to the source component and are in the same column as the target component overlap with the target component's original initial position. If so, determine whether the source component of the other component is above or below the source component of the target component.

[0057] If the source component of the other component is located above, the other component is moved upward; if the source component of the other component is located below, the other component is moved downward.

[0058] The concept of the present invention is described in detail below with reference to the drawings.

[0059] like Figure 1 As shown, the general process of the present invention is as follows.

[0060] First create the starting component;

[0061] Then select a signal pin of the starting component and trace its signal;

[0062] Create the component corresponding to the traceability signal, that is, create the target component;

[0063] The created target components are laid out according to preset rules, and then wiring is performed to connect the source components and the target components.

[0064] Figure 2 A flowchart showing how to create hierarchical components. The components of the present invention include module components and basic logic components. Module components can easily be nested. For example, a bottom-level module component can contain multiple top-level module components. Basic logic components include all basic circuit components such as logical AND, logical OR, inverters, and data selectors.

[0065] First get the full path of the component;

[0066] Segment the component path to obtain the hierarchical relationship of the components;

[0067] Create components layer by layer from top to bottom. Then, starting from the starting component and working toward the top, adjust the size and position of each component layer by layer so that the edges of the components at the bottom level visually surround the components at the top level.

[0068] For example, Figure 4 The complete path of the starting component inst_C is inst_A / inst_B / inst_C, so the complete path can be split according to the symbol " / ", and then inst_A, inst_B, and inst_C are created in sequence, and the sizes of inst_B and inst_A are adjusted in sequence.

[0069] If it is a module-type component, in addition to the external pins, internal pins are also added to support signal tracing inward and outward, such as Figure 4 The effect diagram of building multi-level components is shown in the provided figure.

[0070] Figure 3 A flowchart showing the arrangement and wiring between components.

[0071] Select a signal on a component. The component with the selected signal is called the source component. Signal tracing is triggered. The traced component is obtained through the connection relationship. The traced component is called the target component. The target component is created based on the component information.

[0072] Place the target component in the left or right column of the source component, depending on whether the traceable signal is fan-out or fan-in. Regardless of the column you choose, fan-out should correspond to one direction and fan-in should correspond to the opposite direction.

[0073] Set the initial position of the target component based on the pins of the source component connected to the target component.

[0074] In a specific embodiment, if it is a fan-in signal, a set of predecessor components located in the left column of the source component is obtained. If it is a fan-out signal, a set of successor components located in the right column of the source component is obtained.

[0075] Checks whether there are any components in the corresponding component set whose connection pins are located above and overlap the target component. If so, handles the component based on whether the pins connecting to the source component are located above or below the pins connecting to the source component.

[0076] If the connection pins of the component are above the connection pins of the target component, and the connection pins of the successor component of the component are below the target component, then the target component is inserted below the component and the successor component of the component is translated. Then, other components that are already in the column where the target component is located are obtained, excluding those that are related to the source component, and the successor components located below the target component are translated.

[0077] If the connection pin of the component is below the connection pin of the target component, the target component is set above the component, and the component set in the column and above the component is obtained and translated upward.

[0078] Figure 5 、 Figure 6 The state change diagram of the target component movement is shown when the connecting pin of the component is below the connecting pin of the target component and overlaps with the target component.

[0079] Figure 5 、 6 In the figure, inst_E is the source component, inst_3 is the target component, and the target component that has been moved is displayed, not the position of the target component when it was first generated. Figure 5 The position of inst_3 shown is the ideal position of inst_3 when pin o1 of the source component inst_E is to be connected and aligned with pin i3 of the target component inst_3, and is also referred to as the initial position of inst_3 in the present invention.

[0080] Based on the y coordinate of the connection pin o1 of the source component inst_E and the relative y coordinate of the connection pin i3 of the target component, the y coordinate of the target component's position is calculated as y-dy. Then, because the signal is a fan-out signal, a fixed spacing dx is set based on the x coordinate of the connection pin of the source component to obtain the x+dx coordinate of the target component's position. The coordinates of the target component's initial position are P3(x+dx,y-dy). If it is a fan-in signal, the x coordinate of the target component is xw-dx, where w is the width of the target component.

[0081] After moving the target component to the initial position, the subsequent component set of the source component is obtained, and the components in the same column as the target component are traversed and compared with the target component. According to the upper and lower boundary ranges R[y,y+h] of the component, where y represents the vertical coordinate of the component position and h represents the height of the component, it is determined whether there is an intersection and an overlapping component with the target component.

[0082] Figure 5 、 Figure 6 In the example, after moving the target element inst_3 downward, we compare the upper and lower boundary ranges of the elements in the same column again and find the elements of the successor element set below, that is, Figure 6 The inst_2 element has overlap, and the position of inst_2 is (x t ,y2). At this time, the component is translated downward by the distance y1+h1+h3-y2, where h3 is the height of the target component inst_3.

[0083] In the figure, the target component inst_3 overlaps with the component inst_1, and the component inst_1 is located above the target component inst_3. Therefore, the target component inst_3 is moved downward first, and then the component inst_2 located below in the column is also moved downward.

[0084] Traverse the components in the same column as the target component and obtain the components that are located below the target component and are not connected to the source component, such as Figure 6 If the inst_0 component in the image overlaps with the target component inst_2, it is also translated downward by the distance y1+h1+h3-y2 to obtain Figure 6 The final circuit diagram on the right.

[0085] Figure 7 In the example, after moving the target component to the initial position, the subsequent component set of the source component is obtained, and the components in the same column as the target component are traversed and compared with the target component. According to the upper and lower boundary ranges of the component, the vertical coordinate of the component position is represented, which represents the component height. It is judged whether the component overlaps with the target component. Figure 7 The target component inst_3 overlaps with the component inst_2 in the same column. Since the pin of the target component inst_3 is above the component inst_2, the target component moves up, and the position of the target component inst_2 (x t ,y2). Move the target component position to the top of inst_2 and set the position to (x t ,y2-h3), set the target component inst_3 above this component inst_2.

[0086] Traverse the components in the same column as the target component inst_3 and obtain the components that are above the target component and are not connected to the source component, such as Figure 7 If there is an overlap between the target element inst_3 and the element inst_1 in the first layer, the element inst_1 is translated upward by a distance of y1+h1+h3-y2.

[0087] Due to the existence of multiple levels of elements, when the elements are created and laid out and routed inside, the space needs to be increased, and the size of the element in the previous layer needs to be changed to adapt to the increase in internal space. For the element in the previous layer, since the size of the element changes, the column where the element is located needs to be adjusted. A simple way is to translate the elements below the current column of the element downward, and then perform layout and routing. If there are multiple levels, adjust the layout from the bottom to the top layer by layer. For example, as shown in the effect diagram of the circuit constructed according to signal tracing provided by the present application, the signal c2 in inst_C is traced, the element inst_G is created, the sizes of inst_B and inst_A are changed, and the position of inst_F is affected. After the layout of these elements is completed from the bottom to the top, the routing is performed from the top layer to the bottom layer. Figure 8

[0088] The circuit diagram construction method based on signal tracing provided by the present application acquires element information and creates an element data structure by tracing the signal, and then realizes the construction of the circuit diagram according to a preset layout and routing algorithm. In order to facilitate the cross-level signal tracing, the present application supports displaying multiple levels of modules on the same view, so that the tracing path of the signal can be seen intuitively and clearly.

[0089] The above only describes the preferred embodiments of the present application and is not used to limit the present application. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.​

Claims

1. A method for constructing a signal tracing circuit diagram for EDA software, characterized in that: include: Step 1: Read the design file of the circuit to be analyzed and obtain the connection relationship and hierarchical relationship of all components; Step 2: Determine the starting element of the partial circuit diagram you want to draw. Create child elements of the previously created element in order from top to bottom according to the hierarchical relationship of the starting element until the starting element is created. Adjust the sizes of the corresponding parent elements in order from bottom to top so that the four edges of any child element are visually enclosed by its parent element, and there is a certain distance between the four edges of the parent element and the four edges of its child elements. Step 3: Select the signal pin to be traced from the drawn components. Based on the connection relationship of the components, the selected component is used as the source component, and the component to which the signal pin to be traced is connected is used as the target component. First, determine whether the signal is fan-in or fan-out, and place the target component on the corresponding left or right side of the source component. Step 4: Determine whether other components on the same side of the source component as the target component overlap with the target component and whether the connection pins are located above or below the target component. Then, move the target component in the opposite direction until the components do not overlap. Step 5: Perform wiring to connect the source component and the target component, and return to step 3 until all components of the partial circuit diagram you want to draw are wired.

2. The signal tracing circuit diagram construction method for EDA software according to claim 1, characterized in that: The hierarchical relationship of the starting element is obtained by analyzing the complete path of the starting element.

3. The signal tracing circuit diagram construction method for EDA software according to claim 1, characterized in that: When the signal is a fan-in signal, place the destination component to the left of the source component; when the signal is a fan-out signal, place the destination component to the right of the source component.

4. The signal tracing circuit diagram construction method for EDA software according to claim 1, characterized in that: When the signal is a fan-in signal, place the destination component to the right of the source component; when the signal is a fan-out signal, place the destination component to the left of the source component.

5. The signal tracing circuit diagram construction method for EDA software according to claim 1, characterized in that: When each component is created and adjusted, the coordinate information of the component is recorded or updated, and the size and position of the component are adjusted according to the coordinate information of the component.

6. The signal tracing circuit diagram construction method for EDA software according to claim 5, characterized in that: The coordinate information of the component includes the horizontal coordinate and the vertical coordinate of the upper left corner of the component, the length of the component, the width of the component, and the height between the top of the component and each pin.

7. The signal tracing circuit diagram construction method for EDA software according to claim 1, characterized in that: The elements include module elements and basic logic elements.

8. The signal tracing circuit diagram construction method for EDA software according to claim 7, characterized in that: The module element has inner pins and outer pins.

9. The signal tracing circuit diagram construction method for EDA software according to claim 1, characterized in that: The step 4 comprises: Based on the generated position of the target component, the position of the target component is adjusted so that the pins connecting the target component and the source component are at the same height, and the target component is at an initial position; Determine whether other components connected to the source component and located in the same column as the target component overlap with the target component's original initial position; if so, determine whether the connection pins of the other components to the source component are located above or below the connection pins of the target component to the source component; If the connection pins of other components and the source component are located above, move the target component downward; if the connection pins of other components and the source component are located below, move the target component upward; Determine whether other components that are not connected to the source component and are in the same column as the target component overlap with the target component's original initial position. If so, determine whether the source component of the other component is above or below the source component of the target component. If the source component of the other component is located above, the other component is moved upward; if the source component of the other component is located below, the other component is moved downward.

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