Digital-to-analog converter circuit, chip, and electronic device

Abstract

The invention relates to the field of integrated circuits, in particular to a digital-to-analog converter circuit, a chip and electronic equipment. The digital-to-analog converter circuit comprises a modulator used for modulating an input first digital signal into a second digital signal; the corrector is connected with the modulator and used for correcting the second digital signal according to the correction factor to obtain a third digital signal; the quantizer is connected with the corrector and used for quantizing the third digital signal to obtain a fourth digital signal, and the bit width of the third digital signal is larger than that of the fourth digital signal; the pulse width modulation circuit is connected with the quantizer and used for converting the fourth digital signal into a PWM signal based on a PWM carrier wave, and the PWM carrier wave is a carrier wave with the frequency changing along with time; wherein the correction factor is used for compensating the change of the duty ratio of the PWM signal caused by the frequency change of the PWM carrier. Based on the digital-to-analog converter circuit, the problem of playing audio distortion caused by frequency change of PWM carrier waves can be avoided.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a digital-to-analog converter circuit, chip, and electronic device. Background Art

[0002] The digital-to-analog converter circuit in the digital audio amplifier may include a pulse width modulation (PWM) circuit to convert a digital signal into an analog signal based on PWM to drive a speaker to produce sound.

[0003] However, DAC circuits that use pulse-width modulation (PWM) tend to generate significant electromagnetic radiation at the PWM carrier frequency. Therefore, DAC circuits can further dynamically change the PWM carrier frequency through spread-spectrum modulation (SSM), dispersing the radiated energy generated by PWM over a wider frequency band, thereby reducing the radiation intensity at a single frequency point.

[0004] However, using spread spectrum modulation to change the PWM carrier frequency can cause audio distortion in the digital audio amplifier's output. Specifically, because the duty cycle of the PWM signal generated by the digital-to-analog converter circuit is related to the PWM carrier frequency, changes in the PWM carrier frequency can cause the duty cycle of the PWM signal generated by the digital-to-analog converter circuit to change, leading to audio distortion in the digital audio amplifier's output. Summary of the Invention

[0005] The present application provides a digital-to-analog converter circuit, chip, and electronic device that can compensate for changes in the duty cycle of a PWM signal caused by changes in the PWM carrier frequency, thereby avoiding distortion of the audio output by a digital audio amplifier.

[0006] In a first aspect, the present application provides a digital-to-analog converter circuit, which includes: a modulator for modulating an input first digital signal into a second digital signal; a corrector connected to the modulator, for correcting the second digital signal according to a correction factor to obtain a third digital signal; a quantizer connected to the corrector, for quantizing the third digital signal to obtain a fourth digital signal, wherein the bit width of the third digital signal is greater than the bit width of the fourth digital signal; a pulse width modulation circuit connected to the quantizer, for converting the fourth digital signal into a PWM signal based on a PWM carrier, the PWM carrier being a carrier whose frequency changes with time; wherein the correction factor is used to compensate for changes in the duty cycle of the PWM signal caused by changes in the frequency of the PWM carrier.

[0007] Here, by correcting the second digital signal using the correction factor, changes in the duty cycle of the PWM signal caused by changes in the PWM carrier frequency can be compensated. Therefore, even if the PWM carrier frequency changes, the duty cycle of the PWM signal remains unchanged, thereby avoiding the problem of audio distortion caused by changes in the PWM carrier frequency.

[0008] Furthermore, the DAC circuit first corrects the high-bitwidth second digital signal based on the correction factor to obtain a high-bitwidth third digital signal, and then quantizes the high-bitwidth third digital signal into a low-bitwidth fourth digital signal. It can be understood that the high bitwidth of the second digital signal corresponds to high computational accuracy. Therefore, performing the correction process based on the second digital signal can effectively improve the accuracy of the correction factor, further avoiding audio distortion caused by frequency variations in the PWM carrier.

[0009] In a possible implementation of the first aspect above, the digital-to-analog converter circuit further includes: a divider, wherein a first input end of the divider is connected to an output end of the quantizer, a second input end of the divider is used to receive a correction factor, and the divider is used to output a feedback signal based on the fourth digital signal and the correction factor; an adder, wherein a first input end of the adder is used to receive an input signal of the digital-to-analog conversion circuit, a second input end of the adder is connected to an output end of the divider, and an output end of the adder is connected to a modulator, and the adder is used to add the first input signal and the feedback signal to output a first digital signal to the modulator.

[0010] In a possible implementation of the first aspect, the modulator, the corrector, the quantizer, the divider, and the adder are integrated into the same modulation filter.

[0011] The modulation filter can be a ΔΣ modulation filter. Accordingly, the digital-to-analog converter circuit can implement ΔΣ modulation of the input signal based on a modulator, a corrector, a quantizer, a divider, and an adder. Correction within the ΔΣ modulation filter can shift noise caused by computational errors that may arise from the correction outside the audio band, thereby maintaining the signal-to-noise ratio within the audio band and further ensuring distortion-free playback of the audio.

[0012] In a second aspect, the present application provides another digital-to-analog converter circuit, which includes: a corrector, connected to the input end of the digital-to-analog conversion circuit, for correcting the input signal of the digital-to-analog conversion circuit according to a correction factor to obtain a fifth digital signal; a modulator, for modulating the fifth digital signal to generate a sixth digital signal; a quantizer, connected to the modulator, for quantizing the sixth digital signal to obtain a fourth digital signal, wherein the bit width of the sixth digital signal is greater than the bit width of the fourth digital signal; a pulse width modulation circuit, connected to the quantizer, for converting the fourth digital signal into a PWM signal based on a PWM carrier, the PWM carrier being a carrier whose frequency changes with time; wherein the correction factor is used to compensate for the change in the duty cycle of the PWM signal caused by the frequency change of the PWM carrier.

[0013] This digital-to-analog converter circuit has the same technical effects as the digital-to-analog converter circuit provided in the first aspect. For details, please refer to the detailed description above and will not be repeated here.

[0014] In a possible implementation of the second aspect above, the digital-to-analog converter circuit further includes: an adder, a first input end of the adder being connected to the output end of the corrector, a second input end of the adder being connected to the output end of the quantizer, and an output end of the adder being connected to the modulator, the adder being configured to add the fifth digital signal to the fourth digital signal to output the added signal to the modulator; and the modulator being configured to modulate the added signal to generate a sixth digital signal.

[0015] In a possible implementation of the second aspect, the modulator, the quantizer, and the adder are integrated into the same modulation filter, and the corrector is located outside the modulation filter.

[0016] In a possible implementation of the first aspect or the second aspect, the corrector is a multiplier.

[0017] In a possible implementation of the first aspect or the second aspect, the correction factor K is calculated as follows:

[0018]

[0019] Wherein, Vmax is the maximum value of the PWM carrier, and Vcenter is the center value of the PWM carrier.

[0020] In a possible implementation of the first or second aspect, the maximum value of the PWM carrier wave changes periodically with a first duration as a period, so that the frequency of the PWM carrier wave changes periodically with the first duration as a period.

[0021] In a possible implementation of the first or second aspect above, the pulse width modulation circuit includes: a first memory, an input end of the first memory is connected to the quantizer, and is used to store the fourth digital signal, wherein the depth of the first memory is greater than or equal to a first threshold, and the first threshold is the number of fourth digital signals output by the quantizer within the first time length; and a PWM modulator, a first input end of the PWM modulator is connected to the output end of the first memory, and is used to generate a PWM signal based on a PWM carrier and the fourth digital signal stored in the first memory.

[0022] In a possible implementation of the first or second aspect above, the pulse width modulation circuit further includes: a second memory for storing a maximum carrier value of the PWM carrier, an output end of the second memory being connected to a second input end of the PWM modulator so that the PWM modulator generates a PWM carrier based on the maximum carrier value stored in the second memory, the maximum carrier value being used to determine a frequency of the PWM carrier, wherein the center frequency of the PWM carrier is equal to the sampling frequency of the fourth digital signal.

[0023] Here, the second memory and the first memory can be the same memory, for example, they can be FIFO memories of the same depth. The fourth digital signal input to the first memory and the maximum PWM carrier value input to the second memory are synchronously passed through the first memory and the second memory, thereby ensuring that the signal-to-noise ratio of the output PWM signal is not degraded due to data loss.

[0024] After starting operation, the digital-to-analog converter circuit may pre-store a plurality of fourth digital signals in the first memory (for example, the number of pre-stored fourth digital signals may be greater than or equal to a first threshold). After the pre-storage is completed, the PWM modulator retrieves the fourth digital signal from the first memory to generate a PWM signal. Based on this approach, even if the PWM carrier frequency changes, for example, the PWM carrier frequency is greater than the sampling frequency of the fourth digital signal at certain moments, the PWM modulator can successfully retrieve the fourth digital signal from the first memory, thereby avoiding the phenomenon of sound dropout in the digital audio power amplifier due to the inconsistency between the sampling frequency of the input signal and the frequency of the output PWM signal.

[0025] In a possible implementation of the first or second aspect above, the digital-to-analog converter further includes: a frequency generator, a first output end of the frequency generator is connected to an input end of the second memory, the frequency generator is used to generate a carrier maximum value of the PWM carrier based on the carrier center value, spread spectrum step size and spread spectrum range of the PWM carrier, and output the carrier maximum value to the second memory; a correction factor generator, an input end of the correction factor generator is connected to the second output end of the frequency generator, an output end of the correction factor generator is connected to the corrector, the correction factor generator is used to generate a correction factor based on the carrier center value and the carrier maximum value, and output the correction factor to the corrector.

[0026] In a third aspect, the present application provides a chip comprising the digital-to-analog converter circuit provided by the first aspect and its various possible implementations, or the second aspect and its various possible implementations.

[0027] In a fourth aspect, the present application provides an electronic device, which includes a chip provided by the third aspect and various possible implementations thereof.

[0028] The beneficial effects of the third to fourth aspects mentioned above can be found in the relevant descriptions of the first aspect and its various possible implementations, or the second aspect and its various possible implementations, and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Shown is a circuit structure diagram of a digital-to-analog converter circuit 10' in some technical solutions;

[0030] Figure 2a FIG. 1 is a schematic diagram of the circuit structure of a first digital-to-analog converter circuit 10 provided in an embodiment of the present application;

[0031] Figure 2b FIG. 1 is a schematic diagram of a circuit structure of a first digital-to-analog converter circuit 10 provided in another embodiment of the present application;

[0032] Figure 3 FIG. 1 is a schematic diagram of a circuit structure of a first digital-to-analog converter circuit 10 provided in another embodiment of the present application;

[0033] Figure 4 FIG2 is a schematic diagram of generating a PWM carrier based on the first memory 106 according to an embodiment of the present application;

[0034] Figure 5 FIG2 is a schematic diagram of a PWM carrier with a triangular wave waveform provided in an embodiment of the present application;

[0035] Figure 6 FIG. 2 is a schematic diagram of the circuit structure of the second digital-to-analog converter circuit 20 provided in an embodiment of the present application;

[0036] Figure 7 FIG. 1 is a schematic diagram of the circuit structure of a second digital-to-analog converter circuit 20 provided in another embodiment of the present application. DETAILED DESCRIPTION

[0037] Illustrative embodiments of the present application include, but are not limited to, a digital-to-analog converter circuit, chip, and electronic device.

[0038] The following is an introduction to some terms of this application.

[0039] (1) Pulse width modulation (PWM): In a digital-to-analog converter circuit, pulse width modulation can adjust the pulse width by comparing the amplitude of the input digital signal with the PWM carrier to output a PWM signal with a duty cycle. Furthermore, the digital-to-analog converter circuit can output an analog signal based on the PWM signal to drive the speaker to produce sound. Specifically, according to different ways of generating the PWM carrier, pulse width modulation can be divided into digitally controlled pulse width modulation (hereinafter referred to as "digital PWM") and analog-controlled pulse width modulation. The pulse width modulation used in the digital-to-analog converter circuit provided in this application is digital PWM, and the types of pulse width modulation will not be repeated below.

[0040] (2) Counter: Digital PWM can generate a PWM carrier based on a counter. The core parameters of the counter include the counter step number and the counter clock frequency. The counter step number refers to the number of states the counter goes through in one complete counting cycle when generating the PWM carrier. The counter clock frequency refers to the reference clock frequency that drives the counter. In digital PWM, the PWM carrier frequency is determined by the counter step number and the counter clock frequency. Specifically, PWM carrier frequency = counter clock frequency / counter step number.

[0041] (3) Spread-spectrum modulation (SSM): This technique spreads the signal's spectral energy over a wider frequency band than the original signal, thereby achieving advantages such as interference immunity, low probability of intercept, and optimized electromagnetic compatibility. In digital-to-analog converter circuits using digital PWM, spread-spectrum modulation can reduce electromagnetic interference (EMI) by dynamically changing the PWM carrier frequency. Specifically, spread-spectrum modulation can change the PWM carrier frequency by changing the number of counter steps.

[0042] (4) Duty cycle (DC): This is a key parameter that describes the proportion of time a high level is occupied in a periodic pulse signal. In a digital-to-analog converter circuit using digital PWM, the duty cycle of the PWM signal determines the strength of the converted analog signal. The duty cycle of a PWM signal can be calculated using the following formula: Duty cycle DC = digital signal X / counter step number NS0. Here, digital signal X is the digitized mapping value of the digital signal.

[0043] Using spread spectrum modulation to change the PWM carrier frequency may cause output audio distortion. The following details the causes of audio distortion.

[0044] Based on the above, it can be seen that in a digital-to-analog converter circuit using digital PWM, the PWM carrier frequency can be changed by adjusting the counter step number. Taking the counter clock frequency fc = 50 MHz, the counter step number NS0 = 1000 before spread spectrum modulation, and the counter step number NS1 = 2500 after spread spectrum modulation as an example, before spread spectrum modulation, the PWM carrier frequency f0 = fc / NS0 = 50 kHz; after spread spectrum modulation, the PWM carrier frequency f1 = fc / NS1 = 20 kHz.

[0045] In this scenario, for a digital signal X input to the DAC circuit, when the PWM carrier frequency is f0, the generated PWM signal's duty cycle DC0 is X / NS0; when the PWM carrier frequency is f1, the generated PWM signal's duty cycle DC1 is X / NS1. Clearly, for the same digital signal X, dynamic changes in the PWM carrier frequency will cause the generated PWM signal's duty cycle to change dynamically, leading to dynamic changes in the intensity of the converted analog signal. In this case, the audio output by the digital audio amplifier may be distorted.

[0046] To this end, in some technical solutions, a corrector is added to the digital-to-analog conversion circuit to improve audio distortion. Figure 1 The circuit structure diagram of the digital-to-analog converter circuit 10 ′ in some technical solutions is shown.

[0047] See also Figure 1 The digital-to-analog converter circuit 10' includes a modulator 100, a corrector 101, a quantizer 102, and a pulse width modulation circuit 103. The modulator 100 is configured to modulate the input digital signal S0 into a digital signal S1 through delta-sigma modulation (DSM). The quantizer 102 is connected to the modulator 100 and configured to quantize the high-bitwidth digital signal S1 into a low-bitwidth digital signal S2. The corrector 101 is connected to the quantizer 102 and configured to correct the digital signal S2 into a digital signal S3 based on a correction factor K. The pulse width modulation circuit 103 is connected to the corrector 101 and configured to convert the digital signal S3 into a PWM signal based on a generated PWM carrier, wherein the PWM carrier is a carrier obtained by spread spectrum modulation and whose frequency varies with time.

[0048] exist Figure 1 In the solution shown, by adding a corrector 101 to the digital-to-analog conversion circuit 10', the audio distortion caused by the change in PWM carrier frequency can be compensated to a certain extent. Figure 1 In the illustrated solution, the corrector 101 is located after the quantizer 102. Since the digital signal S2 output by the quantizer 102 is a quantized signal of the digital signal S1 and has a low bit width, the corrector 101 compensates for the audio distortion based on the low bit width digital signal S2, but the compensation effect is limited.

[0049] For example, take the low-bit-width digital signal S2=32, the bit width is 8 bits, the decimal precision is 7 bits, and the original number of steps of the counter N0=128 as an example. Figure 1 The compensation effect of the corrector 101 on the audio signal in the illustrated embodiment.

[0050] Duty cycle DC0' of the PWM signal before spread spectrum modulation:

[0051]

[0052] Taking the counter step number N1=114 after spread spectrum modulation as an example, the digital signal S2 is multiplied by the correction factor K based on the corrector 101, and the digital signal S3 obtained is:

[0053]

[0054] Here, since the accuracy of the signal input to the pulse width modulation circuit 103 (for example, the digital signal S3) is fixed to an integer, when the digital signal S3 obtained according to the correction factor K is not an integer, it is necessary to perform fixed-point rounding on the digital signal S3. After rounding to the fixed point, the digital signal S3 = 29.

[0055] At this time, the duty cycle DC1' calculated based on the corrected and fixed-point processed digital signal S3 is:

[0056]

[0057] Clearly, the duty cycle DC0' of the PWM signal before spread spectrum modulation is 25%, while the duty cycle DC1' of the PWM signal after spread spectrum modulation is approximately 25.44%. In other words, the DAC circuit 10' cannot maintain a consistent duty cycle before and after SSM in practical applications, and thus cannot avoid distortion issues caused by spread spectrum modulation.

[0058] To this end, the present application provides a digital-to-analog converter circuit, which includes: a modulator, used to modulate an input first digital signal into a second digital signal; a corrector, connected to the modulator, used to correct the second digital signal according to a correction factor to obtain a third digital signal; a quantizer, connected to the corrector, used to quantize the third digital signal to obtain a fourth digital signal, wherein the bit width of the third digital signal is greater than the bit width of the fourth digital signal; a pulse width modulation circuit, connected to the quantizer, used to convert the fourth digital signal into a PWM signal based on a PWM carrier, the PWM carrier being a carrier whose frequency changes with time; wherein the correction factor is used to compensate for the change in the duty cycle of the PWM signal caused by the frequency change of the PWM carrier.

[0059] That is, in this application, the second digital signal is corrected using a correction factor to compensate for changes in the duty cycle of the PWM signal caused by changes in the frequency of the PWM carrier. Therefore, even if the frequency of the PWM carrier changes, the duty cycle of the PWM signal remains unchanged. This avoids the problem of audio distortion caused by changes in the frequency of the PWM carrier.

[0060] Furthermore, in the digital-to-analog conversion circuit provided by the present application, the corrector is located before the quantizer. Specifically, the digital-to-analog converter circuit provided by the present application first corrects the second digital signal with a high bit width based on the correction factor to obtain a third digital signal with a high bit width, and then quantizes the third digital signal with a high bit width into a fourth digital signal with a low bit width. It can be understood that the high bit width of the second digital signal corresponds to high calculation accuracy of the second digital signal. Therefore, performing a correction process based on the second digital signal can effectively improve the correction accuracy of the correction factor, further avoiding the problem of audio playback distortion caused by frequency changes of the PWM carrier.

[0061] In addition, it should be made clear that the above-mentioned digital-to-analog converter circuit provided in this application can not only be used for digital audio amplifiers, but can also be used in systems using digital PWM. This application does not make any restrictive descriptions on the application scenarios of the above-mentioned digital-to-analog converter circuit.

[0062] The digital-to-analog converter circuit mentioned in this application is introduced in detail below.

[0063] For example, Figure 2a The circuit structure diagram of a first digital-to-analog converter circuit 10 provided in an embodiment of the present application is shown. Specifically, the first digital-to-analog converter circuit 10 includes a modulator 100, a corrector 101, a quantizer 102, and a pulse width modulation circuit 103. The modulator 100 is configured to modulate an input first digital signal into a second digital signal using delta-sigma modulation (DSM). The corrector 101 is connected to the modulator 100 and is configured to correct the second digital signal according to an input correction factor K to obtain a third digital signal. The correction factor K is configured to compensate for changes in the duty cycle of the PWM signal caused by changes in the frequency of the PWM carrier. The quantizer 102 is connected to the corrector 101 and is configured to quantize the third digital signal from a high bit width to a low bit width to obtain a fourth digital signal having a smaller bit width than the third digital signal. The pulse width modulation circuit 103 is connected to the quantizer 102 and is configured to convert the fourth digital signal into a PWM signal based on a generated PWM carrier, wherein the PWM carrier is a carrier obtained by spread spectrum modulation and has a frequency that varies with time.

[0064] In some embodiments of the present application, reference is made to Figure 2bThe first digital-to-analog converter circuit 10 also includes: a divider 104, a first input end of the divider 104 is connected to the output end of the quantizer 102, a second input end of the divider 104 is used to receive the correction factor K, and the divider 104 is used to output a feedback signal according to the fourth digital signal and the correction factor K; an adder 105, a first input end of the adder 105 is used to receive the input signal of the first digital-to-analog converter circuit 10, a second input end of the adder 105 is connected to the output end of the divider 104, and the output end of the adder 105 is connected to the modulator 100, and the adder 105 is used to add the input signal and the feedback signal to output the first digital signal to the modulator 100.

[0065] Here, the divider 104 may divide the fourth digital signal by the correction factor K to obtain a feedback signal.

[0066] In some embodiments of the present application, the corrector 101 may be a multiplier. Specifically, the corrector 101 may multiply the second digital signal by a correction factor K to obtain a corrected third digital signal.

[0067] In some embodiments of the present application, the correction factor K is calculated as follows:

[0068]

[0069] Wherein, Vmax is the maximum value of the PWM carrier, and Vcenter is the center value of the PWM carrier.

[0070] Here, since the original number of steps N0 of the counter generating the PWM carrier is proportional to the carrier center value Vcenter of the PWM carrier, and the number of steps N1 of the counter after spread spectrum modulation is proportional to the carrier maximum value Vmax of the PWM carrier, the correction factor K has the following relationship:

[0071]

[0072] Next, the effect of using the correction factor K in the first DAC circuit 10 will be described in conjunction with specific application scenarios.

[0073] Specifically, taking the second digital signal X0=524288, the bit width is 22 bits, the decimal precision is 21 bits, the fourth digital signal quantized by the quantizer 102 is 8 bits, the decimal precision is 7 bits, and the original number of steps of the counter N0=128 as an example, the duty cycle DC0 of the PWM signal before spread spectrum modulation is:

[0074]

[0075] Taking the counter step number N1=114 after the spread spectrum modulation as an example, the third digital signal X1 obtained by multiplying the second digital signal X0 by the correction factor K based on the corrector 101 is:

[0076]

[0077] At this time, the duty cycle DC1 of the PWM signal calculated based on the third digital signal X1 is:

[0078]

[0079] Obviously, the duty cycle DC0 of the PWM signal before using the spread spectrum modulation is 25%, and the duty cycle DC1 of the PWM signal after using the spread spectrum modulation is still 25%. That is, based on the first digital-to-analog converter circuit 10 of the present application, the duty cycle before and after using the SSM can be kept consistent in actual application, so as to avoid the distortion problem caused by using the spread spectrum modulation.

[0080] That is, the first digital-to-analog converter circuit 10 provided by the present application can keep the duty cycle consistent after using the SSM in actual application by arranging the corrector 101 before the quantizer 102, so as to avoid the audio distortion problem caused by using the spread spectrum modulation.

[0081] Next, the first digital-to-analog converter circuit 10 provided by the present application will be further described in combination with the accompanying drawings and embodiments.

[0082] In addition to being able to avoid the distortion problem caused by using the spread spectrum modulation, the first digital-to-analog converter circuit 10 provided by the present application can also avoid the phenomenon of audio clipping of the digital audio power amplifier caused by using the spread spectrum modulation.

[0083] Next, first, the reason why the use of the spread spectrum modulation may cause the phenomenon of audio clipping of the digital audio power amplifier will be described.

[0084] In the digital audio power amplifier using PWM, the sampling frequency of the input signal should be equal to the frequency of the output PWM signal, so as to ensure that the digital audio power amplifier will not clip. However, since the frequency of the output PWM signal is determined by the PWM carrier frequency, specifically, the frequency of the output PWM signal is equal to the PWM carrier frequency, when the spread spectrum modulation is applied to change the PWM carrier frequency, the frequency of the output PWM signal will also change. Further, the signal loss may occur in the signal transmission process due to the inconsistency between the sampling frequency of the input signal and the frequency of the output PWM signal, and further cause the phenomenon of audio clipping of the digital audio power amplifier.

[0085] To solve the technical problem, in some embodiments of the present application, referring to Figure 3The pulse width modulation circuit 103 of the first digital-to-analog converter circuit 10 provided in the present application may further include: a first memory 106, wherein an input end of the first memory 106 is connected to the quantizer 102 and is used to store the fourth digital signal, wherein the depth of the first memory 106 is greater than or equal to a first threshold, and the first threshold is the number of fourth digital signals output by the quantizer 102 within the first time duration; and a PWM modulator 107, wherein a first input end of the PWM modulator 107 is connected to the output end of the first memory 106 and is used to generate a PWM signal based on a PWM carrier and the fourth digital signal stored in the first memory 106. The maximum value of the PWM carrier periodically changes with a first time duration, so that the frequency of the PWM carrier periodically changes with a first time duration. Furthermore, the average value of the frequency of the PWM carrier within the first time duration is equal to the sampling frequency of the fourth digital signal.

[0086] Here, the average value of the PWM carrier frequency during the first time period is equal to the sampling frequency of the fourth digital signal. It is understood that, during the first time period, the number of fourth digital signals that can be generated by the first DAC circuit 10 based on the input signal is equal to the number of PWM signals that can be generated based on the fourth digital signal, and both numbers are equal to the first threshold. Therefore, the first DAC circuit 10 can be configured with a first memory 106 having a depth greater than or equal to the first threshold. Upon commencement of operation, the first DAC circuit 10 can pre-store a plurality of fourth digital signals in the first memory 106 (e.g., the number of pre-stored fourth digital signals can be greater than or equal to the first threshold). After pre-storage is complete, the PWM modulator 107 retrieves the fourth digital signal from the first memory 106 to generate the PWM signal. Based on this approach, even if the PWM carrier frequency changes, for example, if the PWM carrier frequency is greater than the sampling frequency of the fourth digital signal at certain moments, the PWM modulator 107 can successfully retrieve the fourth digital signal from the first memory 106, thereby avoiding the phenomenon of audio dropout in the digital audio amplifier due to inconsistency between the sampling frequency of the input signal and the frequency of the output PWM signal.

[0087] It can be understood that the present application does not provide a restrictive description of the number of pre-stored fourth digital signals, and the aforementioned number greater than or equal to the first threshold is only an example.

[0088] This application does not limit the specific depth of the first memory 106. The depth can be selected according to the spread spectrum range and step size to meet the requirement of not causing data loss.

[0089] In an exemplary embodiment, taking the depth of the first memory 106 as M, the number of spread spectrum steps as N, the sampling frequency of the fourth digital signal as FIN, and the PWM carrier frequency as F_SSM(i), 1≤i≤N as an example, the depth M of the first memory 106 must satisfy the following relationship:

[0090] (1 / FIN)*(NM)<(1 / F_SSM(1)+1 / F_SMM(2)+…+1 / F_SMM(N))<(1 / FIN)*(N+M).

[0091] For example, Figure 4 FIG. 1 shows a schematic diagram of generating a PWM carrier based on the first memory 106 .

[0092] Here, Figure 4 Taking the first threshold as 2, the depth of the first memory 106 as 4, and the sampling frequency of the fourth digital signal as 384 kHz as an example, the quantizer 102 sends the fourth digital signal to the first memory 106 at a fixed sampling frequency of 384 kHz, and the PWM modulator 107 obtains the fourth digital signal from the output address of the first memory 106 at a dynamically changing PWM carrier frequency.

[0093] Specifically, the quantizer 102 sends the fourth digital signal D2 to the address [0] of the first memory 106 at a sampling frequency of 384KHz during the T10 period, sends the fourth digital signal D3 to the address [1] of the first memory 106 at a sampling frequency of 384KHz during the T11 period, sends the fourth digital signal D4 to the address [2] of the first memory 106 at a sampling frequency of 384KHz during the T12 period, and sends the fourth digital signal D5 to the address [3] of the first memory 106 at a sampling frequency of 384KHz during the T13 period.

[0094] After the address [0] and the address [1] of the first memory 106 respectively store the fourth digital signal D2 and the fourth digital signal D3, the PWM modulator 107 can obtain the fourth digital signal D2 from the address [0] of the first memory 106 at the PWM carrier frequency of 372KHZ in the T20 period, obtain the fourth digital signal D3 from the address [1] of the first memory 106 at the PWM carrier frequency of 378KHZ in the T21 period, obtain the fourth digital signal D4 from the address [2] of the first memory 106 at the PWM carrier frequency of 384KHZ in the T22 period, and obtain the fourth digital signal D5 from the address [3] of the first memory 106 at the PWM carrier frequency of 390KHZ in the T23 period.

[0095] After the fourth digital signal D2 sent during the T10 period and the fourth digital signal D3 sent during the T11 period are output, the quantizer 102 may again send the fourth digital signal D6 to the address [0] of the first memory 106 at a sampling frequency of 384 kHz during the T14 period, and again send the fourth digital signal D7 to the address [1] of the first memory 106 at a sampling frequency of 384 kHz during the T15 period.

[0096] After the address [0] and the address [1] of the first memory 106 respectively store the fourth digital signal D6 and the fourth digital signal D7, the PWM modulator 107 can obtain the fourth digital signal D6 from the address [0] of the first memory 106 at the PWM carrier frequency of 396KHZ during the T24 period, and obtain the fourth digital signal D7 from the address [1] of the first memory 106 at the PWM carrier frequency of 402KHZ during the T25 period.

[0097] Obviously, during this process, although the PWM carrier frequency is changing dynamically, the PWM modulator 107 can always successfully obtain the fourth digital signal from the first memory 106, and will not cause signal loss during signal transmission due to the inconsistency between the sampling frequency of the fourth digital signal and the frequency of the output fourth digital signal. Therefore, the phenomenon of sound loss in the digital audio amplifier is effectively avoided.

[0098] In some embodiments of this application, see Figure 3 The pulse width modulation circuit 103 further includes a second memory 108 for storing a maximum carrier value of the PWM carrier. An output of the second memory 108 is connected to a second input of the PWM modulator 107, so that the PWM modulator 107 generates a PWM carrier based on the maximum carrier value stored in the second memory 108. The maximum carrier value is used to determine the frequency of the PWM carrier, wherein the center frequency of the PWM carrier is equal to the sampling frequency of the fourth digital signal. The center frequency of the PWM carrier may be an average value of the frequency of the PWM carrier within the first time period.

[0099] Here, the first memory 106 and the second memory 108 may be FIFO memories, and the specifications of the first memory 106 and the second memory 108 may be the same. The fourth digital signal input to the first memory 106 and the maximum PWM carrier signal input to the second memory 108 are synchronously passed through the first memory 106 and the second memory 108, ensuring that the signal-to-noise ratio of the output PWM signal is not degraded due to data loss.

[0100] Here, the PWM carrier generated by the PWM modulator 107 can be a triangular wave or a sawtooth wave, and the center frequency of the PWM carrier can be between 192 kHz and 3 MHz. Accordingly, the PWM modulator 107 can include a triangular wave / sawtooth wave generation module for generating the PWM carrier, and the triangular wave / sawtooth wave generation module can include the aforementioned counter. It should be understood that this application does not limit the waveform of the PWM carrier.

[0101] In some embodiments of this application, see Figure 3The first digital-to-analog converter circuit 10 may further include: a frequency generator 109, an input end of the frequency generator 109 being used to receive a PWM carrier center value and a spread spectrum range, a first output end of the frequency generator 109 being connected to an input end of the second memory 108, and being used to output a maximum carrier value of the PWM carrier to the second memory 108 according to the PWM carrier center value and the spread spectrum range, an input end of a correction factor generator 110 being connected to a second output end of the frequency generator 109, and being used to generate a correction factor K according to the PWM carrier center value and the PWM carrier maximum value output by the frequency generator 109, and an output end of the correction factor generator 110 being connected to the corrector 101, and being used to output the correction factor K to the corrector 101.

[0102] Frequency generator 109 can generate a pseudo-random or periodic PWM carrier maximum value based on the input PWM carrier center value and spread spectrum range. This PWM carrier maximum value is output via second memory 108 to the triangle / sawtooth wave generation module of PWM modulator 107 to generate a PWM carrier with a pseudo-random or periodic frequency pattern. This disperses electromagnetic radiation across a wider frequency band, reducing concentrated radiated energy.

[0103] Furthermore, the input of frequency generator 109 can also receive a step size. Here, the step size refers to the frequency variation interval of the PWM carrier, that is, the change in the instantaneous frequency of the PWM carrier between adjacent moments. For example, if the center frequency fcen corresponding to the PWM carrier center value is 400kHz, the spread spectrum range Δf is 40kHz, and the step size fstep is 2kHz, then the PWM carrier will dynamically vary between 360kHz and 440kHz in steps of 2kHz.

[0104] It will be appreciated that the PWM carrier center value received by frequency generator 109 can be selected based on the center frequency of the PWM carrier. The spread spectrum range and step size received by frequency generator 109 can be selected based on the desired spread spectrum effect. The sequence of PWM carrier maximum values ​​generated by frequency generator 109 can be a pseudo-random number sequence, a geometric sequence, an arithmetic sequence, or the like.

[0105] Frequency generator 109 can generate a variable maximum PWM carrier value based on the input PWM carrier center value, spread spectrum range, and spread spectrum step size. Frequency generator 109 can send the generated maximum PWM carrier value to second memory 108. Furthermore, PWM modulator 107 can read the maximum PWM carrier value from second memory 108 and generate a PWM carrier based on the maximum PWM carrier value. In some embodiments, PWM modulator 107 includes a triangle wave / sawtooth wave generation module that can generate a PWM carrier based on the maximum PWM carrier value stored in second memory 108.

[0106] For example, Figure 5 A schematic diagram of a PWM carrier with a triangular wave waveform is shown.

[0107] See also Figure 5 The PWM carrier center value is 128, the spread spectrum range is 16, and the generation mode is a pseudo-random frequency mode. Specifically, for a maximum PWM carrier value of 119, the PWM carrier frequency is 714 kHz; for a maximum PWM carrier value of 113, the PWM carrier frequency is 678 kHz; for a maximum PWM carrier value of 133, the PWM carrier frequency is 798 kHz; for a maximum PWM carrier value of 141, the PWM carrier frequency is 846 kHz; and for a maximum PWM carrier value of 128, the PWM carrier frequency is 768 kHz. Furthermore, the larger the maximum PWM carrier value, the larger the peak value of the PWM carrier; conversely, the smaller the maximum PWM carrier value, the smaller the peak value of the PWM carrier.

[0108] In some embodiments of this application, see Figure 3 The modulator 100, the corrector 101, the quantizer 102, the divider 104, and the adder 105 may be integrated into the same modulation filter 111. The modulation filter 111 may be a ΔΣ modulation filter. Accordingly, the first DAC circuit 10 may implement ΔΣ modulation of the input signal based on the modulator 100, the corrector 101, the quantizer 102, the divider 104, and the adder 105.

[0109] It's understood that the order, coefficient configuration, and quantization bit width of the ΔΣ modulation filter can be flexibly adjusted to ensure that its output signal-to-noise ratio meets the application requirements. For example, if a better signal-to-noise ratio is required for the ΔΣ modulation filter, its order and quantization bit width can be higher. The oversampling rate is determined by the center frequency of the PWM carrier.

[0110] Here, since the correction link implemented by the first digital-to-analog converter circuit 10 based on the corrector 101 is performed in the ΔΣ modulation filter, and the function of the ΔΣ modulation filter in the first digital-to-analog converter circuit 10 is to move the noise outside the audio band, therefore, performing the correction link in the ΔΣ modulation filter can move the noise caused by the calculation error that may be generated by the correction outside the audio band, thereby not affecting the signal-to-noise ratio in the audio band, and further ensuring that the played audio is not distorted.

[0111] In addition, the present application also provides another second digital-to-analog converter circuit 20, see Figure 6The second digital-to-analog converter circuit 20 includes: a corrector 200, connected to the input end of the second digital-to-analog converter circuit 20, for correcting the input signal of the digital-to-analog converter circuit 20 according to the correction factor K to obtain a fifth digital signal; a modulator 201, for modulating the fifth digital signal to generate a sixth digital signal; a quantizer 202, connected to the modulator 201, for quantizing the sixth digital signal to obtain a fourth digital signal, wherein the bit width of the sixth digital signal is greater than the bit width of the fourth digital signal; a pulse width modulation circuit 203, connected to the quantizer 202, for converting the fourth digital signal into a PWM signal based on a PWM carrier, where the PWM carrier is a carrier whose frequency changes with time; wherein the correction factor K is used to compensate for changes in the duty cycle of the PWM signal caused by changes in the frequency of the PWM carrier.

[0112] The digital-to-analog converter circuit 20 can also perform a correction step first, followed by a quantization step to reduce the bit width of the digital signal. That is, the digital-to-analog converter circuit 20 first corrects the high-bitwidth input signal based on the correction factor K to obtain a high-bitwidth fifth digital signal, and then modulates and quantizes the high-bitwidth fifth digital signal into a low-bitwidth fourth digital signal. It can be understood that due to the high bit width of the input signal, the calculation accuracy of the input signal is correspondingly high. Therefore, performing a correction process based on the input signal can effectively improve the accuracy of the correction factor K, further avoiding the problem of audio playback distortion caused by frequency variations of the PWM carrier.

[0113] Here, the calibrator 200 is substantially the same as the aforementioned calibrator 101, the modulator 201 is substantially the same as the aforementioned modulator 100, the quantizer 202 is substantially the same as the aforementioned quantizer 102, and the pulse width modulation circuit 203 is substantially the same as the aforementioned pulse width modulation circuit 103. A detailed description of the calibrator 200, modulator 201, quantizer 202, and pulse width modulation circuit 203 is omitted here. For details, please refer to the detailed description of the calibrator 101, modulator 100, quantizer 102, and pulse width modulation circuit 103 above.

[0114] In some embodiments of this application, see Figure 7 The second DAC circuit 20 further includes an adder 205, wherein a first input terminal of the adder 205 is connected to the output terminal of the corrector 200, a second input terminal of the adder 205 is connected to the output terminal of the quantizer 102, and an output terminal of the adder 205 is connected to the modulator 201. The adder 205 is configured to add the fifth digital signal and the fourth digital signal to output the added signal to the modulator 201. The quantizer 102 modulates the added signal to generate a sixth digital signal.

[0115] In some embodiments of the present application, the modulator 201, quantizer 202, and adder 205 are integrated into the same modulation filter, and the corrector 200 is located outside the modulation filter. Furthermore, in other embodiments of the present application, the corrector 200, modulator 201, quantizer 202, and adder 205 may be integrated into the same modulation filter. This modulation filter may be the aforementioned ΔΣ modulation filter, with the correction stage implemented before the quantization stage of the ΔΣ modulation filter. This provides high computational accuracy and can move noise generated by computational errors outside the audio band, thereby not affecting the signal-to-noise ratio within the audio band.

[0116] Continue to see Figure 7 The second DAC circuit 20 may further include a first memory 206, a second memory 208, a PWM modulator 207, a frequency generator 209, and a correction factor generator 210. The first memory 206 is substantially the same as the aforementioned first memory 106, the second memory 208 is substantially the same as the aforementioned second memory 108, the PWM modulator 207 is substantially the same as the aforementioned PWM modulator 107, the frequency generator 209 is substantially the same as the aforementioned frequency generator 109, and the correction factor generator 210 is substantially the same as the aforementioned correction factor generator 110.

[0117] The first memory 206, the second memory 208, the PWM modulator 207, the frequency generator 209 and the correction factor generator 210 are not described in detail here. Their specific contents and connection relationships can be found in the detailed description of the first memory 106, the second memory 108, the PWM modulator 107, the frequency generator 109 and the correction factor generator 110 above.

[0118] The present application provides a chip, which may include the first digital-to-analog converter circuit 10 or the second digital-to-analog converter circuit 20 .

[0119] The present application provides an electronic device, which may include the first digital-to-analog converter circuit 10 or the second digital-to-analog converter circuit 20 .

[0120] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed over a network or through other computer-readable media. Therefore, a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), including but not limited to floppy disks, optical disks, optical discs, read-only memories (CD-ROMs), magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, flash memory, or a tangible machine-readable memory for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in electrical, optical, acoustic, or other forms of propagation signals. Therefore, a machine-readable medium includes any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

[0121] In the accompanying drawings, some structural or method features may be shown in a particular arrangement and / or order. However, it should be understood that such a particular arrangement and / or order may not be required. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. In addition, the inclusion of a structural or method feature in a particular figure does not imply that such feature is required in all embodiments, and in some embodiments, such features may not be included or may be combined with other features.

[0122] It should be noted that the units / modules mentioned in the various device embodiments of the present application are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, or a part of a physical unit / module, or can be implemented as a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important. The combination of functions implemented by these logical units / modules is the key to solving the technical problems raised by this application. In addition, in order to highlight the innovative part of this application, the above-mentioned device embodiments of this application do not introduce units / modules that are not closely related to solving the technical problems raised by this application. This does not mean that other units / modules do not exist in the above-mentioned device embodiments.

[0123] It should be noted that in the examples and description of this patent, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprises" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a" do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0124] Although the present application has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the application.

Claims

1. A digital-to-analog converter circuit, characterized in that: The digital-to-analog converter circuit comprises: A modulator, configured to modulate an input first digital signal into a second digital signal; a corrector, connected to the modulator, configured to correct the second digital signal according to a correction factor to obtain a third digital signal; a quantizer, connected to the corrector, and configured to quantize the third digital signal to obtain a fourth digital signal, wherein a bit width of the third digital signal is greater than a bit width of the fourth digital signal; a pulse width modulation circuit connected to the quantizer, configured to convert the fourth digital signal into a PWM signal based on a PWM carrier, wherein the PWM carrier is a carrier whose frequency varies with time; The correction factor is used to compensate for the change in the duty cycle of the PWM signal caused by the change in the frequency of the PWM carrier.

2. The digital-to-analog converter circuit according to claim 1, wherein: The digital-to-analog converter circuit further includes: a divider, wherein a first input terminal of the divider is connected to the output terminal of the quantizer, a second input terminal of the divider is used to receive the correction factor, and the divider is used to output a feedback signal according to the fourth digital signal and the correction factor; An adder, wherein a first input end of the adder is used to receive an input signal of the digital-to-analog converter circuit, a second input end of the adder is connected to the output end of the divider, and an output end of the adder is connected to the modulator, and the adder is used to add the input signal and the feedback signal to output the first digital signal to the modulator.

3. The digital-to-analog converter circuit according to claim 2, wherein: The modulator, the corrector, the quantizer, the divider, and the adder are integrated into the same modulation filter.

4. A digital-to-analog converter circuit, characterized in that: The digital-to-analog converter circuit comprises: a corrector, connected to an input terminal of the digital-to-analog converter circuit, configured to correct the input signal of the digital-to-analog converter circuit according to a correction factor to obtain a fifth digital signal; a modulator, configured to generate a sixth digital signal by modulating the fifth digital signal; a quantizer, connected to the modulator, and configured to quantize the sixth digital signal to obtain a fourth digital signal, wherein a bit width of the sixth digital signal is greater than a bit width of the fourth digital signal; a pulse width modulation circuit connected to the quantizer, configured to convert the fourth digital signal into a PWM signal based on a PWM carrier, wherein the PWM carrier is a carrier whose frequency varies with time; The correction factor is used to compensate for the change in the duty cycle of the PWM signal caused by the change in the frequency of the PWM carrier.

5. The digital-to-analog converter circuit according to claim 4, wherein: The digital-to-analog converter circuit further includes: an adder, wherein a first input terminal of the adder is connected to the output terminal of the corrector, a second input terminal of the adder is connected to the output terminal of the quantizer, and an output terminal of the adder is connected to the modulator, and the adder is configured to add the fifth digital signal and the fourth digital signal to output the added signal to the modulator; Furthermore, the modulator is used to modulate the added signal to generate the sixth digital signal.

6. The digital-to-analog converter circuit according to claim 5, wherein: The modulator, the quantizer and the adder are integrated in the same modulation filter, and the corrector is located outside the modulation filter.

7. The digital-to-analog converter circuit according to any one of claims 1 to 6, characterized in that: The corrector is a multiplier.

8. The digital-to-analog converter circuit according to any one of claims 1 to 7, characterized in that: The correction factor K is calculated as follows: Wherein, Vmax is the maximum value of the PWM carrier, and Vcenter is the center value of the PWM carrier.

9. The digital-to-analog converter circuit according to any one of claims 1 to 8, characterized in that: The maximum value of the carrier of the PWM carrier periodically changes with a first time length as a period, so that the frequency of the PWM carrier periodically changes with the first time length as a period.

10. The digital-to-analog converter circuit according to claim 9, wherein: The pulse width modulation circuit comprises: a first memory, wherein an input end of the first memory is connected to the quantizer, and is used to store the fourth digital signal, wherein a depth of the first memory is greater than or equal to a first threshold, and the first threshold is the number of the fourth digital signals output by the quantizer within the first duration; A PWM modulator, wherein a first input terminal of the PWM modulator is connected to an output terminal of the first memory, and is configured to generate the PWM signal according to the PWM carrier and the fourth digital signal stored in the first memory.

11. The digital-to-analog converter circuit according to claim 10, wherein: The pulse width modulation circuit further includes: a second memory for storing a maximum carrier value of the PWM carrier, wherein an output terminal of the second memory is connected to a second input terminal of the PWM modulator, so that the PWM modulator generates the PWM carrier based on the maximum carrier value stored in the second memory, and the maximum carrier value is used to determine the frequency of the PWM carrier; The center frequency of the PWM carrier is equal to the sampling frequency of the fourth digital signal.

12. The digital-to-analog converter circuit according to claim 11, wherein: The digital-to-analog converter further comprises: a frequency generator, wherein a first output terminal of the frequency generator is connected to an input terminal of the second memory, the frequency generator is configured to generate a maximum carrier value of the PWM carrier according to a carrier center value, a spread spectrum step size, and a spread spectrum range of the PWM carrier, and output the maximum carrier value to the second memory; A correction factor generator, wherein the input end of the correction factor generator is connected to the second output end of the frequency generator, the output end of the correction factor generator is connected to the corrector, and the correction factor generator is used to generate the correction factor according to the carrier center value and the carrier maximum value, and output the correction factor to the corrector.

13. A chip, characterized in that: The chip includes the digital-to-analog converter circuit according to any one of claims 1 to 12.

14. An electronic device, characterized in that: The electronic device comprises the chip according to claim 13.

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