Soft information processing method for LDPC (Low Density Parity Check) decoder and related equipment

Abstract

One or more embodiments of the invention provide an LDPC decoder-oriented soft information processing method and related equipment. The method comprises the following steps: mapping a lifting factor of an input code block to obtain a mapping lifting factor according to the width of an input bus of a decoder and a maximum lifting factor allowed by a communication protocol; according to the mapping lifting factor, the input code block is expanded into a rearrangement code block, and the width of the rearrangement code block is a multiple of the width of the input bus; and storing the rearranged code block into a decoder memory, wherein data only containing the same input code block is stored each time. According to the invention, the data input time delay can be effectively reduced, and the communication transmission efficiency is improved. In addition, the problem of wiring congestion can be effectively relieved.

Description

Technical Field

[0001] One or more embodiments of the present disclosure relate to the technical field, and in particular to a soft information processing method for an LDPC decoder and related devices. Background Art

[0002] It should be noted that the above technical background is merely provided to provide a clear and complete description of the technical solutions of the present invention and to facilitate understanding by those skilled in the art. Simply because these solutions are described in the technical background section of the present invention, it should not be assumed that the above technical solutions are well known to those skilled in the art.

[0003] As wireless communication technology evolves towards 5G / 6G, the fifth-generation Reduced Instruction Set Computer-V (RISC-V) processor is gradually being applied to the physical layer of communication systems due to its open source and customizable features. As the core link in achieving high-speed communication, the physical layer achieves multi-Gbps data throughput per unit area through high-order spectrum efficiency technologies, wide spectrum resource utilization, and advanced multi-antenna technologies to support low-latency, high-bandwidth applications such as 4K video streaming and VR / AR. This places stringent requirements on the latency and throughput of physical layer data processing. As a key processing link in the physical layer, the decoding of low-density parity-check codes (LDPC) has become a system bottleneck.

[0004] LDPC codes, with their excellent error correction performance, have been widely adopted in modern wireless communication standards. In the 5G New Radio (NR) standard, Quasi-Cyclic Low-Density Parity-Check Codes (QC-LDPC) replace the Turbo codes used in Long-Term Evolution (LTE) technology as the core coding scheme for the user data plane.

[0005] In related technologies, approaches to improving LDPC decoder throughput fall into two main categories: optimizing scheduling algorithms to eliminate pipeline conflicts to maximize peak throughput, or employing short codeword parallel processing to improve average throughput. However, performance evaluations of these approaches generally focus solely on computational logic latency, ignoring the data transmission overhead between storage and arithmetic units. In real-world scenarios, as code length and modulation order increase, data transmission latency significantly outweighs computational latency, becoming a key, hidden bottleneck limiting the real-time performance of decoders. Summary of the Invention

[0006] In view of this, the purpose of one or more embodiments of the present disclosure is to propose a soft information processing method and related devices for an LDPC decoder to solve the problem.

[0007] Based on the above objectives, one or more embodiments of the present disclosure provide a soft information processing method for an LDPC decoder, including:

[0008] According to the width of the input bus of the decoder and the maximum lifting factor allowed by the communication protocol, the lifting factor of the input code block is mapped to obtain a mapped lifting factor;

[0009] Expanding the input code block into a rearranged code block according to the mapping lifting factor, wherein the width of the rearranged code block is a multiple of the input bus width;

[0010] The rearranged code blocks are stored in a decoder memory, each storage only containing data of the same input code block.

[0011] Optionally, mapping the lifting factor of the input code block to obtain a mapped lifting factor according to an input bus width of the decoder and a maximum lifting factor allowed by a communication protocol includes:

[0012] Obtaining a grouping coefficient according to a common integer factor of the input bus width and the maximum lifting factor, wherein the grouping coefficient represents a component scale of the lifting factor;

[0013] The lifting factors are mapped according to the grouping coefficient and the maximum lifting factor to obtain a mapped lifting factor.

[0014] Optionally, obtaining a grouping coefficient according to the input bus width and the maximum lifting factor includes:

[0015] Calculating a first set of integer factors of a ratio of the maximum lifting factor bit width to the input bus bit width, and a second set of integer factors of the maximum lifting factor;

[0016] Taking an intersection of the first set of integer factors and the second set of integer factors to obtain at least one common integer factor;

[0017] A common integer factor is selected and the reciprocal of the integer factor is used as the grouping coefficient.

[0018] Optionally, mapping the lifting factors according to the grouping coefficient and the maximum lifting factor to obtain a mapped lifting factor includes:

[0019] Multiplying the maximum lifting factor by the grouping coefficient to obtain a scaling reference value;

[0020] Dividing the lifting factor by the scaling reference value and rounding up the result to obtain a quantization multiple;

[0021] The scaling reference value and the quantization multiple are multiplied to obtain the mapping lifting factor.

[0022] Optionally, the expanding the input code block into a rearranged code block according to the mapping lifting factor includes:

[0023] determining a width of the input code block according to a lifting factor of the input code block;

[0024] determining a width of the rearranged code block according to the mapping lifting factor;

[0025] Determining the number of zero-padding bits according to a difference between the width of the rearranged code block and the width of the input code block;

[0026] According to the number of zero-padding bits, zeros are padded at the end of the input code block to obtain the rearranged code block.

[0027] Optionally, storing the rearranged code blocks into a decoder memory, each storage including only data of the same input code block, comprises:

[0028] In response to determining that the width of the rearranged code block is greater than the width of the input bus, dividing the rearranged code block into a plurality of transmission code blocks, wherein the width of each transmission code block is the same as the width of the input bus;

[0029] The transmission code block is quantized and stored in the decoder memory, and the data of each rearranged code block occupies a continuous address space in the decoder memory.

[0030] Optionally, the width of the decoder memory is set to the product of the maximum number of base matrix columns, the maximum lifting factor of the communication protocol and the quantization accuracy.

[0031] Based on the same inventive concept, one or more embodiments of the present disclosure further provide a soft information processing device for an LDPC decoder, comprising:

[0032] A first calculation module is configured to map the lifting factor of the input code block according to the width of the input bus of the decoder and the maximum lifting factor allowed by the communication protocol to obtain a mapped lifting factor;

[0033] a second calculation module configured to expand the input code block into a rearranged code block according to the mapping lifting factor, wherein the width of the rearranged code block is a multiple of the input bus width;

[0034] The storage module is configured to store the rearranged code block into the decoder memory, and each storage only contains data of the same input code block.

[0035] Based on the same inventive concept, one or more embodiments of the present disclosure also provide an electronic device, including a memory, a processor, and a computer program stored in the memory and runnable on the processor. When the processor executes the program, it implements the soft information processing method for the LDPC decoder as described in any one of the above items.

[0036] Based on the same inventive concept, one or more embodiments of the present disclosure also provide a non-transitory computer-readable storage medium, which stores computer instructions, and the computer instructions are used to enable the computer to execute any of the above-mentioned soft information processing methods for LDPC decoders.

[0037] As can be seen from the foregoing, the soft information processing method for an LDPC decoder provided by one or more embodiments of the present disclosure maps the lifting factor of the input code block to obtain a mapping lifting factor based on the width of the decoder's input bus and the maximum lifting factor allowed by the communication protocol; expands the input code block into a rearranged code block based on the mapping lifting factor, wherein the width of the rearranged code block is a multiple of the input bus width; and stores the rearranged code block in the decoder memory, with each storage containing only data of the same input code block.

[0038] This soft information processing method for LDPC decoders dynamically maps the lifting factor of the input code block according to the decoder input bus width and the maximum lifting factor of the protocol, expands the code block into a rearranged code block that is an integer multiple of the bus width, and ensures that a single storage contains only the data of the same code block, achieving efficient decoding compatible with multiple protocols. It not only breaks through the limitations of traditional schemes on specific protocols and supports adaptive processing of multi-standard lifting factors, but also eliminates cross-block transmission fragmentation through bus width adaptation, reducing data transmission delay.

[0039] The soft information processing device, electronic device, and computer-readable storage medium for an LDPC decoder provided in the present disclosure are all capable of implementing the steps of the above-mentioned soft information processing method for an LDPC decoder, and therefore also have the beneficial effects of the above-mentioned soft information processing method for an LDPC decoder. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate one or more embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only one or more embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0041] Figure 1A flowchart of a soft information processing method for an LDPC decoder according to one or more embodiments of the present disclosure;

[0042] Figure 2 A schematic diagram of the structure of a soft information processing device for an LDPC decoder according to one or more embodiments of the present disclosure;

[0043] Figure 3 A schematic diagram of a process of inputting a code block into a decoder according to an embodiment of the present disclosure;

[0044] Figure 4 A schematic diagram of an input code block input to a decoder according to an embodiment of the related art;

[0045] Figure 5 This is a diagram showing the experimental results of an input delay experiment disclosed herein;

[0046] Figure 6 This is a diagram of the QC-LDPC pipeline decoder architecture used in a throughput experiment of this disclosure;

[0047] Figure 7 This is a graph showing the experimental results of a throughput experiment disclosed herein;

[0048] Figure 8 This is a graph showing the experimental results of a throughput experiment disclosed herein;

[0049] Figure 9 A schematic diagram of the hardware structure of an electronic device according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0050] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0051] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in one or more embodiments of the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in one or more embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0052] As described in the background technology section, LDPC codes have been widely used in modern wireless communication standards due to their excellent error correction performance.

[0053] According to the 3GPP TS 38.212 standard, 5G NR defines two base matrices (BG): BG1 is 46×68 in size and has a nominal mother code rate of 1 / 3; BG2 is 42×52 in size and has a nominal mother code rate of 1 / 5. Puncturing or shortening technology can flexibly adjust the code rate to between 1 / 5 and 8 / 9. c ) size and puncturing, the 5G NR LDPC code set can generate thousands of code patterns, covering payloads up to 8448 bits and the full range of code rates. This requirement requires 5G NR's LDPC scheme to support tens of Gbps of high throughput and low latency transmission to meet the requirements of enhanced mobile broadband (eMBB) scenarios. Meeting these requirements in hardware is challenging.

[0054] In related technologies, LDPC decoder design mainly improves throughput in two ways: optimizing the scheduling algorithm to eliminate pipeline conflicts to achieve maximum peak throughput, or parallelizing short codeword processing to improve average throughput.

[0055] For example, through circular addressing optimization and pipeline structure design, memory access conflicts during decoding can be reduced and peak throughput can be improved. Alternatively, through a reconfigurable circular shift module and a multi-codeword parallel processing architecture, data with different code lengths can be decoded simultaneously.

[0056] However, this type of technical solution still suffers from poor decoder flexibility. The proposed architecture is only targeted at a single communication system, and for decoding systems with multiple lifting factors, a large number of registers and routing resources are generated when quantizing soft information (the soft information in this disclosure is in the form of log-likelihood ratio), resulting in wiring congestion and even timing violations.

[0057] To this end, the present disclosure proposes a soft information processing method for LDPC decoders. For LDPC decoders, the soft decision input bits of the input LDPC decoder are rearranged based on the base graph, code length and other information of the LDPC decoder. In this technical solution, by dynamically mapping the lifting factor of the input code block to a value that matches the decoder input bus width, the code block is expanded to a rearranged code block that is an integer multiple of the bus width, and it is ensured that a single storage only contains the same code block data, thereby achieving efficient decoding compatible with multiple protocols. Through the solution disclosed in the present disclosure, the transmission efficiency of multi-bus configurations can be effectively improved, and wiring congestion can be effectively alleviated. In addition, the technical solution disclosed in the present disclosure is applicable to a variety of communication protocols and different LDPC decoder architectures.

[0058] refer to Figure 1 The soft information processing method for an LDPC decoder according to one or more embodiments of the present disclosure includes the following steps:

[0059] Step S101: mapping the lifting factor of the input code block to obtain a mapped lifting factor according to the width of the decoder's input bus and the maximum lifting factor allowed by the communication protocol;

[0060] Step S102: expanding the input code block into a rearranged code block according to the mapping lifting factor, wherein the width of the rearranged code block is a multiple of the input bus width;

[0061] Step S103: storing the rearranged code blocks into a decoder memory, each storage only containing data of the same input code block.

[0062] In order to adapt to the range of lifting factors of different communication protocols and lay the foundation for subsequent code block width adjustment, independent storage of single code blocks and pipeline parallel processing, the technical solution disclosed in this disclosure first normalizes the lifting factor of the input code block.

[0063] The goal of the above normalization process is to establish a relationship between the mapping lifting factor and the input code block, the maximum lifting factor, and the integer multiple of the decoder input bus width, so as to achieve efficient adaptation of the hardware interface while preserving the original information.

[0064] In some implementations of the present disclosure, a grouping coefficient is introduced as a logical link between the lifting factor and the input bus width, building a bridge from the original lifting factor to the mapped lifting factor.

[0065] That is, it is possible to first obtain a grouping coefficient representing the grouping scale of the lifting factor input code block based on the common integer factor of the input bus width and the maximum lifting factor of the input code block; then, based on the grouping coefficient and the maximum lifting factor, map the lifting factor to obtain a mapped lifting factor.

[0066] After expanding the input code block based on the mapping lifting factor obtained in the above steps, not only can all the data of the original input code block be retained, but the width of the input bus can also be adapted, laying the foundation for subsequent data transmission.

[0067] Specifically, in some implementations of the present disclosure, the step of obtaining the grouping coefficient may include: calculating the ratio of the maximum lifting factor bit width to the input bus bit width, and calculating a first set of integer factors of the ratio; calculating a second set of integer factors of the maximum lifting factor; taking the intersection of the first set of integer factors and the second set of integer factors, selecting a common integer factor, and using the reciprocal of the integer factor as the grouping coefficient.

[0068] It is understandable that the number of the above common integer factors may be equal to or greater than 1. When there are more than one common integer factors, in order to achieve the goal of minimizing the transmission delay, the smallest one among the common integer factors may be selected.

[0069] The above calculation process can be expressed as:

[0070]

[0071] in, Indicates the maximum boost factor allowed by the communication protocol, w bus Indicates the width of the decoder input bus.

[0072] In some implementations of the present disclosure, the step of obtaining the mapping lifting factor may include:

[0073] The product of the maximum boost factor and the above grouping coefficient is regarded as the scaling reference value; the original boost factor is divided by the above scaling reference value to obtain the magnification factor, and the decimal multiple is rounded up.

[0074] The above calculation process can be expressed as:

[0075]

[0076] Among them, Z c Represents the lifting factor of the input code block.

[0077] The bit width of the rearranged code block expanded according to the above mapping lifting factor should be equal to the bit width of the input bus or an integral multiple of the bit width of the input bus.

[0078] In some implementations of the present disclosure, when expanding an input code block into a rearranged code block, the difference between the width of the rearranged code block and the width of the input code block may be determined first, and then zeros may be padded at the end of the input code block based on the difference to obtain the rearranged code block.

[0079] In some examples of the present disclosure, the complete process of mapping an input code block to a rearranged code block can be described as follows:

[0080] An input code block (where i is used to distinguish different input code blocks) Input the computer program and preset the lifting factor Z c , base matrix BG, input bus width w bus , common integer factor γ (α = 1 / γ) and other parameters;

[0081] According to the algorithm mentioned above, calculate the mapping lifting factor corresponding to the above lifting factor

[0082] Create and initialize a new code block All elements in the new code block are 0;

[0083] Execute the loop instruction to migrate the data of the input code block to the corresponding position in the rearranged code block, and fill the excess bits in the rearranged code block with zeros.

[0084] The following is a specific example to illustrate the application of the technical solution of the present disclosure in a practical scenario.

[0085] In a specific embodiment of the present disclosure, a codeword is first obtained from a channel;

[0086] Split the above codeword into n db input code blocks, where each input code block There is Z c *8 bits, and each 8 bits contains a log-likelihood ratio (LLR);

[0087] Quantize the LLRs and expand them to 8 bits (LLRs are generally quantized using 5 bits, 6 bits, or 8 bits. In this disclosure, they are uniformly quantized to 8 bits, and any bits less than 8 bits are padded with zeros);

[0088] According to the maximum lifting factor of the communication protocol and the width of the decoder input bus, the grouping coefficient is calculated as

[0089] According to the above grouping coefficient and the maximum lifting factor of the communication protocol, the scaling reference value is determined to be 32, that is, in this embodiment, the original lifting factor Z is 32. c Grouping, when 1≤Z c ≤32, corresponding to When 33≤Z c ≤64, corresponding to And so on;

[0090] Then, according to the mapping lifting factor, the input code block is mapped to the rearranged code block (by Z c *8 bits data is expanded to ), fill the excess bits in the rearranged code block with zeros;

[0091] After adding necessary header information to the above rearranged code block, it is input into the decoder.

[0092] In some implementations of the present disclosure, when storing a rearranged code block in decoder memory, it is necessary to determine whether the bit width of the rearranged code block is greater than the width of the input bus. If the bit width of the rearranged code block is greater than the width of the input bus, the rearranged code block is divided into multiple transmission code blocks, with the width of each code block consistent with the width of the input bus. If the bit width of the rearranged code block is equal to the width of the input bus, no division is required. This is done to ensure that when the quantized transmission code block is stored in the decoder memory, the data of each rearranged code block occupies continuous address space in the decoder memory.

[0093] In some implementations of the present disclosure, the bit width of the memory of the decoder can be set to max{ColOfBG}×max{z c}×6 to accommodate all codeword lengths.

[0094] In some examples of the present disclosure, the process of storing the rearranged code block into the decoder memory may include: inputting the input code block into the quantization LLR module of the decoder, quantizing each information corresponding to 8 bits of data into 6 bits; then inputting the quantized information into the LLR storage module of the decoder; after all the data of a task are stored in the LLR storage module, storing the data in the LLR storage module in the form of Z c *LLR bit size data is grouped together and all data are input into the decoder pipeline.

[0095] In some implementations of the present disclosure, the LLR storage module may be a buffer register.

[0096] In the present disclosure, an input bus data bus width is 256 bits, BG=1, k b =10 is further explained.

[0097] like Figure 3 As shown, in this embodiment, the input code blocks include Block0 and Block1, and the size of each input code block is 52*8 bits.

[0098] The width of the input bus of this embodiment is 256 bits, and the input code blocks need to be segmented before transmission.

[0099] Each time the transmission module is stored in the LLR storage module, it needs to be quantized by the quantization LLR module. After quantization, the 256-bit transmission module is quantized into 192-bit quantized data.

[0100] like Figure 3 As shown, for the first transmission, the 192-bit wide transmission bus needs to be connected to [0:191], the data transmitted for the first time is all the data of input code block Block0;

[0101] During the second transmission, the 192-bit wide transmission bus needs to be connected to [0:119] and [120:191] to store the data of Block0 and Block1 respectively. At this time, the decoder is ready to receive data. data;

[0102] During the third transmission, the 192-bit wide transmission bus is connected to [0:191], the data transmitted for the third time is all the data of the rearranged code block Block1;

[0103] During the fourth transmission, the 192-bit wide transmission bus is still connected to [0:47] and [48:191] To store the data of Block 1 and Block 2 respectively, the decoder is now ready to receive data and receives the data of Block 1.

[0104] As can be seen, during each transmission, the data on the bus comes only from the same data block. This improvement allows data caching to be achieved with only one buffer register during the entire transmission process. Furthermore, the wiring pattern of the LLR storage module is fixed, and the control logic is simple (only a counter is required to control when the LLR storage module data is output to the decoder).

[0105] Below, relevant technologies in the same application scenario are used for comparison.

[0106] Figure 4 As shown, in the example of the related art, the input code blocks include Block 0, Block 1 and Block 2. The size of each input code block is 52*8 bits.

[0107] The width of the input bus of this embodiment is 256 bits, so each rearranged code block needs to be divided into two transmission code blocks and transmitted in batches.

[0108] Each time the transmission module is stored in the LLR storage module, it needs to be quantized by the quantization LLR module. After quantization, the 256-bit transmission module is quantized into 192-bit quantized data.

[0109] like Figure 4 As shown, during the first transmission, the 192-bit wide transmission bus needs to be connected to R in [0:191], the data transmitted for the first time is all the data of the rearranged code block Block0;

[0110] During the second transmission, the 192-bit wide transmission bus is still connected to R in[0:191] The second transmitted data is all the data of the rearranged code block Block0 (including zero-padding data). At this time, the decoder is ready to receive data and receives the data of Block0;

[0111] During the third transmission, the 192-bit wide transmission bus is still connected to R in [0:191], the data transmitted for the third time is all the data of the rearranged code block Block1;

[0112] During the fourth transmission, the 192-bit wide transmission bus is still connected to R in [0:191], the data transmitted for the fourth time is all the data of the rearranged code block Block1 (including zero-padding data). At this time, the decoder is ready to receive data and receives the data of Block1.

[0113] It can be seen that in the implementation of the related art solution, there is a situation where the data transmitted in one transmission comes from different input code blocks (such as the second and fourth transmissions in the above embodiment), and at least two LLR storage modules are required to store the two copies of data respectively. The related art also shows that the LLR memory (LLR RAM) occupies a large area in the LDPC decoder, especially for those decoders that support long codewords. When supporting the maximum lifting factor Z c = 96, a single LLR RAM occupies 24% of the total area of ​​the test chip. That is, even if the related art uses multiple LLR memories to ignore the impact of transmission delay, it may still cause other problems.

[0114] In addition, related technologies also have problems with complex storage wiring and control logic. This highly complex wiring method will cause serious wiring congestion and even cause timing violations as the number of transmissions increases.

[0115] In order to further verify the technical effect of the disclosed technical solution, the applicant also conducted a verification test.

[0116] The applicant tested the technical solution of the present disclosure in the application scenarios based on BG1 base graph and BG2 base graph respectively. Figure 5 As shown in FIG, when the bus width remains unchanged, the larger the common integer factor is, the smaller the grouping coefficient is, and the lower the transmission delay is.

[0117] The applicant further considered the transmission delay when the minimum grouping coefficient was adopted under different bus widths.

[0118] As shown in the following table, smaller bus widths result in smaller latency, while larger bus widths result in larger delays.

[0119]

[0120] Although the effect of reducing the latency is less obvious when the bus width is smaller, the technical solution of the present disclosure still improves the working frequency of the decoder, and as a result, the transmission efficiency of the system is improved.

[0121] To verify the above conclusion, the applicant tested the technical effects of the technical solution of the present disclosure and the related art based on the same decoder architecture. The decoder architecture is as shown in Figure 6 It should be noted that the decoder architecture to which the technical solution of the present disclosure and the technical solution of the related art are applied only differs in the implementation of the log likelihood ratio input conversion module (LLR In Conversion).

[0122] According to the experimental results, when the related art is implemented on the Kintex UltraScale+xcku5p-ffvb676 FPGA, the maximum working frequency of the baseline can be 192MHz, and the critical path is located in the LLR In Conversion module. Excessive fan-out and wiring complexity increase network latency, which ultimately limits the frequency of the decoder in the related art, resulting in a low final throughput. In the technical solution of the present disclosure, the critical path will be transferred to the second pipeline stage of the QSN unit, which performs a shift operation at this stage.

[0123] The applicant calculates the throughput according to the following throughput calculation formula:

[0124]

[0125] Where f CLK represents the maximum working frequency, N represents the number of codewords, n calc represents the number of periods required for one iteration of the decoder, in this architecture, CR = 22 / 27, BG = 0, which is 146, CR = 22 / 68, BG = 0, which is 628, it max represents the maximum number of iterations, which is 8 times in this architecture.

[0126] As shown in Figure 7 and Figure 8 , the decoder applying the technical solution of the present disclosure is always superior to the baseline interface in terms of throughput in all improvement sizes. Among them, Figure 7 is the experimental result graph under the experimental conditions that the width of the input bus is 32 and the grouping coefficient is 1 / 96. Figure 8 is the experimental result graph under the experimental conditions that the width of the input bus is 256 and the grouping coefficient is 1 / 12.

[0127] It can be seen that in the second experimental background, the peak throughput of the technical solution of the present disclosure reaches 1.85Gbps.

[0128] This shows that, unlike related art, the input interface implemented by the basic disclosed technical solution no longer limits the timing of the decoder. In addition, due to its low hardware overhead and flexible structure, the technical solution of the present disclosure can be adapted to various decoder architectures.

[0129] It can be understood that the method can be executed by any device, equipment, platform, or device cluster with computing and processing capabilities.

[0130] It should be noted that the methods of one or more embodiments of the present disclosure can be performed by a single device, such as a computer or server. The methods of these embodiments can also be applied in a distributed scenario, performed by multiple devices working together. In such a distributed scenario, one of the multiple devices may only perform one or more steps of the methods of one or more embodiments of the present disclosure, and the multiple devices will interact with each other to complete the described methods.

[0131] It should be noted that the above description is of specific embodiments of the present disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in an order different from that described in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order shown or the sequential order to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0132] Based on the same inventive concept, corresponding to any of the above embodiments and methods, the present disclosure also provides a soft information processing device for LDPC decoders. Figure 2 As shown, the above device includes:

[0133] A first calculation module 11 is configured to map the lifting factor of the input code block to obtain a mapped lifting factor according to the width of the decoder's input bus and the maximum lifting factor allowed by the communication protocol;

[0134] a second calculation module 12 configured to expand the input code block into a rearranged code block according to the mapping lifting factor, wherein the width of the rearranged code block is a multiple of the input bus width;

[0135] The storage module 13 is configured to store the rearranged code blocks into the decoder memory, and each storage only includes data of the same input code block.

[0136] For the convenience of description, the above devices are described as being functionally divided into various modules. Of course, when implementing one or more embodiments of the present disclosure, the functions of each module can be implemented in the same or multiple software and / or hardware.

[0137] The apparatus of the above embodiment is used to implement the corresponding method in the above embodiment and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0138] Figure 9 10 is a schematic diagram showing a more specific hardware structure of an electronic device provided in this embodiment. The device may include: a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040 are communicatively connected to each other within the device via the bus 1050.

[0139] The processor 1010 can be implemented using a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided by the embodiments of the present disclosure.

[0140] The memory 1020 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage devices, dynamic storage devices, etc. The memory 1020 can store an operating system and other application programs. When the technical solutions provided by the embodiments of the present disclosure are implemented through software or firmware, the relevant program codes are stored in the memory 1020 and are called and executed by the processor 1010.

[0141] The input / output interface 1030 is used to connect input / output modules to implement information input and output. The input / output modules can be configured as components within the device (not shown in the figure) or can be externally connected to the device to provide corresponding functions. Input devices may include a keyboard, mouse, touch screen, microphone, various sensors, etc., and output devices may include a display, speaker, vibrator, indicator light, etc.

[0142] The communication interface 1040 is used to connect to a communication module (not shown) to enable communication between the device and other devices. The communication module can communicate via a wired method (such as USB, network cable, etc.) or a wireless method (such as mobile network, WiFi, Bluetooth, etc.).

[0143] The bus 1050 comprises a path for transmitting information between the various components of the device (eg, the processor 1010 , the memory 1020 , the input / output interface 1030 , and the communication interface 1040 ).

[0144] It should be noted that although the above device only shows the processor 1010, the memory 1020, the input / output interface 1030, the communication interface 1040, and the bus 1050, in a specific implementation, the device may also include other components necessary for normal operation. In addition, those skilled in the art will understand that the above device may only include the components necessary to implement the embodiments of the present disclosure, and does not necessarily include all the components shown in the figure.

[0145] The electronic devices of the above embodiments are used to implement the corresponding methods in the above embodiments and have the beneficial effects of the corresponding method embodiments, which will not be described in detail here.

[0146] The computer-readable media of this embodiment include permanent and non-permanent, removable and non-removable media that can be used to store information by any method or technology. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.

[0147] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples. Within the scope of the present disclosure, the technical features of the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of different aspects of one or more embodiments of the present disclosure as described above, which are not provided in detail for the sake of simplicity.

[0148] In addition, to simplify the description and discussion, and so as not to obscure one or more embodiments of the present disclosure, known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided figures. In addition, devices may be shown in the form of block diagrams to avoid obscuring one or more embodiments of the present disclosure, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which one or more embodiments of the present disclosure will be implemented (i.e., these details should be fully within the scope of understanding of those skilled in the art). Where specific details (e.g., circuits) are set forth to describe exemplary embodiments of the present disclosure, it will be apparent to those skilled in the art that one or more embodiments of the present disclosure may be implemented without these specific details or with variations in these specific details. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0149] Although the present disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those skilled in the art based on the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0150] The one or more embodiments of the present disclosure are intended to encompass all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the one or more embodiments of the present disclosure should be included within the scope of protection of the present disclosure.

Claims

1. A soft information processing method for LDPC decoder, characterized in that: include: According to the width of the decoder's input bus and the maximum lifting factor allowed by the communication protocol, the lifting factor of the input code block is mapped to obtain a mapped lifting factor; Expanding the input code block into a rearranged code block according to the mapping lifting factor, wherein the width of the rearranged code block is a multiple of the input bus width; The rearranged code blocks are stored in a decoder memory, each storage only containing data of the same input code block.

2. The method according to claim 1, characterized in that The step of mapping the lifting factor of the input code block to obtain a mapped lifting factor according to the input bus width of the decoder and the maximum lifting factor allowed by the communication protocol includes: Obtaining a grouping coefficient according to a common integer factor of the input bus width and the maximum lifting factor, wherein the grouping coefficient represents a component scale of the lifting factor; The lifting factors are mapped according to the grouping coefficient and the maximum lifting factor to obtain a mapped lifting factor.

3. The method according to claim 2, characterized in that The step of obtaining a grouping coefficient according to the input bus width and the maximum lifting factor includes: Calculating a first set of integer factors of a ratio of the maximum lifting factor bit width to the input bus bit width, and a second set of integer factors of the maximum lifting factor; Taking an intersection of the first set of integer factors and the second set of integer factors to obtain at least one common integer factor; A common integer factor is selected and the reciprocal of the integer factor is used as the grouping coefficient.

4. The method according to claim 3, characterized in that Mapping the lifting factors according to the grouping coefficient and the maximum lifting factor to obtain a mapped lifting factor includes: multiplying the maximum lifting factor by the grouping coefficient to obtain a scaling reference value; Dividing the lifting factor by the scaling reference value and rounding up the result to obtain a quantization multiple; The scaling reference value and the quantization multiple are multiplied to obtain the mapping lifting factor.

5. The method according to claim 1, wherein The step of expanding the input code block into a rearranged code block according to the mapping lifting factor comprises: determining a width of the input code block according to a lifting factor of the input code block; determining a width of the rearranged code block according to the mapping lifting factor; Determining the number of zero-padding bits according to a difference between the width of the rearranged code block and the width of the input code block; According to the number of zero-padding bits, zeros are padded at the end of the input code block to obtain the rearranged code block.

6. The method according to claim 1, characterized in that Storing the rearranged code block into a decoder memory, each storage only containing data of the same input code block, including: In response to determining that the width of the rearranged code block is greater than the width of the input bus, dividing the rearranged code block into a plurality of transmission code blocks, wherein the width of each transmission code block is the same as the width of the input bus; The transmission code block is quantized and stored in the decoder memory, and the data of each rearranged code block occupies a continuous address space in the decoder memory.

7. The method according to claim 6, characterized in that The width of the decoder memory is set to the product of the maximum number of base matrix columns, the maximum lifting factor of the communication protocol and the quantization accuracy.

8. A soft information processing device for LDPC decoder, characterized in that: include: A first calculation module is configured to map the lifting factor of the input code block according to the width of the input bus of the decoder and the maximum lifting factor allowed by the communication protocol to obtain a mapped lifting factor; a second calculation module configured to expand the input code block into a rearranged code block according to the mapping lifting factor, wherein the width of the rearranged code block is a multiple of the input bus width; The storage module is configured to store the rearranged code block into the decoder memory, and each storage only contains data of the same input code block.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executed by the processor, wherein: When the processor executes the computer program, the method according to any one of claims 1 to 7 is implemented.

10. A non-transitory computer-readable storage medium, characterized in that The non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 7.

Images