Clocking circuit, receiver and passive optical communication network system

Abstract

Disclosed are a clock circuit, a receiver and a passive optical communication network system. The clock circuit is applied to a receiver in a passive optical communication network and is configured to adjust a clock frequency of an output clock signal based on a transmission protocol. The clock circuit comprises at least one clock path and a frequency divider. The at least one clock path comprises a first clock path. The first clock path receives a reference clock signal from a first phase-locked loop circuit and a control signal from a clock data recovery circuit, and interpolates a converted signal of the reference clock signal using the reference clock signal to output a multi-phase clock signal. The frequency divider receives the multi-phase clock signal and divides the multi-phase clock signal based on a preset frequency division value, which is determined based on the transmission protocol. The clock circuit can be compatible with a clock fast switching scheme of different PON protocol data rates, thereby improving the adaptability and locking performance of the receiver in burst mode.

Description

Technical Field

[0001] This application relates to the field of passive optical network technology, and more particularly to a clock circuit, a receiver, and a passive optical communication network system. Background Technology

[0002] In Passive Optical Networks (PONs), to meet the needs of different users and services, the industry has proposed various transmission protocols, such as GPON, 10G-EPON, 10G-GPON, and 25G / 50G PON. Existing receivers are typically designed for a specific protocol, and their internal clock and data recovery circuits can only adapt to fixed data rates and burst modes. When the receiver needs to switch to another protocol or a different data rate application scenario, the existing circuitry is incompatible, resulting in the same receiver product being applicable only to a single scenario. If support for other protocols is required, the circuitry must be redesigned or the hardware replaced. This limitation not only increases the research and development and manufacturing costs of the equipment but also restricts the flexible application of the receiver in multi-protocol environments. Summary of the Invention

[0003] In view of this, this application discloses a clock circuit, a receiver, and a passive optical communication network system to provide a fast clock switching scheme that is compatible with the data rates of different PON protocols, thereby improving the receiver's adaptability and locking performance in burst mode.

[0004] In a first aspect, this application discloses a clock circuit applied to a receiver in a passive optical communication network, configured to adjust the clock frequency of the output clock signal based on a transmission protocol. The clock circuit includes at least one clock path and a frequency divider. The at least one clock path includes a first clock path. The first clock path receives a reference clock signal from a first phase-locked loop circuit and a control signal from a clock data recovery circuit, and interpolates the converted signal of the reference clock signal using the reference clock signal to output a multi-phase clock signal. The frequency divider receives the multi-phase clock signal and divides the multi-phase clock signal based on a preset division value, which is determined based on the transmission protocol.

[0005] Optionally, the first clock path includes a first delay phase-locked loop, a phase interpolator, and a second delay phase-locked loop connected in sequence; wherein, the first delay phase-locked loop is used to distribute the reference clock signal into multiple equally spaced phase clock signals, the phase interpolator is used to interpolate the multiple equally spaced phase clock signals according to the control signal and output an adjustable phase clock signal, and the second delay phase-locked loop is used to expand the adjustable phase clock signal into a multi-phase clock signal.

[0006] Optionally, the transmission protocol includes a first type of protocol for implementing a fixed data rate, wherein the preset frequency division value corresponding to the first type of protocol is 1; when the fixed data rate is greater than or equal to a first rate threshold, the multi-phase clock signal samples data in the form of clock interpolation, and the relative ratio of the fixed data rate to the clock frequency is the number of phases of the multi-phase clock signal; when the fixed data rate is less than or equal to a second rate threshold, the relative ratio of the fixed data rate to the clock frequency is 1.

[0007] Optionally, the transmission protocol includes a second type of protocol for enabling switching between at least two different data rates, the at least two different data rates including a first data rate and a second data rate, and the first data rate and the second data rate having a multiple relationship, the preset frequency division value corresponding to the second type of protocol being determined based on the multiple relationship between the first data rate and the second data rate; wherein, the frequency divider is configured to select the corresponding preset frequency division value according to the multiple relationship, so as to output a clock signal corresponding to the first data rate or a clock signal corresponding to the second data rate.

[0008] Optionally, the first data rate is the maximum value among at least two different data rates. The first delay phase-locked loop, the phase interpolator, and the second delay phase-locked loop are configured to operate at the highest clock frequency corresponding to the first data rate. When it is necessary to switch to the second data rate, the frequency divider is controlled to output a clock signal corresponding to the second data rate.

[0009] Optionally, at least one clock path includes a second clock path, and the transmission protocol includes a third type of protocol for switching between at least two different data rates. The at least two different data rates include a third data rate and a fourth data rate, and the third data rate and the fourth data rate are not multiples of each other. The preset frequency division value corresponding to the third type of protocol is 1. The first clock path is configured to process the third data rate, and the second clock path is configured to process the fourth data rate. The second clock path receives a reference clock signal from the second phase-locked loop circuit and a control signal from the clock data recovery circuit. The clock circuit also includes a multiplexer connected to the first clock path and the second clock path and configured to select the corresponding clock frequency output. The second clock path has the same structure as the first clock path, or the second clock path includes a third delay phase-locked loop and a phase interpolator connected in sequence.

[0010] Optionally, each delay phase-locked loop and each phase interpolator is statically configured, while the multiplexer and frequency divider are dynamically configured to enable switching between different data rates.

[0011] Optionally, the clock circuit also includes a step size adjustment circuit, which is disposed in any clock path. The step size adjustment circuit is configured to dynamically adjust the step size of the phase interpolator in each clock path at different data rates so that the lock time at different data rates is kept within a preset range.

[0012] Secondly, this application discloses a receiver for use in a passive optical communication network, including a clock circuit as described in the first aspect above.

[0013] Thirdly, this application discloses a passive optical communication network system, including a receiver as described in the second aspect above.

[0014] In summary, the clock circuit, receiver, and passive optical communication network system disclosed in this application have at least the following beneficial effects:

[0015] (1) By introducing a combination structure of multi-stage delay phase-locked loop and phase interpolator in the clock path, high-precision multi-phase clock output is achieved, which can meet the sampling requirements of high-speed optical communication receivers at different rates.

[0016] (2) By using a frequency divider to dynamically switch under protocols with multiple rate relationships, the repeated locking process is avoided, making rate switching more efficient and significantly reducing clock switching delay in burst communication scenarios;

[0017] (3) By using dual clock paths and multiplexers for output selection under protocols where the rates are not multiples of each other, the circuit can be flexibly switched between different protocols, has strong compatibility, and is suitable for multi-protocol passive optical communication networks.

[0018] (4) By statically configuring the delay phase-locked loop and the phase interpolator, and dynamically configuring the frequency divider and the multiplexer, the complexity of loop reconfiguration during switching is reduced, thereby improving system stability and design scalability.

[0019] (5) By setting a step size adjustment circuit in the clock path, the step size of the phase interpolator can be dynamically adjusted at different data rates, ensuring that a fast locking speed can be achieved even in low-rate application scenarios, thereby maintaining consistent locking performance across the entire rate range. Attached Figure Description

[0020] The accompanying drawings used in the description of the embodiments of this application are briefly introduced below.

[0021] Figure 1 This is a structural example diagram of the analog portion of a receiver for a serializer / deserializer provided in an embodiment of this application.

[0022] Figure 2This is a structural example diagram of a clock circuit provided in an embodiment of this application.

[0023] Figure 3 This is a structural example diagram of another clock circuit provided in an embodiment of this application.

[0024] Figure 4 This is a structural example diagram of another clock circuit provided in the embodiments of this application.

[0025] Figure 5 This is a structural example diagram of another clock circuit provided in the embodiments of this application.

[0026] Figure 6 This is a structural example diagram of another clock circuit provided in the embodiments of this application.

[0027] Figure 7 This application provides a clock circuit rate switching method. Detailed Implementation

[0028] To more clearly illustrate the technical solutions of the embodiments of this application, the specific implementation methods of this application will be described below with reference to the accompanying drawings. The accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without creative effort. Adjustments and improvements made without departing from the concept of this application are all within the protection scope of this application.

[0029] To keep the drawings simple, only the parts related to the corresponding embodiments are shown schematically in each figure, and they do not represent the actual structure of the product. In addition, to make the drawings simple and easy to understand, some parts with the same structure or function are only shown schematically in some figures, and there may actually be more or fewer parts with the same structure or function.

[0030] In this application, unless otherwise expressly specified and limited, ordinal numbers, such as "first," "second," etc., are used only to distinguish and describe related objects, and should not be construed as indicating or implying the relative importance or order between related objects; furthermore, they do not represent the quantity of related objects. "Multiple" includes two or more, and other quantifiers are similar. " / " is used to describe the relationship between related objects, indicating an "or" relationship between them. "And / or" is used to describe the relationship between related objects, including any combination relationship between them, such as "a and / or b" including: "a alone," "b alone," or "a and b." "One or more" or "at least one" of multiple objects refers to any object or any combination of multiple objects, such as "one or more of a1, a2, a3" or "at least one of a1, a2, a3" including: "a1 alone," "a2 alone," "a3 alone," "a1 and a2," "a1 and a3," "a2 and a3," or "a1, a2 and a3."

[0031] In existing communication systems, Passive Optical Networks (PONs) are widely used in access network architectures. PON is a point-to-multipoint fiber optic access technology characterized by the connection between the Optical Line Terminal (OLT) and multiple Optical Network Units (ONUs) via passive optical splitters. This architecture eliminates the need for active components in the distribution path, significantly reducing maintenance costs and improving system stability. PON can be applied to scenarios such as home broadband access, enterprise leased lines, video transmission, and mobile communication base station backhaul. To meet the concurrent needs of multiple users, PON systems employ Time Division Multiplexing (TDM) or Wavelength Division Multiplexing (WDM) to separate the data streams of different users and transmit them to the target ONU.

[0032] In a PON system, the receiver (RX) plays a crucial role at the receiving end. The receiver is used to recover the original electrical data from the optical signal, enabling the data to be correctly processed by subsequent digital logic. Because PON systems often carry uplink data in burst transmissions, the data received by the receiver is broken into multiple short data packets, and these packets from different users may differ in rate and protocol. Since different users may use different rate standards (e.g., some user equipment supports 1.25Gbps, some support 2.5Gbps, or even higher), the data rate received by the OLT receiver may vary each time. To correctly recover the data from each user, the RX must be able to quickly switch its internal clock path and sampling configuration according to the received rate; otherwise, data loss or sampling errors will occur. In other words, the receiver needs to have the ability to complete rate adaptation and circuit switching in a very short time so that burst data can be accurately sampled and recovered.

[0033] In high-speed communication receivers, the serializer / deserializer (SerDes) is one of the core modules. The main function of SerDes is to convert data between the internal parallel data bus and the external high-speed serial link. In the deserializer (RX) section, the received data rate is generally dynamic; for example, in a PON system, the received data rate may range from a minimum of 1.25 Gbps to a maximum of 50 Gbps. Whenever the rate changes, the SerDes receiver needs to quickly reconfigure the clock circuit so that the clock data recovery circuit (CDR) can lock before the preamble arrives; otherwise, burst data loss or sampling errors will occur.

[0034] Current PON protocols mainly include EPON, 10G-EPON, GPON, 10G-GPON, and 25G / 50G-GPON. Among them, EPON only supports a fixed rate of 1.25Gbps, therefore there is no need for rate switching; GPON requires dynamic switching between 1.25Gbps and 2.5Gbps; 10G-EPON requires dynamic switching between 10.3125Gbps and 1.25Gbps; 10G-GPON requires dynamic switching between 2.5Gbps and 10Gbps; and 25G / 50G-GPON needs to support dynamic switching between 12.5Gbps, 25Gbps, and 50Gbps rates. In practical applications, only one protocol is used in any given PON scenario. This is because on a single link, the OLT and all ONUs must adhere to the same protocol standard (e.g., GPON or 10G-EPON); otherwise, the frame structure, rate, and synchronization method will be incompatible, making communication impossible. Therefore, the receiver needs to perform rapid switching within the corresponding rate range for the target protocol.

[0035] However, in existing technologies, PON receivers are designed for only a single protocol. For example, one receiver might only support GPON rate switching between 1.25Gbps and 2.5Gbps, while another might only support 10G-EPON rate switching between 1.25Gbps and 10.3125Gbps. In other words, existing receiver products can only adapt to one protocol and a fixed rate range. If the same product is to be used in different PON protocol environments, the clock circuit and SerDes structure must be redesigned. This not only increases R&D and manufacturing costs but also wastes hardware resources and limits the receiver's flexible deployment capabilities in multi-protocol environments. In simpler terms, because the same SerDes RX chip may be used by different operators and equipment manufacturers—some customers needing GPON OLTs, some needing 10G-EPON OLTs, and some needing 25G-PON OLTs—if this chip could be configured to adapt to multiple protocols simultaneously, it could be used in different application scenarios, greatly improving the chip's versatility and market value.

[0036] To address the clock switching problem in multi-rate burst modes, this application proposes a novel clock circuit architecture. The core concept is to provide a clock circuit architecture compatible with multiple PON protocols, specifically tailored to the application requirements of SerDes receivers in passive optical communication networks under multi-protocol, multi-rate burst modes. This architecture addresses switching scenarios where rates have multiple relationships by introducing a frequency divider after the DLL (Dynamic Transmission Logic). It achieves fast switching when rates are not multiple relationships by adding a parallel clock path and utilizing a multiplexer. Furthermore, it incorporates a step size adjustment circuit in the clock path to dynamically adjust the step size of the phase interpolator according to different data rates. This improves or maintains the switching speed while shortening the CDR (Clock Receiver Lock Time), ultimately achieving unified support and fast switching for the receiver under different protocols and rates.

[0037] The following description is in conjunction with the accompanying drawings.

[0038] Please refer to Figure 1 This diagram illustrates a structural example of the analog portion of a receiver for a serializer / deserializer provided in an embodiment of this application. Figure 1As shown, in this structure, the Clock Data Recovery (CDR) circuit controls the phase of the clock path, which is configured to generate an eight-phase clock signal to sample the input data. In burst transmission mode, the data rate received by the receiver is not fixed but may switch between different rates. Since the data rate range involved covers from a minimum of 1.25Gbps NRZ to a maximum of 50Gbps NRZ, traditional receivers cannot rely on a single clock circuit to simultaneously complete CDR locking and data sampling, thus failing to meet the needs of multi-rate application scenarios.

[0039] Please refer to Figure 2 This illustrates a schematic diagram of a clock circuit provided in an embodiment of this application. Figure 2 As shown, the phase-locked loop (PLL in the diagram) provides the receiver's reference clock signal to the first delay PLL (DLL1 in the diagram) in the clock path to generate a multi-phase clock signal. The clock data recovery circuit (CDR in the diagram) outputs a control signal to the phase interpolator (PI in the diagram) to select the target phase. After receiving the multi-phase clock, the PI outputs the target clock signal according to the control signal and passes it to the second delay PLL (DLL2 in the diagram), which further expands the multi-phase clock to generate the multi-phase clock.

[0040] In this embodiment, the number of phases in the multi-phase clock can be configured according to design requirements, such as 4 phases, 8 phases, 16 phases, etc. For example, this application adopts an 8-phase structure: on the one hand, compared with the 4-phase structure, 8 phases can provide finer phase resolution, thereby improving the accuracy of data sampling and the locking performance of CDR; on the other hand, compared with the 16-phase structure, 8 phases have a better balance in terms of hardware resource consumption, power consumption and circuit complexity, thus reducing design costs while improving accuracy.

[0041] When the data rate is greater than or equal to 10Gbps, the 8-phase clock samples the input data using clock interpolation. In this case, the clock frequency corresponds to one-eighth of the input data rate, thus avoiding the circuit implementation difficulties and power consumption issues caused by sampling at excessively high frequencies. Correspondingly, when the data rate is 1.25Gbps or 2.5Gbps, the clock path can directly extract one clock path to sample the input data. In this case, the clock frequency is the same as the input data rate, ensuring sampling stability in low-rate scenarios while avoiding unnecessary circuit overhead. Therefore, this structure can balance the implementation difficulty in high-rate scenarios with the sampling accuracy in low-rate scenarios, improving the receiver's adaptability in multi-rate burst modes.

[0042] Please refer to Figure 3This illustrates a schematic diagram of another clock circuit provided in an embodiment of this application. Figure 3 As shown, this application discloses a clock circuit applied to a receiver in a passive optical communication network, and configured to adjust the clock frequency of the output clock signal based on a transmission protocol. The clock circuit includes at least one clock path and a frequency divider. The at least one clock path includes a first clock path (i.e., clock path 1 in the figure). The first clock path receives a reference clock signal from a first phase-locked loop circuit and a control signal from a clock data recovery circuit, and interpolates the converted signal of the reference clock signal using the reference clock signal to output a multi-phase clock signal. The frequency divider receives the multi-phase clock signal and divides the multi-phase clock signal based on a preset division value, which is determined based on the transmission protocol.

[0043] In this structure, since there is no need for millisecond or even microsecond-level fast switching between different PON protocols, clock rate conversion can be achieved directly through frequency division. Furthermore, considering the relatively long setup time of the delay-locked loop (DLL), switching before the DLL could lead to excessive convergence delay. Therefore, in this embodiment, the frequency divider is placed after the second DLL. When switching to another rate is required, a lower clock rate is output directly by controlling the frequency divider, thus ensuring the overall switching efficiency and stability of the circuit.

[0044] For example, in 10G-GPON applications, the data rate needs to switch between 10Gbps and 2.5Gbps. The operating clock for 10Gbps is 1.25GHz, and the operating clock for 2.5Gbps is 2.5GHz. Therefore, in this embodiment, DLL1, PI, and DLL2 all operate at 2.5GHz. When a switch to 1.25Gbps is needed, the 2.5GHz output can be divided into 1.25GHz by a frequency divider, thus achieving flexible switching between different rates.

[0045] As can be seen, by introducing a frequency divider after DLL2 in this embodiment, the same clock path can be flexibly adapted to different data rates. This not only avoids the hardware overhead and power consumption problems caused by directly designing multiple independent clock circuits at high rates, but also shortens the lock-in time and improves the receiver's adaptability and overall performance in multi-rate burst modes.

[0046] Please refer to some embodiments of this application. Figure 3The first clock path includes a first delay phase-locked loop, a phase interpolator, and a second delay phase-locked loop connected in sequence; wherein, the first delay phase-locked loop is used to distribute the reference clock signal into multiple equally spaced phase clock signals, the phase interpolator is used to interpolate the multiple equally spaced phase clock signals according to the control signal and output an adjustable phase clock signal, and the second delay phase-locked loop is used to expand the adjustable phase clock signal into a multi-phase clock signal.

[0047] Through the above design, on the one hand, the first delay-locked loop can evenly divide the input reference clock to obtain multiple clock signals with high phase resolution, thus providing a stable phase reference for subsequent phase interpolation; on the other hand, the phase interpolator can flexibly adjust the phase under CDR control, realizing accurate selection of sampling points for input data and improving the system's acquisition and tracking capabilities in multi-rate burst modes. Furthermore, the second delay-locked loop expands the phase-interpolated single clock signal to obtain a multi-phase clock signal covering one clock cycle, thereby significantly improving the uniformity and integrity of the clock phase and enhancing the stability and accuracy of the multi-phase clock in subsequent frequency division or data sampling.

[0048] This hierarchical design allows the circuit to ensure high-speed performance while also allowing for flexible switching at low speeds. It avoids the problems of excessively long lock-in time or insufficient phase accuracy that occur with a single DLL structure when the speed range is large. It also reduces the area and power consumption overhead caused by directly stacking multiple independent circuits, thus providing an efficient and scalable clock generation and management solution for multi-protocol, multi-rate PON receivers.

[0049] Please refer to some embodiments of this application. Figure 3 The transmission protocol includes a first type of protocol for implementing a fixed data rate, with a preset frequency division value of 1 corresponding to the first type of protocol; when the fixed data rate is greater than or equal to the first rate threshold, the multi-phase clock signal samples the data in the form of clock interpolation, and the relative ratio of the fixed data rate to the clock frequency is the number of phases of the multi-phase clock signal; when the fixed data rate is less than or equal to the second rate threshold, the relative ratio of the fixed data rate to the clock frequency is 1.

[0050] The first type of protocol could be EPON, with a fixed data rate of 1.25Gbps, which does not involve rate switching requirements. The first rate threshold can be set to 10Gbps, and the second rate threshold can be set to 2.5Gbps (these two rate thresholds can be used in other embodiments of this application). Since the data rate of EPON is less than the second rate threshold, the ratio of the fixed data rate to the clock frequency is 1, meaning the output clock frequency is 1.25GHz. At this time, the preset division value is 1, meaning the divider does not need to perform division operations, as directly outputting the reference clock at this rate is sufficient to meet the data sampling requirements.

[0051] Furthermore, if other application scenarios belonging to the first type of protocol exist, and their fixed data rate is greater than or equal to the first rate threshold, the multi-phase clock signal will sample the data using clock interpolation, ensuring that the relative ratio of the fixed data rate to the clock frequency equals the number of phases of the multi-phase clock signal. Here, "the relative ratio of the fixed data rate to the clock frequency equals the number of phases of the multi-phase clock signal" can be understood as follows: in 8-phase interpolation, the number of phases is 8, and 10Gbps corresponds to a clock of 1.25GHz, i.e., 10 / 1.25=8; therefore, the number of phases equals the relative ratio. This relative ratio refers to the ratio when the data frequency unit is kept at Gbps and the clock frequency unit is kept at GHz. This method flexibly supports data sampling requirements under different fixed-rate protocols without requiring additional new circuit modules.

[0052] Therefore, the beneficial effects of this design scheme are as follows: for fixed-rate protocols that do not require rate switching, it can simplify the circuit structure, reduce unnecessary frequency division and complex control, thereby reducing power consumption and implementation cost; while for fixed-rate protocols with higher rates, it can improve the sampling accuracy and stability by introducing phase interpolation, thereby achieving a balance between performance and resource overhead while ensuring compatibility.

[0053] Please refer to some embodiments of this application. Figure 3The transmission protocol includes a second type of protocol for enabling switching between at least two different data rates, including a first data rate and a second data rate, wherein the first data rate and the second data rate are in a multiple relationship. A preset frequency division value corresponding to the second type of protocol is determined based on this multiple relationship. The frequency divider is configured to select the corresponding preset frequency division value according to the multiple relationship to output a clock signal corresponding to either the first data rate or the second data rate. Furthermore, if the first data rate is the maximum value among the at least two different data rates, the first delay-locked loop, the phase interpolator, and the second delay-locked loop are configured to operate at the highest clock frequency corresponding to the first data rate. When switching to the second data rate is required, the frequency divider is controlled to output a clock signal corresponding to the second data rate.

[0054] It should be noted that the preset division value for the second type of protocol is determined based on the multiple relationship between the first and second data rates. For example, it refers to a multiple relationship between the final output clock frequencies. For instance, when data switches between 10Gbps and 2.5Gbps, the final output clock frequency switches between 2.5GHz and 1.25GHz. In this case, the preset division value is 0.5, meaning that a 1.25GHz clock frequency can be obtained by dividing the 2.5GHz clock by 0.5. Therefore, the preset division value essentially reflects the proportional relationship between the clock frequencies corresponding to different data rates. By controlling the frequency divider to switch according to this ratio, flexible output of multi-rate clocks can be achieved.

[0055] The second type of protocol can be a PON protocol involving rate switching with multiple relationships. For example, 10G-GPON requires switching between 10Gbps and 2.5Gbps, while 25G / 50G PON requires switching between 12.5Gbps, 25Gbps, and 50Gbps. In some other cases, there may be even more data rate switching. Although the number of rates involved differs, they all essentially fall under the scenario of switching between data rates with multiple relationships. Therefore, for ease of explanation, the following description uses the switching between two rates as an example.

[0056] Based on the above protocol, it can be observed that, except for 10G-EPON, the rates of all other PON protocols have a multiple relationship. Since there is no need for rapid switching between different protocols, this means that clock switching at different rates can be directly achieved through frequency division. Considering the slow establishment speed of the delay phase-locked loop (DLL), this application places the rate switching implementation after DLL2. Figure 3As shown, DLL1, the phase interpolator, and DLL2 are first configured to operate at the highest clock frequency corresponding to both data rates. Then, a frequency divider is inserted after DLL2. This allows for a unified locking reference to be established during circuit initialization, reducing the additional delay caused by relocking at different rates. Simultaneously, during rate switching, only frequency adjustment via the frequency divider is needed, eliminating the need to recalibrate DLL and PI, thus achieving faster rate switching and ensuring the continuity and stability of data reception. Furthermore, this method reduces jitter accumulation in low-speed mode, improves the phase accuracy and consistency of the sampling clock, and optimizes overall system performance.

[0057] When switching to a different data rate is required, the frequency divider can be directly controlled to output the clock frequency needed for the corresponding data rate. For example, in a 10G-GPON scenario, data needs to switch between 10Gbps and 2.5Gbps, where 10Gbps corresponds to a clock frequency of 1.25GHz and 2.5Gbps corresponds to a clock frequency of 2.5GHz. Therefore, DLL1, the phase interpolator, and DLL2 can all operate at a 2.5GHz clock frequency. When it is necessary to operate at 1.25Gbps, simply control the frequency divider to divide the 2.5GHz frequency to 1.25GHz to complete the clock rate switch.

[0058] Therefore, the beneficial effects of this design scheme are as follows: by introducing a frequency divider after DLL2 and controlling it based on the rate multiple relationship, the reliance on re-establishing the DLL loop during rate switching can be avoided, significantly shortening the switching time; at the same time, it achieves compatibility support for multiple rate protocols while ensuring circuit stability. Furthermore, this scheme fully utilizes the multiple relationship between rates, resulting in a simple circuit implementation and clear logic control, which not only improves the flexibility of rate switching but also effectively reduces circuit power consumption and implementation cost.

[0059] Please refer to Figure 4 This illustrates a schematic diagram of another clock circuit provided in an embodiment of this application. For example... Figure 4As shown, at least one clock path includes a second clock path (i.e., clock path 2 in the figure). The transmission protocol includes a third type of protocol for switching between at least two different data rates. The at least two different data rates include a third data rate and a fourth data rate, and there is no multiple relationship between the third data rate and the fourth data rate. The preset frequency division value corresponding to the third type of protocol is 1 (i.e., the frequency divider can not perform frequency division operation when processing the third type of protocol). The second clock path has the same structure as the first clock path (i.e., the second clock path includes a third delay phase-locked loop, a phase interpolator, and a fourth delay phase-locked loop connected in sequence). Their functions can be referred to respectively as the first delay phase-locked loop, phase interpolator and second delay phase-locked loop in the second clock path. The first clock path is configured to process the third data rate, the second clock path is configured to process the fourth data rate, and the second clock path receives the reference clock signal from the second phase-locked loop circuit (i.e. PLL2 in the figure, PLL1 in the figure is the first phase-locked loop circuit, which can be referred to in the above embodiment) and the control signal from the clock data recovery circuit. The clock circuit also includes a multiplexer, which is connected to the first clock path and the second clock path and is configured to select the corresponding clock frequency output.

[0060] For the third type of protocol, a typical application scenario is the 10G-EPON protocol. The data rates of the 10G-EPON protocol are 1.25Gbps and 10.3125Gbps, and there is no multiple relationship between them. Therefore, it is impossible to obtain the required clock by extracting a single phase from the eight phases. Furthermore, since the delay-locked loop (DLL) is a low-speed loop, if the rate switching occurs directly before the DLL, the DLL needs microseconds to relock the eight-phase clock, which cannot meet the fast switching requirements in burst mode. To solve this problem, this application implements, for example... Figure 4 As shown, a second clock path is added to the existing clock path, and a multiplexer is used after DLL2 to enable clock selection at different rates. In this scheme, when a 10G-EPON application scenario exists, both phase-locked loops and two sets of clock paths operate simultaneously, and rate switching is directly completed by the multiplexer, ensuring switching speed. It is important to emphasize that the second clock path is only activated in 10G-EPON application scenarios to avoid additional power consumption.

[0061] In theory, if a PON protocol exists that involves switching between three or more data rates that are not multiples of each other, it can achieve fast switching in burst mode by continuously expanding the loop, that is, by setting more clock paths.

[0062] Furthermore, to achieve compatibility with multiple protocols, the clock circuit in this embodiment has limited frequency locking capability of the CDR, making it difficult to cover the different frequency points required by multiple protocols. Therefore, PLLs under different protocols need to be configured at the corresponding frequency points. For example, for the 10G-EPON protocol, PLL1 is configured at 10.3125GHz, while PLL2 is configured at 10GHz. Based on this design concept, the parameters of the clock path can be mapped under different protocols: including the static configuration of the phase interpolator and DLL, and the dynamic configuration of the multiplexer and frequency divider. The core idea of ​​this scheme is: when a circuit requires fast switching, the rate adjustment is achieved by frequency division before the sampling circuit; when a slow loop is involved, the low-speed loop is locked first before the burst, and the switching is completed through the multiplexer, thereby ensuring compatibility while meeting the rate switching requirements of different protocols. It should be noted that for the 10G-EPON scenario, since there is no multiple relationship between the rate points, there is no need to switch through the frequency divider, and the corresponding frequency divider division ratio remains unchanged, that is, the preset division value is 1.

[0063] The clock circuit scheme in this application has significant advantages. First, by adding a frequency divider or multiplexer after DLL2, fast switching between different rates is achieved, effectively solving the problem of slow low-speed loop locking in burst mode, thus ensuring stable sampling and CDR locking of the receiver under multi-rate data. Second, by introducing a second clock path, parallel processing of non-multiple-rate data rates is achieved, enabling special protocols such as 10G-EPON to switch quickly without affecting other protocols, avoiding the shortcomings of traditional single-path schemes that cannot adapt to multi-protocol, multi-rate scenarios. It is worth noting that even protocols with multiple-rate relationships, such as 10G-GPON or 25G / 50G-PON, can be adopted. Figure 4 This approach utilizes a dual-path plus multiplexer scheme, where the division ratio of the frequency divider remains unchanged in these cases, still achieving fast switching while simplifying the overall design. Furthermore, this scheme can combine PI step size adjustment and static / dynamic configuration strategies for DLLs and PLLs (these technical features will be explained in subsequent embodiments), balancing lock-in time optimization and frequency compatibility under different protocols, thus improving the receiver's versatility and reliability. In summary, this scheme can achieve unified support for multiple PON protocols while ensuring switching speed, significantly improving the flexibility and performance of receivers in passive optical communication networks.

[0064] Please refer to Figure 6 This illustrates a schematic diagram of another clock circuit provided in an embodiment of this application. For example... Figure 6 As shown, compared to Figure 4In one embodiment, DLL2 after PI in clock path 2 is removed.

[0065] In the above scheme, clock path 2 is only activated in 10G-EPON applications to address its unique non-multiple rate switching requirements. For other protocols such as 1.25G and 2.5G, data is still processed through clock path 1, and one phase is extracted from the eight-phase clock for sampling. In fact, at 1.25G and 2.5G rates, the DLL after PI is not necessary. By removing DLL2, clock path 2 only needs to generate two-phase clocks to meet the sampling requirements. This simplification not only maintains the equivalent sampling effect of the traditional eight-phase extraction scheme but also significantly reduces hardware overhead and power consumption, improving circuit design efficiency and practicality.

[0066] Please refer to Figure 7 This illustrates a clock circuit rate switching method provided in an embodiment of this application. For example... Figure 7 As shown, in some embodiments of this application, each delay phase-locked loop and each phase interpolator are statically configured, while the multiplexer and frequency divider are dynamically configured to achieve switching between different data rates.

[0067] After the burst mode begins, the initial values ​​corresponding to each rate need to be quickly loaded into the circuit to ensure that the CDR can lock in the shortest possible time. This method still uses a loop unrolling approach. When the application scenario is fixed, the static configurations of the DLL and PI are loaded before the system powers on. Upon receiving the rate information, the MUX selects from multiple sets of dynamic configurations and loads the selected configuration into each module. Here, we take configuration 1, configuration 2, and configuration 3 as examples, which correspond to the initial values ​​obtained at different data rates. However, in practice, more rate configurations can be stored and loaded to cope with more complex application scenarios.

[0068] The advantages of this method are as follows: by combining static and dynamic configuration, the switching between different rates can be completed quickly in burst mode, significantly shortening the CDR lock-in time; at the same time, since the static module does not need to be frequently relocked, the loop establishment delay and power consumption are reduced; the combination of loop unrolling and MUX gating enables the receiver to complete rate switching efficiently and stably in multi-protocol and multi-rate application scenarios, improving the accuracy of data sampling and the reliability of the system.

[0069] Please refer to Figure 5 This illustrates a schematic diagram of another clock circuit provided in an embodiment of this application. For example... Figure 5As shown, the clock circuit also includes a step size adjustment circuit (i.e., step size control in the figure). This step size adjustment circuit is located in any clock path and is configured to dynamically adjust the step size of the phase interpolator in each clock path at different data rates, so that the lock-in time at different data rates remains within a preset range. Figure 5 In this implementation, the step size adjustment circuit is located in the second clock path. In some other embodiments, the step size adjustment circuit may also be located in the first clock path, or not located in the clock path at all. However, compared to not locating it in the clock path, placing the step size adjustment circuit in either clock path has significant advantages: on the one hand, it can directly adjust its step size in real time in conjunction with the operating state of the phase interpolator, reducing the delay caused by additional external control paths; on the other hand, it can reduce cross-module signal interaction, improve the flexibility and response speed of adjustment, thereby achieving a faster lock-in time during rate switching.

[0070] While adjusting the clock frequency, the clock path also needs to adjust the step size of the phase interpolator according to different clock frequencies. This is because rate switching is mainly achieved through a frequency divider, which is located at the end of the clock path, and the input clock frequency received by the PI remains constant. If the PI's step size is fixed, the clock output to the sampling circuit will maintain the same phase shift size at high rates even in low-rate scenarios, resulting in excessively slow phase updates. This ultimately leads to a significantly prolonged lockout time for the CDR, failing to meet application requirements.

[0071] For example, in 10Gbps and 1.25Gbps application scenarios, a Unit Interval (UI) at 10Gbps is 100ps, while a UI at 1.25Gbps is 800ps. If the PI step size remains consistent across both rates, the lockout time of the CDR at 1.25Gbps will be approximately eight times longer or more than at 10Gbps, severely impacting the fast recovery performance in burst mode. Therefore, in application scenarios with different protocols, the PI step size needs to be dynamically adjusted based on clock frequency and data rate.

[0072] In one implementation, a default PI step size can be initially determined based on the highest data rate. When the system experiences a rate switch, the step size adjustment circuit dynamically adjusts the PI step size. Taking 10Gbps and 1.25Gbps as examples, if the PI step size at 10Gbps is 0.5ps / step, then the PI step size at 1.25Gbps should be adjusted to 4ps / step, meaning the step sizes should maintain an approximately eight-fold relationship. By integrating the step size switching circuit within the clock path, the control logic of the CDR can be simplified during rate switching, thereby shortening the lockout time and improving the overall performance of the receiver.

[0073] It should be noted that for protocols where the data rates are multiples of each other (such as 10Gbps and 2.5Gbps, or 10Gbps and 1.25Gbps), the switching relationship of the PI step path can be directly determined by the ratio. However, for protocols where the data rates are not strictly multiples of each other (such as 10.3125Gbps and 1.25Gbps in 10G-EPON), an approximate multiple relationship can be used. For example, the ratio of 10.3125Gbps to 1.25Gbps is close to eight times, so the step path can be switched according to an eight-fold relationship during implementation, thus balancing implementation complexity and circuit robustness.

[0074] In summary, this embodiment achieves dynamic adjustment of the PI step size at different data rates by introducing a step size adjustment circuit in the clock path, effectively ensuring that the CDR lock time remains within a preset range when switching between different rates, thereby improving the adaptability and stability of the receiver in multi-protocol and multi-rate burst modes.

[0075] Based on a similar technical concept, this application discloses a receiver for use in passive optical communication networks, including the clock circuit as described in the above embodiments. By introducing the clock circuit in the above embodiments, the receiver can achieve rapid recovery and stable sampling of input data in multi-protocol, multi-rate burst modes. On the one hand, with the help of the frequency divider introduced after the delay phase-locked loop, the receiver can flexibly switch for data rates with multiple relationships; on the other hand, by setting up multiple parallel clock paths and using a multiplexer for control, the receiver can achieve rapid adaptation to scenarios with different rates and no multiple relationship; at the same time, the introduction of the step size adjustment circuit ensures that the step size of the phase interpolator can be dynamically adjusted according to the data rate during rate switching, thereby effectively shortening the lock-in time of the CDR. Thus, the receiver can remain compatible with multiple PON protocols such as EPON, GPON, 10G-EPON, 10G-GPON, and 25G / 50G PON, improving its versatility and stability in different application scenarios.

[0076] Based on a similar technical concept, this application discloses a passive optical communication network system, including a receiver as described in the above embodiments. By configuring the receiver between the optical line terminal (OLT) and the optical network unit (ONU), the system can support data transmission in multiple PON protocols and multi-rate burst modes in practical networking applications. Since the receiver can dynamically adjust the operating state of the clock path and phase interpolator according to different protocols and rates, the entire passive optical communication network system does not require separate receiver modules for different protocols, reducing the complexity and cost of network equipment. Simultaneously, the system can achieve higher compatibility and adaptability in multi-user shared TDM or WDM transmission environments, thereby meeting the future evolution of passive optical communication networks towards high speed and multi-protocol convergence.

[0077] It should be noted that the meanings of the reference numerals in each figure in this application can also be applied to other figures. For example, in Figure 2-6 In the above, all instances of DLL1 refer to the first delay phase-locked loop, and their functions are identical.

[0078] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail or in a particular embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the above embodiments can be freely combined as needed.

Claims

1. A clock circuit, characterized in that, A receiver used in a passive optical communication network is configured to adjust the clock frequency of the output clock signal based on a transmission protocol, including EPON, 10G-EPON, GPON, 10G-GPON and 25G / 50G-GPON, wherein the clock circuit includes at least one clock path and a frequency divider, and the at least one clock path includes a first clock path. The first clock path receives a reference clock signal from the first phase-locked loop circuit and a control signal from the clock data recovery circuit, and uses the reference clock signal to interpolate the converted signal of the reference clock signal to output a multi-phase clock signal. The frequency divider receives the multi-phase clock signal and divides the multi-phase clock signal based on a preset frequency division value, which is determined based on the transmission protocol. The first clock path includes a first delay phase-locked loop, a phase interpolator, and a second delay phase-locked loop connected in sequence. The first delay phase-locked loop is used to distribute the reference clock signal into multiple equally spaced phase clock signals. The phase interpolator is used to interpolate the multiple equally spaced phase clock signals according to the control signal and output an adjustable phase clock signal. The second delay phase-locked loop is used to expand the adjustable phase clock signal into the multi-phase clock signal.

2. The clock circuit according to claim 1, characterized in that, The transmission protocol includes a first type of protocol for implementing a fixed data rate, wherein the preset frequency division value corresponding to the first type of protocol is 1; When the fixed data rate is greater than or equal to the first rate threshold, the multi-phase clock signal samples data in the form of clock interpolation, and the relative ratio of the fixed data rate to the clock frequency is the number of phases of the multi-phase clock signal. When the fixed data rate is less than or equal to the second rate threshold, the relative ratio of the fixed data rate to the clock frequency is 1.

3. The clock circuit according to claim 2, characterized in that, The transmission protocol includes a second type of protocol for implementing switching between at least two different data rates. The at least two different data rates include a first data rate and a second data rate, and there is a multiple relationship between the first data rate and the second data rate. The preset frequency division value corresponding to the second type of protocol is determined based on the multiple relationship between the first data rate and the second data rate. The frequency divider is configured to select a corresponding preset frequency division value according to the multiplication factor relationship, so as to output a clock signal corresponding to the first data rate or a clock signal corresponding to the second data rate.

4. The clock circuit according to claim 3, characterized in that, The first data rate is the maximum value among the at least two different data rates. The first delay phase-locked loop, the phase interpolator, and the second delay phase-locked loop are configured to operate at the highest clock frequency corresponding to the first data rate. When it is necessary to switch to the second data rate, the frequency divider is controlled to output a clock signal corresponding to the second data rate.

5. The clock circuit according to claim 2, characterized in that, The at least one clock path includes a second clock path, and the transmission protocol includes a third type of protocol for implementing the switching between at least two different data rates. The at least two different data rates include a third data rate and a fourth data rate, and there is no multiple relationship between the third data rate and the fourth data rate. The preset frequency division value corresponding to the third type of protocol is 1. The first clock path is configured to process the third data rate, the second clock path is configured to process the fourth data rate, the second clock path receives a reference clock signal from the second phase-locked loop circuit and a control signal from the clock data recovery circuit, and the clock circuit further includes a multiplexer connected to the first clock path and the second clock path and configured to select the corresponding clock frequency output. Furthermore, the second clock path has the same structure as the first clock path, or the second clock path includes a third delay phase-locked loop and a phase interpolator connected in sequence.

6. The clock circuit according to claim 5, characterized in that, Each of the delay phase-locked loops and each of the phase interpolators are statically configured, while the multiplexer and the frequency divider are dynamically configured to enable switching between different data rates.

7. The clock circuit according to any one of claims 1-6, characterized in that, It also includes a step size adjustment circuit, which is disposed in any of the clock paths. The step size adjustment circuit is configured to dynamically adjust the step size of the phase interpolator in each of the clock paths at different data rates, so that the lock time at different data rates is kept within a preset range.

8. A receiver, characterized in that, Applied to passive optical communication networks, including the clock circuit as described in any one of claims 1-7.

9. A passive optical communication network system, characterized in that, Includes the receiver as described in claim 8.

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