Semiconductor device and forming method thereof

Abstract

The invention provides a semiconductor device and a forming method thereof, and belongs to the field of semiconductors. The semiconductor device and the forming method thereof comprise the following steps: providing a substrate, wherein the substrate comprises a first device region and a second device region; forming a back gate on the substrate in the first device region; depositing two-dimensional material layers in the first device region and the second device region respectively to form a first channel of the first device and a second channel of the second device; a source electrode and a drain electrode are formed on the layers where the first channel and the second channel are located respectively; a first top gate of the first device is formed over the first channel, and a second top gate is formed over the second channel. The back gate is arranged below the first channel of the first device, and the voltage of the back gate is changed, so that the type of the first device is converted. Therefore, the two-dimensional material layers made of the same material can be arranged in the first channel and the second channel, so that the purposes of reducing the difficulty of the manufacturing process of the semiconductor device and reducing the cost are achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for forming the same. Background Art

[0002] Two-dimensional materials are materials in which electrons can move freely only in two dimensions, on a non-nanoscale (1-100nm). Research on their application in semiconductor devices is extensive, with field-effect transistors using transition metal sulfides (MoS2, MoSe2, WS2, WSe2, etc.) as channel materials being the mainstream, and achieving considerable research results.

[0003] The architecture of current two-dimensional field-effect transistors is similar to that of traditional planar field-effect transistors. The device is fabricated on a silicon dioxide substrate. The two-dimensional material forms the transistor's channel, and the gate insulating layer is made of HfO2. The gate, source, and drain electrodes are made of other conductive materials that have low contact resistance with the two-dimensional material. For use in CMOS circuits, the transistors must have both N-type and P-type devices.

[0004] Transition metal sulfides in current two-dimensional materials are essentially all n-type. Currently, chemical doping is often used to convert n-type two-dimensional materials into p-type materials, or to use two two-dimensional materials to create n-type and p-type devices separately. Both methods are complex and increase manufacturing costs. The present invention provides a back-gate controlled device structure that can achieve both n-type and p-type devices using the same channel material without doping.

[0005] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art. Summary of the Invention

[0006] An object of the present invention is to provide a semiconductor device and a method for forming the same, so as to solve the problem of complicated semiconductor device manufacturing process caused by depositing different types of material layers on different types of channels.

[0007] In order to solve the above technical problems, the present invention provides a semiconductor device, comprising:

[0008] A first device includes a first channel formed by a first two-dimensional material layer, wherein the layer where the first channel is located is provided with a source and a drain, a first top gate is formed above the first channel, and a back gate is formed below the first channel, and a voltage is applied to the back gate to switch the type of the first device;

[0009] A second device includes a second channel formed by a second two-dimensional material layer, wherein the layer where the second channel is located is provided with a source and a drain, and a second top gate is formed above the second channel;

[0010] The first two-dimensional material layer and the second two-dimensional material layer are made of the same material.

[0011] Preferably, the first two-dimensional material layer is a P-type material or an N-type material.

[0012] Preferably, the first top gate, the back gate and the second top gate are all planar structures.

[0013] Preferably, the first top gate and the back gate are both ridge structures, and the second top gate is a planar structure.

[0014] Preferably, the first top gate, the back gate and the second top gate are all ridge structures.

[0015] Preferably, the structure of the first top gate is the same as that of the back gate.

[0016] Preferably, the structure of the first top gate is different from that of the back gate.

[0017] Based on the same inventive concept, the present invention also provides a method for forming a semiconductor device, comprising:

[0018] Providing a substrate, the substrate comprising a first device region and a second device region;

[0019] forming a back gate on the substrate of the first device region;

[0020] Depositing two-dimensional material layers in the first device region and the second device region respectively to form a first channel of the first device and a second channel of the second device;

[0021] forming a source electrode and a drain electrode on the layers where the first channel and the second channel are located, respectively;

[0022] A first top gate of the first device is formed above the first channel, and a second top gate is formed above the second channel.

[0023] Preferably, the first two-dimensional material layer is a P-type material or an N-type material.

[0024] Preferably, the back gate is a planar structure or a ridge structure.

[0025] Compared with the prior art, the semiconductor device forming method of the present invention has the following advantages:

[0026] The present invention switches the type of the first device by placing a back gate below the first channel of the first device and changing the voltage of the back gate. Therefore, a two-dimensional material layer of the same material can be placed in the first and second channels, thereby reducing the difficulty and cost of semiconductor device manufacturing.

[0027] The semiconductor device provided by the present invention and the semiconductor device forming method provided by the present invention belong to the same inventive concept. Therefore, the semiconductor device provided by the present invention has at least all the advantages of the semiconductor device forming method provided by the present invention, and has the advantages of simple manufacturing process and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 1 is a schematic diagram of a planar structure of a PMOS device in one embodiment of the present invention;

[0029] Figure 2 1 is a schematic diagram of a planar structure of an NMOS device in one embodiment of the present invention;

[0030] Figure 3 is a schematic diagram of a ridge structure of a PMOS device in one embodiment of the present invention;

[0031] Figure 4 is a schematic diagram of a ridge structure of an NMOS device in one embodiment of the present invention;

[0032] Figure 5 is a flow chart of a method for forming a semiconductor device in one embodiment of the present invention;

[0033] In the figure,

[0034] 100-substrate; 200-back gate;

[0035] 110-silicon oxide layer; 120-fin structure;

[0036] 310 - first dielectric layer; 320 - second dielectric layer;

[0037] 410-source; 420-drain;

[0038] 430-first channel; 440-second channel;

[0039] 500-first top grid; 600-second top grid. DETAILED DESCRIPTION

[0040] In order to make the objects, advantages and features of the present invention clearer, the semiconductor device and its formation method proposed in the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to illustrate certain principles of the present invention in the drawings in the specification may also be slightly simplified. The specific design features of the present invention disclosed herein, including, for example, specific dimensions, directions, positions and shapes, will be determined in part by the specific application and use environment. In addition, in the embodiments described below, the same figure mark is sometimes used in common between different drawings to represent the same part or a part with the same function, and its repeated description is omitted. In this specification, similar numbers and letters are used to represent similar items. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0041] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0042] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0043] The core idea of ​​the present invention is to provide a semiconductor device, which can reduce the number of process steps and lower the manufacturing cost during the manufacture of the semiconductor device.

[0044] In order to realize the above idea, the present invention provides a semiconductor device, Figures 1 to 5A disclosed semiconductor device includes: a first device, comprising a first channel 430 formed from a first two-dimensional material layer; a source 410 and a drain 420 are provided in the layer where the first channel 430 resides; a first top gate 500 is formed above the first channel 430; a back gate 200 is formed below the first channel 430; a voltage is applied to the back gate 200 to switch the type of the first device; a second device, comprising a second channel 440 formed from a second two-dimensional material layer; a source 410 and a drain 420 are provided in the layer where the second channel 440 resides; a second top gate 600 is formed above the second channel 440; wherein the first and second two-dimensional material layers are made of the same material.

[0045] In an embodiment, the first device may be an NMOS device, and the second device may be a PMOS device. In another embodiment, the first device may be a PMOS device, and the second device may be an NMOS device. In another embodiment, the first device is a first PMOS device, and the second device is a second PMOS device. In another embodiment, the first device is a first NMOS device, and the second device is a second NMOS device. The following explanation will be given by taking the case where the first device is a PMOS device and the second device is an NMOS device as an example.

[0046] Specifically, refer to Figure 1 and Figure 2 As shown, as an example, the first top gate 500, the back gate 200, and the second top gate 600 are all planar structures. That is, both the PMOS device and the NMOS device are planar structures. The PMOS device includes a substrate 100. A back gate 200 is formed on the substrate 100. A first dielectric layer 310 is formed on the surface of the back gate 200. A source 410 and a drain 420 are formed on the surface of the first dielectric layer 310. A first channel 430 is provided between the source 410 and the drain 420. The first channel 430 is formed using a first two-dimensional material layer. A first top gate 500 is formed above the first channel 430. A second dielectric layer 320 is further provided between the first top gate 500 and the first channel 430. The first top gate 500 can be a polysilicon layer, a metal layer, or other top gate structures. The metal layer can be a single metal layer or multiple metal layers. The specific structure of the first top gate 500 is not specified herein.

[0047] The NMOS device includes a substrate 100, a first dielectric layer 310 formed on the surface of the substrate 100, and a source 410 and a drain 420 formed on the surface of the first dielectric layer 310. A second channel 440 is provided between the source 410 and the drain 420. The second channel 440 is formed using a second two-dimensional material layer, and a second top gate 600 is formed above the second channel 440. A second dielectric layer 320 is provided between the second top gate 600 and the second channel 440. The second top gate 600 can be a polysilicon layer, a metal layer, or a top gate of other structural types. The metal layer can be a single metal layer or a multi-layer metal layer. The specific structural type of the second top gate is not specifically required herein.

[0048] The first two-dimensional material layer and the second two-dimensional material layer are made of the same material. The materials of the first two-dimensional material layer and the second two-dimensional material layer can be either P-type materials or N-type materials. For example, the first two-dimensional material and the second two-dimensional material can be two-dimensional materials such as MoS2, WSe2, MoSe2, WS2, WSe2, PdS2, GeSe, Ag2N6, S6Zr2, WSe2, Hgl2, BiTel, and ZrCl2. In this embodiment, the material of the first two-dimensional material layer and the second two-dimensional material layer is preferably MoS2. When the materials of the first two-dimensional material layer and the second two-dimensional material layer are both MoS2, the first channel 430 and the second channel 440 are both N-type.

[0049] The substrate 100 may be made of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, or may be silicon-on-insulator (SiO2) or germanium-on-insulator (GeO2). Alternatively, it may be made of other materials, such as III-V compounds such as gallium arsenide. In this embodiment, the substrate 100 is made of silicon dioxide. The first dielectric layer 310 and the second dielectric layer 320 serve as an isolation layer. The materials of the first dielectric layer 310 and the second dielectric layer 320 may be insulating materials such as silicon dioxide, silicon nitride, or a high-k material. In this embodiment, the first dielectric layer 310 and the second dielectric layer 320 preferably use a high-k material as an insulating layer.

[0050] The back gate 200 can be a metal layer, a polysilicon layer, or other gate structure layer. The structure of the back gate 200 can be the same as or different from the first and second top gates 500 and 600. For example, the back gate 200, the first and second top gates 500 and 600 can all be metal layers. In another example, the back gate 200 can be a metal layer, while the first and second top gates 500 and 600 can be polysilicon layers. In this embodiment, when a voltage is applied to the back gate 200, the NMOS device can be converted into an enhancement-mode MOSFET, converting the NMOS device into a PMOS device. When the back gate 200 is grounded, that is, when the voltage applied to the back gate 200 is zero, the first device remains an NMOS device. Therefore, by providing a hidden back gate 200 in the NMOS device and applying a voltage to the back gate 200, the type of the first device can be changed. During device manufacturing, the channels of the first and second devices can be made of the same material, thereby reducing device manufacturing difficulty and cost.

[0051] Specifically, refer to Figure 2 and Figure 3 As another example, the first top gate 500 and the back gate 200 are ridge structures, and the second top gate 600 is a planar structure. Figure 3 The ridge structure shown in FIG. Figure 2 The planar structure shown. The PMOS device includes a substrate 100. A back gate 200 is formed on the substrate 100. The surface of the back gate 200 is coated with a silicon oxide layer 110 as a dielectric layer. A source 410 and a drain 420 are formed on the surface of the silicon oxide layer 110. A first channel 430 is wrapped around the periphery of the silicon oxide layer 110, and the first channel 430 is formed using a first two-dimensional material layer. A first top gate 500 is formed above the first channel 430. A second dielectric layer 320 is also provided between the first top gate 500 and the first channel 430. The first top gate 500 can be a polysilicon layer, a metal layer, or a top gate of other structural types. The metal layer can be a single metal layer or a multi-layer metal layer. No specific requirements are made herein for the specific structural type of the first top gate 500.

[0052] The NMOS device has a planar structure and is the same as the planar structure described above, so it will not be described in detail here.

[0053] Specifically, refer to Figure 3 and Figure 4As another example, the first top gate 500, the back gate 200, and the second top gate 600 are all ridge structures. That is, both the PMOS device and the NMOS device are ridge structures. The PMOS device has the same structure as the ridge structure PMOS device described above and will not be described in detail here.

[0054] The NMOS device has a ridge structure. The NMOS device includes a substrate 100. A fin structure 120 is formed on the surface of the substrate 100 as a support layer for the NMOS. The material of the fin structure 120 can be the same as that of the substrate 100, namely silicon dioxide. A second channel 440 is wrapped around the periphery of the fin structure 120, and the second channel 440 is formed using a second two-dimensional material layer. A second top gate 600 is formed above the second channel 430. A second dielectric layer 320 is provided between the second top gate 600 and the second channel 440. The second top gate 600 can be a polysilicon layer, a metal layer, or a top gate of another structural type. The metal layer can be a single metal layer or a multi-layer metal layer. No specific requirements are made herein for the specific structural type of the second top gate 600. Preferably, the first top gate 500 and the second top gate 600 have the same structure.

[0055] Ginseng Figure 1 、 Figure 2 and Figure 5 As shown, for PMOS devices, Figure 1 The planar structure shown in FIG. 1 and the NMOS device is as shown in FIG. Figure 2 The method for manufacturing a planar structure CMOS includes the following steps S11 to S15:

[0056] Step S11 : providing a substrate 100 , wherein the substrate 100 includes a PMOS device region and an NMOS device region. A wafer is provided as the substrate 100 .

[0057] Step S12: A back gate 200 is formed on the substrate 100 in the PMOS device region. After the wafer is cleaned, a back gate region is formed on the surface of the substrate 100 by photolithography and development. Next, a groove is formed in the back gate region by dry or wet etching. Taking the back gate 200 as a metal layer as an example, physical vapor deposition (i.e., PVD) or evaporation (i.e., EBE) can be used to fill the groove with metal to form the back gate 200 in the back gate region.

[0058] Step S13: Two-dimensional material is grown in the first and second device regions using chemical vapor deposition. Before depositing the two-dimensional material layer, a layer of high-k material is first deposited on the surface of the back gate 200 as the first dielectric layer 310. Next, photolithography and etching are used to form the NMOS and PMOS channels, respectively.

[0059] Step S14: Form a source electrode and a drain electrode in the layers where the first channel 430 and the second channel 440 are located, respectively. Metal can be deposited in the region where the source 410 is located and the region where the drain 420 is located by physical vapor deposition (i.e., PVD) or evaporation to form metal electrodes in the region where the source 410 of the PMOS and the drain 420 is located and the region where the drain 420 is located. The electrodes are usually two layers from the substrate 100 upwards, including a first layer of metal and a second layer of metal. The first layer of metal is a contact metal of the two-dimensional material layer. The material of the first layer of metal can be Cr, Ti, or Ni. The second layer of metal serves as a conductor. The material of the second layer of metal can be Au or Cu.

[0060] Step S15: A first top gate 500 is formed above the first channel 430, and a second top gate 600 is formed above the second channel 440. Before forming the first top gate 500 and the second top gate 600, a layer of High-K material is first grown as the second dielectric layer 320 by atomic layer deposition (i.e., ALD). The second dielectric layer 320 covers the first channel 430, as well as the source 410 and the drain 420 of the layer where the first channel 430 is located. The second dielectric layer 320 isolates the first top gate 500 from the first channel 430. Similarly, the second dielectric layer 320 covers the second channel 440, as well as the source 410 and the drain 420 of the layer where the second channel 440 is located. The second dielectric layer 320 isolates the second top gate 600 from the second channel 440. Next, the first top gate 500 and the second top gate 600 are patterned on the surface of the second dielectric layer 320 by photolithography and development. Finally, a metal layer may be formed on the surface of the second dielectric layer 320 by physical vapor deposition (ie, PVD) or evaporation (ie, EBE) to form the first top gate 500 and the second top gate 600 .

[0061] Ginseng Figure 2 、 Figure 3 and Figure 5 As shown, for PMOS devices, Figure 3 The ridge structure shown in the figure is as follows: Figure 2 The method for manufacturing a planar structure CMOS includes the following steps S21 to S25:

[0062] Step S21 : providing a substrate 100 , wherein the substrate 100 includes a PMOS device region and an NMOS device region. A wafer is provided as the substrate 100 .

[0063] Step S22: Forming a back gate 200 on the substrate 100 in the first device region. After cleaning the wafer, a back gate metal layer is formed on the surface of the wafer by PVD or electroplating. The back gate metal layer is then patterned and etched to form a ridge structure serving as the back gate 200.

[0064] Step S23: Deposit two-dimensional material layers in the first device region and the second device region, respectively, to form a first channel 430 of the first device and a second channel 440 of the second device. Before depositing the two-dimensional material layer, a silicon oxide layer 110 is first deposited on the surface of the back gate 200 as a dielectric layer for the back gate 200. The silicon oxide layer 110 can be made of the same material as the substrate 100, both being silicon dioxide. Then, chemical vapor deposition (CVD) is used to grow the two-dimensional material layer on the surface of the substrate 100. Finally, photolithography and etching are used to form the NMOS and PMOS channels, respectively.

[0065] Step S24: Form a source electrode and a drain electrode in the layers where the first channel 430 and the second channel 440 are located, respectively. Metal can be deposited in the region where the source 410 is located and the region where the drain 420 is located by physical vapor deposition (i.e., PVD) or evaporation to form metal electrodes in the region where the source 410 of the PMOS and the drain 420 is located and the region where the drain 420 is located. The electrodes are usually two layers from the substrate 100 upwards, including a first layer of metal and a second layer of metal. The first layer of metal is a contact metal of the two-dimensional material layer. The material of the first layer of metal can be Cr, Ti, or Ni. The second layer of metal serves as a conductor. The material of the second layer of metal can be Au or Cu.

[0066] Step S25: A first top gate 500 is formed above the first channel 430, and a second top gate 600 is formed above the second channel 440. Before forming the first top gate 500 and the second top gate 600, a layer of High-K material is first grown as the second dielectric layer 320 by atomic layer deposition (i.e., ALD). The second dielectric layer 320 covers the first channel 430, as well as the source 410 and the drain 420 of the layer where the first channel 430 is located, to isolate the first top gate 500 from the first channel 430. At the same time, the second dielectric layer 320 covers the second channel 440, as well as the source 410 and the drain 420 of the layer where the second channel 440 is located, to isolate the second top gate 600 from the second channel 440. Then, the first top gate 500 and the second top gate 600 are patterned on the surface of the second dielectric layer 320 by photolithography and development. Finally, a metal layer may be formed on the surface of the second dielectric layer 320 by PVD or EBE deposition to form the first top gate 500 and the second top gate 600 .

[0067] Ginseng Figure 3 、 Figure 4 and Figure 5 As shown, for PMOS devices, Figure 3 The ridge structure shown in FIG. 1 and the NMOS device are as shown in FIG. Figure 4 The method for fabricating a CMOS ridge structure includes the following steps S31 to S35:

[0068] Step S31 : providing a substrate 100 , wherein the substrate 100 includes a PMOS device region and an NMOS device region. A wafer is provided as the substrate 100 .

[0069] Step S32: Forming a back gate 200 on the substrate 100 in the first device region. After cleaning the wafer, a back gate metal layer is formed on the wafer surface by PVD or electroplating. The back gate metal layer is then patterned and etched to form a ridge structure serving as the back gate 200 in the PMOS device region.

[0070] Step S33: Deposit a two-dimensional material layer in the first device region and the second device region respectively to form a first channel 430 of the first device and a second channel 440 of the second device. Before forming the first channel, a layer of silicon oxide is deposited in the PMOS device region and the NMOS device region by plasma enhanced chemical vapor deposition (i.e., PECVD). The silicon oxide layer 110 in the PMOS device region serves as a dielectric layer on the surface of the back gate 200. The silicon oxide layer deposited in the NMOS device region is etched to form a fin structure 120, which serves as a support layer for NMOS. The silicon oxide layer 110 can be the same material as the substrate 100, that is, silicon dioxide. Pattern the channel regions of PMOS and NMOS. Then, chemical vapor deposition CVD is used to grow a two-dimensional material layer on the surface of the substrate 100. Finally, photolithography and etching are used to form the channels of NMOS and PMOS, respectively.

[0071] Step S34: Form a source electrode and a drain electrode in the layers where the first channel 430 and the second channel 440 are located, respectively. Metal can be deposited in the region where the source 410 is located and the region where the drain 420 is located by physical vapor deposition (i.e., PVD) or magnetron sputtering deposition (i.e., EBE) to form metal electrodes in the region where the source 410 of the PMOS and the drain 420 is located and the region where the drain 420 is located. The electrodes are usually two layers from the substrate 100 upwards, including a first layer of metal and a second layer of metal. The first layer of metal is a contact metal of the two-dimensional material layer. The material of the first layer of metal can be Cr, Ti, or Ni. The second layer of metal serves as a conductor. The material of the second layer of metal can be Au or Cu.

[0072] Step S35: A first top gate 500 is formed above the first channel 430, and a second top gate 600 is formed above the second channel 440. Before executing step S34, a layer of High-K material is grown by atomic layer deposition (i.e., ALD) as the second dielectric layer 320. The second dielectric layer 320 covers the surface of the first two-dimensional material layer and the second two-dimensional material layer. Then, a metal layer can be deposited on the surface of the second dielectric layer 320 by ALD deposition to form the first top gate 500 above the first channel 430 and the second top gate 600 above the second channel 440.

[0073] In this embodiment, by forming a back gate 200 on the substrate 100, the first two-dimensional material layer forming the first channel 430 and the second two-dimensional material layer forming the second channel 440 are made of the same material. This allows the first channel 430 of the PMOS device and the second channel 440 of the NMOS device to be formed simultaneously when manufacturing the PMOS device and the NMOS device. This reduces the process difficulty and cost of semiconductor device manufacturing.

[0074] When in use, when a voltage is applied to the back gate 200, the type of the NMOS device can be changed and the NMOS device can be converted into a PMOS device. When the voltage applied to the back gate 200 is 0, that is, when no voltage is applied to the back gate 200, the type conversion of the NMOS device is not performed.

[0075] In summary, the above embodiments provide detailed descriptions of different configurations of semiconductor devices and methods for forming the same. Of course, the above descriptions are only descriptions of preferred embodiments of the present invention, and are not limitations on the scope of the present invention. The present invention includes but is not limited to the configurations listed in the above embodiments. Those skilled in the art can draw inferences based on the contents of the above embodiments. Any changes or modifications made by those of ordinary skill in the field of the present invention based on the above disclosures shall fall within the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: A first device includes a first channel formed by a first two-dimensional material layer, wherein the layer where the first channel is located is provided with a source and a drain, a first top gate is formed above the first channel, and a back gate is formed below the first channel, and a voltage is applied to the back gate to switch the type of the first device; A second device includes a second channel formed by a second two-dimensional material layer, wherein the layer where the second channel is located is provided with a source and a drain, and a second top gate is formed above the second channel; The first two-dimensional material layer and the second two-dimensional material layer are made of the same material.

2. The semiconductor device according to claim 1, wherein The first two-dimensional material layer is a P-type material or an N-type material.

3. The semiconductor device according to claim 1, wherein The first top gate, the back gate and the second top gate are all planar structures.

4. The semiconductor device according to claim 1, wherein The first top gate and the back gate are both ridge structures, and the second top gate is a planar structure.

5. The semiconductor device according to claim 1, wherein The first top gate, the back gate and the second top gate are all ridge structures. The semiconductor device according to claim 1 , wherein: The structure of the first top gate is the same as that of the back gate.

7. The semiconductor device according to claim 1, wherein The structure of the first top gate is different from that of the back gate.

8. A method for forming a semiconductor device according to any one of claims 1 to 7, characterized in that: include: Providing a substrate, the substrate comprising a first device region and a second device region; forming a back gate on the substrate of the first device region; Depositing two-dimensional material layers in the first device region and the second device region respectively to form a first channel of the first device and a second channel of the second device; forming a source electrode and a drain electrode on the layers where the first channel and the second channel are located, respectively; A first top gate of the first device is formed above the first channel, and a second top gate is formed above the second channel.

9. The method for forming a semiconductor device according to claim 8, wherein: The first two-dimensional material layer is a P-type material or an N-type material.

10. The method for forming a semiconductor device according to claim 9, wherein: The back gate is a planar structure or a ridge structure.

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