Preparation method of hard mask of semiconductor device

Abstract

The invention provides a preparation method of a semiconductor device hard mask, and relates to the technical field of semiconductors. The preparation method comprises the steps that a stacked structure is provided, the stacked structure comprises a magnetic tunnel junction film layer, a first hard mask layer and a second hard mask layer which are sequentially stacked from bottom to top, and the first hard mask layer is made of a metal nitride material; in the main etching step, the patterned second hard mask layer serves as a mask layer, the first hard mask layer is etched to be patterned, and process gas comprises chlorine-containing gas and boron-containing gas. According to the preparation method, the steepness and precision of the second pattern opening formed by etching can be improved, and the effective height of the hard mask is ensured, so that the precision of the target pattern transmitted to the magnetic tunnel junction film layer is ensured, the morphology precision of the MTJ is improved, further miniaturization of the MTJ is facilitated, and the integration level of the MTJ is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a hard mask of a semiconductor device. Background Art

[0002] Magnetic Random Access Memory (MRAM) is a semiconductor device that stores data in the form of magnetic field polarization. It combines the high-speed read and write capabilities of Static Random Access Memory (SRAM) with the high integration of Dynamic Random Access Memory (DRAM). It can be rewritten virtually unlimited times and can be used in systems that require fast, large-scale data storage, data retention after power outages, and rapid recovery.

[0003] The basic structure of an MRAM memory cell is a magnetic tunnel junction (MTJ), which consists of a free layer, a tunnel insulator gate layer, and a fixed layer, from top to bottom. The magnetic field polarization direction of the free layer is variable, while the magnetic field direction of the fixed layer is fixed. The morphological accuracy of the MTJ directly affects the storage performance of the MRAM. In related technologies, a double-layer film structure of a heavy metal and a dielectric layer is generally used as a hard mask for etching the MTJ. However, the high amount of deposits generated during the hard mask patterning process results in poor steepness of the pattern opening formed by the hard mask. This not only affects the tunnel magnetic resistance (TMR) performance and lifespan of the MTJ, but is also detrimental to subsequent process steps and leads to low survival rate of semiconductor devices. Furthermore, the high amount of deposits significantly hinders the etching rate, resulting in prolonged etching time and excessive consumption of the hard mask, which may lead to the risk of short circuits between the subsequent MRAM circuit bit lines and the MTJ. Furthermore, further etching of the pattern opening is difficult, which is not conducive to the miniaturization of the MTJ and the improvement of its integration density. Summary of the Invention

[0004] The object of the present invention is to provide a method for preparing a hard mask for a semiconductor device, so as to solve the technical problems in the related art that the steepness of the pattern opening formed by the hard mask is poor and the further etching of the pattern opening is difficult.

[0005] To solve the above problems, the present invention provides a method for preparing a hard mask for a semiconductor device, the method comprising:

[0006] Providing a stacked structure, the stacked structure comprising a magnetic tunnel junction layer, a first hard mask layer, and a second hard mask layer stacked in sequence from bottom to top, wherein the first hard mask layer is a metal nitride material;

[0007] In the main etching step, the patterned second hard mask layer is used as a mask layer to etch the first hard mask layer to pattern it, wherein the process gas includes a chlorine-containing gas and a boron-containing gas.

[0008] Optionally, in the main etching step, the chlorine-containing gas includes Cl2, and the boron-containing gas includes BCl3, wherein the flow ratio of BCl3 to Cl2 is 1:10 to 1:1.

[0009] Optionally, in the main etching step, the flow rate of BCl3 is 20-100 sccm, the flow rate of Cl2 is 100-180 sccm; the chamber pressure is 5-10 mT; the upper electrode power is 400-1000 W, and the lower electrode power is 30-70 W.

[0010] Optionally, the material of the first hard mask layer is TaN or TiN, and the thickness of the first hard mask layer is 100-200 nm.

[0011] Optionally, before the main etching step, the process includes:

[0012] In the first etching step, the second hard mask layer is etched to pattern it using a fluorine-carbon process gas, wherein the fluorine-carbon process gas includes CF4 and CHF3, and the flow ratio of CF4 to CHF3 is 1:0.4 to 1:0.05.

[0013] Optionally, in the first etching step, the flow rate of CF4 is 150-200 sccm, the flow rate of CHF3 is 10-60 sccm; the chamber pressure is 5-10 mT; the upper electrode power is 500-800 W, and the lower electrode power is 50-100 W.

[0014] Optionally, after the first etching step, the method further comprises:

[0015] In the second etching step, byproducts deposited on the second hard mask layer are removed, wherein the process gas includes an oxygen-containing gas.

[0016] Optionally, in the second etching step, the oxygen-containing gas includes O2, and the flow rate of O2 is 150-200 sccm; the chamber pressure is 5-10 mT; the upper electrode power is 1000-1200 W, and the lower electrode power is 0-50 W.

[0017] Optionally, the stacked structure further includes a planarization layer, an anti-reflective coating layer, and a photoresist layer stacked in sequence from bottom to top, wherein the planarization layer is located on the second hard mask layer; and before the first etching step, the second hard mask layer is patterned:

[0018] Using the patterned photoresist layer as a mask layer, etching the anti-reflective coating to pattern it;

[0019] Using the patterned anti-reflective coating as a mask layer, etching the planarization layer to pattern it;

[0020] The patterned anti-reflective coating and the planarization layer are used as mask layers, and the second hard mask layer is etched to be patterned.

[0021] Optionally, the stacked structure further includes an etch-stop layer, the etch-stop layer is located between the magnetic tunnel junction film layer and the first hard mask layer, and the etch-stop layer is a metallic conductive material.

[0022] In the method for preparing a semiconductor device hard mask provided by the present invention, a patterned second hard mask layer is used as a mask layer, and a process gas including a chlorine-containing gas and a boron-containing gas is used to etch the first hard mask layer. During the etching process, the chlorine-containing gas and the boron-containing gas react with the first hard mask layer of the metal nitride material to produce only a single, small amount of boron nitride deposit, wherein a portion of the boron nitride is deposited on the sidewalls of the second pattern opening to form a passivation layer of relatively small thickness. The passivation layer can protect the sidewalls of the second pattern opening to reduce lateral etching loss of the sidewalls during the etching process. As the etching continues, the rate of lateral etching loss of the passivation layer is approximately balanced with the rate of reaction to generate a new passivation layer, thereby ensuring the continuous protection of the passivation layer on the sidewalls and the verticality of the sidewalls, thereby correspondingly improving the steepness and accuracy of the etching to form the second pattern opening, thereby ensuring the accuracy of the target pattern transferred to the magnetic tunnel junction film layer, improving the morphological accuracy of the obtained MTJ, and ensuring the tunnel magnetoresistance (Tunnel Magnetic Resistance). Resistance (TMR), as well as the survival rate of subsequent process steps and semiconductor devices.

[0023] During the etching process, in addition to the portion of boron nitride deposited on the sidewalls of the second pattern opening, another portion of boron nitride is deposited on the bottom wall of the second pattern opening to form a barrier layer of relatively small thickness. The anisotropic process gas can quickly and effectively bombard and remove the barrier layer, and continue to etch downward to continuously deepen the depth of the second pattern opening. The barrier layer of relatively small thickness has less hindrance to the etching rate, thereby ensuring efficient etching, so that the second pattern opening quickly reaches the bottom end of the first hard mask layer, correspondingly shortening the etching time of the first hard mask layer, reducing excessive consumption of the second hard mask layer and the entire hard mask, thereby increasing the effective height of the hard mask, ensuring the effectiveness of the hard mask in the subsequent etching of the magnetic tunnel junction film layer, improving the morphological accuracy of the MTJ, and reducing the risk of short circuit between the circuit bit line and the MTJ of the subsequent MRAM; at the same time, the target pattern can be smoothly and accurately etched and transferred to the first hard mask layer, which is also conducive to further miniaturization of the MTJ and improving its integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in related technologies, the following briefly introduces the drawings required for use in the specific embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 A schematic diagram of a device structure obtained by a method for preparing a magnetic tunnel junction hard mask according to related art provided in an embodiment of the present invention;

[0026] Figures 2A-2C Schematic diagram of device structures in three steps of a method for preparing a hard mask for a semiconductor device according to an embodiment of the present invention;

[0027] Figure 3 An electron microscope image of the hard mask etching morphology obtained according to the method for preparing a hard mask for a semiconductor device provided by an embodiment of the present invention;

[0028] Figure 4 A first flow chart of a method for preparing a hard mask for a semiconductor device according to an embodiment of the present invention;

[0029] Figure 5 This is a second flow chart of the method for preparing a hard mask for a semiconductor device according to an embodiment of the present invention.

[0030] Description of reference numerals:

[0031] 10-stacked structure; 100-magnetic tunnel junction layer; 200-etch stop layer; 300-first hard mask layer; 310-second pattern opening; 400-second hard mask layer; 410-first pattern opening; 500-planarization layer; 600-antireflective coating; 700-Ta-FO byproduct. DETAILED DESCRIPTION

[0032] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0033] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0034] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0035] Figure 1 A schematic diagram of a device structure obtained according to a method for preparing a magnetic tunnel junction hard mask provided in the relevant technology.

[0036] In the related art, a magnetic tunnel junction film layer 100, a first hard mask layer 300 and a second hard mask layer 400 are sequentially formed on a substrate, wherein the first hard mask layer 300 is a Ta film layer, and the second hard mask layer 400 is a SiN film layer. The double-layer structure composed of the Ta film layer and the SiN film layer serves as a hard mask for the magnetic tunnel junction film layer 100, and the patterning process of the hard mask is as follows: the target pattern required for the magnetic tunnel junction is transferred to the SiN film layer by etching, and then the SiN film layer is used as a mask layer, and a mixed gas of CHF3 and O2 is used to etch the Ta film layer, thereby transferring the target pattern to the Ta film layer to form the hard mask required for etching the MTJ.

[0037] However, in the related art, when CHF3 and O2 are used to etch the Ta film layer to form the target pattern, the reaction of CHF3, O2 and Ta will produce a large amount of Ta-FO by-products 700 and carbon polymers. At the same time, O2 will also oxidize the sidewalls of the pattern opening to form a passivation layer. As the etching depth increases, the deposition amount of Ta-FO by-products, carbon polymers and passivation layer on the sidewalls of the pattern opening increases, causing the sidewalls of the pattern opening to extend in a slope from top to bottom. Accordingly, the steepness of the pattern opening finally formed by the Ta film layer is poor, and the corresponding The MTJ obtained by etching the magnetic tunnel junction film layer 100 using a hard mask composed of a SiN film layer and a Ta film layer has poor precision, which not only affects the performance and life of the tunnel magnetoresistance, but is also not conducive to subsequent process steps and results in a low survival rate of semiconductor devices. In addition, the large amount of deposits has a significant impact on the etching rate, resulting in a long etching time and excessive consumption of the hard mask, which leads to the risk of short circuits between the subsequent MRAM circuit bit lines and the MTJ. At the same time, further etching of the Ta film pattern opening is difficult, which is not conducive to the miniaturization of the MTJ and the improvement of its integration.

[0038] This embodiment provides a method for fabricating a hard mask for a semiconductor device. A first hard mask layer 300 and a second hard mask layer 400 made of a metal nitride material are used as hard masks for a magnetic tunnel junction layer 100. The process gases used to etch the first hard mask layer 300 to form a pattern opening include chlorine-containing gas and boron-containing gas. Only a single, small amount of deposits is produced during the etching process. This not only improves the steepness and precision of the pattern opening, thereby ensuring the accuracy of the pattern opening transferred to the magnetic tunnel junction layer 100 and the resulting MTJ, but also enhances the performance and lifespan of the tunnel magnetoresistive resistor (TMR), as well as the survival rate of subsequent processes and semiconductor devices. Furthermore, the small amount of deposits has a minimal impact on the etching rate, shortening the etching time of the first hard mask layer 300 and reducing etching loss of the effective height of the hard mask, thereby reducing the risk of short circuits between the circuit bit lines and the MTJ in subsequent MRAMs. Furthermore, the target pattern is smoothly and accurately transferred, facilitating further miniaturization of the MTJ to increase its integration density. The method for fabricating a hard mask for a semiconductor device provided by the embodiment of the present invention will be further described in detail below with reference to the accompanying drawings.

[0039] Figures 2A-2C Schematic diagram of device structures in three steps of a method for preparing a hard mask for a semiconductor device provided in an embodiment of the present invention. Figure 3 This is an electron microscope image of the hard mask etching morphology obtained by the method for preparing a hard mask for a semiconductor device provided by an embodiment of the present invention. Figure 4 This is a first flow chart of a method for preparing a hard mask for a semiconductor device according to an embodiment of the present invention.

[0040] like Figure 4As shown, an embodiment of the present invention provides a method for preparing a hard mask of a semiconductor device, comprising:

[0041] S402 provides a stacked structure 10 , which includes a magnetic tunnel junction layer 100 , a first hard mask layer 300 , and a second hard mask layer 400 stacked in sequence from bottom to top, wherein the first hard mask layer 300 is made of a metal nitride material.

[0042] The stacked structure 10 is specifically formed on a substrate (not shown in the figure), or the stacked structure 10 includes a substrate located at the bottom of the magnetic tunnel junction film layer 100; the magnetic tunnel junction film layer 100 specifically includes a free layer, a tunnel insulation gate layer and a fixed layer stacked in sequence from bottom to top, and a double film layer composed of a first hard mask layer 300 and a second hard mask layer 400 serves as a hard mask for the magnetic tunnel junction film layer 100, and the first hard mask layer 300 is a metal nitride material.

[0043] In S404 , a main etching step is performed to etch the first hard mask layer 300 to pattern the second hard mask layer 400 using the patterned second hard mask layer 400 as a mask layer, wherein the process gas includes a chlorine-containing gas and a boron-containing gas.

[0044] like Figure 2B As shown, after the target pattern required for MTJ etching is transferred to the second hard mask layer 400 to form a first pattern opening 410, as shown in FIG. Figure 2C As shown, the main etching step is performed to transfer the target pattern to the first hard mask layer 300 to form a second pattern opening 310, thereby obtaining the hard mask required for etching the magnetic tunnel junction film layer 100; specifically, the patterned second hard mask layer 400 is used as a mask layer, and the first hard mask layer 300 is etched using a process gas including a chlorine-containing gas and a boron-containing gas. During the etching process, the chlorine-containing gas and the boron-containing gas react with the first hard mask layer 300 of the nitride metal material to produce only a single, small amount of boron nitride deposit, wherein a portion of the boron nitride is deposited on the sidewall of the second pattern opening 310 to form a passivation layer of a small thickness. The layer can protect the side walls of the second pattern opening 310 to reduce the lateral etching loss of the side walls during the etching process, and as the etching continues, the speed at which the passivation layer is lateral etched away is approximately balanced with the speed at which a new passivation layer is generated by the reaction, thereby ensuring the continuous protection of the passivation layer on the side walls and ensuring the verticality of the side walls, thereby correspondingly improving the steepness and accuracy of etching to form the second pattern opening 310, thereby ensuring the accuracy of the target pattern being transferred to the magnetic tunnel junction film layer 100, improving the morphological accuracy of the obtained MTJ, and ensuring the performance and life of the tunnel magnetoresistance, as well as the survival rate of subsequent process steps and semiconductor devices.

[0045] During the etching process, in addition to the portion of boron nitride deposited on the sidewalls of the second pattern opening 310, another portion of boron nitride is deposited on the bottom wall of the second pattern opening 310 to form a thin barrier layer. The anisotropic process gas can quickly and effectively bombard and remove the barrier layer, and continue to etch downward to continuously deepen the depth of the second pattern opening 310. The thin barrier layer has a small impact on the etching rate, thereby ensuring efficient etching. The second pattern opening 310 quickly reaches the bottom of the first hard mask layer 300, which correspondingly shortens the etching time of the first hard mask layer 300 and reduces excessive consumption of the second hard mask layer 400 and the entire hard mask. In addition, the effective height of the hard mask is increased, ensuring the effectiveness of the hard mask during the subsequent etching of the magnetic tunnel junction film layer 100, improving the morphological accuracy of the MTJ, and reducing the risk of short circuits between the circuit bit line and the MTJ of the subsequent MRAM. At the same time, the target pattern can be smoothly and accurately etched and transferred to the first hard mask layer 300, which is also conducive to further miniaturization of the MTJ and its improved integration.

[0046] This preparation method is suitable for preparing MRAM circuits below 60nm and can achieve precise transfer of target patterns.

[0047] In the embodiment of the present invention, in the main etching step S404 , the chlorine-containing gas includes Cl 2 , and the boron-containing gas includes BCl 3 , wherein the flow ratio of BCl 3 to Cl 2 is 1:10 to 1:1. Cl2 and BCl3 contain a relatively high Cl content. During the etching process, Cl2 and BCl3 can dissociate into sufficient reactive gas Cl to bombard the first hard mask layer 300 and produce gaseous byproducts. These gaseous byproducts can be extracted during the etching process. Simultaneously, B in BCl3 can react with N in the first hard mask layer 300 to form a single, small amount of BN deposits. Some of these BN deposits form a thin, dynamically balanced passivation layer on the sidewalls of the second pattern openings 310, thereby ensuring continuous and effective protection of the sidewalls of the second pattern openings 310, reducing lateral etching loss on the sidewalls and improving the steepness and topography accuracy of the sidewalls. Another portion of the BN deposits forms a thin barrier layer on the bottom wall of the second pattern openings 310. This barrier layer can be quickly removed by the reactive gas Cl, presenting minimal hindrance to the etching rate and ensuring efficient etching of the bottom wall. This ensures smooth etching, effectively shortens etching time, and reduces excessive consumption of the hard mask.

[0048] In the embodiment of the present invention, the process parameters of the main etching step can be specifically: BCl3 flow rate is 20-100 sccm, Cl2 flow rate is 100-180 sccm; chamber pressure is 5-10 mT; upper electrode power is 400-1000 W, and lower electrode power is 30-70 W.

[0049] In the embodiment of the present invention, the material of the first hard mask layer 300 is TaN or TiN, and the thickness of the first hard mask layer 300 is 100 to 200 nm. On the one hand, the material of the first hard mask layer 300 is TaN or TiN. In addition to being used as a mask layer for etching the magnetic tunnel junction film layer 100, the first hard mask layer 300 can also be used as an electrode layer for the subsequently formed MTJ. On the other hand, the material of the second hard mask layer 400 is SiN. The material of the first hard mask layer 300 is TaN or TiN, and the process gas for etching the first hard mask layer 300 is Cl2 and BCl3. The process gas has a great influence on the second hard mask layer 400 and the first hard mask layer 300. The etching selectivity can reach 3 to 7. During the etching of the first hard mask layer 300, the first hard mask layer 300 can be etched quickly while consuming less of the effective height of the second hard mask layer 400, thereby reducing excessive consumption of the hard mask composed of the first hard mask layer 300 and the second hard mask layer 400, ensuring the effectiveness of the hard mask in the subsequent etching of the magnetic tunnel junction film layer 100, improving the morphology accuracy of the target pattern transferred to the MTJ, and reducing the risk of short circuit between the circuit bit line and the MTJ of the subsequent MRAM.

[0050] Wherein, the first hard mask layer 300 is made of TaN material, and when Cl2 and BCl3 are used as process gases in the main etching step, the etching reaction formula is:

[0051] BCl3+Cl2+TaN→BCl x ↑+TaCl4↑+BN.

[0052] The thickness of the magnetic tunnel junction film layer 100 may be 10-14 nm, and the thickness of the second hard mask layer 400 may be 10-15 nm.

[0053] In the embodiment of the present invention, Figures 2A-2C As shown, the stacked structure 10 further includes an etch-stop layer 200, which is located between the magnetic tunnel junction film layer 100 and the first hard mask layer 300. The etch-stop layer 200 is made of a metallic conductive material. On the one hand, the etch-stop layer 200 serves as a stop layer for etching the second pattern opening 310 during the main etching step, so that the second pattern opening 310 stops at the etch-stop layer 200, thereby controlling the depth of the second pattern opening 310 and reducing uncontrollable damage to the magnetic tunnel junction film layer 100 caused by the main etching step. On the other hand, the etch-stop layer 200 is made of a metallic conductive material, and it can serve as an electrode layer for the subsequently formed MTJ, thereby reducing the conductivity requirements of the first hard mask layer 300 and the corresponding reduction in the nitrogen content requirements of the first hard mask layer 300.

[0054] Specifically, the material of the etch stop layer 200 may be Ru or Ir, and the first hard mask layer 300 of the metal nitride material has a high etching selectivity with the etch stop layer 200 ; the thickness of the etch stop layer 200 may be 5-6 nm.

[0055] In the embodiment of the present invention, before the main etching step of step S404, the following steps are included: a first etching step, in which the second hard mask layer 400 is etched and patterned using a fluorocarbon process gas, wherein the fluorocarbon process gas includes CF4 and CHF3, and the flow ratio of CF4 to CHF3 is 1:0.4 to 1:0.05. Before executing the main etching step to etch the first hard mask layer 300, the first etching step is first executed to etch the second hard mask layer 400 to transfer the target pattern to the second hard mask layer 400; a mixed gas of CF4 and CHF3 with relatively low carbon fluorine content is used as a process gas to etch the second hard mask layer 400, and CF4 is used as the main etching gas. CF4 and CHF3 have high activity. During the etching process, sufficient active gas F can be dissociated to etch the second hard mask layer 400, thereby efficiently and accurately etching the second hard mask layer 400, and accurately transferring the target pattern to the second hard mask layer 400, so that it can be patterned efficiently and accurately, correspondingly reducing the etching consumption of the effective height of the second hard mask layer 400, and ensuring the accuracy of transferring the target pattern to the first hard mask layer 300 in the subsequent main etching step.

[0056] Specifically, when the second hard mask layer 400 is made of SiN material and the process gas of the first etching step is CF4 and CHF3, the etching reaction formula is:

[0057] SiN+CF4+CHF3→SiF4↑+CNF+NH↑.

[0058] Among them, SiF4 and NH produced by the reaction are in gaseous state and can be extracted during the etching process; the CNF produced by the reaction can be deposited on the sidewall of the second pattern opening 310 to form a passivation layer to protect it, so as to reduce the lateral etching of the sidewall during the etching process and improve the verticality of the second pattern opening 310; among them, the addition of CHF3 causes N to form NH free radicals without polymer generation, which can promote the etching of SiN.

[0059] In the embodiment of the present invention, the process parameters of the first etching step can be specifically: CF4 flow rate is 150-200 sccm, CHF3 flow rate is 10-60 sccm; chamber pressure is 5-10 mT; upper electrode power is 500-800 W, and lower electrode power is 50-100 W.

[0060] In an embodiment of the present invention, after the first etching step and before the main etching step, a second etching step is performed to remove byproducts deposited on the second hard mask layer 400, wherein the process gas includes an oxygen-containing gas. After the first etching step etches the second hard mask layer 400 and transfers the target pattern to the second hard mask layer 400, the second etching step is continued. Specifically, the process gas including the oxygen-containing gas is used to remove the deposits formed in the first etching step, thereby improving the morphological accuracy of the first pattern openings 410 formed in the second hard mask layer 400. This improves the morphological accuracy of the second pattern openings 310 transferred to the first hard mask layer 300 in the main etching step using the second hard mask layer 400 as a mask layer, thereby improving the morphological accuracy of the target pattern transferred to the MTJ.

[0061] In the embodiment of the present invention, the process parameters of the second etching step may be: the oxygen-containing gas includes O2, the flow rate of O2 is 150-200 sccm; the chamber pressure is 5-10 mT; the upper electrode power is 1000-1200W, and the lower electrode power is 0-50W.

[0062] The reaction formula for removing CNF deposits in the first etching step using O2 is:

[0063] CNF+O2→CO x ↑+COF2↑+NO x ↑.

[0064] In the embodiment of the present invention, Figures 2A-2B As shown, before the first etching step, the second hard mask layer 400 is patterned through the following process steps: the stacked structure 10 also includes a planarization layer 500, an anti-reflective coating layer 600 and a photoresist layer (not shown in the figure) stacked in sequence from bottom to top, wherein the planarization layer 500 is located on the second hard mask layer 400; before the first etching step, the second hard mask layer 400 is patterned: using the patterned photoresist layer as a mask layer, etching the anti-reflective coating layer 600 to pattern it; using the patterned anti-reflective coating layer 600 as a mask layer, etching the planarization layer 500 to pattern it; using the patterned anti-reflective coating layer 600 as a mask layer, etching the second hard mask layer 400 to pattern it.

[0065] Specifically, the anti-reflective coating 600 is a Siarc coating with a thickness of 20 to 40 nm; the planarization layer 500 is a spin-on carbon (SOC) layer with a thickness of 100 to 300 nm; a target pattern is formed on the photoresist layer, and first, the patterned photoresist layer is used as a mask layer, and a mixed gas of CF4 and CHF3 is used as a process gas to etch the anti-reflective coating 600 to transfer the target pattern to the anti-reflective coating 600 to pattern it; continuously, the anti-reflective coating 600 is used as a mask layer to etch the planarization layer 500, and the specific etching process parameters are: a mixed gas of O2 and Cl2 is used as the process gas, wherein the flow rate of O2 is 80 to 120 sccm, and the flow rate of Cl2 is 20 to 60 sccm; the chamber pressure is 5 to 10 mT; the upper electrode power is 300 to 500 W, and the lower electrode power is 100 to 200 W; the etching time can be determined by the endpoint etching capture method. Continuing, a first etching step is performed using the remaining anti-reflective coating 600 and the planarization layer 500 as mask layers to etch the second hard mask layer 400 to form a pattern.

[0066] Among them, Figure 2B As shown, in addition to removing the byproducts formed in the first etching step, the second etching step can also simultaneously remove the remaining SOC layer.

[0067] Figure 5 This is a second flow chart of the method for preparing a hard mask for a semiconductor device according to an embodiment of the present invention.

[0068] like Figure 5 As shown, the preparation method includes:

[0069] S502 provides a magnetic tunnel junction film layer 100 as a substrate, and sequentially forms an etch stop layer 200 , a first hard mask layer 300 , a second hard mask layer 400 , a planarization layer 500 , an anti-reflective coating layer 600 and a patterned photoresist layer on the substrate.

[0070] S504 uses the patterned photoresist layer as a mask layer to etch the anti-reflection coating 600 to pattern it; uses the patterned anti-reflection coating 600 as a mask layer to etch the planarization layer 500 to pattern it.

[0071] S506 performs a first etching step: using the patterned anti-reflective coating 600 and the planarization layer 500 as mask layers, a carbon-fluorine-containing process gas is used to etch the second hard mask layer 400 to pattern it.

[0072] S508 performs a second etching step: uses oxygen-containing gas as a process gas to etch away the remaining SOC layer and byproducts deposited in the second etching step.

[0073] S510 performs main etching step: taking the patterned second hard mask layer 400 as mask layer, etching the first hard mask layer 300 of metal nitride material with chlorine-containing gas and boron-containing gas to make it patterned.

[0074] Thus, a hard mask as shown in Figure 2C and Figure 3 is obtained.

[0075] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for preparing a hard mask for a semiconductor device, characterized in that: The preparation method comprises: A stacked structure (10) is provided, comprising a magnetic tunnel junction film layer (100), a first hard mask layer (300), and a second hard mask layer (400) stacked in sequence from bottom to top, wherein the first hard mask layer (300) is a metal nitride material; In the main etching step, the first hard mask layer (300) is etched to pattern the first hard mask layer (300) using the patterned second hard mask layer (400) as a mask layer, wherein the process gas includes a chlorine-containing gas and a boron-containing gas.

2. The preparation method according to claim 1, characterized in that In the main etching step, the chlorine-containing gas includes Cl2, and the boron-containing gas includes BCl3, wherein the flow ratio of BCl3 to Cl2 is 1:10 to 1:

1.

3. The preparation method according to claim 2, characterized in that In the main etching step, the flow rate of BCl3 is 20-100 sccm, the flow rate of Cl2 is 100-180 sccm; the chamber pressure is 5-10 mT; the upper electrode power is 400-1000 W, and the lower electrode power is 30-70 W.

4. The preparation method according to claim 1, characterized in that The material of the first hard mask layer (300) is TaN or TiN, and the thickness of the first hard mask layer (300) is 100-200 nm.

5. The preparation method according to any one of claims 1 to 4, characterized in that Before the main etching step, the process includes: In a first etching step, a carbon-fluorine process gas is used to etch the second hard mask layer (400) to pattern it. The carbon-fluorine process gas includes CF4 and CHF3, and the flow ratio of CF4 to CHF3 is 1:0.4 to 1:0.

05.

6. The preparation method according to claim 5, characterized in that In the first etching step, the flow rate of CF4 is 150-200 sccm, the flow rate of CHF3 is 10-60 sccm; the chamber pressure is 5-10 mT; the upper electrode power is 500-800 W, and the lower electrode power is 50-100 W.

7. The preparation method according to claim 5, characterized in that After the first etching step, the method further comprises: In the second etching step, byproducts deposited on the second hard mask layer (400) are removed, wherein the process gas includes an oxygen-containing gas.

8. The preparation method according to claim 7, characterized in that In the second etching step, the oxygen-containing gas includes O2, and the flow rate of O2 is 150-200 sccm; the chamber pressure is 5-10 mT; the upper electrode power is 1000-1200 W, and the lower electrode power is 0-50 W.

9. The preparation method according to claim 5, characterized in that The stacked structure (10) further comprises a planarization layer (500), an anti-reflection coating (600) and a photoresist layer stacked in sequence from bottom to top, wherein the planarization layer (500) is located on the second hard mask layer (400); and before the first etching step, the second hard mask layer (400) is patterned: Using the patterned photoresist layer as a mask layer, etching the anti-reflective coating (600) to pattern it; Using the patterned anti-reflective coating (600) as a mask layer, etching the planarization layer (500) to pattern it; The patterned anti-reflective coating (600) and the planarization layer (500) are used as mask layers, and the second hard mask layer (400) is etched to pattern it.

10. The preparation method according to any one of claims 1 to 4, characterized in that: The stacked structure (10) further comprises an etch stop layer (200), the etch stop layer (200) is located between the magnetic tunnel junction film layer (100) and the first hard mask layer (300), and the etch stop layer (200) is a metal conductive material.

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