Magnetic memory and data reading method of magnetic memory

Abstract

The invention provides a magnetic memory and a data reading method of the magnetic memory, and relates to the technical field of semiconductors, and the magnetic memory comprises a read signal generation circuit, a hysteresis comparison circuit and a switch sequence circuit which are electrically connected with one another; the read signal generation circuit comprises a data magnetic storage unit for generating a data signal and a reference magnetic storage unit for generating a reference signal; the read signal generation circuit inputs a data signal into the switch sequential circuit, inputs a reference signal into a first input end of the hysteresis comparison circuit, and determines a hysteresis interval of the hysteresis comparison circuit through the reference signal; the switch sequential circuit is used for resetting the output end of the hysteresis comparison circuit to be a first logic signal before each time of data reading, and inputting a data signal to the second input end of the hysteresis comparison circuit, so that the hysteresis comparison circuit performs hysteresis comparison on the data signal and a hysteresis interval; the output end of the hysteresis comparison circuit outputs a data reading result, and the layout area and the power consumption are reduced by introducing the hysteresis comparison circuit.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a magnetic memory and a method for reading data from the magnetic memory. Background Art

[0002] Magnetoresistive Random Access Memory (MRAM) is a new type of non-volatile memory technology that combines the advantages of traditional magnetic storage and semiconductor technologies. Magnetic storage technology uses the magnetization state of magnetic materials to store information. Each storage cell typically consists of a small magnetic region whose magnetization direction can represent a binary value of "0" or "1." Data is read by detecting the magnetization state of these regions.

[0003] For example, a data branch and two parallel reference branches are set up, the data branch includes a data magnetic storage unit for generating a data signal, each reference branch includes a reference magnetic storage unit, and the two reference magnetic storage units jointly generate a reference signal, so that the data signal and the reference signal are differentially compared to determine the actual stored data, and then the data is read.

[0004] However, since each data magnetic storage unit requires two reference magnetic storage units for storage, which increases the area of ​​the storage array, how to save reference branches to save area when reading data is a problem that needs to be solved urgently. Summary of the Invention

[0005] The present application provides a magnetic storage device and a data reading method for the magnetic storage device. By introducing a hysteresis comparison circuit and a switch timing circuit, the layout area of ​​the reference branch is saved, the power consumption of the reference branch during data reading is reduced, and the accuracy and stability of data reading are improved.

[0006] In a first aspect, the present application provides a magnetic memory, comprising a read signal generating circuit, a hysteresis comparator circuit, and a switch timing circuit electrically connected to each other;

[0007] The read signal generating circuit includes a data magnetic storage unit for generating a data signal and a reference magnetic storage unit for generating a reference signal; the read signal generating circuit inputs the data signal into the switch timing circuit and inputs the reference signal into the first input terminal of the hysteresis comparator circuit to determine the hysteresis interval of the hysteresis comparator circuit through the reference signal;

[0008] The switching timing circuit is used to reset the output end of the hysteresis comparison circuit to the first logic signal before each data reading, and then input the data signal to the second input end of the hysteresis comparison circuit, so that the hysteresis comparison circuit performs a hysteresis comparison on the data signal and the hysteresis interval, so that the output end of the hysteresis comparison circuit outputs the data reading result.

[0009] Optionally, when the reference magnetic storage unit is in a low-resistance state, the reference signal generated by it is a low-resistance reference signal; when the reference magnetic storage unit is in a high-resistance state, the reference signal generated by it is a high-resistance reference signal;

[0010] The hysteresis interval of the hysteresis comparison circuit is determined by a reference signal, including:

[0011] The threshold value of the hysteresis interval is determined by the low-impedance reference signal and the high-impedance reference signal.

[0012] Optionally, the hysteresis comparison circuit performs hysteresis comparison on the data signal and the hysteresis interval, so that the output terminal of the hysteresis comparison circuit outputs the data reading result, including:

[0013] When the data signal is greater than the threshold value, the data reading result is flipped from the first logic signal to the second logic signal; or, when the data signal is less than the threshold value, the data reading result remains the first logic signal;

[0014] The first logic signal and the second logic signal represent opposite logics.

[0015] Optionally, the hysteresis comparison circuit performs hysteresis comparison on the data signal and the hysteresis interval, so that the output terminal of the hysteresis comparison circuit outputs the data reading result, including:

[0016] When the data signal is less than the threshold value, the data reading result is flipped from the first logic signal to the second logic signal; or, when the data signal is greater than the threshold value, the data reading result remains the first logic signal;

[0017] The first logic signal and the second logic signal represent opposite logics.

[0018] Optionally, the switching timing circuit includes a first switching unit and a second switching unit;

[0019] Among them, the first switch unit is electrically connected to the read signal generating circuit and the second input end of the hysteresis comparator circuit; the second switch unit is electrically connected to the second input end of the hysteresis comparator circuit; by controlling the on and off of the first switch unit and the second switch unit, the output end of the hysteresis comparator circuit is controlled to be reset to the first logic signal, or, by controlling the on and off of the first switch unit and the second switch unit, the data signal is controlled to be input into the second input end of the hysteresis comparator circuit.

[0020] Optionally, the read signal generating circuit includes: a reference signal generating module and a data signal generating module;

[0021] Wherein, the reference signal generating module is electrically connected to the first input terminal of the hysteresis comparator circuit, and the reference signal generating module includes at least one reference magnetic storage unit for generating and outputting a reference signal;

[0022] The data signal generating module is electrically connected to the second input terminal of the hysteresis comparison circuit through the switch timing circuit. The data signal generating module includes at least one data magnetic storage unit for generating and outputting a data signal.

[0023] Optionally, the data signal generating module includes a plurality of data magnetic storage units;

[0024] Wherein, the corresponding data signal generated by each data magnetic storage unit is electrically connected to the second input terminal of the hysteresis comparison circuit, so that multiple data signals share the same reference signal.

[0025] It should be noted that each data magnetic storage unit generates a corresponding data signal electrically connected to the hysteresis comparison circuit, which means that each data magnetic storage unit can be electrically connected to the hysteresis comparison circuit through row selection or column selection, so that multiple data magnetic storage units can share the same hysteresis comparison circuit.

[0026] Optionally, the reference magnetic storage unit includes a magnetic tunnel junction, and the magnetic tunnel junction includes a free layer, a barrier layer, and a reference layer stacked in sequence;

[0027] The magnetization directions of the free layer and the reference layer in the reference magnetic storage unit are parallel, or the magnetization directions of the free layer and the reference layer in the reference magnetic storage unit are antiparallel.

[0028] Optionally, when there are multiple data magnetic storage units, reference magnetic storage units, and hysteresis comparison circuits, the data magnetic storage units are arranged in multiple columns in an array, and the reference magnetic storage units are arranged in at least one column in an array;

[0029] Among them, the data signal generated by each row of data magnetic storage cells is input into the second input end of the hysteresis comparator circuit corresponding to each row, and the reference signal generated by each row of reference magnetic storage cells is input into the first input end of the same hysteresis comparator circuit corresponding to each row, so that each row of data magnetic storage cells shares the same reference magnetic storage cell.

[0030] In a second aspect, the present application provides a method for reading data from a magnetic memory, which is applied to the magnetic memory as described in any one of the first aspects; the method comprises:

[0031] Before each data reading, the output terminal of the hysteresis comparison circuit is reset to a first logic signal;

[0032] The data signal is input to the second input terminal of the hysteresis comparison circuit, so that the hysteresis comparison circuit performs hysteresis comparison on the data signal and the hysteresis interval, and the output terminal of the hysteresis comparison circuit outputs the data reading result.

[0033] In summary, the present application provides a magnetic memory and a data reading method for the magnetic memory, wherein the magnetic memory includes a read signal generating circuit, a hysteresis comparison circuit, and a switch timing circuit. The read signal generating circuit includes a data magnetic storage unit and a reference magnetic storage unit. The data magnetic storage unit generates a data signal, the reference magnetic storage unit generates a reference signal, and the hysteresis comparison circuit uses the reference signal to determine a hysteresis interval. To prevent the flip state of the previous data read from affecting the next read, before each data read, the switch timing circuit resets the output of the hysteresis comparison circuit to a first logic signal, and then compares the input data signal with the hysteresis interval determined by the reference signal through the hysteresis characteristics of the hysteresis comparison circuit. Then, based on the result of the hysteresis comparison, the output of the hysteresis comparison circuit generates a data reading result. Since the hysteresis interval is determined by the reference signal, and the hysteresis characteristics of the hysteresis comparison circuit, such as eliminating output oscillation and resisting noise interference, can make the hysteresis interval effectively represent the reference signal generated by the two traditional reference branches. Thus, firstly, when designing the reference signal, only one reference magnetic storage unit in one reference branch is required to realize data reading. Compared with the setting method of two reference magnetic storage units in the traditional two reference branches, the number of reference branches and the number of reference magnetic storage units are reduced. This design significantly reduces the layout area of ​​the magnetic storage. Secondly, the use of the hysteresis comparison circuit leads to a reduction in the number of reference branches, which can reduce the need to generate and maintain multiple reference signals, thereby reducing the demand for power consumption during the data reading process. Thirdly, when reading data, the hysteresis comparison circuit can eliminate output oscillation and anti-noise interference, thereby improving the accuracy and stability of data reading. In addition, the reset operation before each data reading can also ensure the consistency of the initial state of the hysteresis comparison circuit, thereby further improving the accuracy and stability of data reading. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0035] Figure 1 A schematic diagram of an application scenario of a magnetic storage device provided in an embodiment of the present application;

[0036] Figure 2 A schematic structural diagram of a magnetic storage device provided in an embodiment of the present application;

[0037] Figure 3 A schematic diagram of the circuit structure of a hysteresis comparator provided in an embodiment of the present application;

[0038] Figure 4 A schematic diagram of the relationship between a reference voltage, a data voltage, and a hysteresis interval when a reference magnetic storage unit provided in an embodiment of the present application is in a low-resistance state and a hysteresis comparison circuit has a clockwise transmission characteristic curve;

[0039] Figure 5 A schematic diagram of the relationship between a reference voltage, a data voltage, and a hysteresis interval when a reference magnetic storage unit provided in an embodiment of the present application is in a low-resistance state and a hysteresis comparison circuit has a counterclockwise transfer characteristic curve;

[0040] Figure 6 A schematic diagram of the relationship between a reference voltage, a data voltage, and a hysteresis interval when a reference magnetic storage unit provided in an embodiment of the present application is in a high-resistance state and a hysteresis comparison circuit has a clockwise transfer characteristic curve;

[0041] Figure 7 A schematic diagram of the relationship between a reference voltage, a data voltage, and a hysteresis interval when a reference magnetic storage unit provided in an embodiment of the present application is in a high-resistance state and a hysteresis comparison circuit has a counterclockwise transfer characteristic curve;

[0042] Figure 8 A schematic diagram of a mapping relationship between the switch states of a first switch unit and a second switch unit of a magnetic memory and a data reading method flow provided in an embodiment of the present application;

[0043] Figure 9 A schematic diagram of the circuit structure and signal flow of a magnetic memory provided in an embodiment of the present application;

[0044] Figure 10 A schematic diagram of a read signal generating circuit structure and signal flow of a magnetic memory provided in an embodiment of the present application;

[0045] Figure 11 A schematic diagram of a read signal generating circuit structure and signal flow of another magnetic memory provided in an embodiment of the present application;

[0046] Figure 12 A diagram showing the overall architecture of a magnetic storage device according to an embodiment of the present application;

[0047] Figure 13 A flowchart of a data reading method for a magnetic storage device provided in an embodiment of the present application is provided.

[0048] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0049] To facilitate a clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. For example, the first input terminal and the second input terminal are merely used to distinguish different input terminals and do not limit their order. Those skilled in the art will understand that the words "first" and "second" do not limit the quantity or execution order, and the words "first" and "second" do not necessarily mean that they are different.

[0050] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0051] In this application, "at least one" means one or more, and "more" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or plural.

[0052] Magnetic memory has a non-volatile magnetic storage array. When reading data, the magnetic storage array usually relies on a sensitive amplifier to compare the voltage or current of the data bit and the reference bit. The reference voltage generation requires area and power consumption overhead, and different methods have different overheads.

[0053] In one possible implementation, data reading is performed based on a self-reference method. Specifically, a data branch and two parallel reference branches are set. The data branch includes a data magnetic storage unit for generating a data signal. Each reference branch includes a reference magnetic storage unit. The two reference magnetic storage units jointly generate a reference signal. In the data writing phase, two adjacent magnetic storage units can be written into opposite data states, one of which serves as a data bit and the other as a reference bit. When reading data, the actual stored data is determined by comparing the data signals of the two adjacent bits with the reference signals for differential comparison to achieve data reading.

[0054] However, since each data magnetic storage cell requires two reference magnetic storage cells, the area of ​​the storage array is doubled, thereby significantly increasing the area cost.

[0055] In another possible implementation, data reading is performed based on a mutual reference method. Specifically, an average voltage or average current representing the data "1" and "0" is designed in the magnetic storage array, and multiple data bits share the average voltage or average current. When reading data, the stored information is determined by comparing the data of each magnetic storage unit with the average voltage or average current. Since multiple data bits share the same reference, the area cost is reduced.

[0056] However, the process of generating an average voltage or an average current each time data is read increases the power consumption of the magnetic storage array, which is twice that of the self-reference method, so the power consumption of data reading using the mutual-reference method is high.

[0057] Through the above method, it was found that when reading data in a magnetic storage array, it typically relies on a sense amplifier to compare the voltage or current of the data bit with the reference bit. However, generating the reference voltage involves a certain area and power consumption overhead, and current technical solutions have difficulty optimizing both aspects simultaneously.

[0058] In response to the above problems, the present application provides a magnetic memory that introduces a hysteresis comparator circuit and a switch timing circuit, thereby saving the layout area of ​​the reference branch, reducing the power consumption of the reference branch during data reading, and improving the accuracy and stability of data reading.

[0059] It should be noted that the magnetic memory provided in this application can be applied to a variety of application scenarios, including embedded systems, industrial control, automotive electronics, Internet of Things devices, etc. For example, the application in Internet of Things devices is taken as an example. Figure 1 A schematic diagram of an application scenario of a magnetic storage device provided in an embodiment of the present application is shown in FIG. Figure 1As shown, the terminal device 200 reads data through the internal magnetic memory 100, and the magnetic memory 100 includes a read signal generating circuit, a hysteresis comparison circuit and a switch timing circuit.

[0060] When reading data from a data magnetic storage cell in a row, the data magnetic storage cell generates a data signal and inputs the generated data signal into the switching timing circuit. In response, the reference magnetic storage cell corresponding to the row generates a reference signal, which is input into the first input terminal of the hysteresis comparator circuit. The hysteresis interval of the hysteresis comparator circuit is determined by the reference signal.

[0061] It should be noted that the hysteresis interval can be determined by determining the midpoint and width of the hysteresis interval. The midpoint of the hysteresis interval can be determined by a reference signal, while the width of the interval in the hysteresis comparison circuit is determined by the threshold adjustment module in the hysteresis comparison circuit (specifically, by the ratio of the two resistors in the threshold adjustment module). The ratio of the two resistors in the threshold adjustment module is also determined by the reference signal. Therefore, it can be understood that the hysteresis interval is determined by the reference signal.

[0062] Furthermore, the switching timing circuit inputs the data signal to the second input terminal of the hysteresis comparison circuit, so that the hysteresis comparison circuit uses its hysteresis characteristics to compare the input data signal with the hysteresis interval determined by the reference signal. Then, the hysteresis comparison circuit generates and outputs a data reading result based on the result of the hysteresis comparison. This data reading result reflects the state of the data signal relative to the reference signal, thereby realizing data reading.

[0063] It is understandable that the terminal device 200 uses the above method to read data from the data magnetic storage units on different rows or columns, and visually displays the data reading results on the terminal device 200 for the user to view.

[0064] Before the data in the data magnetic storage unit is read, the switching timing circuit resets the output end of the hysteresis comparison circuit to the first logic signal. This step ensures that the hysteresis comparison circuit starts the comparison operation in a known initial state, avoiding interference from the previous data reading.

[0065] It should be noted that the embodiment of the present application does not limit the specific application scenario of the magnetic memory 100, and the above is only an example.

[0066] For example, Figure 2 A schematic diagram of the structure of the magnetic storage device provided in the embodiment of the present application is shown in FIG. Figure 2 As shown, the magnetic memory 100 includes a read signal generating circuit 101, a hysteresis comparator circuit 102 and a switch timing circuit 103 which are electrically connected to each other;

[0067] The read signal generating circuit 101 includes a data magnetic storage unit 11 for generating a data signal and a reference magnetic storage unit 12 for generating a reference signal. The read signal generating circuit 101 inputs the data signal into the switch timing circuit 103 and inputs the reference signal into the first input terminal of the hysteresis comparator circuit 102, so as to determine the hysteresis interval of the hysteresis comparator circuit 102 through the reference signal.

[0068] The switching timing circuit 103 is used to reset the output end of the hysteresis comparison circuit 102 to the first logic signal before each data reading, and then input the data signal to the second input end of the hysteresis comparison circuit 102, so that the hysteresis comparison circuit 102 performs a hysteresis comparison on the data signal and the hysteresis interval, so that the output end of the hysteresis comparison circuit 102 outputs the data reading result.

[0069] The present application provides a magnetic memory 100, which includes a read signal generating circuit 101, a hysteresis comparison circuit 102, and a switching timing circuit 103. The read signal generating circuit 101 includes a data magnetic storage unit 11 and a reference magnetic storage unit 12. The data magnetic storage unit 11 generates a data signal, and the reference magnetic storage unit 12 generates a reference signal. The hysteresis comparison circuit 102 uses the reference signal to determine a hysteresis interval. To prevent the flip state of the previous data read from affecting the next read, before each data read, the switching timing circuit 103 resets the output of the hysteresis comparison circuit 102 to a first logic signal. Then, using the hysteresis characteristics of the hysteresis comparison circuit 102, the input data signal is compared with the hysteresis interval determined by the reference signal. Then, based on the result of the hysteresis comparison, the output of the hysteresis comparison circuit 102 generates a data read result. Because the hysteresis interval is determined by the reference signal, and the hysteresis characteristics of the hysteresis comparison circuit 102, such as eliminating output oscillation and resisting noise interference, can make the hysteresis interval effectively represent the reference signal generated by the two traditional reference branches. Thus, firstly, when designing the reference signal, only one reference magnetic storage unit 12 in one reference branch is required to realize data reading. Compared with the setting method of two reference magnetic storage units in the traditional two reference branches, the number of reference branches and the number of reference magnetic storage units 12 are reduced. This design significantly reduces the layout area of ​​the magnetic memory 100. Secondly, the use of the hysteresis comparison circuit 102 leads to a reduction in the number of reference branches, which can reduce the need to generate and maintain multiple reference signals, thereby reducing the demand for power consumption during the data reading process. Thirdly, when reading data, the hysteresis comparison circuit 102 can eliminate output oscillation and anti-noise interference, thereby improving the accuracy and stability of data reading. In addition, the reset operation before each data reading can also ensure the consistency of the initial state of the hysteresis comparison circuit 102, thereby further improving the accuracy and stability of data reading.

[0070] In the embodiment of the present application, the data signal is used to indicate the data stored in the data magnetic storage unit 11. When the data needs to be read, the data magnetic storage unit 11 will convert the stored data into an electrical signal form and output it as a data signal. The electrical signal can be represented by a data voltage or a data current. The embodiment of the present application does not specifically limit the form of the data signal. It should be noted that in the following embodiments, the data voltage is used as an example for explanation.

[0071] Accordingly, the reference signal is used to determine the hysteresis interval of the hysteresis comparison circuit 102. The hysteresis interval may refer to the threshold range of the hysteresis comparison circuit 102 when performing signal comparison, which determines the sensitivity and threshold range of the comparison. The embodiment of the present application does not specifically limit the method of determining the hysteresis interval based on the reference signal. Optionally, the hysteresis interval may be understood as a window value that lasts for a period of time.

[0072] It is understandable that the reference signal can be represented by a reference voltage or a reference current, and this embodiment of the present application does not specifically limit this.

[0073] It should be noted that before each data reading, the switching timing circuit 103 will reset the output end of the hysteresis comparison circuit 102 to the first logic signal. This reset operation ensures that the hysteresis comparison circuit 102 starts working from a known initial state, avoiding the influence of the previous reading operation on the current operation. Furthermore, after the reset is completed, the switching timing circuit 103 inputs the data signal to the second input end of the hysteresis comparison circuit 102 to provide a data signal to be compared, and then the hysteresis comparison circuit 102 uses its hysteresis characteristics to compare the data signal with the hysteresis interval determined by the reference signal. According to the comparison result, the output end of the hysteresis comparison circuit 102 generates a data reading result, which reflects the state of the data signal relative to the reference signal, thereby realizing data reading.

[0074] Among them, the hysteresis characteristic allows the hysteresis comparison circuit 102 to remain stable for a period of time when the data signal approaches the threshold, thereby reducing misjudgment. Optionally, the hysteresis comparison circuit 102 can be represented by a hysteresis comparator. The embodiment of the present application does not specifically limit the form of expression of the hysteresis comparison circuit 102. The hysteresis comparator is a special type of comparator circuit, which has a hysteresis characteristic and can prevent the output from frequently switching back and forth due to noise or other interference when the input signal approaches the threshold.

[0075] It should be noted that in the present application, the switch timing is set by the switch timing circuit 103 to avoid interference with the last data reading. For example, if the circuit caches the voltage information read previously, it may directly interfere with subsequent readings. The present application disconnects the data path by setting the switch timing between the two readings to avoid interference between the two readings.

[0076] Optionally, the first input terminal can be a non-inverting input terminal or an inverting input terminal. When the first input terminal is a non-inverting input terminal, the second input terminal is an inverting input terminal. When the first input terminal is an inverting input terminal, the second input terminal is a non-inverting input terminal. Therefore, it can be concluded that the hysteresis comparison circuit 102 can be positively connected to the read signal generating circuit 101 or reversely connected to the read signal generating circuit 101. Accordingly, when the hysteresis comparison circuit 102 is positively connected to the read signal generating circuit 101, the hysteresis comparison circuit 102 is reversely connected to the switch timing circuit 103. When the hysteresis comparison circuit 102 is reversely connected to the read signal generating circuit 101, the hysteresis comparison circuit 102 is positively connected to the switch timing circuit 103.

[0077] Taking the hysteresis comparator circuit 102 as an example, Figure 3 A schematic diagram of the circuit structure of the hysteresis comparator provided in an embodiment of the present application is shown in FIG. Figure 3 As shown in A, it is a model diagram of the hysteresis comparator 104, in which the reference voltage Vref and the data voltage Vdata are connected at different positions. Figure 3 As shown in B, it is the positive connection mode of the hysteresis comparator 104. Figure 3 Figure C shows the reverse connection of the hysteresis comparator 104. The forward connection refers to the reference voltage Vref being input to the non-inverting input terminal (usually marked "+") of the hysteresis comparator 104, and the data voltage Vdata being input to the inverting input terminal (usually marked "-") of the hysteresis comparator 104. The reverse connection refers to the reference voltage Vref being input to the inverting input terminal (usually marked "-") of the hysteresis comparator 104, and the data voltage Vdata being input to the non-inverting input terminal (usually marked "+") of the hysteresis comparator.

[0078] The hysteresis comparator 104 includes a comparator 21 and a threshold adjustment module 22. The threshold adjustment module 22 is used to adjust the threshold of the hysteresis interval of the hysteresis comparator 104. The input of the threshold adjustment module 22 serves as the non-inverting input of the hysteresis comparator 104. The output of the threshold adjustment module 22 is electrically connected to the non-inverting input of the comparator 21. The inverting input of the comparator 21 serves as the inverting input of the hysteresis comparator 104. The threshold adjustment module 22 includes a first resistor R1 and a second resistor R2. The first ends of the first resistor R1 and the second resistor R2 are both electrically connected to the non-inverting input of the comparator 21. The second end of the first resistor R1 serves as the input of the threshold adjustment module 22 and also serves as the non-inverting input of the hysteresis comparator 104. The second end of the second resistor R2 is electrically connected to the output of the comparator 21 and also serves as the output of the hysteresis comparator 104.

[0079] In this way, setting the threshold adjustment module 22 in the hysteresis comparator 104 is conducive to more accurately adjusting the hysteresis interval of the hysteresis comparator 104, so that the hysteresis interval threshold can be adjusted and set according to the demand for the reference signal, so that the hysteresis interval can more effectively represent the reference signal, thereby improving reading stability and accuracy.

[0080] In the present application, the data magnetic storage unit 11 and the reference magnetic storage unit 12 generate a data signal and a reference signal, respectively, ensuring the accuracy and stability of the signal. Furthermore, by using the reference signal to set the hysteresis interval, the hysteresis comparison circuit 102 can more accurately judge the state of the data signal, thereby improving the accuracy of data reading. Before each reading, the output end of the hysteresis comparison circuit 102 is reset through the control of the switching timing circuit 103, ensuring the consistency of the initial state of the hysteresis comparison circuit 102, reducing the possibility of misjudgment, avoiding interference with the previous data reading operation, and reducing the need for complex control logic. Furthermore, after the hysteresis comparison circuit 102 is reset, based on the characteristics of the hysteresis comparison circuit 102, the data signal is compared with the hysteresis interval, thereby outputting a stable data reading result.

[0081] Therefore, based on the characteristics of the hysteresis comparator circuit 102, the hysteresis interval can flexibly represent a traditional reference signal. In this way, during the data reading process, by resetting first and then performing the read operation, only one reference magnetic storage unit 12 in one reference branch is required to complete the data reading. Compared with the traditional arrangement of two reference magnetic storage units 12 in two reference branches, the number of reference branches and the number of reference magnetic storage units are reduced, which significantly reduces the layout area of ​​the magnetic memory 100. The reduction in the number of reference branches can reduce the need to generate and maintain multiple reference signals, thereby reducing the power consumption required during the data reading process.

[0082] Optionally, when the reference magnetic storage unit 12 is in a low-resistance state, the reference signal generated by it is a low-resistance reference signal; when the reference magnetic storage unit 12 is in a high-resistance state, the reference signal generated by it is a high-resistance reference signal;

[0083] Determining the hysteresis interval of the hysteresis comparison circuit 102 by using the reference signal includes:

[0084] The threshold value of the hysteresis interval is determined by the low-impedance reference signal and the high-impedance reference signal.

[0085] It should be noted that the hysteresis interval can be determined by determining the midpoint and width of the hysteresis interval. Therefore, the threshold value is jointly determined by the midpoint and width of the hysteresis interval. The midpoint of the interval is determined by the reference signal (for example, the average value of the reference signal is set as the midpoint of the interval), and the width of the interval is determined by the threshold adjustment module 22 in the hysteresis comparison circuit 102 (specifically, it is determined by the ratio of the two resistors in the threshold adjustment module 22), and the ratio of the two resistors in the threshold adjustment module 22 is still determined by the reference signal. Specifically, the ratio of the two resistors in the threshold adjustment module 22 is determined by the low-resistance reference signal and the high-resistance reference signal. Based on this, it can be understood that the threshold value is determined by the low-resistance reference signal and the high-resistance reference signal.

[0086] In the embodiment of the present application, the reference magnetic storage unit 12 includes a magnetic tunnel junction, which includes a free layer, a barrier layer, and a reference layer stacked in sequence. The reference magnetic storage unit 12 also includes a spin-orbit moment layer, which is adjacent to the free layer. The data magnetic storage unit 11 also includes a magnetic tunnel junction, which includes a free layer, a barrier layer, and a reference layer stacked in sequence. The reference magnetic storage unit 12 and the data magnetic storage unit 11 also include a spin-orbit moment layer, which is adjacent to the free layer. When a write current is applied to the spin-orbit moment layer, a spin-orbit moment effect is generated, causing the magnetization direction of the free layer to flip or remain unchanged.

[0087] The low resistance state may refer to the magnetization directions of the free layer and the reference layer of the magnetic tunnel junction being in a parallel state, so that the reference magnetic tunnel junction is in a low resistance state. For example, when the write current passed through the spin-orbit moment layer is less than the critical current threshold, the corresponding resistance of the magnetic tunnel junction is less than the critical threshold, and the low resistance state can be used to represent a logic "0" or "low" signal. The high resistance state may refer to the magnetization directions of the free layer and the reference layer of the magnetic tunnel junction being in an antiparallel state, so that the reference magnetic tunnel junction is in a high resistance state. For example, when the write current passed through the spin-orbit moment layer is greater than the critical current threshold, the corresponding resistance of the magnetic tunnel junction is greater than the critical threshold, and the high resistance state can be used to represent a logic "1" or "high" signal.

[0088] It should be noted that the embodiment of the present application does not specifically limit the setting of the critical threshold value, and the critical threshold value can be set based on the characteristics of the reference magnetic storage unit 12 or the characteristics of the circuit.

[0089] Alternatively, the low-resistance state can be understood as the parallel state, and the high-resistance state can be understood as the anti-parallel state. In magnetic memory, the parallel state typically represents a logical "0" in the memory cell, and the anti-parallel state typically represents the memory cell state opposite to the parallel state, mapped to a logical "1." Alternatively, the parallel state typically represents a logical "1" in the memory cell, and the anti-parallel state typically represents the memory cell state opposite to the parallel state, mapped to a logical "0."

[0090] Optionally, the low-impedance reference signal may be represented by a first voltage Vp, the high-impedance reference signal may be represented by a second voltage Vap, and the threshold value may be represented by Vh, where Vh = (Vp + Vap) / 2. The threshold value Vh may represent either an upper threshold value or a lower threshold value.

[0091] For example, Figure 4 A schematic diagram of the relationship between the reference voltage, the data voltage, and the hysteresis interval when a reference magnetic storage unit is in a low-resistance state and the hysteresis comparator circuit has a clockwise transfer characteristic curve is provided in an embodiment of the present application. Taking the hysteresis comparator 104 having a clockwise transfer characteristic curve as an example, the reference voltage Vref is the first reference voltage Vp as an example. Figure 4 As shown in A, the normal distribution of the reference voltage (or data voltage) generated when the reference magnetic storage unit 12 (or data magnetic storage unit 11) is in the parallel state and the anti-parallel state respectively, the average reference voltage (or average data voltage) in the parallel state is the first voltage Vp, and the average reference voltage (or average data voltage) in the anti-parallel state is the second voltage Vap. Figure 4 As shown in Figure B, the lower threshold value of the hysteresis interval of the hysteresis comparator 104 is Vh1, and the upper threshold value is Vh2. The first voltage Vp is set within the hysteresis interval so that Vh1<Vp<Vh2, and the lower threshold value Vh1 and the upper threshold value Vh2 are symmetrical about the first voltage Vp. The output terminal of the hysteresis comparator 104 is a high level VDD or a low level VSS. Figure 4As shown in C, the hysteresis interval is set between the first voltage Vp and the second voltage Vap, and the threshold value Vh of the hysteresis interval is the upper threshold value Vh2. By adjusting the threshold value adjustment module, Vh = Vh2 = (Vp + Vap) / 2. The normal distribution curves of the reference magnetic storage cell 12 or the data magnetic storage cell 11 in the parallel state are all less than the upper threshold value Vh2, and the normal distribution curves of the reference magnetic storage cell 12 or the data magnetic storage cell 11 in the antiparallel state are all greater than the upper threshold value Vh2. The upper threshold value Vh2 designed as described above can completely distinguish the first voltage Vp and the second voltage Vap of the data magnetic storage cell 11. In other words, by simply comparing the data voltage with the upper threshold value Vh2, it is possible to determine whether the data voltage is the first voltage Vp or the second voltage Vap, thereby reading the data in the data magnetic storage cell 11.

[0092] Optionally, taking the hysteresis comparator 104 as an example, as shown in FIG. Figure 3 As shown, by adjusting the ratio of the first resistor R1 to the second resistor R2 , the threshold value Vh of the hysteresis comparator 104 can be determined such that Vh=(Vp+Vap) / 2.

[0093] Optionally, the first resistor R1 and the second resistor R2 satisfy the following formula:

[0094]

[0095] The reference voltage Vref is set to the first voltage Vp, Vcc is the power supply voltage applied to the hysteresis comparator 104, and Vref is the voltage at the input terminal of the hysteresis comparator 104. As long as the first resistor R1 and the second resistor R2 satisfy the above formula, Vh=(Vp+Vap) / 2 can be satisfied.

[0096] It should be noted that the ratio of the first resistor R1 and the second resistor R2 may not be an integer. The first resistor R1 and the second resistor R2 are respectively composed of multiple small resistors with the same resistance connected in series. Therefore, one or two resistors of the first resistor R1 and the second resistor R2 can be set as fine-tuning resistors to cope with parasitic and process influences.

[0097] It should also be noted that when the reference signal is Vp, the threshold value Vh is the upper threshold value Vh2, and when the reference signal is Vap, the threshold value Vh is the lower threshold value Vh1. In this way, the hysteresis interval determined by the upper threshold value or the lower threshold value can represent a traditional reference signal.

[0098] It should be noted that the hysteresis interval can be determined by determining the midpoint and width of the hysteresis interval. Therefore, the threshold value is jointly determined by the midpoint and width of the hysteresis interval. The midpoint of the interval is determined by the reference signal (for example, the average value of the reference signal is set to the midpoint of the interval), and the interval width is determined by the ratio of the first resistor R1 and the second resistor R2. The ratio of the first resistor R1 to the second resistor R2 is still determined by the reference signal (that is, the low-resistance reference signal and the high-resistance reference signal). Based on this, it can be understood that the threshold value is determined by the low-resistance reference signal and the high-resistance reference signal.

[0099] In addition, during the actual process, if the low-resistance reference signal and the high-resistance reference signal are inconsistent with the design due to process errors, and the threshold value determined based on the ratio of the first resistor R1 and the second resistor R2 cannot meet the reading requirements, the resistance values ​​of the first resistor R1 and the second resistor R2 can be further adjusted according to actual needs so that the ratio of the first resistor R1 and the second resistor R2 meets the threshold value required for actual reading.

[0100] In this way, by clearly defining the low-resistance reference signal and the high-resistance reference signal, the threshold value of the hysteresis interval can be precisely set, thereby improving the accuracy of signal comparison. Moreover, by utilizing the different resistance states of the reference magnetic storage unit 12 to generate the reference signal, only one reference branch is required to achieve effective signal comparison, simplifying the circuit design. Since only one reference branch is required, unnecessary circuit complexity and power consumption are reduced. During data reading, the hysteresis comparison circuit 102 can eliminate output oscillation and resist noise interference, thereby improving the accuracy and stability of data reading. In addition, by adjusting the resistance state of the reference magnetic storage unit 12, the threshold value of the hysteresis interval can also be flexibly changed, allowing the magnetic storage device 100 to adapt to different application requirements.

[0101] Optionally, the hysteresis comparison circuit 102 performs hysteresis comparison on the data signal and the hysteresis interval, so that the output terminal of the hysteresis comparison circuit 102 outputs the data reading result, including:

[0102] When the data signal is greater than the threshold value, the data reading result is flipped from the first logic signal to the second logic signal; or, when the data signal is less than the threshold value, the data reading result remains the first logic signal;

[0103] The first logic signal and the second logic signal represent opposite logics.

[0104] It should be noted that the hysteresis characteristic means that the hysteresis comparison circuit 102 has different thresholds when the signal rises and falls. Therefore, the threshold has an upper threshold and a lower threshold.

[0105] It is understood that the first logic signal and the second logic signal are opposite. For example, the first logic signal can be a high level or a logic "1," while the second logic signal can be a low level or a logic "0." The first logic signal can also be a low level or a logic "0," while the second logic signal can be a high level or a logic "1." The embodiments of the present application do not limit the specific form of the logic signal.

[0106] Optionally, reference magnetic storage cells with different resistance states and / or reference signals in different states may correspond to different data reading results.

[0107] For example, Figure 4 As shown in Figure C, assuming that the hysteresis comparator 104 has a clockwise transfer characteristic curve and the reference voltage Vref is the first voltage Vp, the first logic signal is represented by a high level VDD or a logic "1," the second logic signal is represented by a low level VSS or a logic "0," and the hysteresis interval threshold Vh is the upper threshold Vh2. Therefore, before data is read, the switching timing circuit 103 first sets the output of the hysteresis comparator 104 to a high level VDD, that is, the output of the hysteresis comparator 104 is set to a logic "1," resetting the output to the initial first logic signal. Then, the switching timing circuit 103 sets the second input terminal to the corresponding data voltage Vdata again and compares the data voltage Vdata with the upper threshold value Vh2. If the data voltage Vdata is greater than the upper threshold value Vh2, the output terminal flips from the first logic signal (i.e., high level VDD or logic "1") to the second logic signal (i.e., low level VSS or logic "0"). If the data voltage Vdata is less than the upper threshold value Vh2, the output terminal maintains the first logic signal (i.e., high level VDD or logic "1").

[0108] For example, Figure 5 A schematic diagram of the relationship between the reference voltage, the data voltage and the hysteresis interval when the reference magnetic storage unit provided in the embodiment of the present application is in a low resistance state and the hysteresis comparison circuit has a counterclockwise transmission characteristic curve, as shown in FIG. Figure 5As shown, taking the case where the hysteresis comparator 104 has a counterclockwise transfer characteristic curve and the reference voltage Vref is the first voltage Vp, the first logic signal is represented by a low level VSS or a logic "0", the second logic signal is represented by a high level VDD or a logic "1", and the threshold value Vh of the hysteresis interval is the upper threshold value Vh2. Therefore, before data is read, the switching timing circuit 103 first sets the output of the hysteresis comparator 104 to a low level VSS, that is, the output of the hysteresis comparator 104 is set to a logic "0", resetting the output to the initial first logic signal. Then, the switching timing circuit 103 sets the second input terminal to the corresponding data voltage Vdata again and compares the data voltage Vdata with the upper threshold value Vh2. If the data voltage Vdata is greater than the upper threshold value Vh2, the output terminal flips from the first logic signal (i.e., low level VSS or logic "0") to the second logic signal (i.e., high level VDD or logic "1"). If the data voltage Vdata is less than the upper threshold value Vh2, the output terminal maintains the first logic signal (i.e., low level VSS or logic "0").

[0109] For example, Figure 6 A schematic diagram of the relationship between the reference voltage, the data voltage and the hysteresis interval when the reference magnetic storage unit provided in the embodiment of the present application is in a high-resistance state and the hysteresis comparison circuit has a clockwise transfer characteristic curve, as shown in FIG. Figure 6 As shown, taking the example of a hysteresis comparator 104 having a clockwise transfer characteristic curve and a reference voltage Vref being the second voltage Vap, the first logic signal is represented by a high level VDD or a logic "1," the second logic signal is represented by a low level VSS or a logic "0," and the hysteresis interval threshold Vh is the lower threshold Vh1. Therefore, before data is read, the switching timing circuit 103 first sets the output of the hysteresis comparator 104 to a high level VDD, i.e., the output of the hysteresis comparator 104 is set to a logic "1," resetting the output to the initial first logic signal. Then, the switching timing circuit 103 sets the second input terminal to the corresponding data voltage Vdata again, and compares the data voltage Vdata with the lower threshold value Vh1. If the data voltage Vdata is less than the lower threshold value Vh1, the output terminal maintains the first logic signal (high level VDD or logic "1"). If the data voltage Vdata is greater than the lower threshold value Vh1, the output terminal flips from the first logic signal (i.e., high level VDD or logic "1") to the second logic signal (i.e., low level VSS or logic "0").

[0110] Compared to the existing use of a single threshold comparator, when the input signal has noise near the threshold, such as a small fluctuation, the output signal may frequently flip, resulting in erroneous logical judgment. The present application sets the threshold value, so that the hysteresis comparator circuit 102 has better immunity to small fluctuations and noise of the input data signal. Even if the input data signal has noise fluctuations near the threshold, as long as the noise fluctuation does not exceed the hysteresis interval, the output will not flip incorrectly, thereby improving the noise immunity and avoiding jitter of the output signal, thereby making the output of the hysteresis comparator circuit 102 more stable. In addition, the resistance state of the corresponding reference magnetic storage unit 12 and the transfer characteristic curve of the hysteresis comparator circuit 102 can be adjusted and set according to the corresponding relationship between the required data voltage size and the first logic signal and the second logic signal generated at the output terminal in actual application, thereby improving the flexibility of circuit design.

[0111] Optionally, the hysteresis comparison circuit 102 performs hysteresis comparison on the data signal and the hysteresis interval, so that the output terminal of the hysteresis comparison circuit 102 outputs the data reading result, including:

[0112] When the data signal is less than the threshold value, the data reading result is flipped from the first logic signal to the second logic signal; or, when the data signal is greater than the threshold value, the data reading result remains the first logic signal;

[0113] The first logic signal and the second logic signal represent opposite logics.

[0114] For example, Figure 7 A schematic diagram of the relationship between the reference voltage, the data voltage and the hysteresis interval when the reference magnetic storage unit provided in the embodiment of the present application is in a high-resistance state and the hysteresis comparison circuit has a counterclockwise transmission characteristic curve, as shown in FIG. Figure 7As shown, taking the case where the hysteresis comparator 104 has a counterclockwise transfer characteristic curve and the reference voltage Vref is the second voltage Vap, the first logic signal is represented by a high level VDD or a logic "1", the second logic signal is represented by a low level VSS or a logic "0", and the threshold value Vh of the hysteresis interval is the lower threshold value Vh1. Therefore, before data is read, the switching timing circuit 103 first sets the output of the hysteresis comparator 104 to a high level VDD, that is, the output of the hysteresis comparator 104 is set to a logic "0", resetting the output to the initial first logic signal. Then, the switching timing circuit 103 sets the second input terminal to the corresponding data voltage Vdata again and compares the data voltage Vdata with the lower threshold value Vh1. If the data voltage Vdata is less than the lower threshold value Vh1, the output terminal flips from the first logic signal (i.e., high level VDD or logic "1") to the second logic signal (i.e., low level VSS or logic "0"). If the data voltage Vdata is greater than the lower threshold value Vh1, the output terminal maintains the first logic signal (high level VDD or logic "1").

[0115] It is understandable that if the input signal fluctuates near a single threshold, such as due to noise interference, the existing comparator may frequently flip the output, resulting in a logic error. However, the present application adopts a hysteresis interval. By setting the threshold value, the output will only flip when the data signal is lower than the threshold value. In this way, even if the input signal fluctuates slightly near the threshold value, as long as it does not exceed the hysteresis interval, the output will not flip erroneously, thereby improving the noise resistance and avoiding false triggering caused by noise or small fluctuations. In addition, since the hysteresis characteristic ensures that the output changes the flip state only when the data signal clearly crosses the hysteresis interval, unnecessary flips can be reduced, thereby reducing the overall power consumption of the magnetic memory 100. In addition, the resistance state of the corresponding reference magnetic storage unit 12 and the transfer characteristic curve of the hysteresis comparison circuit 102 can be adjusted and set according to the corresponding relationship between the required data voltage size and the first logic signal and the second logic signal generated at the output end in actual application, thereby improving the flexibility of circuit design.

[0116] Optionally, the switch timing circuit 103 includes a first switch unit and a second switch unit;

[0117] Among them, the first switch unit is electrically connected to the read signal generating circuit 101 and the second input end of the hysteresis comparator circuit 102; the second switch unit is electrically connected to the second input end of the hysteresis comparator circuit 102; by controlling the on and off of the first switch unit and the second switch unit, the output end of the hysteresis comparator circuit 102 is controlled to be reset to the first logic signal, or, by controlling the on and off of the first switch unit and the second switch unit, the data signal is controlled to be input into the second input end of the hysteresis comparator circuit 102.

[0118] In the embodiment of the present application, one end of the second switch unit is electrically connected to the second input end of the hysteresis comparator circuit 102, and the other end is grounded (GND). Taking the hysteresis comparator circuit 102 as an example, when the first switch unit is in the open state and the second switch unit is in the closed state, the second input end of the hysteresis comparator 104 is grounded to GND, so that the output end of the hysteresis comparator 104 is reset to the first logic signal. When the first switch unit is in the closed state and the second switch unit is in the open state, the second input end of the hysteresis comparator 104 is electrically connected to the read signal generating circuit 101, so that the data signal is input to the second input end of the hysteresis comparator 104.

[0119] It should be noted that in order to prevent the flip state of the previous reading from affecting the next data reading, it is necessary to control the on and off of the first switch unit and the second switch unit before each data reading to set the input voltage to the initial non-flipped level so that the output end of the hysteresis comparator circuit 102 is reset to the first logic signal.

[0120] It should also be noted that the embodiments of the present application do not limit the specific switch types of the first switch unit and the second switch unit. Optionally, the first switch unit and the second switch unit can be metal-oxide-semiconductor field-effect transistors (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), bipolar transistors (Bipolar Junction Transistor, BJT), complementary metal-oxide-semiconductor switches (Complementary Metal-Oxide-Semiconductor Switch, CMOS), solid-state relays (Solid-State Relay, SSR), transmission gates, etc.

[0121] For example, Figure 8 A schematic diagram of the mapping relationship between the switch states of the first switch unit and the second switch unit of a magnetic memory and the data reading method flow is provided in an embodiment of the present application, as shown in FIG. Figure 8As shown, using a parallel magnetic tunnel junction (MTJ) unit for data reading, with the second switch unit and the first switch unit being the first switch S1 and the second switch S2, respectively, as an example, S801: before each data read, the first switch S1 is closed and the second switch S2 is opened, thereby grounding the input signal at the second input terminal of the hysteresis comparator circuit 102, thereby resetting the output terminal of the hysteresis comparator circuit 102 to the first logic signal. Furthermore, S802: the first switch S1 is opened and the second switch S2 is closed, thereby controlling the data signal to be input to the second input terminal of the hysteresis comparator circuit 102. S803: the first switch S1 remains opened and the second switch S2 remains closed, and a hysteresis comparison is performed between the data signal and the hysteresis interval to obtain a data read result.

[0122] In this way, by independently controlling the on and off of the two switch units, the circuit's operating mode can be flexibly switched to be in reset mode or data reading mode. This dual-switch design isolates the data signal and data reading result of the previous data reading from the current data reading, preventing interference from the previous data reading. In addition, by controlling the on and off of the input signal through two switch units, it can also ensure that the hysteresis comparator circuit is not affected by external noise during reset, avoiding false triggering.

[0123] Optional, such as Figure 9 As shown, the read signal generating circuit 101 includes: a reference signal generating module 13 and a data signal generating module 14;

[0124] The reference signal generating module 13 is electrically connected to the first input terminal of the hysteresis comparator circuit 102 , and the reference signal generating module 13 includes at least one reference magnetic storage unit 12 for generating and outputting a reference signal;

[0125] The data signal generating module 14 is electrically connected to the second input terminal of the hysteresis comparator circuit 102 through the switch timing circuit 103 . The data signal generating module 14 includes at least one data magnetic storage unit 11 for generating and outputting a data signal.

[0126] For example, Figure 9 A schematic diagram of a circuit structure and signal flow of a magnetic memory provided in an embodiment of the present application is shown in FIG. Figure 9As shown, taking the hysteresis comparator 104 as an example of the hysteresis comparator 102, the read signal generating circuit 101 includes a reference signal generating module 13 and a data signal generating module 14. The reference signal generating module 13 is electrically connected to the first input terminal of the hysteresis comparator 104, and is used to generate and output a reference signal to the hysteresis comparator 104. The data signal generating module 14 is electrically connected to the second input terminal of the hysteresis comparator 104 through the first switching unit, and is used to generate and output a data signal to the hysteresis comparator 104. Further, based on the switching timing setting of the hysteresis comparator 104, the data is read out.

[0127] Optionally, the reference signal generating module 13 includes a reference magnetic storage unit 12 for generating a reference signal, and the data signal generating module 14 includes a data magnetic storage unit 11 for generating a data signal.

[0128] It is understandable that the comparator in the magnetic memory 100 is designed as a hysteresis comparator 104, so that the reference signal generating module 13 only needs a reference magnetic storage unit 12 in one state to generate the reference signal required for reading, but the reading process requires the cooperation of the first switching unit and the second switching unit.

[0129] For example, Figure 10 A schematic diagram of a read signal generating circuit structure and signal flow of a magnetic memory provided in an embodiment of the present application is shown in FIG. Figure 10 As shown, taking the hysteresis comparator 104 as an example of the hysteresis comparator circuit 102, the reference signal generating module 13 includes at least one reference magnetic storage unit 12, one end of the reference magnetic storage unit 12 is connected to the first transistor 15, the second transistor 16 and the third transistor 17 in sequence, and the other end of the reference magnetic storage unit 12 is connected to the ground through the fourth transistor 18. The third transistor 17 is used to determine the path of the current flowing in the circuit, the second transistor 16 is used to perform column selection, the first transistor 15 is used to isolate or transmit the signal to the hysteresis comparator 104, and the fourth transistor 18 is used to control the data writing direction.

[0130] The data signal generating module 14 includes at least one data magnetic storage unit 11, one end of the data magnetic storage unit 11 is connected to the fifth transistor 19, the sixth transistor 20 and the seventh transistor 23 in sequence, and the other end of the data magnetic storage unit 11 is grounded through the eighth transistor 24. The function of the seventh transistor 23 is similar to that of the third transistor 17, the function of the sixth transistor 20 is similar to that of the second transistor 16, the function of the fifth transistor 19 is similar to that of the first transistor 15, and the function of the eighth transistor 24 is similar to that of the fourth transistor 18, which will not be repeated here.

[0131] Optionally, the first transistor 15, the second transistor 16, the fourth transistor 18, the fifth transistor 19, the sixth transistor 20 and the eighth transistor 24 are N-type metal-oxide-semiconductor field-effect transistors, and the third transistor 17 and the seventh transistor 23 are P-type metal-oxide-semiconductor field-effect transistors.

[0132] A first input terminal of the hysteresis comparator 104 is electrically connected to a connection terminal of the third transistor 17 and the seventh transistor 23, and is substantially connected to the gate of the third transistor 17, but is not directly electrically connected thereto. A second input terminal of the hysteresis comparator 104 is electrically connected to the gate of the seventh transistor 23 based on the first switch unit (the second switch S2 is taken as an example in the figure).

[0133] It is understandable that the first input terminal of the hysteresis comparator 104 may also have other connection modes, for example, Figure 11 A schematic diagram of a read signal generating circuit structure and signal flow of another magnetic memory provided in an embodiment of the present application is shown in FIG. Figure 11 As shown, Figure 10 The difference is that the first input terminal of the hysteresis comparator 104 is directly connected to the gate of the third transistor 17, and the read link also needs to be connected to an external bias voltage.

[0134] In this way, the design of separating the reference signal generating module 13 and the data signal generating module 14 and connecting them to the hysteresis comparator circuit 102 respectively can share part of the current path, such as the bias circuit, thereby reducing the total power consumption. Moreover, since the reference signal generating module 13 and the data signal generating module 14 can be set independently, they can adapt to different storage states, such as the parallel state and the anti-parallel state of the magnetic tunnel junction.

[0135] Optionally, the data signal generating module 14 includes a plurality of data magnetic storage units 11;

[0136] The corresponding data signal generated by each data magnetic storage unit 11 is electrically connected to the second input terminal of the hysteresis comparator circuit 102 , so that the multiple data signals share the same reference signal.

[0137] It should be noted that the corresponding data signal generated by each data magnetic storage unit 11 is electrically connected to the hysteresis comparison circuit 102, which means that each data magnetic storage unit 11 can be electrically connected to the hysteresis comparison circuit 102 through row selection or column selection, so that multiple data magnetic storage units 11 can share the same hysteresis comparison circuit 102.

[0138] Exemplarily, the magnetic tunnel junction of the reference magnetic storage unit 12 can generate a stable reference signal (for example, a reference voltage Vref) and input the reference signal to the first input end of the hysteresis comparator 104, and the plurality of data magnetic storage units 11, for example, the data magnetic storage units 11 in the parallel state in the magnetic storage 100, generate respective data signals (for example, data voltages Vdata), and further, the data signal generation module 14 and the switch timing circuit 103 are time-divisionally gated and sequentially connected to the second input end of the hysteresis comparator 104, and the hysteresis comparator 104 performs hysteresis comparison on each data signal (for example, the data voltage Vdata) and the determined hysteresis interval of the reference signal (for example, the reference voltage Vref) to output a corresponding logic signal “0” or “1”.

[0139] It can be understood that the existing magnetic storage 100 generally needs at least two reference branches when performing data reading, and each reference branch includes one reference magnetic storage unit 12, one reference magnetic storage unit 12 is in a parallel state, and the other reference magnetic storage unit 12 is in an antiparallel state, and the present application only needs one reference magnetic storage unit 12 based on the design of the hysteresis comparison circuit, that is, the data signals generated by the plurality of data magnetic storage units 11 share the same reference signal to realize data reading, wherein the reference magnetic storage unit 12 required by the present application can be in a parallel state or an antiparallel state, for example, as shown in the array, the state of the reference magnetic storage unit 12 is not specifically limited in the embodiment of the present application. Figure 12

[0140] Therefore, the plurality of data magnetic storage units 11 share the same reference signal, that is, there is only one reference branch of the reference magnetic storage unit when reading data, the repeated reference magnetic storage units 12 are reduced, thereby saving the layout area, and the reference signal path only needs to generate the reference signal once, and the plurality of data signals can be compared in time, the current for generating the reference voltage is reduced, thereby reducing the reading power consumption, in addition, the plurality of data magnetic storage units 11 take the same reference signal as a reference, and the logic misjudgment caused by the reference signal fluctuation can be avoided.

[0141] Optionally, the reference magnetic storage unit 12 includes a magnetic tunnel junction, and the magnetic tunnel junction includes a free layer, a barrier layer, and a reference layer which are sequentially stacked.

[0142] The magnetization directions of the free layer and the reference layer in the reference magnetic storage unit 12 are in a parallel state, or the magnetization directions of the free layer and the reference layer in the reference magnetic storage unit 12 are in an antiparallel state.

[0143] ​It should be noted that the magnetic memory 100 uses the tunneling magnetoresistance (TMR) effect to implement data storage. Its basic unit is a magnetic tunnel junction. The magnetic memory 100 determines the stored data value by measuring the resistance of the magnetic tunnel junction to read the data.

[0144] In this application, the magnetic tunnel junction is composed of three stacked layers, namely the free layer, the barrier layer, and the reference layer. The magnetization direction of the free layer can be changed by an external magnetic field or current. The barrier layer is an insulating layer whose thickness affects the tunneling magnetoresistance effect. The magnetization direction of the reference layer is fixed.

[0145] Therefore, the magnetization directions of the free layer and the reference layer are parallel, that is, the directions are the same, indicating that the reference magnetic storage unit is in a low-resistance state; the magnetization directions of the free layer and the reference layer are antiparallel, that is, the directions are opposite, indicating that the reference magnetic storage unit 12 is in a high-resistance state. In this way, when the magnetization directions of the free layer and the reference layer are parallel, a low-resistance reference signal can be generated; when the magnetization directions of the free layer and the reference layer are antiparallel, a high-resistance reference signal can be generated.

[0146] It can be understood that by designing the reference magnetic storage unit 12 as above, the magnetization state of the reference magnetic storage unit 12 is not disturbed by the read and write operations, thereby providing a long-term stable reference signal. Moreover, regardless of whether the reference magnetic storage unit 12 is in a parallel state or an anti-parallel state, the method of the present application can be applied, which greatly improves the flexibility of application. In addition, the reference magnetic storage unit 12 is designed to have a fixed magnetization direction, eliminating the circuit for dynamically adjusting the reference signal and simplifying the circuit design and control logic of the magnetic storage.

[0147] Optionally, when the number of the data magnetic storage unit 11, the reference magnetic storage unit 12, and the hysteresis comparison circuit 102 is plural, the data magnetic storage unit 11 is configured to be arranged in a plurality of columns in an array, and the reference magnetic storage unit 12 is configured to be arranged in at least one column in an array;

[0148] Among them, the data signal generated by each row of data magnetic storage units 11 is input into the second input end of the hysteresis comparison circuit 102 corresponding to each row, and the reference signal generated by each row of reference magnetic storage units 12 is input into the first input end of the same hysteresis comparison circuit 102 corresponding to each row, so that each row of data magnetic storage units 11 shares the same reference magnetic storage unit 12.

[0149] For example, Figure 12 This is a general architecture diagram of a magnetic storage provided in an embodiment of the present application, such as Figure 12As shown, there are N columns of data magnetic storage cells 11, 1 column of reference magnetic storage cells 12, and M rows of data magnetic storage cells 11 and reference magnetic storage cells 12, respectively. The data magnetic storage cells 11 corresponding to each row share the reference signal generated by the reference magnetic storage cells 12 corresponding to the row. M is a natural number greater than 1, and N is a natural number greater than 1.

[0150] Optionally, the magnetic memory 100 includes, in addition to the read signal generating circuit 101 , the hysteresis comparison circuit 102 and the switch timing circuit 103 , a word line selection module 105 , a driving module 106 and a bit line selection module 107 .

[0151] It should be noted that the reference magnetic storage unit 12 does not necessarily have to be Figure 12 As shown, it is on the far right of the array. It can be in any column. The embodiment of the present application does not specifically limit the deployment position of the reference magnetic storage unit 12.

[0152] Therefore, each row of data magnetic storage cells 11 shares one reference magnetic storage cell 12, which can greatly save area compared to requiring an independent column of reference magnetic storage cells 12 for each column. Moreover, only one hysteresis comparison circuit 102 is required for each row, rather than one hysteresis comparison circuit 102 for each column, which can greatly reduce the area of ​​the analog circuit. In addition, the same hysteresis comparison circuit 102 can also process multiple columns of data in a time-sharing manner, reducing repeated current paths and lowering power consumption.

[0153] It is understandable that the data reading method of the magnetic memory provided in the present application can be applicable to the magnetic memory 100 that only needs to adjust the resistance state of the reference magnetic storage unit 12.

[0154] Exemplarily, the present application further provides a data reading method for a magnetic memory, which is applied to the magnetic memory 100 as in any one of the above embodiments; Figure 13 A flowchart of a method for reading data from a magnetic storage device provided in an embodiment of the present application is shown in FIG. Figure 13 As shown, the data reading method of the magnetic storage device includes the following steps:

[0155] S1301, before each data reading, resetting the output terminal of the hysteresis comparison circuit to a first logic signal;

[0156] S1302 , inputting a data signal to the second input terminal of the hysteresis comparison circuit, so that the hysteresis comparison circuit performs hysteresis comparison on the data signal and the hysteresis interval, thereby causing the output terminal of the hysteresis comparison circuit to output a data reading result.

[0157] It should be noted that the specific implementation principle and effects of the data reading method of the magnetic memory can be found in the corresponding descriptions and effects of the above embodiments, and will not be elaborated here.

[0158] In the several embodiments provided herein, it should be understood that the disclosed modules and methods can be implemented in other ways. For example, the division of modules is merely a logical functional division, and actual implementations may employ other division methods, such as combining or integrating multiple modules or components into another system, or omitting or disabling certain features. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interface, while the indirect coupling or communication connection between modules may be electrical, mechanical, or other.

[0159] Modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical units, that is, they may be located in one place or distributed across multiple network elements. Some or all of these modules may be selected to implement the solution of this embodiment based on actual needs.

[0160] In addition, the functional modules in the various embodiments of the present application may be integrated into a single processing unit, or each module may exist physically separately, or two or more modules may be integrated into a single unit. The above-mentioned modules may be implemented in the form of hardware or hardware plus software functional units.

[0161] It should be understood that the above-mentioned magnetic memory can be a magnetic random access memory or a non-volatile memory (NVM), such as at least one disk memory, or a USB flash drive, a mobile hard disk, a read-only memory, a magnetic disk or an optical disk, etc.

[0162] The magnetic storage cells arranged in an array may be located in any type of non-volatile memory device or a combination thereof, such as an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a flash memory, a magnetic disk, or an optical disk.

[0163] The magnetic memory may also be applied to application specific integrated circuits (ASICs), which is not specifically limited in the embodiments of the present application.

[0164] It should be noted that for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all optional embodiments, and the actions and modules involved are not necessarily required by this application.

[0165] It should be further noted that, although the various steps in the flowchart are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps may be performed in other orders. Moreover, at least a portion of the steps in the flowchart may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily performed at the same time, but may be performed at different times. The execution order of these sub-steps or stages is not necessarily to be performed in sequence, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0166] In the above embodiments, the description of each embodiment has its own emphasis. For parts not described in detail in a particular embodiment, please refer to the relevant description of other embodiments. The technical features of the above embodiments can be combined in any way. To keep the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0167] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered merely as exemplary, and the true scope and spirit of the present application are indicated by the claims.

[0168] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A magnetic memory, characterized in that: It includes a read signal generating circuit, a hysteresis comparison circuit and a switch timing circuit which are electrically connected to each other; The read signal generating circuit includes a data magnetic storage unit for generating a data signal and a reference magnetic storage unit for generating a reference signal; the read signal generating circuit inputs the data signal into the switch timing circuit and inputs the reference signal into the first input terminal of the hysteresis comparator circuit, so as to determine the hysteresis interval of the hysteresis comparator circuit through the reference signal; The switching timing circuit is used to reset the output end of the hysteresis comparison circuit to a first logic signal before each data reading, and then input the data signal to the second input end of the hysteresis comparison circuit, so that the hysteresis comparison circuit performs a hysteresis comparison on the data signal and the hysteresis interval, so that the output end of the hysteresis comparison circuit outputs the data reading result.

2. The magnetic memory according to claim 1, wherein When the reference magnetic storage unit is in a low-resistance state, the reference signal generated by it is a low-resistance reference signal; when the reference magnetic storage unit is in a high-resistance state, the reference signal generated by it is a high-resistance reference signal; The determining the hysteresis interval of the hysteresis comparison circuit by using the reference signal includes: The threshold value of the hysteresis interval is determined by the low-impedance reference signal and the high-impedance reference signal.

3. The magnetic memory according to claim 2, wherein The hysteresis comparison circuit performs hysteresis comparison on the data signal and the hysteresis interval, so that the output terminal of the hysteresis comparison circuit outputs a data reading result, including: When the data signal is greater than the threshold value, the data reading result is flipped from the first logic signal to the second logic signal; or, when the data signal is less than the threshold value, the data reading result remains the first logic signal; The first logic signal and the second logic signal represent opposite logics.

4. The magnetic memory according to claim 2, wherein: The hysteresis comparison circuit performs hysteresis comparison on the data signal and the hysteresis interval, so that the output terminal of the hysteresis comparison circuit outputs a data reading result, including: When the data signal is less than the threshold value, the data reading result is flipped from the first logic signal to the second logic signal; or, when the data signal is greater than the threshold value, the data reading result remains the first logic signal; The first logic signal and the second logic signal represent opposite logics.

5. The magnetic memory according to claim 1, wherein The switch timing circuit includes a first switch unit and a second switch unit; The first switch unit is electrically connected to the read signal generating circuit and the second input end of the hysteresis comparator circuit; the second switch unit is electrically connected to the second input end of the hysteresis comparator circuit; the output end of the hysteresis comparator circuit is reset to the first logic signal by controlling the on and off of the first switch unit and the second switch unit, or the data signal is input to the second input end of the hysteresis comparator circuit by controlling the on and off of the first switch unit and the second switch unit.

6. The magnetic memory according to claim 1, wherein The read signal generating circuit includes: a reference signal generating module and a data signal generating module; Wherein, the reference signal generating module is electrically connected to the first input terminal of the hysteresis comparator circuit, and the reference signal generating module includes at least one reference magnetic storage unit, which is used to generate and output the reference signal; The data signal generating module is electrically connected to the second input terminal of the hysteresis comparison circuit through the switch timing circuit. The data signal generating module includes at least one data magnetic storage unit, which is used to generate and output the data signal.

7. The magnetic memory according to claim 6, wherein: The data signal generating module includes a plurality of the data magnetic storage units; The corresponding data signal generated by each data magnetic storage unit is electrically connected to the second input terminal of the hysteresis comparison circuit, so that multiple data signals share the same reference signal.

8. The magnetic memory according to claim 1, wherein The reference magnetic storage unit includes a magnetic tunnel junction, and the magnetic tunnel junction includes a free layer, a barrier layer, and a reference layer stacked in sequence; The magnetization directions of the free layer and the reference layer in the reference magnetic storage unit are parallel, or the magnetization directions of the free layer and the reference layer in the reference magnetic storage unit are antiparallel.

9. The magnetic memory according to claim 1, wherein When the number of the data magnetic storage unit, the reference magnetic storage unit, and the hysteresis comparison circuit is plural, the data magnetic storage unit is arranged in a plurality of columns in an array, and the reference magnetic storage unit is arranged in at least one column in an array; Among them, the data signal generated by the data magnetic storage unit in each row is input into the second input end of the hysteresis comparison circuit corresponding to each row, and the reference signal generated by the reference magnetic storage unit in each row is input into the first input end of the same hysteresis comparison circuit corresponding to each row, so that the data magnetic storage units in each row share the same reference magnetic storage unit.

10. A method for reading data from a magnetic memory, characterized in that: Applied to the magnetic memory according to any one of claims 1 to 9; the method comprising: Resetting the output terminal of the hysteresis comparison circuit to a first logic signal before each data reading; The data signal is input to the second input terminal of the hysteresis comparison circuit, so that the hysteresis comparison circuit performs hysteresis comparison on the data signal and the hysteresis interval, and the output terminal of the hysteresis comparison circuit outputs a data reading result.

Images