Artificial intelligence-based embedded development method, system, device and storage medium

Abstract

The application relates to an artificial intelligence-based embedded development method, system, device and storage medium, wherein the method comprises the following steps: converting a component into a standardized digital twin model; constructing a standardized hardware module library based on the standardized digital twin model, and constructing a hardware intermediate layer; creating a component template through a graphical interface, and obtaining configuration information of a user-configured component based on the standardized digital twin model; performing configuration processing on the component template based on the configuration information, generating a target component, and saving the target component into a component library; creating a hardware template through the graphical interface, determining a master control chip from the component library, and obtaining hardware configuration parameters through the hardware intermediate layer; performing configuration on the hardware template according to the hardware configuration parameters and the master control chip, generating target hardware information, and generating burnable firmware information and a hardware physical list based on the target hardware information. The application reduces the development threshold and improves cross-platform adaptation efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of embedded system development, and in particular to an embedded development method and system based on artificial intelligence, a device and a storage medium. BACKGROUND

[0002] Traditional embedded system development has significant technical bottlenecks, mainly in three aspects: first, the development process is heavily dependent on the professional skills of the developer, requiring deep hardware knowledge, underlying programming ability and familiarity with specific chip architecture. This high threshold results in long development cycles and high labor costs. Second, due to the architectural differences between different hardware platforms, the development results are difficult to implement cross-platform reuse. When faced with diverse hardware environments (such as various sensors and communication protocols), repeated development of adaptation code is required, resulting in resource waste. Third, the existing development mode has low efficiency in software and hardware collaborative design, and the functional modules lack standardized specifications, making it difficult to ensure system stability, especially in application scenarios such as industrial automation and smart home that require rapid response to market changes. These problems seriously hinder product iteration speed.

[0003] With the rapid development of Internet of Things technology, the demand for edge computing devices is growing exponentially, which puts higher requirements on embedded system development. The current industry urgently needs a solution that can digitize hardware capabilities, standardize development processes, and dynamically optimize resource allocation through artificial intelligence technology to break through the technical barriers of traditional development modes and meet the urgent needs of the intelligent manufacturing field to shorten product development cycles and reduce production costs. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide an embedded development method and system based on artificial intelligence, a device and a storage medium to reduce the development threshold and improve cross-platform adaptation efficiency.

[0005] To solve the above technical problems, the embodiments of the present application provide an embedded development method based on artificial intelligence, comprising:

[0006] Converting components into standardized digital twin models;

[0007] Building a standardized hardware module library based on the standardized digital twin models, and building a hardware intermediate layer;

[0008] Creating a component template through a graphical interface, and obtaining configuration information of user-configured components based on the standardized digital twin models;

[0009] Configuring the component template based on the configuration information, generating a target component, and saving the target component to a component library;

[0010] create a hardware template through the graphical interface, determine a master control chip from the component library, and obtain hardware configuration parameters through the hardware intermediate layer;

[0011] configure the hardware template according to the hardware configuration parameters and the master control chip, generate target hardware information, and generate burnable firmware information and a hardware physical list based on the target hardware information.

[0012] To solve the above technical problems, an embodiment of the present application provides an embedded development system based on artificial intelligence, comprising:

[0013] a digital twin model construction module configured to convert components into standardized digital twin models;

[0014] a hardware module library construction module configured to construct a standardized hardware module library based on the standardized digital twin models and construct a hardware intermediate layer;

[0015] a component template creation module configured to create a component template through a graphical interface and obtain configuration information of a user-configured component based on the standardized digital twin models;

[0016] a target component generation module configured to configure the component template based on the configuration information, generate a target component, and save the target component into a component library;

[0017] a hardware template creation module configured to create a hardware template through the graphical interface, determine a master control chip from the component library, and obtain hardware configuration parameters through the hardware intermediate layer;

[0018] a target hardware information generation module configured to configure the hardware template according to the hardware configuration parameters and the master control chip, generate target hardware information, and generate burnable firmware information and a hardware physical list based on the target hardware information.

[0019] To solve the above technical problems, an embodiment of the present application provides an embedded development system based on artificial intelligence, comprising:

[0020] To solve the above technical problems, an embodiment of the present application provides an embedded development system based on artificial intelligence, comprising:

[0021] The embodiment of the application provides an embedded development method, system, device and storage medium based on artificial intelligence. The method comprises the following steps: converting a component into a standardized digital twin model; constructing a standardized hardware module library based on the standardized digital twin model, and constructing a hardware intermediate layer; creating a component template through a graphical interface, and obtaining configuration information of a user-configured component based on the standardized digital twin model; performing configuration processing on the component template based on the configuration information, generating a target component, and saving the target component into a component library; creating a hardware template through the graphical interface, determining a master control chip from the component library, and obtaining hardware configuration parameters through the hardware intermediate layer; performing configuration on the hardware template according to the hardware configuration parameters and the master control chip, generating target hardware information, and generating burnable firmware information and a hardware physical list based on the target hardware information. The embodiment of the application constructs a hardware module library and an intermediate layer through a standardized digital twin model, realizes hardware configuration automation in combination with a graphical interface, solves the problems of dependence on manual experience and difficulty in cross-platform adaptation in a traditional development process, and has the advantages of reducing a development threshold, improving cross-platform adaptation efficiency, and enhancing the ability of soft and hardware collaborative design. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the scheme in the application, the drawings needed in the description of the embodiments of the application will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0023] Figure 1 is the implementation flowchart of the embedded development method based on artificial intelligence provided by the embodiment of the application;

[0024] Figure 2 is the implementation flowchart of the first sub-process in the embedded development method based on artificial intelligence provided by the embodiment of the application;

[0025] Figure 3 is the implementation flowchart of the second sub-process in the embedded development method based on artificial intelligence provided by the embodiment of the application;

[0026] Figure 4 is the implementation flowchart of the third sub-process in the embedded development method based on artificial intelligence provided by the embodiment of the application;

[0027] Figure 5 is the implementation flowchart of the fourth sub-process in the embedded development method based on artificial intelligence provided by the embodiment of the application;

[0028] Figure 6is a fifth sub-flow implementation flowchart of the artificial intelligence-based embedded development method provided by the embodiment of the present application;

[0029] Figure 7 is a sixth sub-flow implementation flowchart of the artificial intelligence-based embedded development method provided by the embodiment of the present application;

[0030] Figure 8 is a schematic diagram of the artificial intelligence-based embedded development system provided by the embodiment of the present application;

[0031] Figure 9 is a schematic diagram of the electronic device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the description and claims of this application as well as the above abstract are intended to cover all alternatives, modifications, and equivalents thereof in accordance with the scope of the application as claimed. The terms "comprising", "having", "including", and "containing" used herein are meant to be interpreted in a non-limiting manner.

[0033] Reference herein to "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase that the phrase in the specification appear in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily all directed to the same application. It is explicitly contemplated that embodiments described herein can be combined with each other, even though not explicitly described or illustrated.

[0034] In order to make the technical personnel in the art better understand the scheme of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings.

[0035] The present application will be described in detail below with reference to the drawings and embodiments.

[0036] It should be noted that the artificial intelligence-based embedded development method provided by the embodiments of the present application is generally executed by an electronic device, and accordingly, the artificial intelligence-based embedded development system is generally configured in the electronic device.

[0037] In the prior art, embedded system development has long relied on manual writing of underlying driver code and hardware configuration, and developers need to be proficient in multiple chip architectures and hardware protocols, resulting in long development cycles and high labor costs. Under the traditional development mode, there is a lack of unified standards for the description of hardware component parameters, and compatibility verification between devices of different manufacturers consumes a lot of time, and functional modules are difficult to reuse across projects. Especially in the development scenario of smart home devices, in the face of the combination and configuration of dozens of sensors and communication modules, engineers need to repeatedly debug hardware interface protocols and manually generate device driver code, and there is a problem of low efficiency of software and hardware collaborative design.

[0038] To solve the above problems, it is found that the lack of standardization of hardware parameters is the key factor leading to low development efficiency, and then a physical component is converted into an interactive digital model to form a unified hardware abstraction layer. To solve the cross-platform adaptation problem, a middle layer is built to decouple hardware capabilities and software calls. To solve the technical bottleneck of graphical configuration and automatic generation, a parameter mapping mechanism based on digital twin model is designed, so that hardware function selection can be converted into visual operation. Therefore, the present application proposes an embedded development method based on artificial intelligence, including: converting components into standardized digital twin models; building a standardized hardware module library based on the standardized digital twin models, and building a hardware middle layer; creating a component template through a graphical interface, and obtaining configuration information of the user-configured components based on the standardized digital twin models; configuring the component template based on the configuration information, generating a target component, and saving it to a component library; creating a hardware template through a graphical interface, determining a master chip from the component library, and obtaining hardware configuration parameters through the hardware middle layer; configuring the hardware template according to the hardware configuration parameters and the master chip, generating target hardware information, and generating burnable firmware information and a hardware physical list based on the target hardware information. Specifically, after physical components are digitally modeled, a standard parameter library is formed, and when a developer selects a required functional module on a graphical interface, the system automatically retrieves the parameter constraint range of the corresponding digital twin model. The hardware middle layer real-time analyzes the communication protocol differences between the master chip and the peripheral module, and automatically completes the interface protocol conversion during the configuration of the hardware template. When the user completes the hardware topology design, the system automatically generates the burnable firmware according to the drive logic in the digital twin model, and outputs the bill of materials required for manufacturing based on the physical property model. The compatibility detection module real-time checks the pin level matching degree and bus load capacity during the configuration process to ensure the feasibility of the hardware scheme.

[0039] Please refer to Figure 1 , Figure 1 An embodiment of the embedded development method based on artificial intelligence is shown.

[0040] It should be noted that the method of the present application does not exclude Figure 1The flow sequence shown is limited, and the method comprises the following steps:

[0041] S1: converting the components into a standardized digital twin model.

[0042] Specifically, the present application provides a low-code visual development platform, which abstracts hardware operations into graphical modules, and users can complete function configuration without directly writing underlying code. An AI-driven automatic code generation engine is introduced to automatically generate adaptive code according to hardware models and requirements, reducing the workload of manual transplantation. In the platform, a hardware abstraction layer (HAL) and a standardized component library are designed, encapsulating the general interfaces of common sensors and communication protocols to realize “one development, multiple platform deployment”. Through AI model analysis of historical project data, the optimal component combination is intelligently recommended, and the module reuse rate is improved to more than 70%. The present application constructs an embedded special low-code framework, supports NVIDIARKRTOSbare machine and other embedded running environments, and provides graphical operation of hardware configuration guide.

[0043] In the embodiments of the present application, the attributes, functions, etc. of each component are converted into a standardized digital twin model, which is convenient for calling and combining during design. The standardized digital twin model includes physical attributes (pin definition / electrical parameters / protocol standard), functional attributes (thing model / driving interface / energy consumption model), and production data (supplier / quality inspection standard / historical failure rate).

[0044] The standardized digital twin model refers to a structured data set formed by digitizing the physical attributes, pin functions and driving logic of the components, which can be specifically implemented by parsing the component data manual to extract basic parameters and generating a function mapping file in combination with the chip pin definition diagram. The model provides a unified benchmark for the standardized description of hardware modules.

[0045] Please refer to Figure 2 , Figure 2 A specific embodiment of step S1 is shown, which is described in detail as follows:

[0046] S11: obtaining component data manual, chip pin definition diagram and business requirement document;

[0047] S12: parsing the component data manual to extract the basic attributes of the components, generating a structured parameter table, and performing physical attribute digitization modeling based on the structured parameter table to generate a physical attribute model file;

[0048] S13: performing pin function mapping based on the chip pin definition diagram to generate a pin function mapping file, and constructing a thing model description file based on the business requirement document;

[0049] S14: generating a driver file according to the data manual register description and the historical driver library;

[0050] S15: performing digital twin model packaging based on the physical property model file, the pin function mapping file and the driver file, generating the standardized digital twin model, and storing the standardized digital twin model to the component library.

[0051] Specifically, the component data manual is converted into a structured parameter table through automatic analysis, and the key fields in the parameter table are used to construct a physical property model file, so as to eliminate the error risk of manual interpretation. The pin definition diagram of the chip is processed through image recognition and function mapping to generate a pin function mapping file, and the physical model attributes extracted from the business requirement document are combined to realize the semantic alignment of the hardware interface and the business function. The driving code fragments stored in the historical driver library are matched with the register description in the data manual to automatically generate a driver file adapted to the current component, thereby avoiding repeated development. Finally, the physical property model, the pin function mapping file and the driver file are integrated and packaged into a standardized digital twin model, which is stored in the component library for subsequent development and calling, so as to ensure the model consistency of the same component in different projects.

[0052] Among them, the component data manual refers to a technical document containing electrical characteristics and working parameters of a component, and the text and table data can be extracted by using a PDF analysis tool to construct the basic attributes of the standardized model. The pin definition diagram of the chip refers to a schematic diagram describing the physical pin layout and function allocation of the chip, and the pin number and function label can be extracted by using an image recognition algorithm to realize the semantic mapping of the pin function and the business requirement. The business requirement document refers to an instruction file describing the function scene of a device, and the key physical model attributes can be extracted by using natural language processing technology to generate a device function description file. The structured parameter table refers to the conversion of unstructured technical parameters into machine-readable table data, and the key field extraction can be realized by using regular expression matching technology to provide input for physical property modeling. The physical property model file refers to a digital model describing the size, power consumption and interface type of a component, and a standardized three-dimensional model can be generated by using a parameterized modeling tool to realize the unified description of hardware properties. The driver file refers to software code for controlling hardware operation, and the similar code fragments in the register description and the historical driver library can be matched to automatically generate the driver file, thereby reducing the amount of manual coding.

[0053] S2: constructing a standardized hardware module library based on the standardized digital twin model, and constructing a hardware intermediate layer.

[0054] In the embodiments of the present application, a standardized hardware module library is established, which can support: interaction between modules through a unified communication protocol; automatic generation of hardware topology and dependency through a graphical interface to drag modules. A version compatibility engine is introduced to ensure the stability of the mixed use of new and old modules. The establishment of a standardized hardware module library improves the reuse rate, improves the development efficiency and improves the fault positioning efficiency. The hardware middleware layer can provide a unified device API and a dynamic adaptation engine. The unified device API can mask hardware differences (such as different manufacturers' sensors unified as "data acquisition services"). The dynamic adaptation engine can automatically load drivers and configuration parameters according to the actual hardware.

[0055] Among them, the hardware intermediate layer refers to an abstract interface layer that encapsulates the differences of the hardware bottom layer. Specifically, a unified device API is used to encapsulate the register operation instructions of different chips, and a dynamic adaptation engine is used to automatically match the communication protocol. This intermediate layer eliminates the impact of hardware differences on the upper layer application.

[0056] Please refer to Figure 3 , Figure 3 An embodiment of step S2 is shown as follows:

[0057] S21: According to the historical project hardware scheme and the industry device topology graph, the function dimension is disassembled and the module label is generated to generate a module classification tree structure;

[0058] S22: The modules in the module classification tree structure are standardized in pin interface and unified in communication protocol to obtain a target module classification tree structure;

[0059] S23: The modules in the target module classification tree structure are encapsulated to generate the standardized hardware module library;

[0060] S24: The hardware parameters of the standardized digital twin model are used to construct the hardware intermediate layer.

[0061] Specifically, by analyzing the circuit topology and function configuration in the historical project hardware scheme, the function dimension characteristics of modules such as sensors and communication units are extracted to form a tree index structure classified by functions such as power management and data acquisition. For example, for the temperature sensor module in the industrial control device, by analyzing its pin definition and protocol type in different projects, the pin voltage standard is unified by using a level conversion chip, and the communication protocol is standardized by converting Modbus to MQTT protocol. The completed standardized module is encapsulated as a callable library unit containing a driver file and an interface definition, and stored in the module library. The hardware intermediate layer generates a standardized API interface for the upper layer application by analyzing the register address and clock frequency parameters contained in the digital twin model, such as mapping the sampling rate parameters of different types of ADC modules to a unified numerical acquisition interface.

[0062] Among them, the function dimension disintegration refers to the decomposition of historical project schemes according to the hardware function type, which can be implemented by extracting function keywords using semantic analysis algorithm, and is used to eliminate the problem of chaotic function division. The module label generation refers to adding a function attribute label to each module, which can be implemented by extracting common features of industry device topology graph using natural language processing technology, and is used to establish a unified function classification system. The pin interface standardization refers to unifying the physical connection specifications of modules, which can be implemented by using protocol converters to adapt the electrical parameters of different pin interfaces, and is used to solve the problem of physical connection incompatibility between hardware modules. The communication protocol unification refers to converting different protocols into a standard format recognizable by the intermediate layer, which can be implemented by using protocol conversion middleware, and is used to eliminate the interaction barriers caused by communication protocol differences. The module classification tree structure refers to the module index system organized by function level, which can be implemented by storing module labels and function dimension information using tree data structure, and is used to realize fast retrieval and calling of modules. The target module classification tree structure refers to the module organization structure after the interface and protocol standardization, which can be implemented by using version control technology to retain the module relationship of different standard versions, and is used to support the compatible adaptation of multi-version hardware platforms. The standardized hardware module library refers to a set of hardware components with unified interfaces, which can be implemented by storing module drivers and configuration parameters in the form of binary library files, and is used to improve the module reuse efficiency. The hardware intermediate layer refers to an abstract interface layer connecting hardware modules and application layer, which can be implemented by using dynamic link library technology to realize semantic mapping of hardware parameters, and is used to shield the differences of underlying hardware.

[0063] Please refer to Figure 4 , Figure 4 An embodiment of step S24 is shown as follows:

[0064] S241: Functionally semantic mapping of hardware parameters of the standardized digital twin model is performed to generate a hardware capability list;

[0065] S242: A unified device API and a dynamic adaptation engine are constructed according to the hardware capability list to construct the hardware intermediate layer.

[0066] Specifically, the hardware intermediate layer construction process first extracts the functional attributes of the hardware parameters in the digital twin model through semantic mapping, generating a hardware capability list containing hardware function descriptions, interface specifications, performance indicators, and other elements. Based on this list, a unified device API establishes standardized interface calling specifications, such as uniformly converting the differentiated data formats of temperature sensors and humidity sensors into JSON format output. The dynamic adaptation engine automatically detects hardware configurations and loads corresponding driver modules at device startup by parsing the functional descriptions and interface parameters in the hardware capability list, such as automatically selecting the optimal interrupt handling strategy for different types of master chips. When the hardware configuration changes, the adaptation engine re-establishes the interface mapping relationship through the reflection mechanism without the need for manual modification of the application layer code.

[0067] Among them, the functional semantic mapping refers to the conversion of discrete hardware parameters in the digital twin model into functional descriptions with business semantics, which can be implemented using semantic tag matching algorithms and knowledge graph technology, such as mapping GPIO pin voltage parameters to "switch control interface" semantic tags. This process converts low-level hardware characteristics into functional units recognizable by upper-layer applications, eliminating the semantic gap between hardware parameters and application requirements. The unified device API refers to the standardized encapsulation of heterogeneous hardware interfaces, which can be implemented using middleware technology to achieve protocol conversion and interface abstraction, such as unifying different sensor communication protocols into a standardized data acquisition interface. This interface shields the differences between underlying hardware and provides a consistent calling method for upper-layer business. The dynamic adaptation engine refers to a runtime component that automatically adjusts resource allocation based on actual hardware configuration, which can be implemented using a rule engine and reflection mechanism, such as dynamically loading matching drivers based on the hardware capability list. This component realizes the automatic matching of software and hardware interfaces by real-time parsing of hardware capabilities.

[0068] S3: Create a component template through a graphical interface and obtain configuration information of a user-configured component based on the standardized digital twin model.

[0069] Specifically, the user can design a single component on the graphical interface, which includes component basic information, pin count, pin number, pin function, model attributes (events, attributes, telemetry, instructions), and the upload of the adapted system driver.

[0070] Among them, the graphical interface creates a component template, which means generating a hardware configuration prototype through visual drag-and-drop components. This is achieved using a node-style editor to visually configure pin connection relationships, which reduces the technical threshold for hardware design.

[0071] Please refer to Figure 5 , Figure 5 One specific implementation of step S3 is shown below:

[0072] S31: receiving a template creation request of a user, and creating the component template in the graphical interface according to the template creation request;

[0073] S32: obtaining configuration information of the user-configured component according to the standardized digital twin model, wherein the configuration information comprises component basic information, pin quantity, pin serial number, pin function, and physical model attribute.

[0074] Specifically, after the user selects a component type through the graphical interface, the system automatically loads the pre-defined parameters of the component based on the standardized digital twin model, such as pin function mapping files and physical model description files. The user fills in the basic information of the component name, model, etc. through the visual form, and selects the pin serial number and function allocation based on the pin layout diagram provided by the system, such as configuring the GPIO pin as input or output mode. In this process, the physical model attribute is presented in the form of a drop-down menu or a check box, such as setting the sensor range or communication protocol type. After the configuration is completed, the system automatically checks the logical consistency of the pin function and the physical model attribute, such as detecting whether the I2C pin is incorrectly assigned as the UART function, so as to generate configuration information that conforms to the real characteristics of the hardware.

[0075] Wherein, the graphical interface creating the component template refers to the visual design of the component template through drag-and-drop operation or parameterized form, which can be realized by HTML5 canvas technology or graphical configuration engine, and is used to convert hardware configuration operation from code writing to graphical interaction, reducing the complexity of user operation. Wherein, the pin quantity and pin serial number refer to the standard pin layout data generated by analyzing the chip pin definition diagram, which can be realized by pin mapping table or pin coordinate system, and is used to automatically map the relationship between physical pin and logical function, preventing hardware connection errors. Wherein, the physical model attribute refers to the device function description data defined based on the business requirement document, which can be realized by attribute-value pair or state-event model, and is used to abstract hardware function into a standardized interface that can be called by software, supporting subsequent firmware automatic generation. The physical model attribute includes event, attribute, telemetry, instruction, etc.

[0076] S4: performing configuration processing on the component template based on the configuration information, generating a target component, and saving the target component to a component library.

[0077] Specifically, the component template is configured with basic information (such as name, signal and classification), pin information (such as n number, electrical characteristics) and physical model definition. After the configuration is completed, drive management, code uploading and component generation processing are performed to generate the target component. The target component is saved to the component library. The target component can be audited, and if the audit fails, the component template is returned to create a component for re-designing the component. If the audit is passed, the target component can be published to the market platform.

[0078] S5: creating a hardware template through the graphical interface, determining a master control chip from the component library, and obtaining hardware configuration parameters through the hardware intermediate layer.

[0079] Specifically, after the component design is completed, intelligent hardware assembly can be performed, which includes creating an intelligent hardware template, selecting required components (master control chip + peripherals), defining intelligent hardware information (product basic information, terminal information, component information, device physical model attribute information), generating a burnable BSP, generating a BOM list of intelligent hardware, and publishing the intelligent hardware template to the market platform.

[0080] The graphical interface refers to a man-machine interface for building a hardware topology structure through a visual operation panel, and can be implemented by using a drag-and-drop component library and a connection editor. The hardware connection relationship is converted into a combination of graphical elements to reduce the complexity of user operation.

[0081] Please refer to Figure 6 , Figure 6 An embodiment of step S5 is shown as follows:

[0082] S51: receiving a hardware template creation request of a user, and creating the hardware template in the graphical interface according to the hardware template creation request;

[0083] S52: determining the master control chip from the component library, and receiving a target peripheral module determined by the user;

[0084] S53: obtaining the hardware configuration parameters through the hardware intermediate layer, wherein the hardware configuration parameters include product basic information, terminal information, component information and device physical model attribute information.

[0085] Specifically, after a user initiates a hardware template creation request through a graphical interface, the system automatically generates a blank hardware topology canvas. When a master chip is selected from a component library, its pin definition, driver file, and communication protocol have been standardized and encapsulated through a digital twin model, avoiding manual data manual review. The selection process of peripheral modules is displayed through a pre-classified tree structure. The user drags the target module to the canvas according to the functional requirements, and the system automatically calls the hardware intermediate layer to verify the interface matching degree between modules. In the process of obtaining hardware configuration parameters, product basic information defines device application scenarios, terminal information is associated with deployment environment parameters, component information integrates physical size and electrical characteristics, and model attribute information describes business function logic. After semantic conversion by the hardware intermediate layer, the four types of parameters form a unified format of configuration instruction set. This process converts the traditional register configuration code operation into visual parameter setting, and eliminates cross-platform differences through the protocol adaptation capability of the intermediate layer.

[0086] Among them, the master chip refers to the core processor unit of the embedded system, which can be selected from the pre-set standardized digital twin model component library, and realized plug and play through the encapsulated pin definition and driver file. The target peripheral module refers to the sensor, communication module and other auxiliary functional units selected by the user, which are specifically screened through the pre-classified tags of the standardized hardware module library to ensure that the interface protocol is compatible with the master chip. The hardware intermediate layer refers to the protocol conversion layer connecting physical hardware and upper layer application, which is specifically realized by unified device API and dynamic adaptation engine, and converts heterogeneous hardware parameters into standardized configuration instructions through semantic mapping. The hardware configuration parameters refer to the constraint condition set containing device type, deployment environment, physical properties and business functions, which are specifically generated by analyzing the structured parameters of the digital twin model to provide complete input data for firmware generation.

[0087] S6: configuring the hardware template according to the hardware configuration parameters and the master chip, generating target hardware information, and generating burnable firmware information and hardware physical inventory based on the target hardware information.

[0088] Please refer to Figure 7 , Figure 7 An embodiment of step S6 is shown as follows:

[0089] S61: add the peripheral module and the master chip to the hardware template, and perform compatibility detection;

[0090] S62: if the compatibility detection passes, configure the hardware template based on the hardware configuration parameters to generate the target hardware information;

[0091] S63: generate the burnable firmware information and the hardware physical inventory according to the target hardware information.

[0092] Specifically, the hardware template defines the connection rules through the preset interface, and starts the automatic detection process after receiving the topological relationship between the peripheral module and the master chip. The compatibility detection stage cross- verifies the working voltage, communication protocol version and pin assignment logic of each module. When the I2C bus rate exceeds the support range of the master chip or the SPI chip selection signal is not correctly mapped, the system will return an error code and mark the conflict node. The configuration parameters detected will be injected into the hardware template to generate a complete circuit description file. The compilation tool calls the standardized driver library according to the file to generate a deployable firmware program, and the material management module extracts all component specifications to form a structured hardware bill of materials document.

[0093] Compatibility detection refers to matching verification of interface protocols and electrical parameters between the master chip and the peripheral module, which can be implemented by using a protocol consistency verification tool combined with a hardware parameter comparison algorithm, and is used to prevent signal level mismatch or communication protocol conflict. Hardware template refers to an editable framework that predefines hardware connection relationships, which can be used to build a topological structure by graphical drag-and-drop components, and is used to carry hardware configuration parameters to form a complete hardware solution. Burnable firmware information refers to a compiled binary executable file, which can be generated by using a cross-compilation tool chain combined with a driver adaptation layer, and can be directly written into the target device memory for running. Hardware physical inventory refers to a collection of bill of materials and interface definition documents, which can be automatically output by a BOM generator combined with an interface mapping table, and is used to guide component selection and assembly in the production process.

[0094] In the embodiments of the present application, components are converted into standardized digital twin models; a standardized hardware module library is constructed based on the standardized digital twin models, and a hardware intermediate layer is constructed; a component template is created through a graphical interface, and configuration information of a user-configured component is obtained based on the standardized digital twin models; the component template is configured based on the configuration information, a target component is generated, and the target component is saved to a component library; a hardware template is created through the graphical interface, a master chip is determined from the component library, and hardware configuration parameters are obtained through the hardware intermediate layer; the hardware template is configured according to the hardware configuration parameters and the master chip, target hardware information is generated, and burnable firmware information and a hardware physical inventory are generated based on the target hardware information. The embodiments of the present application construct a hardware module library and an intermediate layer through standardized digital twin models, realize hardware configuration automation in combination with a graphical interface, solve the problems of relying on manual experience and difficulty in cross-platform adaptation in the traditional development process, and have the advantages of reducing the development threshold, improving the cross-platform adaptation efficiency, and enhancing the soft and hardware collaborative design capability.

[0095] Please refer to Figure 8 , as an embodiment of the aboveFigure 1 To achieve the method, the application provides an embodiment of an artificial intelligence-based embedded development system, and the device embodiment corresponds to the method embodiment Figure 1 The device can be applied to various electronic devices.

[0096] As Figure 8 The artificial intelligence-based embedded development system of the embodiment includes a digital twin model construction module 71, a hardware module library construction module 72, a component template creation module 73, a target component generation module 74, a hardware template creation module 75, and a target hardware information generation module 76.

[0097] The digital twin model construction module 71 is configured to convert a component into a standardized digital twin model.

[0098] The hardware module library construction module 72 is configured to construct a standardized hardware module library based on the standardized digital twin model and construct a hardware intermediate layer.

[0099] The component template creation module 73 is configured to create a component template through a graphical interface and obtain configuration information of a user-configured component based on the standardized digital twin model.

[0100] The target component generation module 74 is configured to configure the component template based on the configuration information, generate a target component, and save the target component to a component library.

[0101] The hardware template creation module 75 is configured to create a hardware template through the graphical interface, determine a master control chip from the component library, and obtain hardware configuration parameters through the hardware intermediate layer.

[0102] The target hardware information generation module 76 is configured to configure the hardware template based on the hardware configuration parameters and the master control chip, generate target hardware information, and generate burnable firmware information and a hardware physical list based on the target hardware information.

[0103] Further, the digital twin model construction module 71 includes:

[0104] A data acquisition unit is configured to acquire component data manuals, chip pin definition diagrams, and business requirement documents.

[0105] A modeling unit is configured to parse the component data manuals to extract basic attributes of the components, generate a structured parameter table, and perform physical attribute digital modeling based on the structured parameter table to generate a physical attribute model file.

[0106] A mapping unit is configured to perform pin function mapping based on the chip pin definition diagram, to generate a pin function mapping file, and to construct a physical model description file based on the service requirement document;

[0107] A driver file generation unit is configured to generate a driver file according to a data manual register description and a historical driver library;

[0108] A standardized digital twin model generation unit is configured to perform digital twin model packaging based on the physical property model file, the pin function mapping file and the driver file, to generate the standardized digital twin model, and to store the standardized digital twin model into the component library.

[0109] Further, the hardware module library construction module 72 includes:

[0110] A module classification tree structure generation unit is configured to perform function dimension disassembly and module label generation according to a historical project hardware scheme and an industry device topology diagram, so as to generate a module classification tree structure;

[0111] A standardization unit is configured to perform pin interface standardization and communication protocol unification on the modules in the module classification tree structure, so as to obtain a target module classification tree structure;

[0112] A standardized hardware module library generation unit is configured to package the modules in the target module classification tree structure, so as to generate the standardized hardware module library;

[0113] A hardware intermediate layer construction unit is configured to construct the hardware intermediate layer based on the hardware parameters of the standardized digital twin model.

[0114] Further, the hardware intermediate layer construction unit includes:

[0115] A hardware capability list generation unit is configured to perform function semantic mapping on the hardware parameters of the standardized digital twin model, so as to generate a hardware capability list;

[0116] A dynamic adaptation unit is configured to construct a unified device API and a dynamic adaptation engine according to the hardware capability list, so as to construct the hardware intermediate layer.

[0117] Further, the component template creation module 73 includes:

[0118] A template creation request receiving unit is configured to receive a template creation request of a user, and to create the component template on the graphical interface according to the template creation request;

[0119] The configuration information generation unit is configured to acquire configuration information of the user configuration component from the standardized digital twin model, wherein the configuration information comprises component basic information, pin number, pin serial number, pin function, and physical model attribute.

[0120] Further, the hardware template creation module 75 comprises:

[0121] The hardware template creation request receiving unit is configured to receive a hardware template creation request of a user, and create the hardware template on the graphical interface according to the hardware template creation request.

[0122] The master control chip determination unit is configured to determine the master control chip from the component library, and receive a target peripheral module determined by the user.

[0123] The hardware configuration parameter acquisition unit is configured to acquire the hardware configuration parameter through the hardware intermediate layer, wherein the hardware configuration parameter comprises product basic information, terminal information, component information, and device physical model attribute information.

[0124] Further, the target hardware information generation module 76 comprises:

[0125] The compatibility detection unit is configured to add the peripheral module and the master control chip into the hardware template, and perform compatibility detection.

[0126] The configuration unit is configured to, if the compatibility detection passes, configure the hardware template based on the hardware configuration parameter, and generate the target hardware information.

[0127] The burnable firmware information generation unit is configured to generate the burnable firmware information and the hardware physical list according to the target hardware information.

[0128] To solve the above technical problems, the embodiment of the present application further provides an electronic device. For details, please refer to Figure 9 , Figure 9 The embodiment of the present application is a basic structure block diagram of the electronic device.

[0129] The electronic device 8 comprises a memory 81, a processor 82, and a network interface 83 which are connected to each other through a system bus and communicate with each other. It should be pointed out that, Figure 9The electronic device 8 is shown to have three components, a memory 81, a processor 82, and a network interface 83, but it is understood that not all of the illustrated components are required to be implemented, and more or fewer components can be implemented instead. As understood by one skilled in the art, the electronic device is a device capable of automatically performing numerical calculations and / or information processing according to pre-set or stored instructions, and the hardware thereof includes, but is not limited to, a microprocessor, an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), an embedded device, etc.

[0130] The electronic device can be a desktop computer, a notebook computer, a palm computer, a cloud server, or the like. The electronic device can interact with a user through a keyboard, a mouse, a remote controller, a touchpad, a voice control device, or the like.

[0131] The memory 81 includes at least one type of readable storage medium, such as a flash memory, a hard disk, a multimedia card, a card-type memory (e.g., an SD or DX memory, etc.), a random access memory (RAM), a static random access memory (SRAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a programmable read-only memory (PROM), a magnetic memory, a magnetic disk, an optical disk, etc. In some embodiments, the memory 81 can be an internal storage unit of the electronic device 8, such as a hard disk or a memory of the electronic device 8. In other embodiments, the memory 81 can also be an external storage device of the electronic device 8, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, etc. equipped on the electronic device 8. Of course, the memory 81 can include both an internal storage unit and an external storage device of the electronic device 8. In this embodiment, the memory 81 is generally used to store an operating system and various application software installed on the electronic device 8, such as program codes of the embedded development method based on artificial intelligence, etc. In addition, the memory 81 can also be used to temporarily store various data that have been output or will be output.

[0132] The processor 82 may, in some embodiments, be a central processing unit (CPU), a controller, a microcontroller, a microprocessor, or other data processing chip. The processor 82 is generally used to control the overall operation of the electronic device 8. In the present embodiment, the processor 82 is used to run program codes or process data stored in the memory 81, such as program codes of the above-mentioned artificial intelligence-based embedded development method, to implement various embodiments of the artificial intelligence-based embedded development method.

[0133] The network interface 83 may include a wireless network interface or a wired network interface, and is generally used to establish a communication connection between the electronic device 8 and other electronic devices.

[0134] The present application also provides another implementation, i.e., to provide a computer-readable storage medium, which stores a computer program, and the computer program can be executed by at least one processor to make the at least one processor execute the steps of an artificial intelligence-based embedded development method as described above.

[0135] From the above description of the embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software and the necessary general hardware platform, of course, they can also be implemented by hardware, but in many cases, the former is a better implementation. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as a ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for making a terminal device (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) execute the methods of various embodiments of the present application.

[0136] Obviously, the above-described embodiments are only some of the embodiments of the present application, not all the embodiments, and the preferred embodiments of the present application are given in the drawings, but do not limit the scope of the present application. The present application can be implemented in many different forms, and conversely, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing specific embodiments, or make equivalent replacements to some technical features. Any equivalent structure made by using the contents of the specification and drawings, directly or indirectly applied to other related technical fields, is also within the scope of protection of the present application.

Claims

1. An embedded development method based on artificial intelligence, characterized in that, include: Transform components into standardized digital twin models; A standardized hardware module library is constructed based on the standardized digital twin model, and a hardware middleware layer is built. Component templates are created through a graphical interface, and configuration information of user-configured components is obtained based on the standardized digital twin model. Based on the configuration information, the component template is configured to generate a target component, and the target component is saved to the component library. A hardware template is created through the graphical interface, the main control chip is determined from the component library, and hardware configuration parameters are obtained through the hardware middleware layer. Configure the hardware template according to the hardware configuration parameters and the main control chip, generate target hardware information, and generate programmable firmware information and hardware physical list based on the target hardware information; The construction of a standardized hardware module library based on the standardized digital twin model, and the construction of a hardware middleware layer, includes: Based on historical project hardware solutions and industry equipment topology diagrams, functional dimensions are broken down and module tags are generated to create a module classification tree structure. The pin interfaces of the modules in the module classification tree structure are standardized and the communication protocols are unified to obtain the target module classification tree structure; The modules in the target module classification tree structure are encapsulated to generate the standardized hardware module library; The hardware middleware layer is constructed based on the hardware parameters of the standardized digital twin model. The construction of the hardware middleware layer based on the parameters of the standardized digital twin model includes: The hardware parameters of the standardized digital twin model are mapped using functional semantics to generate a hardware capability list; Based on the hardware capability list, a unified device API and a dynamic adaptation engine are built to construct the hardware middleware layer.

2. The embedded development method based on artificial intelligence according to claim 1, characterized in that, The process of converting components into standardized digital twin models includes: Obtain component datasheets, chip pin definition diagrams, and business requirements documents; The component datasheet is analyzed to extract the basic attributes of the components, generate a structured parameter table, and perform digital modeling of physical attributes based on the structured parameter table to generate a physical attribute model file. Based on the chip pin definition diagram, pin functions are mapped to generate a pin function mapping file, and a construction model description file is built based on the business requirements document. Generate driver files based on the register descriptions in the datasheet and the historical driver library; Based on the physical property model file, the pin function mapping file, and the driver file, a digital twin model is encapsulated to generate the standardized digital twin model, and the standardized digital twin model is stored in the component library.

3. The embedded development method based on artificial intelligence according to claim 1, characterized in that, The step of creating component templates through a graphical interface and obtaining configuration information of user-configured components based on the standardized digital twin model includes: Receive a user's template creation request, and create the component template on the graphical interface according to the template creation request; The configuration information of the user-configured components is obtained based on the standardized digital twin model, wherein the configuration information includes basic component information, number of pins, pin serial number, pin function, and object model attributes.

4. The embedded development method based on artificial intelligence according to any one of claims 1 to 3, characterized in that, The steps of creating a hardware template through the graphical interface, determining the main control chip from the component library, and obtaining hardware configuration parameters through the hardware middleware layer include: Receive a user's hardware template creation request, and create the hardware template on the graphical interface according to the hardware template creation request; The main control chip is determined from the component library, and the target peripheral module determined by the user is received. The hardware configuration parameters are obtained through the hardware middleware layer, wherein the hardware configuration parameters include basic product information, terminal information, component information, and device object model attribute information.

5. The embedded development method based on artificial intelligence according to claim 4, characterized in that, The step of configuring the hardware template according to the hardware configuration parameters and the main control chip, generating target hardware information, and generating programmable firmware information and a hardware physical list based on the target hardware information includes: Add the peripheral module and the main control chip to the hardware template and perform compatibility testing; If the compatibility test passes, the hardware template is configured based on the hardware configuration parameters to generate the target hardware information; The programmable firmware information and the hardware physical list are generated based on the target hardware information.

6. An embedded development system based on artificial intelligence, characterized in that, include: The digital twin model building module is used to transform components into standardized digital twin models; The hardware module library construction module is used to construct a standardized hardware module library based on the standardized digital twin model and to construct a hardware middleware layer. The component template creation module is used to create component templates through a graphical interface and obtain configuration information of user-configured components based on the standardized digital twin model. The target component generation module is used to configure the component template based on the configuration information, generate a target component, and save the target component to the component library; The hardware template creation module is used to create hardware templates through the graphical interface, determine the main control chip from the component library, and obtain hardware configuration parameters through the hardware middleware layer. The target hardware information generation module is used to configure the hardware template according to the hardware configuration parameters and the main control chip, generate target hardware information, and generate programmable firmware information and hardware physical list based on the target hardware information. The hardware module library construction module includes: The module classification tree structure generation unit is used to decompose the functional dimensions and generate module tags based on the hardware solutions of historical projects and the topology diagram of industry equipment, so as to generate a module classification tree structure. The standardization unit is used to standardize the pin interfaces and unify the communication protocols of the modules in the module classification tree structure to obtain the target module classification tree structure; A standardized hardware module library generation unit is used to encapsulate the modules in the target module classification tree structure to generate the standardized hardware module library. The hardware capability list generation unit is used to perform functional semantic mapping on the hardware parameters of the standardized digital twin model to generate a hardware capability list. The dynamic adaptation unit is used to build a unified device API and a dynamic adaptation engine based on the hardware capability list to construct the hardware middleware layer.

7. An electronic device, characterized in that, It includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the artificial intelligence-based embedded development method as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the artificial intelligence-based embedded development method as described in any one of claims 1 to 5.

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