Universal measurement and control system data flow control bus architecture method and system

Abstract

The invention provides a universal measurement and control system data flow control bus architecture method and system, and relates to the technical field of measurement and control, and the method comprises the steps: distributing independent address spaces for a plurality of driving modules through a main control module, building a parameter mapping table and a buffer region, and enabling a plurality of test channels to share an interrupt signal and store the interrupt signal in an interrupt vector register; generating an interrupt signal based on a relationship between the buffer data volume and a threshold; sequencing according to the channel priority reference value, and dynamically adjusting the priority based on the load rate; and the main control module determines an interrupt source according to the interrupt vector and dynamically adjusts a prefetching strategy according to the measurement and control data flow. The system data processing efficiency and the resource utilization rate are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of measurement and control technology, and in particular to a general measurement and control system data flow control bus architecture method and system. BACKGROUND

[0002] With the rapid development of technology, measurement and control systems have been widely used in aerospace, industrial automation, energy management and other fields. A measurement and control system usually consists of a master control module and multiple drive modules, and needs to process a large amount of data flow and control signals. These systems require efficient data transmission capabilities, accurate control mechanisms and reliable real-time performance. Traditional measurement and control system data flow control usually adopts a fixed bus architecture, and uses a pre-set static configuration method in data transmission, interrupt processing and resource allocation.

[0003] The current measurement and control system has the following deficiencies in data flow control bus architecture: First, the traditional measurement and control system lacks flexibility in allocating address space to multiple test channels, usually using a fixed division method, resulting in low utilization of address resources and difficulty in optimizing and adjusting according to actual application requirements, especially when the number of test channels changes, the system architecture needs to be redesigned. Second, the existing interrupt processing mechanism generally adopts a fixed priority strategy, which cannot dynamically adjust the interrupt response order according to the actual running load, and in the case of high system load, high priority tasks may occupy system resources for a long time, causing the response of low priority but equally important test channels to be delayed too much. SUMMARY

[0004] The present application provides a general measurement and control system data flow control bus architecture method and system, which can solve the problems in the prior art.

[0005] In a first aspect of the present application, a general measurement and control system data flow control bus architecture method is provided, comprising:

[0006] The master control module allocates independent address space to multiple drive modules through a data bus and an address bus, the master control module sends parameter configuration information to the multiple drive modules, establishes a parameter mapping table for each test channel according to the verified parameter configuration information, and opens up a sending buffer and a receiving buffer according to the parameter mapping table;

[0007] The multiple test channels of the multiple test units share one interrupt signal, and multiple interrupt signals are stored in an interrupt vector register, the interrupt vector register is used to store the interrupt state of each test channel of each test unit;

[0008] When the amount of data in the sending buffer is less than a sending data interrupt threshold value, or the amount of data in the receiving buffer is greater than a receiving data interrupt threshold value, the test unit sets the interrupt state of the corresponding test channel in the interrupt vector register and generates a sending interrupt signal or a receiving interrupt signal;

[0009] A priority reference value corresponding to each test channel is determined, and interrupt requests of the multiple test channels are prioritized to generate an interrupt response queue; within a preset statistical time window, the active time and the interrupt count of each test channel are accumulated to calculate the load rate of each test channel, and the priority is dynamically adjusted according to the load rate;

[0010] The host module determines the test unit generating an interrupt and the test channel corresponding thereto according to the value of the interrupt vector register, reads the corresponding data length according to the test channel, judges whether to trigger data prefetching according to the test and control data flow, calculates the prefetching yield rate and dynamically adjusts the prefetching strategy when data prefetching is triggered.

[0011] The host module determines the test unit generating an interrupt and the test channel corresponding thereto according to the value of the interrupt vector register, and after reading the corresponding data length according to the test channel, the method further comprises:

[0012] If it is determined that a sending test channel generates an interrupt, the host module writes a data frame corresponding to the data length into the sending buffer according to the address space of the corresponding test unit, and when the amount of data in the sending buffer is greater than the sending data interrupt threshold value after writing, the test unit automatically clears the sending interrupt signal and clears the corresponding interrupt state in the interrupt vector register.

[0013] If it is determined that a receiving test channel generates an interrupt, the host module reads a data frame corresponding to the data length from the receiving buffer according to the address space of the corresponding test unit, and when the amount of data in the receiving buffer is less than the receiving data interrupt threshold value after reading, the test unit automatically clears the receiving interrupt signal and clears the corresponding interrupt state in the interrupt vector register.

[0014] The host module sends parameter configuration information to the multiple drive modules, establishes a parameter mapping table for each test channel according to the parameter configuration information that passes the verification, and separately opens a sending buffer and a receiving buffer according to the parameter mapping table, comprising:

[0015] The host module sends parameter configuration information to the drive module using a hierarchical structure, and the parameter configuration information includes global configuration layer parameters and channel configuration layer parameters.

[0016] The driving module receives the parameter configuration information, and performs validity verification on the parameter configuration information. A parameter mapping table is established for each test channel according to the parameter configuration information that passes the verification. The parameter mapping table includes a channel identifier, a channel type, a data frame format configuration, and an interrupt threshold setting.

[0017] The test unit calculates a sending buffer size and a receiving buffer size according to the parameter mapping table. The sending buffer size is the larger one of a product of a sending frame length and a buffer coefficient and a double value of a sending data interrupt threshold. The receiving buffer size is the larger one of a product of a receiving frame length and a buffer coefficient and a double value of a receiving data interrupt threshold.

[0018] The test unit allocates a starting address of the sending buffer and the receiving buffer according to a system memory alignment requirement, and establishes a buffer descriptor. The buffer descriptor includes a buffer base address, a read-write pointer, a data counter, and a state flag.

[0019] The multiple test channels of the multiple test units share one interrupt signal. The multiple interrupt signals are stored in an interrupt vector register. The interrupt vector register is used to store an interrupt state of each test channel of each test unit, and includes:

[0020] The multiple test channels of the multiple test units share one interrupt signal. The multiple interrupt signals of the multiple test channels are stored in an interrupt vector register. A bit width of the interrupt vector register is determined by a product of a total number of test units and a number of channels of each test unit. A position of each test channel in the interrupt vector register is determined by a sum of a product of a test unit number and the number of channels of each test unit and a channel number.

[0021] A priority reference value corresponding to each test channel is determined, and interrupt requests of the multiple test channels are prioritized to generate an interrupt response queue. In a preset statistical time window, an active time and an interrupt count of each test channel are accumulated to calculate a load rate of each test channel. The priority sorting is dynamically adjusted according to the load rate, and includes:

[0022] Queue state information of each test channel is obtained. A priority reference value of each test channel is calculated according to the queue state information according to the following formula:

[0023] The priority reference value = basic priority + waiting queue length / maximum queue length + waiting time / maximum waiting time.

[0024] The interrupt requests of the multiple test channels are prioritized based on the priority reference value to generate an interrupt response queue. A trigger time when each test channel enters the interrupt response queue is recorded in an interrupt state table.

[0025] Processing interrupt requests in sequence according to the order of the interrupt response queue, recording the interrupt response time of each test channel in the interrupt status table, and calculating the interrupt response time of each test channel according to the interrupt triggering time and the interrupt response time, wherein the interrupt response time includes interrupt detection time, priority arbitration time, and service processing time;

[0026] Within a preset statistical time window, the active time and interrupt count of each test channel are accumulated, the ratio of the active time to the statistical time window is recorded as the time occupancy rate, the ratio of the interrupt count to the interrupt processing capacity is recorded as the interrupt occupancy rate, and the load rate of each test channel is calculated based on the time occupancy rate and the interrupt occupancy rate:

[0027] Calculate the average load rate of the multiple test channels, and use the average of the absolute values ​​of the deviations between the load rate of each test channel and the average load rate as a load balancing factor; and dynamically adjust the priority ranking based on the comparison result of the load balancing factor and a preset load threshold.

[0028] Determine whether to trigger data prefetching based on the measurement and control data stream. When data prefetching is triggered, calculate the prefetching yield rate and dynamically adjust the prefetching strategy, including:

[0029] Recording the access time and number of times when the measurement and control data stream is written into the preset multi-level cache structure, generating a data stream access sequence, matching the data stream access sequence with a historical access sequence to obtain access pattern similarity, and determining whether to trigger data prefetching based on the access pattern similarity;

[0030] When data prefetching is triggered, the number of prefetch hits and prefetch misses is counted, the latency reduction caused by the prefetch hits is calculated, the prefetch yield rate is calculated based on the ratio of the latency reduction rate to the prefetch resource overhead, and the prefetch strategy is dynamically adjusted based on the prefetch yield rate;

[0031] determining a recent access time interval of the measurement and control data stream, calculating a temporal locality score for each measurement and control data stream based on the recent access time interval, using the temporal locality score as a data replacement priority, and selecting replacement data based on the data replacement priority when space in the preset multi-level cache structure is insufficient;

[0032] Count the number of dirty data in the preset multi-level cache structure, calculate the dirty data ratio, calculate the consistency maintenance overhead based on the dirty data ratio and the hierarchical position of the preset multi-level cache structure, and trigger cache consistency synchronization when the consistency maintenance overhead exceeds the preset overhead threshold.

[0033] A second aspect of an embodiment of the present invention provides a universal measurement and control system data flow control bus architecture system, including:

[0034] The first unit is configured to allocate independent address spaces to the plurality of driver modules via a data bus and an address bus by the main control module, send parameter configuration information to the plurality of driver modules, establish a parameter mapping table for each test channel according to the verified parameter configuration information, and respectively open a sending buffer and a receiving buffer according to the parameter mapping table;

[0035] A second unit, for multiple test channels of the multiple test units to share an interrupt signal, the multiple interrupt signals are stored in an interrupt vector register, and the interrupt vector register is used to store the interrupt status of each test channel of each test unit;

[0036] a third unit, configured to, when the amount of data in the sending buffer is less than the sending data interruption threshold, or when the amount of data in the receiving buffer is greater than the receiving data interruption threshold, set the interrupt status of the corresponding test channel in the interrupt vector register and generate a sending interruption signal or a receiving interruption signal;

[0037] The fourth unit is configured to determine a priority reference value corresponding to each test channel, prioritize the interrupt requests of the multiple test channels, and generate an interrupt response queue; within a preset statistical time window, accumulate the active time and interrupt count of each test channel to calculate the load rate of each test channel, and dynamically adjust the priority ranking according to the load rate;

[0038] The fifth unit is used for the main control module to determine the test unit that generates the interrupt and its corresponding test channel according to the value of the interrupt vector register, read the corresponding data length according to the test channel, and determine whether to trigger data prefetching according to the measurement and control data flow. When data prefetching is triggered, the prefetching yield rate is calculated and the prefetching strategy is dynamically adjusted.

[0039] According to a third aspect of an embodiment of the present invention, an electronic device is provided, including:

[0040] processor;

[0041] a memory for storing processor-executable instructions;

[0042] The processor is configured to call the instructions stored in the memory to execute the aforementioned method.

[0043] According to a fourth aspect of an embodiment of the present invention, a computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the method described above is implemented.

[0044] The beneficial effects of this application are as follows:

[0045] The present invention establishes a parameter mapping table for each test channel and opens a sending buffer and a receiving buffer respectively, thereby achieving effective management and scheduling of the measurement and control system data flow, avoiding data blocking and loss, and ensuring the integrity and accuracy of the measurement and control data.

[0046] The present invention realizes the rational allocation of measurement and control system resources by determining the priority reference value of the test channel and dynamically adjusting the priority sorting according to the load rate, improves the system response speed and processing efficiency, and effectively solves the priority conflict problem in multi-channel data flow control.

[0047] The present invention manages the interrupt status of multiple test units through an interrupt vector register, and combines a data prefetch mechanism with a dynamically adjusted prefetch strategy to reduce system waiting time, optimize the data transmission process, and improve the real-time performance and throughput of the overall measurement and control system. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 Schematic diagram of the flow of a data flow control bus architecture method for a measurement and control system generally used in an embodiment of the present invention;

[0049] Figure 2 A schematic diagram of a transmission and reception protocol between a driver module and a test module according to an embodiment of the present invention;

[0050] Figure 3 This is a flow chart of data transmission according to an embodiment of the present invention;

[0051] Figure 4 This is a flow chart of data reception according to an embodiment of the present invention. DETAILED DESCRIPTION

[0052] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0053] The following specific embodiments are used to describe the technical solution of the present invention in detail. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0054] Figure 1 This is a flow chart of a method for controlling the data flow of a measurement and control system according to an embodiment of the present invention. Figure 1As shown, the method includes:

[0055] The main control module allocates independent address spaces to the multiple driver modules through the data bus and the address bus, sends parameter configuration information to the multiple driver modules, establishes a parameter mapping table for each test channel according to the verified parameter configuration information, and opens a sending buffer and a receiving buffer according to the parameter mapping table;

[0056] The multiple test channels of the multiple test units share one interrupt signal, the multiple interrupt signals are stored in an interrupt vector register, and the interrupt vector register is used to store the interrupt status of each test channel of each test unit;

[0057] When the amount of data in the sending buffer is less than the sending data interruption threshold, or when the amount of data in the receiving buffer is greater than the receiving data interruption threshold, the test unit sets the interrupt status of the corresponding test channel in the interrupt vector register and generates a sending interruption signal or a receiving interruption signal;

[0058] Determine the priority reference value corresponding to each test channel, and prioritize the interrupt requests of multiple test channels to generate an interrupt response queue; within a preset statistical time window, accumulate the active time and interrupt count of each test channel to calculate the load rate of each test channel, and dynamically adjust the priority ranking according to the load rate;

[0059] The main control module determines the test unit that generates the interrupt and its corresponding test channel according to the value of the interrupt vector register, reads the corresponding data length according to the test channel, and determines whether to trigger data prefetching according to the measurement and control data flow. When data prefetching is triggered, the prefetching yield rate is calculated and the prefetching strategy is dynamically adjusted.

[0060] In an optional embodiment, after the main control module determines the test unit generating the interrupt and its corresponding test channel according to the value of the interrupt vector register and reads the corresponding data length according to the test channel, the method further includes:

[0061] If it is determined that the sending test channel generates an interrupt, the main control module writes a data frame corresponding to the data length into the sending buffer of the corresponding test unit according to the address space of the test unit. When the amount of data in the sending buffer after writing is greater than the sending data interrupt threshold, the test unit automatically clears the sending interrupt signal and clears the corresponding interrupt status in the interrupt vector register to zero;

[0062] If it is determined that a transmit channel of a test unit generates an interrupt, the host module reads a data frame corresponding to the data length from the transmit buffer of the test unit according to the address space of the test unit. When the amount of data in the transmit buffer is less than the transmit interrupt threshold value after the reading, the test unit automatically clears the transmit interrupt signal and clears the corresponding interrupt state in the interrupt vector register.

[0063] Exemplarily, the system comprises a host module and a plurality of test units, each test unit having a transmit channel and a receive channel. Each test unit has a unique address space, comprising a transmit buffer and a receive buffer. The system is further provided with an interrupt vector register for storing the interrupt state information of each test unit.

[0064] When an interrupt occurs, the host module first reads the value of the interrupt vector register, each bit of which corresponds to the interrupt state of a specific channel of a test unit. For example, in a system with 8 test units, the interrupt vector register can be a 16-bit register, in which bits 0 to 7 correspond to the transmit channel interrupt states of test units 1 to 8, and bits 8 to 15 correspond to the receive channel interrupt states of test units 1 to 8. A value of 1 indicates that the channel generates an interrupt, and a value of 0 indicates that the channel has no interrupt.

[0065] According to the value of the interrupt vector register, the host module determines the number of the test unit and the type of the channel that generates the interrupt. For example, if the value of the interrupt vector register is 0x0102 (binary 0000000100000010), it indicates that the transmit channel of test unit 2 and the receive channel of test unit 9 generate interrupts.

[0066] After determining the source of the interrupt, the host module reads the data length information of the corresponding channel. The data length can be stored in a specific register of the test unit, for example, the base address of the test unit is 0x1000, the transmit data length register address can be 0x1004, and the receive data length register address can be 0x1008.

[0067] For an interrupt generated by a transmit test channel, the processing flow is as follows:

[0068] 1. The host module determines that the transmit channel of test unit X generates an interrupt by reading the interrupt vector register;

[0069] 2. The host module reads the transmit data length register of test unit X to obtain the data length N bytes to be transmitted;

[0070] 3. The host module calculates the transmit buffer address of test unit X, for example, for test unit 1, the transmit buffer base address can be 0x1100;

[0071] 4. The master module writes N bytes of data into the transmit buffer. These data can be preset test data, such as an incrementing sequence (0x00, 0x01, 0x02...) or a specified test pattern;

[0072] 5. If the amount of data in the transmit buffer after the write exceeds the transmit data interrupt threshold, the test unit automatically clears the transmit interrupt signal;

[0073] 6. The test unit clears the corresponding bit in the interrupt vector register.

[0074] For example, assume that the transmit channel of test unit 1 generates an interrupt, the transmit data length is 256 bytes, the transmit buffer currently has 100 bytes of data, and the transmit data interrupt threshold is 300 bytes. After the master module writes 256 bytes of data into the transmit buffer, the amount of data in the buffer becomes 356 bytes, which exceeds the threshold of 300 bytes. Therefore, the test unit automatically clears the transmit interrupt and clears the 0th bit in the interrupt vector register.

[0075] For an interrupt generated by the receive test channel, the processing flow is as follows:

[0076] 1. The master module determines that the receive channel of test unit Y generated an interrupt by reading the interrupt vector register;

[0077] 2. The master module reads the receive data length register of test unit Y to obtain the data length M bytes that need to be read;

[0078] 3. The master module calculates the receive buffer address of test unit Y. For example, for test unit 2, the base address of the receive buffer can be 0x2200;

[0079] 4. The master module reads M bytes of data from the receive buffer and can perform data integrity verification and other operations;

[0080] 5. If the amount of data in the receive buffer after the read is less than the receive data interrupt threshold, the test unit automatically clears the receive interrupt signal;

[0081] 6. The test unit clears the corresponding bit in the interrupt vector register.

[0082] For example, assume that the receive channel of test unit 2 generates an interrupt, the receive data length is 512 bytes, the receive buffer currently has 600 bytes of data, and the receive data interrupt threshold is 200 bytes. After the master module reads 512 bytes of data from the receive buffer, the amount of data in the buffer becomes 88 bytes, which is lower than the threshold of 200 bytes. Therefore, the test unit automatically clears the receive interrupt and clears the 9th bit in the interrupt vector register.

[0083] By monitoring changes in the interrupt vector register in real time, the master control module can promptly respond to the data exchange needs of each test unit, achieving efficient data testing. In practical applications, the interrupt thresholds for sending and receiving data can be dynamically adjusted according to system requirements to optimize data exchange efficiency. For example, for high-speed data streams, a higher threshold can be set to reduce interrupt frequency; for situations requiring real-time response, a lower threshold can be set to increase response speed.

[0084] In addition, the system can set an interrupt mask register, allowing the main control module to selectively ignore interrupt requests from certain test units. The bit structure of the interrupt mask register is the same as that of the interrupt vector register. When a bit is set to 1, the interrupt request of the corresponding channel is masked. This mechanism can be used for system debugging and specific test scenarios.

[0085] Through the above-mentioned data interaction method based on the interrupt mechanism, the system can efficiently handle data interaction of multiple test units and multiple channels, fully utilize hardware resources, reduce the polling overhead of the main control module, and improve overall test efficiency.

[0086] In an optional embodiment, the main control module sends parameter configuration information to the multiple driver modules, establishes a parameter mapping table for each test channel according to the verified parameter configuration information, and opens a sending buffer and a receiving buffer respectively according to the parameter mapping table, including:

[0087] The main control module sends parameter configuration information to the driver module using a hierarchical structure, wherein the parameter configuration information includes global configuration layer parameters and channel configuration layer parameters;

[0088] After receiving the parameter configuration information, the driver module verifies the validity of the parameter configuration information and establishes a parameter mapping table for each test channel according to the verified parameter configuration information, wherein the parameter mapping table includes a channel identifier, a channel type, a data frame format configuration, and an interrupt threshold setting;

[0089] The test unit calculates the sending buffer size and the receiving buffer size according to the parameter mapping table, the sending buffer size being the larger value of the product of the sending frame length and the buffer coefficient and twice the value of the sending data interruption threshold; the receiving buffer size being the larger value of the product of the receiving frame length and the buffer coefficient and twice the value of the receiving data interruption threshold;

[0090] The test unit allocates the starting addresses of the sending buffer and the receiving buffer according to the system memory alignment requirement, and establishes a buffer descriptor, wherein the buffer descriptor includes a buffer base address, a read / write pointer, a data counter and a status flag.

[0091] The master control module uses a hierarchical structure to send parameter configuration information to the driver module. This hierarchical structure includes global configuration layer parameters and channel configuration layer parameters. Global configuration layer parameters apply to all test channels and include basic parameters such as system clock frequency (e.g., 100MHz), bus width (e.g., 32-bit), and interrupt mode (e.g., level trigger, edge trigger). Channel configuration layer parameters are specific to each test channel and include channel identifiers (e.g., CH_0, CH_1, CH_2), channel type (e.g., CAN, ARINC429, MIL-1553B), data frame format (e.g., standard frame, extended frame), communication rate (e.g., 1Mbps for CAN, 100Kbps for ARINC429), and interrupt threshold settings (e.g., transmit interrupt threshold of 8, receive interrupt threshold of 16).

[0092] Parameter configuration information is transmitted via the system bus using a predefined command format. For example, global configuration layer parameters use a command header beginning with 0xAA, followed by a parameter type identifier and specific parameter value; channel configuration layer parameters use a command header beginning with 0xBB, followed by a channel identifier, parameter type, and specific parameter value. Parameter transmission uses a handshake mechanism to ensure reliability. After sending configuration information, the master module waits for an acknowledgment signal from the driver module. If no acknowledgment is received within a timeout, the master module resends the information.

[0093] After receiving the parameter configuration information, the driver module first parses the instruction format, extracts the parameter type and value, and then performs validity verification. Validation includes parameter range verification, parameter combination logic verification, and hardware compatibility verification. For example, using a CAN channel, parameter range verification checks whether the communication rate is within the supported range (40 Kbps to 1 Mbps); parameter combination logic verification ensures that the data length does not exceed 8 bytes when the extended frame format is selected; and hardware compatibility verification confirms the number and type of channels supported by the current hardware platform. The verification process returns a verification result code: 0 indicates successful verification, while a non-zero value indicates a specific verification failure.

[0094] After verification, the driver module creates a parameter mapping table for each test channel. This parameter mapping table is implemented as an array of structures, each corresponding to a test channel. The structure contains fields such as channel identifier, channel type, data frame format configuration, and interrupt threshold settings. For example, for CAN channel CH_0, its parameter mapping table might contain: channel identifier = 0, channel type = CAN_TYPE (value = 1), data frame format = STANDARD_FRAME (value = 0), transmit interrupt threshold = 8, and receive interrupt threshold = 16. The parameter mapping table is stored in a fixed area of ​​system memory and is accessed by the test unit via a pointer.

[0095] The test unit calculates the required transmit and receive buffer sizes for each channel based on the parameter mapping table. The calculation formula takes into account the data frame length, buffering factor, and interrupt threshold settings. The transmit buffer size is the larger value of the transmit frame length multiplied by the buffering factor or twice the transmit data interrupt threshold. The receive buffer size is the larger value of the receive frame length multiplied by the buffering factor or twice the receive data interrupt threshold.

[0096] For example, assuming the standard CAN frame length is 16 bytes (including data and header), the buffer factor is 2.5, and the transmit interrupt threshold is 8, the transmit buffer size is calculated as: max(16 × 2.5, 8 × 2) = max(40, 16) = 40 bytes. Similarly, if the receive interrupt threshold is 16, the receive buffer size is: max(16 × 2.5, 16 × 2) = max(40, 32) = 40 bytes. The buffer factor is set to a balance between communication rate, system response time, and resource utilization, and is typically between 1.5 and 3.

[0097] After calculating the buffer size, the test unit allocates buffer space based on the system's memory alignment requirements. Alignment requirements are typically integer multiples of the system's word length, such as 4-byte alignment for 32-bit systems and 8-byte alignment for 64-bit systems. The allocation process uses memory management functions to ensure that the buffer's starting address meets the alignment requirements and returns a pointer to the allocated memory. For example, on a 32-bit system, if the calculated buffer size is 40 bytes, the actual allocated buffer size might be 44 bytes to meet 4-byte alignment.

[0098] After buffer allocation is complete, the test unit creates a buffer descriptor for each buffer. The buffer descriptor contains the buffer base address (e.g., 0x80010000), a read pointer (initial value equal to the base address), a write pointer (initial value equal to the base address), a data counter (initial value 0), and status flags (e.g., EMPTY, FULL, ERROR, etc.). The buffer descriptor manages data read and write operations at runtime. The read and write pointers are updated in a circular buffer fashion, wrapping back to the beginning when the end of the buffer is reached.

[0099] Through the above steps, the test system completes parameter configuration and buffer establishment, providing a foundation for subsequent data transmission and reception operations. This method improves the flexibility and stability of the system through layered parameter configuration, strict verification, and dynamic calculation of buffer size.

[0100] In an optional embodiment, the multiple test channels of the multiple test units share an interrupt signal, the multiple interrupt signals are stored in an interrupt vector register, and the interrupt vector register is used to store the interrupt status of each test channel of each test unit, including:

[0101] Multiple test channels of multiple test units share an interrupt signal, and the interrupt signals of the multiple test channels are stored in an interrupt vector register. The bit width of the interrupt vector register is determined by the product of the total number of test units and the number of channels of each test unit, and the position of each test channel in the interrupt vector register is determined by the product of the test unit number and the number of channels of each test unit and the sum of the channel number.

[0102] In this embodiment, multiple test channels across multiple test units share a single interrupt signal. This design reduces the number of interrupt signal lines in the system and simplifies hardware design. For example, in a system consisting of eight test units, each with four test channels, if each channel has a separate interrupt signal, a total of 32 interrupt signal lines would be required. This embodiment allows these signals to be combined into a single shared interrupt signal, significantly simplifying system design.

[0103] This implementation incorporates an interrupt vector register to store the interrupt status of each test channel in each test unit. The bit width of this register is calculated based on the product of the total number of test units and the number of channels in each test unit. For the example of a system with eight test units and four channels per test unit, the bit width of the interrupt vector register should be 8 × 4 = 32 bits.

[0104] In the interrupt vector register, each bit corresponds to the interrupt status of a specific test channel. To determine the location of a specific test channel in the interrupt vector register, this embodiment adopts a mapping algorithm: location index = test unit number × number of channels per test unit + channel number.

[0105] In specific implementation, when the system is initialized, the interrupt vector register is first configured. Assuming the system contains four test units (numbered 0 to 3), each test unit contains two channels (numbered 0 to 1), the bit width of the interrupt vector register is 4 × 2 = 8 bits. The system will allocate a corresponding position in the interrupt vector register for each test channel:

[0106] The corresponding position of channel 0 of test unit 0 is: 0×2+0=0 (bit 0);

[0107] The corresponding position of channel 1 of test unit 0 is: 0×2+1=1 (bit 1);

[0108] The corresponding position of channel 0 of test unit 1 is: 1×2+0=2 (second position);

[0109] Corresponding position of channel 1 of test unit 1: 1×2+1=3 (3rd position);

[0110] The corresponding position of channel 0 of test unit 2 is: 2×2+0=4 (the 4th position);

[0111] The corresponding position of channel 1 of test unit 2 is: 2×2+1=5 (5th position);

[0112] The corresponding position of channel 0 of test unit 3 is: 3×2+0=6 (the 6th position);

[0113] The corresponding position of channel 1 of test unit 3 is: 3×2+1=7 (the 7th position);

[0114] When a test channel triggers an interrupt during the test, the system performs the following steps:

[0115] 1. The test channel generates an interrupt signal, which is sent to the central processing unit;

[0116] 2. The system writes this interrupt signal to the corresponding position of the interrupt vector register. For example, if channel 1 of test unit 2 generates an interrupt, the system will set the 5th bit (position index: 2×2+1=5) of the interrupt vector register to 1;

[0117] 3. After receiving the interrupt signal, the CPU reads the interrupt vector register and checks which bits are set to 1 to determine which test channels have generated the interrupt.

[0118] 4. The CPU determines the priority interrupt source based on the information in the interrupt vector register and executes the corresponding interrupt service routine;

[0119] 5. After processing a specific interrupt, the CPU clears the corresponding bit in the interrupt vector register to indicate that the interrupt has been processed.

[0120] Assume that there are 16 test units in a chip test system, and each test unit has 8 test channels. According to this embodiment, the bit width of the interrupt vector register is 16×8=128 bits.

[0121] When the system is running, if channel 3 of test unit 5, channel 6 of test unit 9, and channel 2 of test unit 12 generate interrupts simultaneously, the system sets the following bits in the interrupt vector register to 1:

[0122] - Channel 3 of test unit 5: 5×8+3=43 (43rd bit);

[0123] - Channel 6 of test unit 9: 9×8+6=78 (78th bit);

[0124] - Channel 2 of test unit 12: 12×8+2=98 (98th bit);

[0125] After reading the interrupt vector register, the CPU finds bits 43, 78, and 98 are set to 1, confirming that the interrupts originated from these three test channels. Based on a pre-set priority strategy (e.g., low-order bits first or specific bits first), the processor determines which interrupt to handle first. For example, if the low-order bits first strategy is used, the interrupt from channel 3 of test unit 5 (bit 43) will be handled first, followed by the interrupt from channel 6 of test unit 9 (bit 78), and finally the interrupt from channel 2 of test unit 12 (bit 98).

[0126] After processing the first interrupt, the processor clears bit 43 of the interrupt vector register to indicate that the interrupt has been processed, and then continues to process the remaining interrupts.

[0127] This embodiment effectively solves the interrupt management problem in a multi-test unit multi-channel system through the design of a shared interrupt signal and interrupt vector register, reduces hardware complexity, improves system response efficiency, and supports flexible interrupt priority strategy implementation.

[0128] In an optional embodiment, determining a priority reference value corresponding to each test channel, and prioritizing interrupt requests from multiple test channels to generate an interrupt response queue; accumulating the active time and interrupt count of each test channel within a preset statistical time window to calculate a load rate of each test channel, and dynamically adjusting the priority order based on the load rate includes:

[0129] Obtain the queue status information of each test channel, and calculate the priority reference value of each test channel according to the queue status information using the following formula:

[0130] Priority benchmark value = basic priority + waiting queue length / maximum queue length + waiting time / maximum waiting time;

[0131] Prioritize the interrupt requests of the plurality of test channels based on the priority reference value, generate an interrupt response queue, and record the triggering moment of each test channel entering the interrupt response queue in an interrupt status table;

[0132] Processing interrupt requests in sequence according to the order of the interrupt response queue, recording the interrupt response time of each test channel in the interrupt status table, and calculating the interrupt response time of each test channel according to the interrupt triggering time and the interrupt response time, wherein the interrupt response time includes interrupt detection time, priority arbitration time, and service processing time;

[0133] Within a preset statistical time window, the active time and interrupt count of each test channel are accumulated, the ratio of the active time to the statistical time window is recorded as the time occupancy rate, the ratio of the interrupt count to the interrupt processing capacity is recorded as the interrupt occupancy rate, and the load rate of each test channel is calculated based on the time occupancy rate and the interrupt occupancy rate:

[0134] Calculate the average load rate of the multiple test channels, and use the average of the absolute values ​​of the deviations between the load rate of each test channel and the average load rate as a load balancing factor; and dynamically adjust the priority ranking based on the comparison result of the load balancing factor and a preset load threshold.

[0135] The system sets an initial base priority for each test channel. In actual applications, the base priority can be pre-configured according to business needs. For example, for critical business modules, the base priority can be set to 8; for general business modules, it can be set to 5; and for low-urgency modules, it can be set to 3.

[0136] The system obtains queue status information for each test channel in real time, including the current queue length, maximum queue length, current wait time, and maximum wait time. For example, for test channel A, the status information obtained might be: queue length 5, maximum queue length 10, wait time 300 milliseconds, and maximum wait time 1000 milliseconds.

[0137] Based on the queue status information obtained, the system will calculate the priority baseline value of the test channel. The calculation method is: add the basic priority, the ratio of the waiting queue length to the maximum queue length, and the ratio of the waiting time to the maximum waiting time. Taking the above-mentioned test channel A as an example, assuming its basic priority is 5, its priority baseline value is calculated as: 5 + (5 / 10) + (300 / 1000) = 6. For test channel B, if its basic priority is 3, the waiting queue length is 7, the maximum queue length is 10, the waiting time is 500 milliseconds, and the maximum waiting time is 1000 milliseconds, its priority baseline value is 3 + (7 / 10) + (500 / 1000) = 4.2.

[0138] Based on the calculated priority base value, the system sorts the interrupt requests from multiple test channels and creates an interrupt response queue. A higher priority base value indicates a higher position in the interrupt response queue. The system also records the trigger time of each test channel entering the interrupt response queue in the interrupt status table. For example, the trigger time for test channel A is 13:45:30.500, and the trigger time for test channel B is 13:45:30.600.

[0139] The system processes the interrupt requests in the order of the interrupt response queue. During the process, the system records the interrupt response time of each test channel. For example, the response time of test channel A is 13:45:30.550, and the response time of test channel B is 13:45:30.700. The system calculates the interrupt response time according to the trigger time and the response time, including the interrupt detection time, the priority arbitration time, and the service processing time. For test channel A, the interrupt response time is 50 milliseconds, which can be further divided into: interrupt detection time 10 milliseconds, priority arbitration time 5 milliseconds, and service processing time 35 milliseconds.

[0140] Within a preset statistical time window (for example, 10 minutes), the system accumulates the active time and the interrupt count of each test channel. Assuming that within the 10-minute window, the accumulated active time of test channel A is 120 seconds, and the interrupt count is 80 times; the accumulated active time of test channel B is 300 seconds, and the interrupt count is 50 times. The system calculates the time occupancy rate as the ratio of the active time to the statistical time window, and calculates the interrupt occupancy rate as the ratio of the interrupt count to the interrupt processing capacity.

[0141] If the interrupt processing capacity of the system is 200 times per 10 minutes, then the time occupancy rate of test channel A is 120 / 600 = 0.2, and the interrupt occupancy rate is 80 / 200 = 0.4; the time occupancy rate of test channel B is 300 / 600 = 0.5, and the interrupt occupancy rate is 50 / 200 = 0.25. The system calculates the load rate through the time occupancy rate and the interrupt occupancy rate, which can be calculated by weighted average, for example, load rate = time occupancy rate x 0.6 + interrupt occupancy rate x 0.4. Accordingly, the load rate of test channel A is 0.2 x 0.6 + 0.4 x 0.4 = 0.28; and the load rate of test channel B is 0.5 x 0.6 + 0.25 x 0.4 = 0.4.

[0142] The system calculates the average load rate of all test channels, which is (0.28 + 0.4) / 2 = 0.34 in this example. Then the absolute value of the deviation of the load rate of each test channel from the average load rate is calculated: 0.28 - 0.34 = 0.06 for test channel A, and 0.4 - 0.34 = 0.06 for test channel B. The average of all absolute deviation values is taken as the load balancing factor, which is (0.06 + 0.06) / 2 = 0.06 in this example.

[0143] The system compares the load balancing factor with a preset load threshold (for example, 0.1). If it is less than the threshold, it means that the system load distribution is relatively balanced; if it is greater than or equal to the threshold, it means that the system load distribution is uneven, and the priority needs to be dynamically adjusted. The adjustment method can be to increase the basic priority of the test channel with low load rate, or to reduce the basic priority of the test channel with high load rate.

[0144] For example, if the load balancing factor 0.06 is less than the threshold value 0.1, the existing priority setting is maintained; if the calculated load balancing factor is 0.15, which is greater than the threshold value 0.1, the system will increase the base priority of the test channel A with lower load rate from 5 to 6, or decrease the base priority of the test channel B with higher load rate from 3 to 2.

[0145] Through the above dynamic adjustment mechanism, the system can realize the balanced allocation of the test channel load, improve the overall processing efficiency and resource utilization rate, and ensure the timely response of the key business.

[0146] In an optional embodiment, whether to trigger data prefetching is judged according to the measurement and control data flow, when the data prefetching is triggered, the prefetching benefit rate is calculated and the prefetching strategy is dynamically adjusted, which includes:

[0147] The access time and access frequency when the measurement and control data flow writes the preset multi-level cache structure are recorded to generate a data flow access sequence, the data flow access sequence is matched with a historical access sequence to obtain an access mode similarity, whether to trigger data prefetching is judged according to the access mode similarity;

[0148] When the data prefetching is triggered, the prefetching hit frequency and the prefetching miss frequency are counted, the time delay reduction amount caused by the prefetching hit is calculated, the prefetching benefit rate is calculated according to the ratio of the time delay reduction amount to the prefetching resource overhead, and the prefetching strategy is dynamically adjusted based on the prefetching benefit rate;

[0149] The latest access time interval of the measurement and control data flow is determined, the time locality score of each measurement and control data flow is calculated according to the latest access time interval, the time locality score is taken as a data replacement priority, and when the preset multi-level cache structure is insufficient in space, the replacement data is selected according to the data replacement priority;

[0150] The number of dirty data in the preset multi-level cache structure is counted, the dirty data proportion is calculated, the consistency maintenance overhead is calculated according to the dirty data proportion and the hierarchical position of the preset multi-level cache structure, and the cache consistency synchronization is triggered when the consistency maintenance overhead exceeds the preset overhead threshold.

[0151] The present application sets a preset multi-level cache structure in the measurement and control data processing system, which includes at least three levels of cache: L1 cache (smallest capacity and fastest speed), L2 cache (moderate capacity and speed), and L3 cache (largest capacity and relatively slow speed). The system records the read and write operations of the measurement and control data flow in each level of cache in real time, including the access time and the access frequency.

[0152] For the judgment of the data stream access pattern, the system adopts the access sequence matching method. Specifically, the system takes the last N (for example, N = 100) data access records as the current access sequence, and compares it with the stored historical access sequence. The comparison method is to calculate the similarity of the current access sequence and the historical sequence. The similarity calculation adopts the sequence matching algorithm, and the number of the same data blocks accessed at the same position in the two sequences is divided by the total length of the sequence. For example, if the current sequence and a certain historical sequence access the same data block at 75 of the 100 positions, the similarity is 75%. When the similarity exceeds a preset threshold (such as 70%), the system considers that a stable access pattern is recognized, and triggers the data prefetching mechanism.

[0153] After triggering the data prefetching, the system will predict the data blocks that are likely to be accessed next according to the identified access pattern, and load these data from the low-speed storage device to the cache in advance. The system sets a prefetch depth parameter for each identified access pattern, and the initial value is set to 4, indicating that 4 data blocks that are likely to be accessed next are prefetched at a time.

[0154] The system continuously monitors the prefetching effect, and counts the number of prefetch hits and misses. The prefetch hit means that the prefetched data is indeed accessed by the subsequent operation; the prefetch miss means that the prefetched data is not accessed. At the same time, the system calculates the time delay saved by each prefetch hit. For example, if it takes 10 milliseconds to read a data block from the disk to the L3 cache, and it only takes 0.5 milliseconds to read from the L3 cache to the L1 cache, then each prefetch hit can save 9.5 milliseconds.

[0155] The calculation of the prefetch yield rate is based on the ratio of the time delay reduction amount to the prefetch resource overhead. The time delay reduction amount is equal to the number of prefetch hits multiplied by the time saved by each hit; the prefetch resource overhead includes the CPU time and additional energy consumption occupied by the prefetch operation. Assuming that the system has performed 200 prefetches in the past 5 minutes, of which 150 hits, and each hit saves 9.5 milliseconds, the total time delay reduction amount is 1425 milliseconds; if the 200 prefetches consume a total of 500 milliseconds of CPU time and additional energy consumption of 200 milliseconds, then the prefetch yield rate is 1425 / (500+200)≈2.04.

[0156] According to the prefetch yield rate, the system dynamically adjusts the prefetching strategy. When the yield rate is greater than a preset threshold (such as 1.5), the system increases the prefetch depth (the maximum is not more than 16); when the yield rate is less than another threshold (such as 0.8), the system reduces the prefetch depth (the minimum is not less than 1); when the yield rate is between the two thresholds, the current prefetch depth is kept unchanged.

[0157] For cache space management, the system introduces a data replacement mechanism based on temporal locality. The system records the recent access time of each data block, and calculates the time interval between two adjacent accesses. For data blocks with shorter intervals (showing stronger temporal locality), the system gives them higher retention priority; for data blocks with longer intervals, it gives them lower priority. Specifically, the system uses the inverse of the average access interval of a data block as the temporal locality score. For example, if the average interval of the last 5 accesses of a data block is 2 seconds, its temporal locality score is 0.5; if the average access interval of another data block is 10 seconds, its score is 0.1. When the cache space is insufficient and data needs to be replaced, the system replaces data blocks with lower scores first.

[0158] To maintain cache consistency, the system continuously monitors the number of dirty data (data that has been modified but has not yet been written back to the next level of storage) in each level of cache. The system calculates the dirty data ratio (the number of dirty data blocks divided by the total number of cache blocks), and determines the urgency of consistency maintenance according to the cache level position. For caches located at higher levels (such as L1), the allowed dirty data ratio threshold is lower; for low-level caches (such as L3), the allowed threshold is higher. For example, for L1 cache, the dirty data ratio threshold is set to 30%; for L2 cache, it is set to 50%; for L3 cache, it is set to 70%.

[0159] The consistency maintenance overhead calculation takes into account the dirty data ratio and cache level. When the dirty data ratio exceeds the threshold for the corresponding level, or there is data in the dirty data block that has not been synchronized for a long time (such as more than 5 minutes), the system triggers a cache consistency synchronization operation to write the dirty data back to the next level of storage, ensuring data consistency.

[0160] Through the above mechanisms, the present application realizes intelligent prefetching and efficient cache management of measurement and control data streams, significantly improving system performance and data access efficiency.

[0161] Reference Figures 1 to 4 A specific embodiment of the present application is as follows:

[0162] In the overall system of the embodiment of the present application, the main control module completes the issuance of data and instructions and the reception of data, the system is composed of multiple drive modules and test units, the main control module sends instructions and data information to different drive modules through a data bus and an address bus while reading back the received data information, each drive module is allocated an independent address space, and the drive modules and the test units use a general data interaction protocol to complete data transmission and reception.

[0163] The main control module sends parameter information to the drive module: sends data interrupt threshold, sends data length, sends data frame format and sends data information, and the main control module simultaneously sends write-receive data interrupt threshold, write data frame format, write-receive data frame length to the drive module.

[0164] After multiple test units simultaneously enter the system test flow, the test units individually open their own receiving buffer and sending buffer, the sending buffer stores the data frame information sent by the main control, and the receiving buffer stores the data frame information returned by the device under test; when the number of data in the sending buffer is less than the sending interrupt threshold, a sending interrupt signal is generated; multiple test channels of multiple test units share one interrupt signal, multiple interrupt signals form an interrupt vector register, and the interrupt vector register stores the interrupt signals of the corresponding module and the corresponding channel; when the main control module receives the interrupt signal, it enters the interrupt processing state, first reads the value of the interrupt vector, judges which test unit and which channel generate the interrupt, then reads the data length of the corresponding test unit and the corresponding channel; if it is a sending channel, the corresponding data length of data frame is directly written into the sending buffer of the corresponding address; when the amount of data in the buffer is greater than the sending interrupt threshold, the sending interrupt signal is automatically cleared, and the corresponding bit in the interrupt vector is cleared to zero; if it is a receiving channel, the length of the received data is read, and after reading is completed, the corresponding length of data is read from the receiving buffer at one time; when the amount of data in the receiving buffer is less than the receiving interrupt threshold, the receiving interrupt signal is automatically cleared, and the corresponding bit in the interrupt vector is cleared to zero.

[0165] The universal data flow control bus architecture system of the test and control system of the embodiment of the application comprises:

[0166] The first unit is configured to allocate independent address spaces to multiple drive modules by a data bus and an address bus by a main control module, the main control module sends parameter configuration information to the multiple drive modules, establishes a parameter mapping table for each test channel according to the verified parameter configuration information, and opens a sending buffer and a receiving buffer according to the parameter mapping table.

[0167] The second unit is configured to share one interrupt signal by multiple test channels of multiple test units, and multiple interrupt signals are stored in an interrupt vector register, and the interrupt vector register is configured to store the interrupt state of each test channel of each test unit.

[0168] The third unit is configured to set the interrupt state of the corresponding test channel in the interrupt vector register and generate a sending interrupt signal or a receiving interrupt signal when the amount of data in the sending buffer is less than the sending data interrupt threshold or the amount of data in the receiving buffer is greater than the receiving data interrupt threshold.

[0169] The fourth unit is configured to determine a priority reference value corresponding to each test channel, and to prioritize the interrupt requests of the multiple test channels to generate an interrupt response queue; in a preset statistical time window, the active time and the interrupt count of each test channel are accumulated to calculate the load rate of each test channel, and the priority is dynamically adjusted according to the load rate.

[0170] The fifth unit is configured to determine the test unit and the corresponding test channel generating the interrupt according to the value of the interrupt vector register, to read the corresponding data length according to the test channel, to determine whether to trigger data prefetching according to the test and control data flow, to calculate the prefetching yield rate and to dynamically adjust the prefetching strategy when data prefetching is triggered.

[0171] In a third aspect, an electronic device is provided, including:

[0172] a processor;

[0173] a memory for storing processor-executable instructions;

[0174] The processor is configured to invoke the instructions stored in the memory to execute the method described above.

[0175] In a fourth aspect, a computer-readable storage medium is provided, which stores computer program instructions, and the computer program instructions are executed by a processor to implement the method described above.

[0176] The present application can be a method, device, system and / or computer program product. The computer program product can include a computer readable storage medium having computer readable program instructions stored therein, which are used to perform various aspects of the present application.

[0177] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A general measurement and control system data flow control bus architecture method, characterized in that: include: The main control module allocates independent address spaces to the multiple driver modules through the data bus and the address bus, sends parameter configuration information to the multiple driver modules, establishes a parameter mapping table for each test channel according to the verified parameter configuration information, and opens a sending buffer and a receiving buffer according to the parameter mapping table; The multiple test channels of the multiple test units share one interrupt signal, the multiple interrupt signals are stored in an interrupt vector register, and the interrupt vector register is used to store the interrupt status of each test channel of each test unit; When the amount of data in the sending buffer is less than the sending data interruption threshold, or when the amount of data in the receiving buffer is greater than the receiving data interruption threshold, the test unit sets the interrupt status of the corresponding test channel in the interrupt vector register and generates a sending interruption signal or a receiving interruption signal; Determine the priority reference value corresponding to each test channel, and prioritize the interrupt requests of multiple test channels to generate an interrupt response queue; Within a preset statistical time window, the active time and interrupt count of each test channel are accumulated to calculate the load rate of each test channel, and the priority ranking is dynamically adjusted according to the load rate; The main control module determines the test unit that generates the interrupt and its corresponding test channel according to the value of the interrupt vector register, reads the corresponding data length according to the test channel, and determines whether to trigger data prefetching according to the measurement and control data flow. When data prefetching is triggered, the prefetching yield rate is calculated and the prefetching strategy is dynamically adjusted.

2. The method according to claim 1, characterized in that After the main control module determines the test unit generating the interrupt and its corresponding test channel according to the value of the interrupt vector register, and reads the corresponding data length according to the test channel, the method further includes: If it is determined that the sending test channel generates an interrupt, the main control module writes a data frame corresponding to the data length into the sending buffer of the corresponding test unit according to the address space of the test unit. When the amount of data in the sending buffer after writing is greater than the sending data interrupt threshold, the test unit automatically clears the sending interrupt signal and clears the corresponding interrupt status in the interrupt vector register to zero; If it is determined that an interrupt is generated in the receiving test channel, the main control module reads a data frame corresponding to the data length from its receiving buffer according to the address space of the corresponding test unit. When the amount of data in the receiving buffer after reading is less than the receiving data interrupt threshold, the test unit automatically clears the receiving interrupt signal and clears the corresponding interrupt status in the interrupt vector register.

3. The method according to claim 1, characterized in that The main control module sends parameter configuration information to the multiple driver modules, establishes a parameter mapping table for each test channel according to the verified parameter configuration information, and opens a sending buffer and a receiving buffer respectively according to the parameter mapping table, including: The main control module sends parameter configuration information to the driver module using a hierarchical structure, wherein the parameter configuration information includes global configuration layer parameters and channel configuration layer parameters; After receiving the parameter configuration information, the driver module verifies the validity of the parameter configuration information and establishes a parameter mapping table for each test channel according to the verified parameter configuration information, wherein the parameter mapping table includes a channel identifier, a channel type, a data frame format configuration, and an interrupt threshold setting; The test unit calculates the sending buffer size and the receiving buffer size according to the parameter mapping table, the sending buffer size being the larger value of the product of the sending frame length and the buffer coefficient and twice the value of the sending data interruption threshold; the receiving buffer size being the larger value of the product of the receiving frame length and the buffer coefficient and twice the value of the receiving data interruption threshold; The test unit allocates the starting addresses of the sending buffer and the receiving buffer according to the system memory alignment requirement, and establishes a buffer descriptor, wherein the buffer descriptor includes a buffer base address, a read / write pointer, a data counter and a status flag.

4. The method according to claim 1, wherein The multiple test channels of the multiple test units share an interrupt signal, the multiple interrupt signals are stored in an interrupt vector register, and the interrupt vector register is used to store the interrupt status of each test channel of each test unit, including: Multiple test channels of multiple test units share an interrupt signal, and the interrupt signals of the multiple test channels are stored in an interrupt vector register. The bit width of the interrupt vector register is determined by the product of the total number of test units and the number of channels of each test unit, and the position of each test channel in the interrupt vector register is determined by the product of the test unit number and the number of channels of each test unit and the sum of the channel number.

5. The method according to claim 1, wherein Determining a priority reference value corresponding to each test channel, and prioritizing interrupt requests of multiple test channels to generate an interrupt response queue; accumulating the active time and interrupt count of each test channel within a preset statistical time window to calculate the load rate of each test channel, and dynamically adjusting the priority order according to the load rate includes: Obtain the queue status information of each test channel, and calculate the priority reference value of each test channel according to the queue status information using the following formula: Priority benchmark value = basic priority + waiting queue length / maximum queue length + waiting time / maximum waiting time; Prioritize the interrupt requests of the plurality of test channels based on the priority reference value, generate an interrupt response queue, and record the triggering moment of each test channel entering the interrupt response queue in an interrupt status table; Processing interrupt requests in sequence according to the order of the interrupt response queue, recording the interrupt response time of each test channel in the interrupt status table, and calculating the interrupt response time of each test channel according to the interrupt triggering time and the interrupt response time, wherein the interrupt response time includes interrupt detection time, priority arbitration time, and service processing time; Within a preset statistical time window, the active time and interrupt count of each test channel are accumulated, the ratio of the active time to the statistical time window is recorded as the time occupancy rate, the ratio of the interrupt count to the interrupt processing capacity is recorded as the interrupt occupancy rate, and the load rate of each test channel is calculated based on the time occupancy rate and the interrupt occupancy rate: Calculate the average load rate of the multiple test channels, and use the average of the absolute values ​​of the deviations between the load rate of each test channel and the average load rate as a load balancing factor; and dynamically adjust the priority ranking based on the comparison result of the load balancing factor and a preset load threshold.

6. The method according to claim 1, characterized in that Determine whether to trigger data prefetching based on the measurement and control data stream. When data prefetching is triggered, calculate the prefetching yield rate and dynamically adjust the prefetching strategy, including: Recording the access time and number of times when the measurement and control data stream is written into the preset multi-level cache structure, generating a data stream access sequence, matching the data stream access sequence with a historical access sequence to obtain access pattern similarity, and determining whether to trigger data prefetching based on the access pattern similarity; When data prefetching is triggered, the number of prefetch hits and prefetch misses is counted, the latency reduction caused by the prefetch hits is calculated, the prefetch yield rate is calculated based on the ratio of the latency reduction rate to the prefetch resource overhead, and the prefetch strategy is dynamically adjusted based on the prefetch yield rate; determining a recent access time interval of the measurement and control data stream, calculating a temporal locality score for each measurement and control data stream based on the recent access time interval, using the temporal locality score as a data replacement priority, and selecting replacement data based on the data replacement priority when space in the preset multi-level cache structure is insufficient; Count the number of dirty data in the preset multi-level cache structure, calculate the dirty data ratio, calculate the consistency maintenance overhead based on the dirty data ratio and the hierarchical position of the preset multi-level cache structure, and trigger cache consistency synchronization when the consistency maintenance overhead exceeds the preset overhead threshold.

7. A universal measurement and control system data flow control bus architecture system, used to implement the method according to any one of claims 1 to 6, characterized in that: include: The first unit is configured to allocate independent address spaces to the plurality of driver modules via a data bus and an address bus by the main control module, send parameter configuration information to the plurality of driver modules, establish a parameter mapping table for each test channel according to the verified parameter configuration information, and respectively open a sending buffer and a receiving buffer according to the parameter mapping table; A second unit, for multiple test channels of the multiple test units to share an interrupt signal, the multiple interrupt signals are stored in an interrupt vector register, and the interrupt vector register is used to store the interrupt status of each test channel of each test unit; a third unit, configured to, when the amount of data in the sending buffer is less than the sending data interruption threshold, or when the amount of data in the receiving buffer is greater than the receiving data interruption threshold, set the interrupt status of the corresponding test channel in the interrupt vector register and generate a sending interruption signal or a receiving interruption signal; The fourth unit is used to determine the priority reference value corresponding to each test channel, and prioritize the interrupt requests of multiple test channels to generate an interrupt response queue; Within a preset statistical time window, the active time and interrupt count of each test channel are accumulated to calculate the load rate of each test channel, and the priority ranking is dynamically adjusted according to the load rate; The fifth unit is used for the main control module to determine the test unit that generates the interrupt and its corresponding test channel according to the value of the interrupt vector register, read the corresponding data length according to the test channel, and determine whether to trigger data prefetching according to the measurement and control data flow. When data prefetching is triggered, the prefetching yield rate is calculated and the prefetching strategy is dynamically adjusted.

8. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to execute the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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