Timed task execution method, system, equipment and medium

Abstract

The invention discloses a timed task execution method, system and device and a medium, and particularly relates to the technical field of interruption timing, and the technical key points are as follows: based on a pulse edge of a received pulse signal, triggering kernel interruption and sending an event to an application layer; and the application layer executes the periodic timed task according to the event period and a preset application layer control logic. Kernel interruption is directly triggered through a pulse edge, an event is sent to an application layer, a polling-free link of ''interruption triggering-event pushing-task execution'' is realized by binding GPIO interruption with a kernel event notification mode, polling or high-frequency interruption is replaced, and the CPU occupancy rate of a system is reduced; a timing function is realized by using a general purpose input / output (GPIO) interface without depending on a specific hardware clock source, an embedded platform without a high-precision clock module is supported, and the hardware cost is reduced; and meanwhile, signal transmission delay fluctuation is avoided through a closed loop circuit design, and high reliability can still be kept in an electromagnetic interference complex environment.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of interrupt timing, in particular to a timing task execution method, system, device and medium. BACKGROUND

[0002] At present, the Linux system provides a multi-level timer mechanism to meet the needs of different precision and application scenarios. The main technologies include: jiffies based on system clock interrupt (tick), time wheel managed by multi-level linked list, hrtimer technology supporting higher precision timing based on red-black tree management, and event-triggering mechanism instead of periodic tick interrupt.

[0003] Although the current timing technology can meet the needs of some industrial automation products, it is still insufficient for products with high real-time requirements and strict jitter requirements. First, the timing accuracy of jiffies and time wheel technology is too low, and sometimes the jitter is as high as tens of microseconds. Second, the hrtimer technology can provide higher precision timing requirements, but it will increase CPU overhead, and the timing jitter also cannot meet the needs of some strict industrial products.

[0004] Therefore, the present application aims to provide a timing task execution method, system, device and medium to solve the above-mentioned related problems. SUMMARY

[0005] The technical problem to be solved by the present application is that the existing Linux timing technology cannot meet the needs of some industrial products for high real-time and low jitter. The purpose is to provide a timing task execution method, system, device and medium, which directly triggers a kernel interrupt and sends an event to the application layer based on the pulse edge of the received pulse signal, uses the binding of GPIO interrupt and kernel event notification method to realize the "interrupt trigger-event push-task execution" non-polling link, replaces polling or high-frequency interrupt, reduces system CPU occupancy, and is suitable for high-concurrency low-power consumption scenarios; by not relying on a specific hardware clock source, using a general GPIO interface to realize timing function, supporting embedded platforms without high-precision clock modules, and reducing hardware cost; at the same time, through the closed loop circuit design, signal transmission delay fluctuation is avoided, and high reliability can still be maintained in complex electromagnetic interference environments.

[0006] The present application is realized by the following technical solutions: A timing task execution method, the method comprising: triggering a kernel interrupt and sending an event to the application layer based on the pulse edge of the received pulse signal; wherein the event carries event information, and the event information includes an event period; The application layer executes the periodic timing task according to the preset application layer control logic according to the event period.

[0007] Further, based on the pulse edge of the received pulse signal, a kernel interrupt is triggered and an interrupt event is sent to the application layer, specifically: A pulse signal is generated by using a pulse generator, and the pulse signal is input to a GPIO pin through a pre-constructed loop circuit. The GPIO pin detects the pulse signal, and after detecting the pulse edge of the pulse signal, triggers a kernel interrupt and calls a pre-constructed interrupt service program to record an interrupt timestamp; the kernel pushes an event to the application layer after the interrupt.

[0008] Further, the method further comprises: The application layer listens to events through a poll interface, and the application program is in a blocked state when there is no event triggering; the application layer wakes up the blocked application layer task when there is an event triggering.

[0009] Further, the application layer wakes up the blocked application layer task when there is an event triggering, specifically: when there is an event triggering, the application layer wakes up the blocked application layer task through an eventfd or shared memory.

[0010] The application further comprises a timing task execution system, which is used in the timing task execution method described in any one of the above, and the system comprises: An interrupt triggering module is configured to trigger a kernel interrupt based on the pulse edge of the received pulse signal and send an event to the application layer; wherein the event carries event information, and the event information includes an event period. A task execution module is configured to execute a periodic timing task according to a preset application layer control logic according to the event period.

[0011] Further, based on the pulse edge of the received pulse signal, a kernel interrupt is triggered and an interrupt event is sent to the application layer, specifically: A pulse signal is generated by using a pulse generator, and the pulse signal is input to a GPIO pin through a pre-constructed loop circuit. The GPIO pin detects the pulse signal, and after detecting the pulse edge of the pulse signal, triggers a kernel interrupt and calls a pre-constructed interrupt service program to record an interrupt timestamp; the kernel pushes an event to the application layer after the interrupt.

[0012] Further, the system further comprises: The application layer listens to events through a poll interface, and the application program is in a blocked state when there is no event triggering; the application layer wakes up the blocked application layer task when there is an event triggering.

[0013] The application further provides a computer device comprising a system memory and a processor, wherein the system memory stores a computer program, and the processor implements the steps of the method according to any one of the preceding method embodiments when executing the computer program.

[0014] The application further provides a computer readable storage medium, which stores a computer program, and the computer program implements the steps of the method according to any one of the preceding method embodiments when executed by a processor.

[0015] The application further provides a computer program product comprising instructions which, when executed by a cluster of computer devices, cause the cluster of computer devices to perform the method according to any one of the preceding method embodiments.

[0016] Compared with the prior art, the application has the following advantages and beneficial effects: In the application, the kernel interrupt is directly triggered and the event is sent to the application layer based on the pulse edge of the received pulse signal, the binding of the GPIO interrupt and the kernel event notification mode is utilized, the non-polling link of 'interrupt triggering->event pushing->task execution' is realized, the polling or high-frequency interrupt is replaced, the system CPU occupancy is reduced, and the application is suitable for high-concurrency and low-power consumption scenarios; the timing function is realized by utilizing the general GPIO interface without depending on a specific hardware clock source, the embedded platform without a high-precision clock module is supported, and the hardware cost is reduced; meanwhile, the signal transmission delay fluctuation is avoided by the closed-loop circuit design, and high reliability can be maintained in a complex electromagnetic interference environment. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the example embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the application, and therefore should not be considered as limiting the scope. For those skilled in the art, other related drawings can also be obtained without creative labor. In the drawings: Figure 1 The method flowchart of the timing task execution method in the embodiment is shown in the figure; Figure 2 The circuit schematic diagram of the closed-loop circuit in the embodiment is shown in the figure; Figure 3 The module connection schematic diagram of the timing task execution system in the embodiment is shown in the figure; Figure 4 The structure schematic diagram of the computer device in the embodiment is shown in the figure. DETAILED DESCRIPTION

[0018] Exemplary embodiments of the present disclosure are described herein below with reference to the accompanying drawings, in which various details of embodiments of the present disclosure are set forth in order to provide a thorough understanding of the present disclosure. It will be apparent, however, to those skilled in the art that various changes and modifications can be made to the embodiments described herein without departing from the scope of the present disclosure. Also, the description set forth herein is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure. As used herein, the term "comprises" is intended to mean that there is a possibility of including the listed elements, not excluding other elements.

[0019] In the present disclosure, the terms "first", "second", and the like are used to describe various elements only and do not intend to limit the positional relationship, the timing relationship, or the importance of the elements, and the terms are used only to distinguish one element from another element. In some examples, the first element and the second element can refer to the same instance of the element, and in some cases, based on the context of the description, they can also refer to different instances.

[0020] The terms used in the description of various examples in the present disclosure are only for the purpose of describing the specific examples and are not intended to be limiting. Unless the number of elements is specifically limited, the element can be one or more than one, if the number of elements is not specifically limited. In addition, the term "and / or" used in the present disclosure encompasses any one of the listed items and all possible combinations thereof.

[0021] Embodiment 1 Referring to Figure 1 , Figure 1 A method flow diagram of a timing task execution method is shown, wherein the method comprises: S1: triggering a kernel interrupt and sending an event to an application layer based on a pulse edge of a received pulse signal; wherein the event carries event information, and the event information includes an event period; Specifically, in the present embodiment, a pulse signal is first generated by a pulse generator, and the pulse signal is input to a GPIO pin through a pre-constructed loop circuit. The GPIO pin detects the pulse signal, and after detecting the pulse edge of the pulse signal, triggers a kernel interrupt and calls a pre-constructed interrupt service program to record an interrupt timestamp. The kernel pushes an event to the application layer after the interrupt.

[0022] It should be noted that in the present embodiment, a high-precision pulse signal (the precision can reach nanoseconds) is generated by a pulse generator, and the signal frequency can be dynamically configured, so as to avoid kernel timer jitter through an external high-speed pulse signal, completely separate from the kernel timer subsystem, and the timing precision is determined by hardware, so as to eliminate timing jitter caused by system scheduling and interrupt delay, and the timing precision is improved to the hardware limit. The pulse signal is looped back to the GPIO pin of the CPU to form a closed-loop detection path, referring to Figure 2 , Figure 2A circuit schematic diagram of the loopback loop is shown, Figure 2 The IRQ in the block is a loopback signal, which is looped back from the PH14 port of the pulse transmitter to the PA7 port of the CPU processor; after the GPIO pin detects the pulse edge, a hardware interrupt is triggered, and then an interrupt service program (ISR) is called to record the interrupt timestamp, wherein the interrupt service program is built in advance by the driver designer and is mainly used for recording the timestamp and marking and processing events (eventfd), registering the GPIO interrupt service program (ISR), configuring the edge trigger mode (rising edge / falling edge), modifying the interrupt affinity and priority according to the application requirement, and using the event mechanism in the interrupt processing function to notify the application layer; the pulse frequency adjustment is supported to adjust the timing time according to the user requirement, and this technology is a conventional technical means in the field, which will not be described in detail here; after the interrupt is triggered, an event is pushed to the application layer by the kernel, a periodic task is triggered based on the event (the period is determined by the pulse signal period), and the scheduling delay of the traditional timer is eliminated. Meanwhile, it should be noted that a GPIO pin supporting high-speed interrupt (such as a dedicated interrupt pin) is selected, and a current-limiting resistor and a TVS diode are connected in series to prevent overvoltage / overcurrent damage to the pin.

[0023] S2: The application layer executes a periodic timing task according to a preset application layer control logic according to the event period.

[0024] Specifically, in this embodiment, the application layer first performs event listening through a poll interface, and the application program is in a blocked state when there is no event triggering; when there is event triggering, the application layer wakes up the blocked application layer task through eventfd or shared memory; and then the application layer executes a periodic timing task according to a preset application layer control logic according to the event period.

[0025] It should be noted that in this embodiment, the event period is determined by the pulse signal period, and by adjusting the pulse signal period, different timing time requirements can be met; at the same time, a timing task is created, and the period is set to 400us; the task sends a pulse signal to the opposite FPGA, which is used as a synchronization enable signal at the FPGA end and also as a periodic signal of the timing task, so as to realize synchronous communication with the FPGA before and ensure the integrity of data between the two.

[0026] Meanwhile, it should be noted that in this embodiment, the application layer control logic is determined according to the application requirement, and this technical content is a conventional technical means in the field, which will not be described in detail here; for example, in this application, the application layer control logic is as follows: after receiving the kernel event, a communication protocol is sent to the FPGA end through the LBC bus communication interface provided by the system, and then data from the FPGA is received through the LBC bus again, and a complete data protocol communication with the FPGA is performed once.

[0027] Specifically, in the embodiment, by cooperating the hardware pulse signal with the system interrupt technology, the PLC application program does not need to use the jiffies mechanism to implement a timing task, the problem of high jitter is solved, the real-time performance and stability of product operation are ensured; the timing task is implemented on the hardware, and the kernel notifies the application layer in the form of an event, so that the application does not need to poll the task all the time, and the system overhead of the application is reduced; the application layer is encapsulated with the file system interface, the application can conveniently adjust the pulse width, so that the period of the timing task is changed, and the timing implemented on the hardware level also ensures the accuracy of time.

[0028] In another embodiment, the interrupt service program can be further optimized, the interrupt service program only performs key operations (such as setting a flag and recording a timestamp), the time consumption is controlled to be less than 1 μs, the interrupt priority is configured, and event loss caused by high-priority interrupt preemption is avoided.

[0029] Embodiment 2 Referring to Figure 3 The application further includes a timing task execution system, which is used in the timing task execution method described in any one of the preceding embodiments, and the system includes: An interrupt triggering module 100 is configured to trigger a kernel interrupt and send an event to an application layer based on a pulse edge of a received pulse signal, wherein the event carries event information, and the event information includes an event period. A task execution module 200 is configured to execute a periodic timing task according to a preset application layer control logic based on the event period.

[0030] Further, the kernel interrupt is triggered and the interrupt event is sent to the application layer based on the pulse edge of the received pulse signal, specifically, a pulse generator is used to generate a pulse signal, the pulse signal is input to a GPIO pin through a pre-constructed loop circuit; the GPIO pin detects the pulse signal, and after detecting the pulse edge of the pulse signal, the kernel interrupt is triggered and a pre-constructed interrupt service program is called to record an interrupt timestamp; the kernel pushes the event to the application layer after the interrupt.

[0031] Further, the system further includes that the application layer listens to the event through a poll interface, and the application program is in a blocked state when there is no event triggering; the application layer wakes up the blocked application layer task when there is an event triggering.

[0032] It should be noted that the modules in the system of embodiment 2 correspond to the steps in the method of embodiment 1, and the steps in the method of embodiment 1 have been described in detail in embodiment 1, and the content of the modules in the system will not be described in detail in embodiment 2.

[0033] Embodiment 3 Referring to Figure 4 As shown in the figure, the embodiment further provides a computer device including a system memory 1005 and a processor 1001, the system memory 1005 stores a computer program, and the processor 1001 implements the steps of the method of any one of the above embodiments when executing the computer program.

[0034] It should be noted that the processor 1001 is configured to execute the steps of the above method embodiments according to the instructions in the program code. Alternatively, the processor 1001 implements the functions of each module / unit in the above system / device embodiments when executing the computer program.

[0035] Specifically, in the embodiment, the computer program can be divided into one or more modules / units, and the one or more modules / units are stored in the system memory 1005 and executed by the processor 1001 to complete the present application. The one or more modules / units can be a series of computer program instruction segments capable of completing a specific function, which are used to describe the execution process of the computer program in the terminal device.

[0036] The terminal device can be a desktop computer, a notebook, a palm computer, and a cloud server, etc. The terminal device can include, but is not limited to, the processor 1001 and the system memory 1005. Those skilled in the art can understand that it does not constitute a limitation on the terminal device, and can include more or less components than the figure, or combine certain components, or different components, for example, the terminal device can also include an input / output device 1003, a network access device 1002, a bus 1006, etc.

[0037] The processor 1001 can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor.

[0038] The system memory 1005 can be an internal storage unit of the terminal device, for example, a hard disk or a memory of the terminal device. The system memory 1005 can also be a storage device 1004 of the terminal device, for example, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the terminal device. Further, the system memory 1005 can also include both the internal storage unit of the terminal device and the storage device 1004. The system memory 1005 is used to store computer programs and other programs and data required by the terminal device. The system memory 1005 can also be used to temporarily store data that has been output or will be output.

[0039] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, system and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be described here.

[0040] Embodiment 4 The embodiment provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the steps of the method in any one of the above embodiments.

[0041] The computer readable storage medium may, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared or semiconductor system, system or device, or any combination of the above. More specific examples (non-exhaustive list) of the computer readable storage medium include an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a register, a hard disk, an optical fiber, a compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above, or any other form of computer readable storage medium known in the art.

[0042] An example storage medium is coupled to the processor such that the processor can read information from, and can write information to, the storage medium. Of course, the storage medium can be a part of the processor. Consistent with the teachings provided herein, a processor (or multiple processors) can be used to implement a controller, or portions of a controller. The processor and the storage medium can be located in a single ASIC chip. In an embodiment of the application, the computer-readable storage medium can be embodied in a computer program product that can include software. Software can be in the form of source code, object code, executable code, or other formats. Software can be compiled or interpreted. Drive, disk, and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray Disc (BD) where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable storage media. Moreover, transmission media such as carrier waves can be employed to carry also computer-readable code sequences. A computer-readable storage medium can be any medium that can be accessed by a computer. By way of example, and not limitation, such computer- readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired computer code in a form

[0043] Embodiment 5 This embodiment also provides a computer program product containing instructions which, when executed by a cluster of computer devices, cause the cluster of computer devices to perform the method as described in embodiment 1.

[0044] The above detailed description merely describes exemplary embodiments of the application, and is not intended to limit the scope of the application. The embodiments described above are merely given as examples and are not intended to limit the scope of the application. The scope of the application is limited only by the claims.

Claims

1. A method for executing a scheduled task, characterized in that: Methods include: Based on the pulse edge of the received pulse signal, triggering a kernel interrupt and sending an event to the application layer; wherein the event carries event information, and the event information includes an event period; The application layer executes periodic timing tasks according to the preset application layer control logic based on the event cycle.

2. A method for executing a scheduled task according to claim 1, characterized in that: Based on the pulse edge of the received pulse signal, the kernel interrupt is triggered and an interrupt event is sent to the application layer. Specifically: Generate a pulse signal using a pulse generator, and input the pulse signal to the GPIO pin through a pre-built loopback circuit; The GPIO pin detects the pulse signal, and after detecting the pulse edge of the pulse signal, it triggers a kernel interrupt and calls the pre-built interrupt service routine to record the interrupt timestamp; The kernel pushes events to the application layer after the interrupt.

3. A scheduled task execution method according to claim 1, characterized in that: The method also includes: The application layer monitors events through the poll interface. When no event is triggered, the application is in a blocked state. When an event is triggered, the application layer wakes up the blocked application layer task.

4. A method for executing a scheduled task according to claim 1, characterized in that: When an event is triggered, the application layer wakes up the blocked application layer task. Specifically, when an event is triggered, the application layer wakes up the blocked application layer task through eventfd or shared memory.

5. A scheduled task execution system, characterized in that: The system is used in a scheduled task execution method according to any one of claims 1 to 4, and the system includes: An interrupt triggering module, configured to trigger a kernel interrupt based on the pulse edge of the received pulse signal and send an event to the application layer; wherein the event carries event information, and the event information includes an event period; The task execution module is used by the application layer to execute periodic timing tasks according to the event cycle and the preset application layer control logic.

6. A scheduled task execution system according to claim 5, characterized in that: Based on the pulse edge of the received pulse signal, the kernel interrupt is triggered and an interrupt event is sent to the application layer. Specifically: Generate a pulse signal using a pulse generator, and input the pulse signal to the GPIO pin through a pre-built loopback circuit; The GPIO pin detects the pulse signal, and after detecting the pulse edge of the pulse signal, it triggers a kernel interrupt and calls the pre-built interrupt service routine to record the interrupt timestamp; The kernel pushes events to the application layer after the interrupt.

7. A scheduled task execution system according to claim 5, characterized in that: The system also includes: The application layer monitors events through the poll interface. When no event is triggered, the application is in a blocked state. When an event is triggered, the application layer wakes up the blocked application layer task.

8. A computer device comprising a system memory and a processor, wherein the system memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 4 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 4 are implemented.

10. A computer program product comprising instructions, characterized in that When the instructions are executed by a computer device cluster, the computer device cluster is caused to perform the method according to any one of claims 1 to 4.

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