Exception code location methods and electronic devices

Abstract

This application relates to the field of computer technology, and in particular to an exception code localization method and electronic device. The method includes: obtaining the instantaneous value of the stack pointer register at the time of the code fault; starting from the instantaneous value, tracing back at least one level of stack space information from the address segment space pointed to by the stack pointer register, and extracting the exception interruption location pointer at the time of the code fault; storing the at least one level of stack space information and the exception interruption location pointer in a preset data space; determining the target layer address data based on the at least one level of stack space information, and locating the fault code location based on the target layer address data and the section information in a preset module mapping file. This solves the problem that related technologies struggle to quickly and accurately locate the fault code location when anomalies occur during BIOS firmware development, improving the debugging efficiency and reliability of the underlying firmware.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to an exception code location method and electronic device. Background Technology

[0002] In modern server computer systems, the BIOS (Basic Input / Output System) is the first firmware program executed when the computer starts up. It mainly completes hardware initialization self-test, controls the boot process, guides the hardware to gradually run the operating system, and is the only entry point for configuring the underlying hardware. The BIOS is the cornerstone of computer booting, directly determining whether the hardware can work properly and providing the lowest-level hardware control capabilities. Its failure or misconfiguration will cause the computer to fail to boot or run abnormally. Therefore, when a BIOS boot failure occurs, timely and effective location of the fault code is a very important and urgent requirement.

[0003] In related technologies, methods for locating BIOS code faults include collecting serial port log information (including resource logs, one-key logs, etc.) to analyze the problem points, or using XDP (eXpress Data Path) for low-level debugging at the register level.

[0004] However, the methods in related technologies are difficult to quickly and accurately locate the fault code when BIOS firmware development anomalies occur. Extensive analysis and verification are required to find the problem, which urgently needs to be solved. Summary of the Invention

[0005] This application provides an abnormal code location method and electronic device to solve the problem that when an abnormality occurs in BIOS firmware development, it is difficult for related technologies to quickly and accurately locate the fault code, thereby improving the debugging efficiency and reliability of the underlying firmware.

[0006] To achieve the above objectives, a first aspect of this application proposes an exception code location method, the method comprising the following steps:

[0007] Get the instantaneous value of the stack pointer register when the code failure occurs;

[0008] Starting from the instantaneous value, the data in the address segment space pointed to by the stack pointer register is traced back at least one level of stack space information, and the exception interruption location pointer when the code fault occurs is extracted. The at least one level of stack space information and the exception interruption location pointer are stored in a preset data space.

[0009] Based on the at least one stack space information, the target layer address data is determined, and based on the target layer address data, the fault code location is located according to the section information in the preset module mapping file.

[0010] The above-mentioned technical means solve the problem that it is difficult to quickly and accurately locate the fault code when BIOS firmware development anomalies occur, thereby improving the debugging efficiency and reliability of the underlying firmware.

[0011] The abnormal code localization method proposed in this application obtains the instantaneous value of the stack pointer register when a code fault occurs. Starting from the instantaneous value, the data in the address segment space pointed to by the stack pointer register is traced back at least one level of stack space information, and the abnormal interruption location pointer at the time of the code fault is extracted. The at least one level of stack space information and the abnormal interruption location pointer are stored in a preset data space. Based on the at least one level of stack space information, the target layer address data is determined, and based on the target layer address data, the fault code location is located according to the section information in the preset module mapping file. This solves the problem that related technologies struggle to quickly and accurately locate the fault code location when anomalies occur during BIOS firmware development, improving the debugging efficiency and reliability of the underlying firmware.

[0012] To achieve the above objectives, a second aspect of this application provides an anomaly code location device, comprising:

[0013] The acquisition module is used to acquire the instantaneous value of the stack pointer register when a code failure occurs;

[0014] The storage module is used to trace back at least one level of stack space information from the address segment space pointed to by the stack pointer register, starting from the instantaneous value, and to extract the exception interruption location pointer when the code fault occurs, and to store the at least one level of stack space information and the exception interruption location pointer into a preset data space.

[0015] The positioning module is used to determine the target layer address data based on the at least one level stack space information, and to locate the fault code location based on the target layer address data and the section information in the preset module mapping file.

[0016] To achieve the above objectives, a third aspect of this application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the exception code location method as described in the above embodiments.

[0017] To achieve the above objectives, a fourth aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which is executed by a processor to implement the exception code location method as described in the above embodiments.

[0018] To achieve the above objectives, a fifth aspect of this application provides a computer program product storing a computer program that, when executed by a processor, implements the exception code location method as described in the above embodiments.

[0019] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0020] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0021] Figure 1 This is a flowchart of the exception code location method provided according to an embodiment of this application;

[0022] Figure 2 This is a schematic diagram of a typical stack frame structure under the BIOS C calling convention according to an embodiment of this application;

[0023] Figure 3 This is a schematic diagram of an added exception handling according to an embodiment of this application;

[0024] Figure 4 This is a schematic diagram illustrating code matching using stack space information according to an embodiment of this application;

[0025] Figure 5 This is a schematic diagram of an exception code location device provided according to an embodiment of this application;

[0026] Figure 6 This is a schematic diagram of the structure of an electronic device provided according to an embodiment of this application. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0028] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0029] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] Those skilled in the art will understand that in modern server computer systems, the BIOS is an important component. As the first firmware program executed when the computer starts up, it mainly performs the following tasks:

[0031] Hardware initialization self-test: At the moment of power-on, the BIOS immediately initializes and performs a comprehensive test on core hardware such as the CPU (Central Processing Unit), memory, graphics card, and hard drive. If critical hardware fails (such as damaged memory or an unrecognized hard drive), the BIOS will interrupt the boot process through a beeping alarm or on-screen error message to prevent further damage, acting as the "first line of defense" against hardware failure.

[0032] Boot process control: The BIOS determines the loading order of the operating system, searching for bootable devices and loading the bootloader according to preset rules (such as hard drive → USB flash drive → optical drive). If the boot order is incorrect or the boot device is abnormal, the system will be unable to enter the operating system (such as displaying "No Boot Device Found").

[0033] The BIOS guides the hardware to gradually run the operating system: it provides a standardized hardware control interface for the operating system, enabling the system to indirectly manage hardware (such as reading and writing disks, keyboard input). Although modern operating systems may directly manipulate hardware, the BIOS is still responsible for transmitting critical parameters (such as hardware configuration information), ensuring software and hardware compatibility.

[0034] The sole entry point for configuring the underlying hardware: Users can adjust the following through the BIOS setup interface (accessed by pressing Del / F2, etc.): boot device priority (essential for system installation); hardware parameters (such as CPU overclocking and memory timings); security features (such as setting a BIOS password and TPM (Trusted Platform Module) encryption); and power management policies (affecting energy consumption and performance). These settings directly impact system stability and performance and cannot be modified through the operating system.

[0035] Therefore, the BIOS is the cornerstone of computer startup, directly determining whether hardware can function properly, whether the system can boot correctly, and providing the lowest-level hardware control capabilities. Its failure or misconfiguration will cause the computer to fail to boot or run abnormally. Therefore, timely and effective location of the fault code is a crucial and urgent need when a BIOS boot failure occurs. Existing methods for BIOS code fault location include: collecting serial port log information (including resource logs, one-key logs, etc.) to analyze the problem point; and using XDP (eXpressDataPath) for low-level register-level debugging. Each of these methods has its advantages and disadvantages, but none can efficiently and quickly locate the fault code directly; extensive analysis and verification are required to find the problem. To meet the need for rapid location of fault code after a BIOS anomaly, this invention proposes a highly efficient and convenient anomaly code location method that uses a dynamic stack backtracking mechanism to accurately locate the code position.

[0036] The following description, with reference to the accompanying drawings, describes the exception code location method and electronic device proposed according to embodiments of this application.

[0037] Figure 1 This is a flowchart of an exception code location method according to an embodiment of this application.

[0038] For example, such as Figure 1 As shown, this exception code location method includes the following steps:

[0039] In step S101, the instantaneous value of the stack pointer register at the time of the code failure is obtained.

[0040] The instantaneous value of the stack pointer register refers to the memory address value held by the stack pointer register in the central processing unit at a specific clock cycle or at the moment of instruction execution.

[0041] Specifically, it obtains the current value stored in the stack pointer register (such as the ESP or RSP register in the x86 architecture) at the instant the code failure occurs; this instantaneous value represents the top position of the function call stack in memory when the exception is triggered, and is the absolute starting point for subsequent stack backtracking and call chain reconstruction.

[0042] In step S102, starting from the instantaneous value, the data in the address segment space pointed to by the stack pointer register is traced back to at least one level of stack space information, and the exception interruption location pointer when the code fault occurs is extracted. The at least one level of stack space information and the exception interruption location pointer are stored in the preset data space.

[0043] The exception interrupt location pointer is the memory address of the instruction that was about to be executed but failed to execute, automatically pushed onto the stack when the CPU detects an exception or error event that cannot be processed during execution, before triggering a hardware interrupt and jumping to the exception handler. The pre-defined data space is statically specified before compilation and directly used in the exception handling code. It reliably stores critical diagnostic or status information when specific events (such as system exceptions) occur.

[0044] Specifically, starting from the instantaneous value of the stack pointer register, the data in the address segment space pointed to by the register is backtracked 10 levels and saved to the private data space (the preset data space). To ensure the balance between the data space and the actual use value, 10 levels of stack space information are stored. The instruction pointer before the interrupt is searched in the stack space. This pointer is the pointer to the location where the exception interrupted. The found instruction pointer before the interruption, RIP (EIP) (Routing Information Protocol), is stored in the corresponding location in the private data space.

[0045] In step S103, the target layer address data is determined based on at least one level of stack space information, and the fault code location is located based on the target layer address data and the section information in the preset module mapping file.

[0046] Among them, the target layer address data is the key memory address contained in the stack frame of the currently selected object to be analyzed in the multi-layer function call chain information obtained through the stack backtracking mechanism. It is used to match with the mapping file to locate the fault code.

[0047] Specifically, the top-level address data (i.e., target layer address data) is obtained from the stack space information. The key target layer address data is parsed and determined. The persistent stack information transmitted by the BIOS is compared with the section information defined in the preset module mapping file (MAP file). From the section information, address constraints (the starting address and length of the section) are found through enumeration. If the information traversal fails, it means that the stack space information stored at that level and afterwards is an invalid cached random value, and the traversal will not continue. Based on the function call stack frame structure, the current function call location can be calculated. The stack frame structure is as follows: Figure 2 As shown, Figure 2 This is a schematic diagram of a typical stack frame structure under the BIOS C calling convention in one embodiment of this application. Since BIOS uses the C calling convention, the stack frame structure can be pre-set. Then, the detailed offset address is calculated using the instruction pointer and the executable binary file, thereby accurately locating the code block.

[0048] Further, in some embodiments, locating the fault code location based on the target layer address data and according to the section information in the preset module mapping file includes: determining the target segment where the target layer address data is located from the preset module mapping file; determining the module mapping table information of the target segment, locking the executable section in the module mapping table information, and determining whether the target layer address data is within the area range determined by the executable section; if the target layer address data is within the area range determined by the executable section, determining the actual offset data of the target layer address data corresponding to the target segment; taking the next layer address data of the target layer address data as the target layer address data, and re-executing the step of determining the target segment where the target layer address data is located from the preset module mapping file to obtain the actual offset data of at least some layer address data corresponding to the target segment; mapping the actual offset data of at least some layer address data corresponding to the target segment to the actual location in the source code, and locating the fault code location according to the mapping result.

[0049] Understandably, the top-level address data (i.e., the target layer address data) is retrieved from the stack space information. Using this address data as a reference, a query is performed in the FV_MAP to find the PE (Portable Executable) section (i.e., the target section) where the reference address data resides. Then, the MAP information (module mapping table information) of the module corresponding to this PE section is searched in the build directory tree. In the MAP, the TEXT segment (i.e., the executable segment) is first locked. It is then checked whether the address data used as a reference condition is within the range from Start to Start+Length. If it is not within this range, a parsing error occurs. If it is within this range, the actual offset of the target layer address data relative to the starting address of the target segment is calculated, and this offset data is temporarily stored as a valid result. The remaining 9 layers in the stack space are processed in the same order as listed above, finding their corresponding offset addresses in the PE file, until no valid segment can be matched (indicating that subsequent stack information may be invalid data) or the parsing depth limit is reached. By combining the module's pdb (ProgramDatabase, symbol database) file with the source code, the offset addresses in the PE file are mapped to the actual locations in the source code, thereby locating the code block. This achieves efficient and automated accurate fault code location, significantly improving the debugging efficiency of the underlying software.

[0050] Furthermore, in some embodiments, determining the actual offset data corresponding to the target segment from the target layer address data includes: obtaining a relative offset address based on the target layer address data and the base address in the module mapping table information; and determining the actual offset data corresponding to the target segment from the target layer address data based on the relative offset address.

[0051] Furthermore, in some embodiments, obtaining the relative offset address based on the base address in the target layer address data and the module mapping table information includes: calculating the difference between the target layer address data and the base address in the module mapping table information; and using the difference as the relative offset address.

[0052] Furthermore, in some embodiments, determining the actual offset data of the target layer address data corresponding to the target segment based on the relative offset address includes: searching for the first column address and the second column address closest to the relative offset address from a preset address library, wherein the first column address is less than or equal to the relative offset address, and the second column address is greater than or equal to the relative offset address; determining the relative virtual offset address based on the first column address and / or the second column address, and using the sum of the relative virtual offset address and the base address in the module mapping table information as the actual offset data of the target layer address data corresponding to the target segment.

[0053] Understandably, by subtracting the BASE address from the moduleMAP (module mapping table information) from the address data information (target layer address data) used as a reference, a relative offset address is obtained. Based on this relative offset address, a search is performed in the Address column to find two adjacent columns, such that the Address of the upper column (first column address) is less than or equal to the relative offset address, and the Address of the lower column (second column address) is greater than or equal to the relative offset address. The first column of these two adjacent columns is used as a reference to derive the BASE + relative virtual offset address (actual offset data), which effectively improves the accuracy and robustness of fault address mapping, ensuring reliable location of source code even in complex binary environments.

[0054] Furthermore, in some embodiments, after determining whether the target layer address data is within the region defined by the executable section, the method further includes: if the target layer address data is not within the region defined by the executable section, generating parsing error information.

[0055] Understandably, once it is determined that the target layer address data is not within the address range defined by the executable section, a parsing error message is immediately generated, indicating that the address of this layer cannot be matched with any valid code segment, and subsequent analysis will terminate the backtracking process of the stack address of this layer and deeper layers.

[0056] Furthermore, in some embodiments, before obtaining the instantaneous value of the stack pointer register when the code fault occurs, the method further includes: disabling maskable interrupts and obtaining the current state of the single-step debug switch of the target processor's status register; determining whether the current state is a non-set state; if the current state is a non-set state, determining whether the code fault is a repairable fault; if the code fault is a repairable fault, storing at least some of the register data.

[0057] The non-set state is the state when a binary flag or switch has a value of 0 (logical "no" or "off").

[0058] It is understandable that disabling maskable interrupts prevents processing errors caused by interference from other interrupts in the processing routine; the status of the TF bit (Trap Flag) in the target processor's status register is checked. If the bit is not set (i.e., single-step debugging is not enabled), it is further determined whether the current code fault is an unrecoverable serious fault (such as a minor error that can be recovered by a preset routine). If it is confirmed to be a repairable fault, all general-purpose registers are saved to protect the context; this embodiment may also save the data of some registers; it should be noted that the foregoing explanation of saving all general-purpose registers also applies to saving the data of some registers in this embodiment, which will not be repeated here.

[0059] Furthermore, in some embodiments, after a code failure occurs, the method further includes: collecting exception descriptor entries in the interrupt descriptor table; determining the exception descriptor corresponding to the code failure from the exception descriptor entries, so as to locate the exception code based on the entry base address corresponding to the exception descriptor.

[0060] In a segmented memory architecture, the entry base address is the starting physical address of a memory segment defined by a segment descriptor. It serves as the reference address for calculating the actual entry point of code logic such as exception handlers.

[0061] Understandably, this involves collecting each exception descriptor entry from the IDT (Interrupt Descriptor Table) descriptors, finding the entry base address for handling the relevant exception information within the ENTRY field of each exception descriptor entry (the ENTRY field contains five parts: the low-order word portion of OFFSETADDR, the high-order word portion of OFFSETADDR, the SELECT part, the RESERVE part, and the ATTRIBUTE part; the entry offset address is the address obtained by merging the high-order and low-order words of OFFSETADDR, and the entry base address is the BASE address from the descriptor information indexed from the GDT (Global Descriptor Table) using the SELECT part; in the GDT descriptor, base31:24, base23:16, base... The three parts of address15:00 are combined to form the entry base address. The actual address of the processing code is obtained by adding the length of the entry offset address to the entry base address. These processing codes are enumerated, and the stack pointer register is saved in the pre-processing stage before entering the processing logic. The stack pointer is saved to a suitable memory space location. To ensure the integrity of the information and the feasibility of space implementation, 10 layers of stack space are saved, and the instruction pointer is stored at the same time. The entry base address is used as the key reference. The actual entry point of the exception handler is calculated by combining the offset, which provides the core basis for accurately locating and analyzing the execution start point of the exception code.

[0062] Furthermore, in some embodiments, after storing at least one level of stack space information and the exception interruption location pointer to a preset data space, the method further includes: writing the at least one level of stack space information stored in the preset data space to a log channel; and / or sharing the at least one level of stack space information stored in the preset data space to the target controller.

[0063] Understandably, when a code exception occurs during BIOS execution, the stack space information is saved to a preset data space (to ensure a balance between data space and actual usage value, 10 levels of stack space information are stored). Then, the stack space information saved in the exception handling routine is sent out through the log channel or shared method, which can be sent to the BMC (Baseboard Management Controller) (target controller) or the log port; the information is presented from the inside out and the data is persistently stored for later use.

[0064] Therefore, when a BIOS crashes or encounters other anomalies during operation, it can utilize its own characteristics and the stack frame structure of functions to send out backtracking information that is helpful for problem analysis. After obtaining the stack information data, this embodiment uses the section information in the MAP file to quickly exhaustively enumerate the code segment where the abnormal code is located. At the same time, combined with the PE file, the problematic code can be accurately located, saving troubleshooting time and eliminating a lot of manual operation and analysis. Furthermore, this embodiment is simple and easy to operate, with a simple and convenient operation method, making it easy for ordinary engineers to implement and deploy. This embodiment can reduce the duration of the fault, and the fault can be quickly located and resolved in a short time, allowing for a rapid restoration of normal operation.

[0065] To facilitate those skilled in the art to further understand the exception code location method of the embodiments of this application, the following is combined with... Figures 3 to 4 The embodiments shown will be described in detail.

[0066] Specifically, such as Figure 3 As shown, Figure 3 This is a schematic diagram of the exception handling added according to an embodiment of this application. The embodiment disables maskable interrupts to prevent interference from other interrupts in the processing routine, thus preventing processing errors. It checks the state of the TF bit in the status register; if the bit is not set, it continues. It determines whether it is an unrepairable serious fault; if not, it saves all general-purpose registers to protect the context. It allocates a private data space (this space can be hard-specified in advance, but cannot conflict with existing module areas). It reads the stack pointer register RSP (ESP) and performs a 10-level backtracking on the data in the address segment pointed to by the register, while saving it to the private data space. It searches for the instruction pointer before the interrupt in the stack space; this pointer is the position pointer of the interrupted instruction. It stores the found instruction pointer RIP (EIP) before the interrupt in the corresponding location in the private data space. It sends the data already saved in the private data space to the BMC (Baseboard Management Controller) via log transmission or sharing for data persistence.

[0067] Furthermore, such as Figure 4 As shown, Figure 4This is a schematic diagram illustrating code matching using stack space information according to an embodiment of this application. In this embodiment, the top-level address data is obtained from the stack space information. Using this address data as a reference condition, a query is performed in the FV_MAP. First, the PE segment containing the address data used as the reference condition is located. Then, the MAP information of the module corresponding to the PE segment is searched from the build directory tree. In the module MAP, the TEXT segment (code segment) is first locked, and it is checked whether the address data used as the reference condition is within the range from Start to Start+Length. If it is not within this range, a parsing error occurs; if it is within this range, the process continues. The module address data is subtracted from the address data used as the reference condition. The BASE address in the MAP is used to obtain the relative offset address. Based on this relative offset address, a search is performed in the Address field to find two adjacent columns, such that the Address of the upper column is less than or equal to the relative offset address, and the Address of the lower column is greater than or equal to the relative offset address. The first column of these two adjacent columns is used as a reference to obtain the BASE + relative virtual offset address, which is the offset address in the PE file. The remaining 9 layers in the stack space are then processed in the same order to find their corresponding offset addresses in the PE file. By comparing the module's pdb (Program Database) file with the source code, the offset address in the PE file is mapped to the actual location in the source code, thereby locating the code block.

[0068] According to the abnormal code localization method proposed in this application, the instantaneous value of the stack pointer register at the time of the code fault is obtained; starting from the instantaneous value, the data in the address segment space pointed to by the stack pointer register is traced back at least one level of stack space information, and the abnormal interruption position pointer at the time of the code fault is extracted. The at least one level of stack space information and the abnormal interruption position pointer are stored in a preset data space; based on the at least one level of stack space information, the target layer address data is determined, and based on the target layer address data, the fault code location is located according to the section information in the preset module mapping file. This solves the problem that related technologies are difficult to quickly and accurately locate the fault code location when anomalies occur in BIOS firmware development, improving the debugging efficiency and reliability of the underlying firmware.

[0069] Next, the abnormal code location device proposed according to the embodiments of this application is described with reference to the accompanying drawings.

[0070] Figure 5 This is a block diagram of an exception code location device according to an embodiment of this application.

[0071] like Figure 5As shown, the exception code locating device 10 includes: an acquisition module 100, a storage module 200, and a locating module 300.

[0072] Among them, the acquisition module 100 is used to acquire the instantaneous value of the stack pointer register when a code fault occurs;

[0073] The storage module 200 is used to trace back at least one level of stack space information from the address segment space pointed to by the stack pointer register, starting from the instantaneous value, and extract the exception interruption location pointer when the code failure occurs, and store at least one level of stack space information and exception interruption location pointer into a preset data space.

[0074] The positioning module 300 is used to determine the target layer address data based on at least one level of stack space information, and to locate the fault code location based on the target layer address data and the section information in the preset module mapping file.

[0075] Further, in some embodiments, locating the fault code location based on the target layer address data and according to the section information in the preset module mapping file includes: determining the target segment where the target layer address data is located from the preset module mapping file; determining the module mapping table information of the target segment, locking the executable section in the module mapping table information, and determining whether the target layer address data is within the area range determined by the executable section; if the target layer address data is within the area range determined by the executable section, determining the actual offset data of the target layer address data corresponding to the target segment; taking the next layer address data of the target layer address data as the target layer address data, and re-executing the step of determining the target segment where the target layer address data is located from the preset module mapping file to obtain the actual offset data of at least some layer address data corresponding to the target segment; mapping the actual offset data of at least some layer address data corresponding to the target segment to the actual location in the source code, and locating the fault code location according to the mapping result.

[0076] Furthermore, in some embodiments, determining the actual offset data corresponding to the target segment from the target layer address data includes: obtaining a relative offset address based on the target layer address data and the base address in the module mapping table information; and determining the actual offset data corresponding to the target segment from the target layer address data based on the relative offset address.

[0077] Furthermore, in some embodiments, obtaining the relative offset address based on the base address in the target layer address data and the module mapping table information includes: calculating the difference between the target layer address data and the base address in the module mapping table information; and using the difference as the relative offset address.

[0078] Furthermore, in some embodiments, determining the actual offset data of the target layer address data corresponding to the target segment based on the relative offset address includes: searching for the first column address and the second column address closest to the relative offset address from a preset address library, wherein the first column address is less than or equal to the relative offset address, and the second column address is greater than or equal to the relative offset address; determining the relative virtual offset address based on the first column address and / or the second column address, and using the sum of the relative virtual offset address and the base address in the module mapping table information as the actual offset data of the target layer address data corresponding to the target segment.

[0079] Furthermore, in some embodiments, after determining whether the target layer address data is within the region defined by the executable section, the method further includes: if the target layer address data is not within the region defined by the executable section, generating parsing error information.

[0080] Furthermore, in some embodiments, before obtaining the instantaneous value of the stack pointer register when the code fault occurs, the method further includes: disabling maskable interrupts and obtaining the current state of the single-step debug switch of the target processor's status register; determining whether the current state is a non-set state; if the current state is a non-set state, determining whether the code fault is a repairable fault; if the code fault is a repairable fault, storing at least some of the register data.

[0081] Furthermore, in some embodiments, after a code failure occurs, the method further includes: collecting exception descriptor entries in the interrupt descriptor table; determining the exception descriptor corresponding to the code failure from the exception descriptor entries, so as to locate the exception code based on the entry base address corresponding to the exception descriptor.

[0082] Furthermore, in some embodiments, after storing at least one level of stack space information and the exception interruption location pointer to a preset data space, the method further includes: writing the at least one level of stack space information stored in the preset data space to a log channel; and / or sharing the at least one level of stack space information stored in the preset data space to the target controller.

[0083] According to the abnormal code location device proposed in this application, the present application acquires the instantaneous value of the stack pointer register when a code fault occurs; starting from the instantaneous value, the data in the address segment space pointed to by the stack pointer register is traced back at least one level of stack space information, and the abnormal interruption location pointer at the time of the code fault is extracted; the at least one level of stack space information and the abnormal interruption location pointer are stored in a preset data space; based on the at least one level of stack space information, the target layer address data is determined, and based on the target layer address data, the fault code location is located according to the section information in the preset module mapping file. This solves the problem that related technologies struggle to quickly and accurately locate the fault code location when anomalies occur during BIOS firmware development, improving the debugging efficiency and reliability of the underlying firmware.

[0084] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device may include:

[0085] The memory 601, the processor 602, and the computer program stored on the memory 601 and capable of running on the processor 602.

[0086] When the processor 602 executes the program, it implements the exception code location method provided in the above embodiments.

[0087] Furthermore, electronic devices also include:

[0088] Communication interface 603 is used for communication between memory 601 and processor 602.

[0089] The memory 601 is used to store computer programs that can run on the processor 602.

[0090] The memory 601 may include high-speed RAM (Random Access Memory) memory, and may also include non-volatile memory, such as at least one disk storage.

[0091] If the memory 601, processor 602, and communication interface 603 are implemented independently, then the communication interface 603, memory 601, and processor 602 can be interconnected via a bus to complete communication between them. The bus can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 6The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0092] Optionally, in a specific implementation, if the memory 601, processor 602, and communication interface 603 are integrated on a single chip, then the memory 601, processor 602, and communication interface 603 can communicate with each other through an internal interface.

[0093] The processor 602 may be a CPU (Central Processing Unit), an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of this application.

[0094] This application also provides a non-volatile computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the above-described exception code location method.

[0095] This application also provides a computer program product, including a computer program, which, when executed by a processor, implements the above-described method for locating abnormal codes.

[0096] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0097] The above provides a detailed description of an anomaly code location method provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for locating exception codes, characterized in that, Includes the following steps: Get the instantaneous value of the stack pointer register when the code failure occurs; Starting from the instantaneous value, the data in the address segment space pointed to by the stack pointer register is traced back at least one level of stack space information, and the exception interruption location pointer when the code fault occurs is extracted. The at least one level of stack space information and the exception interruption location pointer are stored in a preset data space. Based on the at least one level of stack space information, target layer address data is determined, and based on the target layer address data, the fault code location is located according to the section information in the preset module mapping file. The exception interrupt location pointer is the memory address of the instruction that was about to be executed but failed to execute, automatically pushed onto the stack before triggering a hardware interrupt and jumping to the exception handler when the central processing unit detects an exception or error event that cannot be processed during execution. Locating the fault code location based on the target layer address data and the section information in the preset module mapping file includes: determining the target segment where the target layer address data is located from the preset module mapping file; determining the module mapping table information of the target segment, and then... The executable section is locked in the information, and it is determined whether the target layer address data is within the region range determined by the executable section. If the target layer address data is within the region range determined by the executable section, the actual offset data corresponding to the target segment is determined. The address data of the next layer of the target layer address data is used as the target layer address data, and the step of determining the target segment where the target layer address data is located from the preset module mapping file is re-executed to obtain at least some layer address data corresponding to the actual offset data of the target segment. The actual offset data corresponding to the target segment of the at least some layer address data is mapped to the actual location in the source code, and the fault code location is located according to the mapping result.

2. The method according to claim 1, characterized in that, Determining the actual offset data corresponding to the target segment from the target layer address data includes: The relative offset address is obtained based on the target layer address data and the base address in the module mapping table information; The actual offset data corresponding to the target segment is determined based on the relative offset address.

3. The method according to claim 2, characterized in that, The step of obtaining the relative offset address based on the target layer address data and the base address in the module mapping table information includes: Calculate the difference between the target layer address data and the base address in the module mapping table information; The difference is used as the relative offset address.

4. The method according to claim 2, characterized in that, The step of determining the actual offset data of the target layer address data corresponding to the target segment based on the relative offset address includes: Search the preset address library for the first column address and the second column address that are closest to the relative offset address, wherein the first column address is less than or equal to the relative offset address, and the second column address is greater than or equal to the relative offset address; Based on the first column address and / or the second column address, a relative virtual offset address is determined, and the sum of the relative virtual offset address and the base address in the module mapping table information is used as the actual offset data of the target layer address data corresponding to the target segment.

5. The method according to claim 1, characterized in that, After determining whether the target layer address data is within the region defined by the executable section, the method further includes: If the target layer address data is not within the region defined by the executable section, a parsing error message is generated.

6. The method according to claim 1, characterized in that, Before obtaining the instantaneous value of the stack pointer register at the time of the code failure, the following steps are also included: Disable maskable interrupts and obtain the current state of the single-step debug switch in the target processor's status register; Determine whether the current state is a non-set state; If the current state is the non-set state, then determine whether the code fault is a repairable fault; If the code fault is a repairable fault, then at least a portion of the register data is stored.

7. The method according to claim 6, characterized in that, Following the occurrence of the code failure, the following is also included: Acquire exception descriptor entries in the interrupt descriptor table; The exception descriptor corresponding to the code fault is determined from the exception descriptor entries, so as to locate the exception code based on the entry base address corresponding to the exception descriptor.

8. The method according to claim 1, characterized in that, After storing the at least one level stack space information and the exception interrupt location pointer into the preset data space, the method further includes: Write the at least one level stack space information stored in the preset data space into the log channel; And / or, share the at least one level stack space information stored in the preset data space to the target controller.

9. An electronic device, characterized in that, include: A memory, a processor, and a computer program stored in the memory and executable on the processor, the processor executing the program to implement the exception code location method as described in any one of claims 1-8.

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