Low-jitter injection-locked phase-locked loop based on two-dimensional time-space correction technique

Abstract

The application relates to the technical field of radio frequency integrated circuits, and discloses a low-jitter injection-locked phase-locked loop based on a two-dimensional space-time correction technology, which comprises a phase-locked loop, a frequency-locked loop and a sub-sampling phase-locked loop; an injection-locked circuit is used for providing an injection pulse signal into the phase-locked loop; a two-dimensional space-time correction circuit is connected with an oscillation signal and the injection pulse signal at an input end, and outputs a delay adjustment signal to the injection-locked circuit at an output end; the two-dimensional space-time correction circuit compares the period and phase information of the oscillation signal and the injection pulse signal, generates a delay adjustment signal and feeds back the delay adjustment signal to the injection-locked circuit, improves the injection strength, expands the noise suppression bandwidth, solves the problems of difficult injection alignment and difficult optimal pulse width of the injection-locked structure, realizes low jitter of the phase-locked loop, and provides a technical solution for the application of the injection-locked phase-locked loop in a high-clock-precision and low-jitter millimeter wave communication and high-speed data conversion system.

Description

Technical Field

[0001] This invention relates to the field of radio frequency integrated circuit technology, and specifically to a low-jitter injection-locked phase-locked loop based on two-dimensional spatiotemporal correction technology. Background Technology

[0002] A phase-locked loop (PLL) is a closed-loop control circuit that synchronizes the frequency and phase of an output signal with the input signal through a feedback mechanism. Its core function is to lock the frequency and phase of the input signal, thereby outputting a stable and synchronized signal. It can perform operations such as frequency synthesis, clock recovery, and modulation / demodulation. In the field of communications, it is used in wireless transceivers to achieve carrier synchronization and frequency synthesis, ensuring accurate demodulation and transmission of signals during transmission. In electronic devices, it can be used to generate high-precision clock signals, ensuring the synchronous operation of various modules in digital systems. In radar and navigation systems, it can accurately track frequency changes of target signals, improving measurement accuracy and reliability. As a key component of modern electronic systems, the PLL plays a crucial role in wireless communication, integrated circuits, and measurement and control equipment due to its frequency tracking, signal purification, and synchronization capabilities, and is one of the core technologies for achieving stable and precise signal control.

[0003] Injection-locked phase-locked loops (PLLs) exhibit significant advantages in high-frequency integrated systems due to their unique phase synchronization mechanism. By injecting a signal to pull the phase of the oscillator, they can achieve an ultra-wideband frequency locking range, making them particularly suitable for scenarios with stringent bandwidth requirements, such as millimeter-wave communication and high-speed frequency synthesis. Unlike traditional PLLs, they do not require complex loop filter designs, simplifying some circuit modules. Furthermore, thanks to the injection-locking mechanism, they inherently possess low jitter characteristics, providing clock signals with higher timing stability in high-speed data transmission, meeting the jitter-sensitive application requirements of high-frequency SerDes transceivers. Simultaneously, this mechanism effectively suppresses the inherent phase noise of the oscillator, exhibiting excellent signal purity in the high-frequency band, making them ideal for scenarios with extremely high phase noise requirements, such as radar and satellite communication. However, the core drawback of injection-locked phase-locked loops lies in their extremely stringent dependence on the zero-crossing phase alignment accuracy of the injected signal and the local oscillation signal. The midpoint of the injected pulse must precisely coincide with the corresponding zero-crossing point of the oscillation signal within an extremely narrow time window. Any nanosecond-level timing misalignment will lead to the accumulation of phase errors, instability of the locking loop, and consequently, frequency jumps, a surge in phase noise, or even complete locking failure. At the same time, the injection intensity is directly related to the width of the injected pulse, affecting the jitter performance of the phase-locked loop.

[0004] Therefore, how to accurately align the midpoint of the injection pulse signal with the zero-crossing point of the oscillation signal, while ensuring the optimal injection pulse width to guarantee sufficient injection strength, in order to overcome the inherent defects of the injection locking structure and fully realize its application potential in low jitter, low phase noise, etc., is a key technical challenge that urgently needs to be solved by technicians in this field. Summary of the Invention

[0005] To address the problems existing in the prior art, this invention proposes a low-jitter injection-locked phase-locked loop (PLL) based on two-dimensional spatiotemporal correction technology. The PLL includes a subsampling locking loop, a frequency-locking loop, an injection-locking circuit, and a two-dimensional spatiotemporal correction circuit. The correction path comprises two parts: injection time correction and injection pulse width correction. The two-dimensional spatiotemporal correction circuit compares the period and phase information of the oscillation signal and the injected pulse signal, generating a delay adjustment signal that is fed back to the injection-locking circuit. This improves the injection intensity and expands the noise suppression bandwidth, solving the problems of difficult injection alignment and optimal pulse width in the injection-locking structure. It achieves low jitter in the PLL, providing a technical solution for the application of injection-locked PLLs in millimeter-wave communication and high-speed data conversion systems requiring high clock accuracy and low jitter.

[0006] This invention proposes a low-jitter injection-locked phase-locked loop based on two-dimensional spatiotemporal correction technology, wherein the injection-locked phase-locked loop comprises;

[0007] A phase-locked loop (PLL) includes a frequency-locked loop and a subsampled PLL; the subsampled PLL is used to achieve phase locking, and the frequency-locked loop is used to achieve frequency locking; in the PLL signal locking process, frequency locking is completed first, followed by phase locking.

[0008] An injection locking circuit, which is connected to the phase-locked loop, is used to provide injection pulse signals to the phase-locked loop;

[0009] A two-dimensional spatiotemporal correction circuit has an input terminal connected to an oscillation signal and an injected pulse signal, and an output terminal outputting a delay adjustment signal to an injection locking circuit. By comparing the period and phase information of the oscillation signal and the injected pulse signal, the two-dimensional spatiotemporal correction circuit generates a delay adjustment signal that is fed back to the injection locking circuit, thereby realizing the correction of the time and pulse width of the injected pulse signal.

[0010] Furthermore, the two-dimensional spatiotemporal correction circuit includes injection time correction and injection pulse width correction;

[0011] The injection time correction output first delay adjustment signal is sent to the injection locking circuit, which is used to correct the time of the injection pulse signal so that the midpoint of the injection pulse signal is aligned with the zero-crossing point of the oscillation signal.

[0012] The injection pulse width correction outputs a second delay adjustment signal to the injection locking circuit, which is used to correct the pulse width of the injection pulse signal, thereby increasing the injection intensity of the pulse signal and suppressing phase-locked loop jitter.

[0013] Furthermore, the injection locking circuit includes a first variable delay unit, a second variable delay unit, and an AND logic gate;

[0014] The input terminal of the first variable delay unit is connected to a reference signal and a first delay adjustment signal;

[0015] The input terminal of the second variable delay unit is connected to the output terminal of the first variable delay unit and the second delay adjustment signal;

[0016] The output terminals of the first variable delay unit and the second variable delay unit are both connected to the input terminals of the AND gate, and the output terminal of the AND gate outputs an injected pulse signal.

[0017] Furthermore, the injection time correction includes a first comparator, a first accumulator, and a second subsampling phase detector;

[0018] The input of the second subsampling phase detector is connected to the oscillation signal and the injected pulse signal, its output is connected to the negative input of the first comparator, the positive input of the first comparator is connected to the voltage, the output of the first comparator is connected to the input of the first accumulator, and the output of the first accumulator outputs the first delay adjustment signal;

[0019] The injection pulse width correction includes a second comparator, a second accumulator, and a second charge pump;

[0020] The input terminal of the second charge pump is connected to the oscillation signal and the injection pulse signal, and its output terminal is connected to the negative input terminal of the second comparator. The positive input terminal of the second comparator is connected to the voltage, and the output terminal of the second comparator is connected to the input terminal of the second accumulator. The output terminal of the second accumulator outputs the second delay adjustment signal.

[0021] Furthermore, the second subsampling phase detector includes a first capacitor and a fifth NMOS transistor; the gate of the fifth NMOS transistor is connected to an oscillation signal, its drain is connected to an injection pulse signal, the source of the fifth NMOS transistor is connected to one end of the first capacitor, and serves as the output terminal of the second subsampling phase detector; the other end of the first capacitor is grounded.

[0022] Furthermore, the second charge pump includes a second capacitor, a sixth NMOS transistor, and a fourth PMOS transistor;

[0023] The source of the fourth PMOS transistor is connected to a power supply, and its gate is connected to an injected pulse signal; the gate of the sixth NMOS transistor is connected to an oscillation signal, and its source is grounded; the drain of the sixth NMOS transistor is connected to the drain of the fourth PMOS transistor and one end of the second capacitor, and serves as the output terminal of the second charge pump; the other end of the second capacitor is grounded.

[0024] Furthermore, both the first variable delay unit and the second variable delay unit include a variable current source, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a first inverter, a second inverter, and several stages of delay units;

[0025] The input terminal of the first inverter is the input terminal of the first variable delay unit and the second variable delay unit;

[0026] The output of the second inverter is the output of both the first variable delay unit and the second variable delay unit;

[0027] The negative terminal of the variable current source is connected to the power supply, and its positive terminal is connected to the gate and drain of the first NMOS transistor. The control terminal of the variable current source is connected to a delay adjustment signal. The gate of the first NMOS transistor is connected to the drain of the first NMOS transistor, the gate of the second NMOS transistor, and the VN voltage. The source of the first NMOS transistor and the source of the second NMOS transistor are both grounded. The drain of the second NMOS transistor is connected to the gate of the first PMOS transistor, the drain of the first PMOS transistor, and the VP voltage. The source of the first PMOS transistor is connected to the power supply.

[0028] The output of the first inverter is connected to the first input of the first stage delay unit. The first input of each stage delay unit is connected to the output of the previous stage delay unit. The second input of each stage delay unit is connected to the VP voltage. The third input of each stage delay unit is connected to the VN voltage. The output of the last stage delay unit is connected to the input of the second inverter.

[0029] Furthermore, each delay unit includes a second PMOS transistor, a third PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;

[0030] In each delay unit, the gate of the second PMOS transistor is the second input terminal of the delay unit, the source of the second PMOS transistor is connected to the power supply, and its drain is connected to the source of the third PMOS transistor; the gate of the third PMOS transistor is connected to the gate of the fourth NMOS transistor and is the first input terminal of the delay unit; the drain of the third PMOS transistor is connected to the drain of the fourth NMOS transistor and is the output terminal of the delay unit; the source of the fourth NMOS transistor is connected to the drain of the third NMOS transistor, the source of the third NMOS transistor is grounded, and the gate of the third NMOS transistor is the third input terminal of the delay unit.

[0031] Furthermore, the frequency-locked loop includes a frequency and phase detector, a first charge pump, a frequency divider, a loop filter, and an injection-locked oscillator;

[0032] The injection-locked oscillator outputs an oscillation signal;

[0033] The frequency divider's input is connected to an oscillation signal, and its output is connected to a frequency and phase detector. The other input of the frequency and phase detector is connected to a reference signal. The output of the frequency and phase detector is connected to the input of the first charge pump. The output of the first charge pump is connected to the input of the loop filter. The output of the loop filter is connected to the injection-locked oscillator.

[0034] Furthermore, the subsampling phase-locked loop includes a first subsampling phase detector and a transconductance module;

[0035] The input of the first subsampling phase detector is connected to the reference signal and the oscillation signal, and its output is connected to the input of the transconductance module. The output of the transconductance module is connected to the other input of the loop filter. The first subsampling phase detector, the transconductance module, the loop filter, and the injection-locked oscillator form the subsampling phase-locked loop.

[0036] Compared with the prior art, the present invention has the following beneficial technical effects:

[0037] This invention proposes a low-jitter injection-locked phase-locked loop (PLL) based on two-dimensional spatiotemporal correction technology. By employing two-dimensional correction of injection time and injection pulse width, it achieves precise alignment between the injection pulse midpoint and the zero-crossing point of the oscillation signal, as well as optimal pulse width. This overcomes the shortcomings of traditional injection-locked PLLs, eliminates phase shift caused by injection, improves injection strength, expands the noise suppression bandwidth, and enhances the PLL's jitter suppression capability, resulting in low jitter. Furthermore, it employs a subsampling architecture to avoid the contribution of frequency dividers to phase noise, reducing in-band phase noise. This invention, through two-dimensional spatiotemporal correction technology, compensates for the mechanism defects of traditional injection-locked PLLs, realizing a low-jitter, low-phase-noise PLL system. It provides a key technological foundation for next-generation communication systems with high timing accuracy requirements and is suitable for high-frequency communication systems, radar, millimeter-wave receivers, and other scenarios requiring low jitter and low phase-noise ranges. Attached Figure Description

[0038] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0039] Figure 1 A schematic diagram of the overall structure of the low-jitter injection-locked phase-locked loop based on two-dimensional spatiotemporal correction technology provided by the present invention;

[0040] Figure 2 A schematic diagram of the specific structure of the low-jitter injection-locked phase-locked loop based on two-dimensional spatiotemporal correction technology provided by the present invention;

[0041] Figure 3 A schematic diagram of the injection locking circuit and the two-dimensional spatiotemporal correction circuit provided by the present invention;

[0042] Figure 4 This is a schematic diagram of the circuit structure of the variable delay unit in the injection locking circuit provided by the present invention. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0044] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0045] In the description of this invention, it should be noted that the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings, or the orientation or positional relationships commonly used when the product of this invention is in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. In addition, the terms "first," "second," "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0046] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0047] It should be noted that, where there is no conflict, the features in the embodiments of the present invention can be combined with each other.

[0048] like Figure 1 As shown, the present invention provides a low-jitter injection-locked phase-locked loop based on two-dimensional spatiotemporal correction technology, specifically comprising:

[0049] A phase-locked loop (PLL) consists of a frequency-locked loop (PLL) and a subsampling PLL. The subsampling PLL is used to achieve phase locking, while the frequency-locked loop is used to achieve frequency locking. In the PLL signal locking process, frequency locking is completed first, followed by phase locking.

[0050] An injection locking circuit, which is connected to the phase-locked loop, is used to provide injection pulse signals to the phase-locked loop;

[0051] The two-dimensional spatiotemporal correction circuit has an input terminal connected to an oscillation signal and an injected pulse signal, and an output terminal outputting a delay adjustment signal to the injection locking circuit. By comparing the period and phase information of the oscillation signal and the injected pulse signal, the two-dimensional spatiotemporal correction circuit generates a delay adjustment signal that is fed back to the injection locking circuit, thereby realizing the correction of the time and pulse width of the injected pulse signal.

[0052] In some embodiments of the present invention, the injection locking circuit and the two-dimensional spatiotemporal correction circuit are the core components of the phase-locked loop (PLL) to achieve low jitter. The injection time correction achieves precise alignment between the midpoint of the injection pulse and the zero-crossing point of the oscillation signal, and the injection pulse width correction achieves the optimal injection pulse width, improves the injection intensity, expands the noise suppression bandwidth, and suppresses PLL jitter. The frequency-locking loop is the frequency-locking part of the PLL, and the frequency-locking loop is a traditional charge pump PLL structure. The subsampling PLL is the phase-locking part of the PLL. The traditional subsampling frequency-locking loop and the subsampling PLL are used together to achieve frequency and phase locking. First, the frequency-locking loop works to complete the frequency locking, and then the subsampling PLL works to complete the phase locking.

[0053] like Figure 2 and Figure 3 As shown, the two-dimensional spatiotemporal correction circuit includes injection time correction and injection pulse width correction. The injection time correction outputs a first delay adjustment signal to the injection locking circuit, which is used to correct the time of the injected pulse signal so that the midpoint of the injected pulse signal is precisely aligned with the zero-crossing point of the oscillation signal. The injection pulse width correction outputs a second delay adjustment signal to the injection locking circuit, which is used to correct the pulse width of the injected pulse signal so that the injection intensity of the pulse signal is increased and the phase-locked loop jitter is suppressed.

[0054] The injection-locked circuit includes a first variable delay unit, a second variable delay unit, and an AND gate; the input of the first variable delay unit is connected to a reference signal and a first delay adjustment signal; the input of the second variable delay unit is connected to the output of the first variable delay unit and the second delay adjustment signal; the outputs of the first and second variable delay units are both connected to the input of the AND gate, and the output of the AND gate outputs an injection pulse signal.

[0055] Specifically, the injection time correction includes a first comparator, a first accumulator, and a second subsampling phase detector; the input of the second subsampling phase detector is connected to the oscillation signal and the injection pulse signal, its output is connected to the negative input of the first comparator, the positive input of the first comparator is connected to the voltage, the output of the first comparator is connected to the input of the first accumulator, and the output of the first accumulator outputs a first delay adjustment signal;

[0056] The injection pulse width correction includes a second comparator, a second accumulator, and a second charge pump. The input of the second charge pump is connected to the oscillation signal and the injection pulse signal, and its output is connected to the negative input of the second comparator. The positive input of the second comparator is connected to the voltage, and the output of the second comparator is connected to the input of the second accumulator. The output of the second accumulator outputs a second delay adjustment signal.

[0057] In some embodiments of the present invention, the two-dimensional spatiotemporal correction circuit compares the period and phase information of the injected pulse signal and the oscillation signal, and then generates a feedback signal to adjust the delay of the first variable delay unit and the second variable delay unit. The first delay adjustment signal adjusts the delay of the first variable delay unit to achieve the optimal injection time, that is, the midpoint of the injected pulse is aligned with the zero-crossing point of the oscillation signal. The second delay adjustment signal adjusts the delay of the second variable delay unit to achieve the optimal injection pulse width, which is 1 / 4 of the oscillation signal period. The two-dimensional adjustment of the injection time and the injection pulse width solves the bottleneck of the injection-locked phase-locked loop, improves the injection strength, expands the noise suppression bandwidth, and achieves low jitter of the phase-locked loop.

[0058] Specifically, in the injection time correction path, after the injected pulse signal is sampled by the second subsampling phase detector, the output signal containing the phase error of the injected pulse signal and the oscillation signal is input to the negative input of the first comparator. The first comparator compares this signal containing the phase error with the comparison threshold voltage and outputs +1 or -1, which is accumulated by the first accumulator, and outputs the first delay adjustment signal to adjust the first variable delay unit. If the output voltage of the second subsampling phase detector is higher than the comparison threshold voltage, the first comparator outputs -1, the output voltage of the first accumulator decreases, and the delay of the first variable delay unit decreases. If the output voltage of the second subsampling phase detector is lower than the comparison threshold voltage, the first comparator outputs +1, the output voltage of the first accumulator increases, and the delay of the first variable delay unit increases. This adjusts the generation time of the injected pulse signal to achieve the optimal injection time, that is, the midpoint of the injected pulse is aligned with the zero-crossing point of the oscillation signal.

[0059] In the injected pulse width correction path, the injected pulse signal and the oscillation signal enter the second charge pump. The injected pulse signal controls the charging of the second charge pump, and the oscillation signal controls the discharging of the second charge pump. The signal output by the second charge pump, representing the error between the injected pulse width and the optimal pulse width, enters the negative input of the second comparator. The second comparator compares this signal, which includes the width error, with the comparison threshold voltage and outputs +1 or -1. After the output of the second comparator, it is accumulated by the second accumulator. The second accumulator outputs a second delay adjustment signal to adjust the second variable delay unit. If the output voltage of the second charge pump is higher than the comparison threshold voltage, the second comparator outputs -1, the output voltage of the second accumulator decreases, and the delay of the second variable delay unit decreases. If the output voltage of the second charge pump is lower than the comparison threshold voltage, the second comparator outputs +1, the output voltage of the first accumulator increases, and the delay of the second variable delay unit increases. This adjusts the width of the injected pulse signal to achieve the optimal injected pulse width, which is 1 / 4 of the oscillation signal period.

[0060] like Figure 3 As shown, the second subsampling phase detector includes a first capacitor C1 and a fifth NMOS transistor N5; the gate of the fifth NMOS transistor N5 is connected to the oscillation signal, its drain is connected to the injected pulse signal, the source of the fifth NMOS transistor N5 is connected to one end of the first capacitor C1, and is the output terminal of the second subsampling phase detector; the other end of the first capacitor C1 is grounded.

[0061] The second charge pump includes a second capacitor C2, a sixth NMOS transistor N6, and a fourth PMOS transistor P4; the source of the fourth PMOS transistor P4 is connected to the power supply, and its gate is connected to the injected pulse signal; the gate of the sixth NMOS transistor N6 is connected to the oscillation signal, its source is grounded, the drain of the sixth NMOS transistor N6 is connected to the drain of the fourth PMOS transistor P4 and one end of the second capacitor C2, and serves as the output terminal of the second charge pump; the other end of the second capacitor C2 is grounded.

[0062] like Figure 4 As shown, both the first and second variable delay units include a variable current source, a first NMOS transistor N1, a second NMOS transistor N2, a first PMOS transistor P1, a first inverter, a second inverter, and several stages of delay units. The input terminal of the first inverter is the input terminal of both the first and second variable delay units; the output terminal of the second inverter is the output terminal of both the first and second variable delay units. The negative terminal of the variable current source is connected to the power supply, and its positive terminal is connected to the gate and drain of the first NMOS transistor N1. The control terminal of the variable current source is connected to the delay adjustment signal. The gate of the first NMOS transistor N1 is connected to the drain of the first NMOS transistor N1. The gate of the second NMOS transistor N2 is connected to the voltage VN; the source of the first NMOS transistor N1 and the source of the second NMOS transistor N2 are both grounded; the drain of the second NMOS transistor N2 is connected to the gate of the first PMOS transistor N1, the drain of the first PMOS transistor P1, and the voltage VP; the source of the first PMOS transistor P1 is connected to the power supply; the output of the first inverter is connected to the first input of the first stage delay unit; the first input of each stage delay unit is connected to the output of the previous stage delay unit; the second input of each stage delay unit is connected to the voltage VP; the third input of each stage delay unit is connected to the voltage VN; the output of the last stage delay unit is connected to the input of the second inverter.

[0063] Specifically, each delay unit includes a second PMOS transistor P2, a third PMOS transistor P3, a third NMOS transistor N3, and a fourth NMOS transistor N4. In each delay unit, the gate of the second PMOS transistor P2 is the second input terminal of the delay unit, the source of the second PMOS transistor P2 is connected to the power supply, and its drain is connected to the source of the third PMOS transistor P3. The gate of the third PMOS transistor P3 is connected to the gate of the fourth NMOS transistor N4 and is the first input terminal of the delay unit. The drain of the third PMOS transistor P3 is connected to the drain of the fourth NMOS transistor N4 and is the output terminal of the delay unit. The source of the fourth NMOS transistor N4 is connected to the drain of the third NMOS transistor N3, the source of the third NMOS transistor N3 is grounded, and the gate of the third NMOS transistor N3 is the third input terminal of the delay unit.

[0064] In some embodiments of the present invention, in the variable delay unit, the delay adjustment signal adjusts the variable current source to change the VP voltage and VN voltage, thereby altering the delay of each stage of the delay unit and controlling the delay of the entire variable delay unit. Specifically, when the voltage of the delay adjustment signal decreases, the current of the variable current source increases, the VN voltage increases, the VP voltage decreases, and the conduction of the third NMOS transistor N3 and the second PMOS transistor P2 in each stage of the delay unit is higher, resulting in a decrease in the delay of each stage of the delay unit, and thus a decrease in the delay of the variable delay unit. Conversely, when the voltage of the delay adjustment signal increases, the current of the variable current source decreases, the VN voltage decreases, the VP voltage increases, and the conduction of the third NMOS transistor N3 and the second PMOS transistor P2 in each stage of the delay unit decreases, resulting in an increase in the delay of each stage of the delay unit, and thus an increase in the delay of the variable delay unit.

[0065] The frequency-locked loop includes a frequency and phase detector, a first charge pump, a frequency divider, a loop filter, and an injection-locked oscillator. The injection-locked oscillator outputs an oscillation signal. The input of the frequency divider is connected to the oscillation signal, and its output is connected to the frequency and phase detector. The other input of the frequency and phase detector is connected to a reference signal. The output of the frequency and phase detector is connected to the input of the first charge pump. The output of the first charge pump is connected to the input of the loop filter, and the output of the loop filter is connected to the injection-locked oscillator.

[0066] The subsampling phase-locked loop includes a first subsampling phase detector and a transconductance module. The input of the first subsampling phase detector is connected to a reference signal and an oscillation signal, and its output is connected to the input of the transconductance module. The output of the transconductance module is connected to the other input of the loop filter. The first subsampling phase detector, the transconductance module, the loop filter, and the injection-locked oscillator form a subsampling phase-locked loop.

[0067] In some embodiments of the present invention, phase and frequency locking of the phase-locked loop is achieved collaboratively by a subsampling phase-locked loop and a frequency-locked loop. First, the frequency-locked loop performs its work to complete the frequency locking task. Once the frequency is locked, the frequency-locked loop stops operating, and the subsampling phase-locked loop then starts to perform phase tracking and ultimately achieves locking.

[0068] Specifically, in this invention, within the frequency-locked loop, a conventional three-state PFD with a dead time is used as the frequency and phase detector; this frequency and phase detector is used to detect the phase difference between the reference signal and the output signal of the frequency divider. When the reference signal frequency... Higher than the injection-locked oscillator frequency after being divided by N by the frequency divider That is When the frequency and phase detector (PFD) outputs a phase advance pulse, it controls the injection current of the first charge pump; and when At this time, the phase-frequency detector (PFD) outputs a phase-lag pulse, controlling the first charge pump's current draw. The output current I of the first charge pump is...CP It will be integrated through a loop filter to generate the control voltage V. CTRL Control voltage V CTRL The oscillation frequency of the injection-locked oscillator can be adjusted until... Frequency locking is achieved. After frequency locking is completed, the subsampling phase-locked loop (PLL) begins operation. In the subsampling PLL, the first subsampling phase detector uses a low-frequency reference signal to subsample the high-frequency injection-locked oscillator output signal, converting the phase error between the reference signal and the oscillation signal into a voltage signal. Voltage signal containing phase error information It will be converted into a current signal by the transconductance module, and then a smoothed voltage signal V will be generated by the loop filter. CTRL This allows for precise adjustment of the phase of the output signal of the injection-locked oscillator to ensure phase locking.

[0069] This invention utilizes two-dimensional spatiotemporal correction technology. Injection time correction achieves precise alignment between the midpoint of the injected pulse and the zero-crossing point of the oscillation signal, with an alignment phase error of less than 1.67%. Injection pulse width correction achieves the optimal injection pulse width, i.e., 1 / 4 of the oscillation signal period, which improves the injection intensity, expands the noise suppression bandwidth, and effectively suppresses jitter. At the same time, the subsampling phase-locked loop structure further reduces phase noise, providing a technical solution for the application of injection-locked oscillators in millimeter-wave communication and high-speed data conversion systems with high clock accuracy and low jitter requirements.

[0070] The embodiments given above are preferred examples for implementing the present invention, and the present invention is not limited to the above embodiments. Any non-essential additions or substitutions made by those skilled in the art based on the technical features of the present invention are within the protection scope of the present invention.

Claims

1. A low-jitter injection-locked phase-locked loop based on two-dimensional spatiotemporal correction technology, characterized in that, The injection-locked phase-locked loop includes: A phase-locked loop (PLL) includes a frequency-locked loop and a subsampled PLL; the subsampled PLL is used to achieve phase locking, and the frequency-locked loop is used to achieve frequency locking; in the PLL signal locking process, frequency locking is completed first, followed by phase locking. An injection locking circuit, which is connected to the phase-locked loop, is used to provide injection pulse signals to the phase-locked loop; A two-dimensional spatiotemporal correction circuit has an input terminal connected to an oscillation signal and an injected pulse signal, and an output terminal outputting a delay adjustment signal to an injection locking circuit. By comparing the period and phase information of the oscillation signal and the injected pulse signal, the two-dimensional spatiotemporal correction circuit generates a delay adjustment signal that is fed back to the injection locking circuit, thereby realizing the correction of the time and pulse width of the injected pulse signal. The two-dimensional spatiotemporal correction circuit includes injection time correction and injection pulse width correction; the injection time correction outputs a first delay adjustment signal to the injection locking circuit, which is used to correct the time of the injected pulse signal so that the midpoint of the injected pulse signal is aligned with the zero-crossing point of the oscillation signal; the injection pulse width correction outputs a second delay adjustment signal to the injection locking circuit, which is used to correct the pulse width of the injected pulse signal, thereby increasing the injection intensity of the pulse signal and suppressing phase-locked loop jitter. The injection locking circuit includes a first variable delay unit, a second variable delay unit, and an AND gate; the input of the first variable delay unit is connected to a reference signal and a first delay adjustment signal; the input of the second variable delay unit is connected to the output of the first variable delay unit and the second delay adjustment signal; the outputs of the first and second variable delay units are both connected to the input of the AND gate, and the output of the AND gate outputs an injection pulse signal.

2. The low-jitter injection-locked phase-locked loop based on two-dimensional spatiotemporal correction technology according to claim 1, characterized in that, The injection time correction includes a first comparator, a first accumulator, and a second subsampling phase detector; The input of the second subsampling phase detector is connected to the oscillation signal and the injected pulse signal, its output is connected to the negative input of the first comparator, the positive input of the first comparator is connected to the voltage, the output of the first comparator is connected to the input of the first accumulator, and the output of the first accumulator outputs the first delay adjustment signal; The injection pulse width correction includes a second comparator, a second accumulator, and a second charge pump; The input terminal of the second charge pump is connected to the oscillation signal and the injection pulse signal, and its output terminal is connected to the negative input terminal of the second comparator. The positive input terminal of the second comparator is connected to the voltage, and the output terminal of the second comparator is connected to the input terminal of the second accumulator. The output terminal of the second accumulator outputs the second delay adjustment signal.

3. A low-jitter injection-locked phase-locked loop based on two-dimensional spatiotemporal correction technology according to claim 2, characterized in that, The second subsampling phase detector includes a first capacitor and a fifth NMOS transistor; the gate of the fifth NMOS transistor is connected to an oscillation signal, its drain is connected to an injection pulse signal, the source of the fifth NMOS transistor is connected to one end of the first capacitor and serves as the output terminal of the second subsampling phase detector; the other end of the first capacitor is grounded.

4. A low-jitter injection-locked phase-locked loop based on two-dimensional spatiotemporal correction technology according to claim 2, characterized in that, The second charge pump includes a second capacitor, a sixth NMOS transistor, and a fourth PMOS transistor; The source of the fourth PMOS transistor is connected to a power supply, and its gate is connected to an injected pulse signal; the gate of the sixth NMOS transistor is connected to an oscillation signal, and its source is grounded; the drain of the sixth NMOS transistor is connected to the drain of the fourth PMOS transistor and one end of the second capacitor, and serves as the output terminal of the second charge pump; the other end of the second capacitor is grounded.

5. A low-jitter injection-locked phase-locked loop based on two-dimensional spatiotemporal correction technology according to claim 1, characterized in that, Both the first variable delay unit and the second variable delay unit include a variable current source, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a first inverter, a second inverter, and several stages of delay units; The input terminal of the first inverter is the input terminal of the first variable delay unit and the second variable delay unit; The output of the second inverter is the output of both the first variable delay unit and the second variable delay unit; The negative terminal of the variable current source is connected to the power supply, and its positive terminal is connected to the gate and drain of the first NMOS transistor. The control terminal of the variable current source is connected to a delay adjustment signal. The gate of the first NMOS transistor is connected to the drain of the first NMOS transistor, the gate of the second NMOS transistor, and the VN voltage. The sources of the first NMOS transistor and the second NMOS transistor are both grounded. The drain of the second NMOS transistor is connected to the gate of the first PMOS transistor, the drain of the first PMOS transistor, and the VP voltage. The source of the first PMOS transistor is connected to the power supply. The output of the first inverter is connected to the first input of the first stage delay unit. The first input of each stage delay unit is connected to the output of the previous stage delay unit. The second input of each stage delay unit is connected to the VP voltage. The third input of each stage delay unit is connected to the VN voltage. The output of the last stage delay unit is connected to the input of the second inverter.

6. A low-jitter injection-locked phase-locked loop based on two-dimensional spatiotemporal correction technology according to claim 5, characterized in that, Each delay unit includes a second PMOS transistor, a third PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; In each delay unit, the gate of the second PMOS transistor is the second input terminal of the delay unit, the source of the second PMOS transistor is connected to the power supply, and its drain is connected to the source of the third PMOS transistor; the gate of the third PMOS transistor is connected to the gate of the fourth NMOS transistor and is the first input terminal of the delay unit; the drain of the third PMOS transistor is connected to the drain of the fourth NMOS transistor and is the output terminal of the delay unit; the source of the fourth NMOS transistor is connected to the drain of the third NMOS transistor, the source of the third NMOS transistor is grounded, and the gate of the third NMOS transistor is the third input terminal of the delay unit.

7. A low-jitter injection-locked phase-locked loop based on two-dimensional spatiotemporal correction technology according to claim 1, characterized in that, The frequency-locked loop includes a frequency and phase detector, a first charge pump, a frequency divider, a loop filter, and an injection-locked oscillator; The injection-locked oscillator outputs an oscillation signal; The frequency divider's input terminal is connected to the oscillation signal, and its output terminal is connected to the frequency and phase detector; the other input terminal of the frequency and phase detector is connected to the reference signal, the output terminal of the frequency and phase detector is connected to the input terminal of the first charge pump, the output terminal of the first charge pump is connected to the input terminal of the loop filter, and the output terminal of the loop filter is connected to the injection-locked oscillator.

8. A low-jitter injection-locked phase-locked loop based on two-dimensional spatiotemporal correction technology according to claim 7, characterized in that, The subsampling phase-locked loop includes a first subsampling phase detector and a transconductance module; The input of the first subsampling phase detector is connected to the reference signal and the oscillation signal, and its output is connected to the input of the transconductance module. The output of the transconductance module is connected to the other input of the loop filter. The first subsampling phase detector, the transconductance module, the loop filter, and the injection-locked oscillator form the subsampling phase-locked loop.

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