Display chip for intelligent power management and preparation method

Abstract

The invention provides a display chip for intelligent power management and a preparation method, and belongs to the technical field of display chips. Comprising a substrate, a buffer region, a multi-quantum well region, an LED region and an intelligent display region, wherein the substrate, the buffer region and the multi-quantum well region are sequentially stacked, and the LED region and the intelligent display region are arranged above the multi-quantum well region in different regions; the substrate and the buffer region serve as a display chip substrate, provide mechanical support and adjust lattice mismatch stress between different materials; the multi-quantum well region provides a basic carrier transport structure for the LED region and the intelligent display region; the LED area and the intelligent display area are based on the multi-quantum well area, and the cooperation of the light emitting function and the display function is achieved through the specific structures of the LED area and the intelligent display area. The LED light-emitting function and the intelligent display function are integrated, the integrated design of power management and display is achieved, and the function integration level and the energy utilization efficiency of a display chip are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display chip, in particular to a display chip for intelligent power management and a preparation method thereof. BACKGROUND

[0002] With the rapid development of electronic devices, intelligent power management technology plays an increasingly important role in improving system energy efficiency, prolonging battery life, and ensuring safe operation of devices. In particular, in the field of display technology, the combination of integrated power management and display functions has become a trend in the industry.

[0003] Currently, intelligent power management systems usually adopt a discrete design architecture, i.e., power switching devices (such as silicon-based MOSFET or discrete GaNHEMT) and status indicator LEDs, protection circuits (such as current sensors, comparators, and logic control units) are connected through PCB board level to realize functional integration. This scheme relies on external ADC, driving chip and signal processing circuit to monitor the load state, and provides visual feedback through independent LED or digital display screen, and the protection function is realized through overcurrent detection IC or MCU. However, this discrete design has the disadvantages of large size, low integration, limited response speed, etc., and is difficult to meet the needs of modern electronic devices for miniaturization and high efficiency.

[0004] In the field of display chips, existing technologies mainly focus on improving LED light efficiency and display performance. For example, Chinese Patent Publication No. CN105161586A discloses an LED epitaxial structure with a combined barrier multi-quantum well and a preparation method thereof. The structure is composed of InGaN potential well layer, InAlGaN barrier layer, GaN barrier layer and InAlGaN barrier layer periodically stacked, which essentially improves the crystal quality and internal quantum efficiency, and improves the device performance and light efficiency. Chinese Patent Publication No. CN105355737B proposes a high light efficiency quantum well combined LED epitaxial structure, including a lower multi-quantum well structure, a constant temperature multi-quantum well structure and an upper multi-quantum well structure, which can effectively reduce the stress between the well and barrier interfaces, relieve the bending of the energy band, and improve the efficiency of hole and electron injection into the active region and the radiation recombination efficiency.

[0005] In addition, Chinese Patent Publication No. CN109755360A introduces a multi-quantum well LED epitaxial structure with a combined well, which is composed of a GaN barrier layer and a combined well layer composed of a periodic superposition structure. The combined well structure is composed of a low-In-concentration InGaN well layer, a high-In-concentration InGaN well layer, and a low-In-concentration InGaN well layer, which can significantly block and diffuse N-type electron injection and enhance the ability of quantum well bound electrons. Chinese Patent Publication No. CN110047924B provides a high-resistance buffer layer using a GaN-based narrow well multi-quantum well structure and a preparation method. By designing the content of Al in the multiple multi-quantum well structure stress transfer layers to decrease from bottom to top, the device performance is improved. Chinese Patent Publication No. CN105932124B discloses an LED epitaxial structure, which increases the reverse breakdown voltage by inserting a low-temperature grown n-type GaN layer in the traditional stress release superlattice structure, effectively improving the reliability of LED products.

[0006] However, the above-mentioned prior art mainly focuses on the improvement of LED luminous efficiency and display performance, and has not yet solved the problem of high integration of intelligent power management and display function. The existing discrete design scheme has the following obvious defects: 1. Large system size: the PCB board level connection of discrete components occupies a large space, which is difficult to meet the miniaturization demand of portable devices; 2. Low integration: power management, display and protection functions are scattered in different chips, increasing system complexity and cost; 3. Response speed is limited: signal transmission delay between discrete components reduces the response speed of the system to abnormal state, affecting the protection effect; 4. Higher power consumption: multi-chip solution increases signal transmission path and interface loss, reducing the overall energy efficiency of the system; 5. Insufficient reliability: the connection between multiple discrete components increases the system failure points, reducing the overall reliability.

[0007] Therefore, it is urgent to develop a display chip that highly integrates intelligent power management function and display function to solve the above technical problems and meet the needs of modern electronic devices for miniaturization, high efficiency and high reliability. SUMMARY

[0008] In order to solve the technical problems of large size, low integration, limited response speed and other technical problems caused by the discrete design of the existing intelligent power management technical scheme, realize the miniaturization and intelligentization of the power module, the present application provides a display chip for intelligent power management and a preparation method.

[0009] To achieve the above-mentioned purpose, the present application provides the following solutions:

[0010] A display chip for intelligent power management, comprising a substrate and buffer zone, a multi-quantum well zone, and an LED zone and an intelligent display zone arranged in the multi-quantum well zone in sequence; the substrate and buffer zone serve as the base of the display chip, provide mechanical support and adjust the lattice mismatch stress between different materials; the multi-quantum well zone provides a basic carrier transport structure for the LED zone and the intelligent display zone; the LED zone and the intelligent display zone realize the cooperation of light emitting and display functions through their respective unique structures based on the multi-quantum well zone.

[0011] Preferably, the substrate and buffer zone comprises a substrate layer and a buffer layer, the buffer layer is epitaxially grown on the surface of the substrate layer, and the buffer layer adopts Fe or C doped GaN material; the substrate layer is one of a silicon substrate, a sapphire substrate or a homo-GaN substrate.

[0012] Preferably, the multi-quantum well zone comprises an intrinsic GaN layer, an InGaN multi-quantum well structure and an AlGaN barrier layer; the intrinsic GaN layer is deposited on the surface of the buffer layer of the substrate and buffer zone and directly connected with the buffer layer; the InGaN multi-quantum well structure is grown on the surface of the intrinsic GaN layer and directly connected with the intrinsic GaN layer; the AlGaN barrier layer covers the surface of the InGaN multi-quantum well structure and directly connected with the InGaN multi-quantum well structure; a two-dimensional electron gas is formed at the heterojunction between the AlGaN barrier layer and the InGaN multi-quantum well structure due to spontaneous polarization and piezoelectric effect, and the carrier transport capability is enhanced by utilizing the inherent polarization characteristics of III-nitride materials.

[0013] Preferably, the LED zone comprises a first P-GaN layer above the AlGaN barrier layer of the multi-quantum well zone, serving as a hole injection layer; a Ni / Au composite metal layer evaporated on the surface of the first P-GaN layer, forming a low-resistance ohmic contact after high-temperature alloying treatment; and a drain prepared on the Ni / Au composite metal layer, used for completing the interconnection of the LED zone device.

[0014] Preferably, the intelligent display zone comprises a source electrode and a gate electrode prepared on the surface of the AlGaN barrier layer of the multi-quantum well zone, both of which adopt a metal electrode structure; a SiN passivation layer covering the AlGaN barrier layer, used for repairing the interface defects introduced by the etching process and improving the stability of the device; a second P-GaN layer below the gate electrode, used for reducing the off-state leakage current by depleting the 2DEG under the gate; a first P-GaN layer between the AlGaN barrier layer and an anode, serving as a hole injection layer; and an anode adopting a Ni / Au metal layer structure, forming an ohmic contact with the first P-GaN layer after high-temperature annealing, used for realizing the electrical interconnection of the intelligent display zone.

[0015] Preferably, the first P-GaN layer is a hole injection layer shared by the LED area and the smart display area, and forms an ohmic contact with the metal electrodes of the two areas, respectively; and the drain is an interconnection structure shared by the LED area and the smart display area, and is deposited on the anode metal layer of the two areas, respectively, to complete the electrical output.

[0016] The application further provides a preparation method of the display chip for intelligent power management.

[0017] S1, preparing an epitaxial wafer comprising a substrate layer, a buffer layer, an intrinsic GaN layer, an InGaN multi-quantum well layer, an AlGaN barrier layer and a P-GaN layer, and cleaning the epitaxial wafer by using an arowana solution and a BOE solution;

[0018] S2, after photoetching the epitaxial wafer by using a photoresist, achieving mesa isolation by using ICP etching, and cleaning the epitaxial wafer again;

[0019] S3, etching a light-emitting area and a photoelectric detection area on the P-GaN layer, then cleaning and annealing the epitaxial wafer under an inert atmosphere to repair surface damage of the epitaxial wafer; the P-GaN layer comprises a first P-GaN layer and a second P-GaN layer;

[0020] S4, after step S3, sequentially preparing a source electrode, an anode electrode, a gate electrode and a drain electrode on the epitaxial wafer; wherein photoetching, metal evaporation and sputtering, peeling and annealing are included to form a contact, and the preparation of the display chip is completed.

[0021] Preferably, in S4, when the source electrode is prepared, LOR10A+AZ5214E double-layer photoresist is used for photoetching, Ti / Al / Ni / Au metal is electron-beam evaporated, and ohmic contact is formed by annealing at 850 DEG C for 30 seconds in an N2 environment after peeling; when the anode electrode is prepared, Ni / Au is electron-beam evaporated, and ohmic contact is formed by annealing at 550 DEG C for 5 minutes in an air environment after peeling.

[0022] Preferably, in S4, when the gate electrode and the drain electrode are prepared, Ni / Au is formed by magnetron sputtering to form a Schottky contact; the peeling process is as follows: the sample is soaked in acetone for 15 minutes, and then is soaked in an NMP solution at 90 DEG C for 15 minutes.

[0023] According to the specific embodiments of the application, the following technical effects are achieved:

[0024] (1) The application realizes monolithic integration of the high-efficiency power switch and the photoelectric indication function on a single chip, realizes miniaturization and intelligentization of the power module, significantly improves the integration degree and response speed compared with the existing discrete scheme, eliminates signal transmission delay and parasitic loss in the traditional multi-chip scheme, and reduces PCB occupation space and system complexity.

[0025] (2) The application directly fuses the two-dimensional electron gas channel and the InGaN quantum well, improves the injection efficiency of carriers, and greatly improves the light intensity of the InGaN quantum well layer; at the same time, the wiring loss and delay between the discrete switching device and the indicator light in the traditional power module are eliminated, and the response speed and reliability are significantly improved;

[0026] (3) The application can realize dynamic load protection, multi-level state coding and other advanced functions through the cooperative design of the gate control signal of the HEMT and the LED light output; and the LED can not only provide intuitive state feedback, but also be directly associated with the working parameters of the HEMT through its photoelectric properties, to realize more accurate real-time protection and diagnosis. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings described below are only some embodiments of the application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0028] Figure 1 A two-dimensional structure schematic diagram of a display chip provided for the embodiments of the application;

[0029] Figure 2 A light-out function diagram of a display chip provided for the embodiments of the application;

[0030] Figure 3 A flow principle diagram of a display chip preparation method provided for the embodiments of the application;

[0031] Explanation of reference signs:

[0032] 1, substrate layer; 2, buffer layer; 3, intrinsic GaN layer; 4, InGaN multi-quantum well structure; 5, AlGaN barrier layer; 6, source electrode; 7, gate electrode; 8, first P-GaN layer; 9, anode; 10, drain electrode; 11, SiN passivation layer; 12, second P-GaN layer; 13, substrate and buffer zone; 14, multi-quantum well zone; 15, intelligent display zone; 16, LED zone. DETAILED DESCRIPTION

[0033] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0034] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] Example

[0036] like Figure 1 As shown, this embodiment provides a display chip for intelligent power management, including a substrate and a buffer zone 13, a multi-quantum well region 14 stacked in sequence, and an LED region 16 and an intelligent display region 15 arranged in regions above the multi-quantum well region 14; the substrate and the buffer zone 13 serve as the base of the display chip, providing mechanical support and adjusting the lattice mismatch stress between different materials; the multi-quantum well region 14 provides a basic carrier transport structure for the LED region 16 and the intelligent display region 15; the LED region 16 and the intelligent display region 15 are based on the multi-quantum well region 14, and realize the coordinated light-emitting and display functions through their respective unique structures.

[0037] The substrate and buffer zone 13 serve as the base of the display chip, providing mechanical support and regulating lattice mismatch stress between different materials. The substrate and buffer zone 13 comprises a substrate layer 1 and a buffer layer 2. Buffer layer 2 is epitaxially grown on the surface of substrate layer 1 and is made of Fe- or C-doped GaN material. Substrate layer 1 can be made of a silicon substrate, sapphire substrate, or a homogeneous GaN substrate.

[0038] The multi-quantum well region 14 provides a basic carrier transport structure for the LED region 16 and the smart display region 15. The multi-quantum well region 14 includes an intrinsic GaN layer 3, an InGaN multi-quantum well structure 4, and an AlGaN barrier layer 5. The intrinsic GaN layer 3 is deposited on the surface of the buffer layer 2 between the substrate and the buffer region 13 and is directly connected to the buffer layer 2. The InGaN multi-quantum well structure 4 is grown on the surface of the intrinsic GaN layer 3 and is directly connected to the intrinsic GaN layer 3. The AlGaN barrier layer 5 covers the surface of the InGaN multi-quantum well structure 4 and is directly connected to the InGaN multi-quantum well structure 4. At the heterojunction between the AlGaN barrier layer 5 and the InGaN multi-quantum well structure 4, a two-dimensional electron gas is formed due to spontaneous polarization and piezoelectric effect, utilizing the inherent polarization characteristics of the group III nitride material to enhance the carrier transport capability.

[0039] The LED region 16 includes a first P-GaN layer 8 above the AlGaN barrier layer 5 in the multi-quantum well region 14 as a hole injection layer; a Ni / Au composite metal layer evaporated on the surface of the first P-GaN layer 8, which is alloyed at a high temperature of 550°C to form a low-resistance ohmic contact. The drain 10 prepared on the Ni / Au composite metal layer adopts a Ti / Al / Ni / Au multilayer metal structure to complete the device interconnection of the LED region 16.

[0040] The smart display region 15 includes a source 6 and a gate 7 prepared on the surface of the AlGaN barrier layer 5 in the multi-quantum well region 14, both of which adopt a metal electrode structure. The source 6 adopts a Ti / Al / Ni / Au multilayer metal structure, and the gate 7 adopts a Ni / Au structure. A SiN passivation layer 11 covering the AlGaN barrier layer 5 is deposited by a PECVD process to repair the interface defects introduced by the etching process and improve the stability of the device. A second P-GaN layer 12 below the gate 7 reduces the off-state leakage current by depleting the 2DEG under the gate. The first P-GaN layer 8 between the AlGaN barrier layer 5 and the anode 9 serves as a hole injection layer. The anode 9 adopting a Ni / Au metal stack structure forms an ohmic contact with the first P-GaN layer 8 after annealing at a high temperature of 550°C, and is used to realize the electrical interconnection of the smart display region 15.

[0041] In the embodiment, the first P-GaN layer 8 is a hole injection layer shared by the LED region 16 and the smart display region 15, and forms an ohmic contact with the metal electrodes of the two regions, respectively. The drain 10 is an interconnection structure shared by the LED region 16 and the smart display region 15, and is deposited on the metal layer of the anode 9 of the two regions to complete the electrical output. This shared structure design simplifies the device manufacturing process, reduces the photolithography steps, and at the same time ensures the electrical interconnection performance between the LED region 16 and the smart display region 15.

[0042] Referring to Figure 2 , the smart power management display chip realizes the effective combination of the light-emitting and display functions through the cooperative work of the LED region 16 and the smart display region 15. When the LED region 16 works, electrons are injected from the drain 10, and light is emitted through the recombination of the electrons and holes in the multi-quantum well region 14. The smart display region 15 controls the two-dimensional electron gas channel through the gate 7 to adjust the current size, thereby realizing the smart power management function. The two functional regions share the multi-quantum well region 14 as a basic carrier transport structure, which greatly improves the device integration and energy utilization efficiency.

[0043] In addition, as Figure 3 shown, the embodiment further provides a preparation method of a display chip for smart power management, including the following steps:

[0044] S1, prepare an epitaxial wafer containing a substrate layer, a buffer layer, an intrinsic GaN layer, an InGaN multi-quantum well layer, an AlGaN barrier layer, and a P-GaN layer, and clean the epitaxial wafer by piranha solution and BOE solution;

[0045] In the present preparation method, the basic structure of the epitaxial wafer is the same as the display chip structure for intelligent power management described above, including a substrate and a buffer region, a multi-quantum well region, and a LED region and an intelligent display region arranged in different regions. The material selection and function of the substrate layer, the buffer layer, the intrinsic GaN layer, the InGaN multi-quantum well layer, the AlGaN barrier layer, and the P-GaN layer are the same as described in Embodiment One. In the cleaning process, piranha solution is used first to remove organic contaminants, and then BOE solution is used to remove surface oxide layers to ensure that the surface of the epitaxial wafer is clean.

[0046] S2, after photoresist is used to photoetch the epitaxial wafer, mesa isolation is achieved by ICP etching, and the epitaxial wafer is cleaned again;

[0047] After photoetching is completed, mesa isolation is performed using ICP etching process, and the etching depth is controlled at about 500 nm to ensure electrical isolation of each functional region. After etching is completed, the standard cleaning process is used again to remove residues.

[0048] S3, etching the light-emitting region and the photodetecting region on the P-GaN layer, then cleaning, and annealing to repair surface damage of the epitaxial wafer in an inert atmosphere; the P-GaN layer includes a first P-GaN layer and a second P-GaN layer;

[0049] In this step, the light-emitting region and the photodetecting region are defined on the P-GaN layer by photoetching and etching process. The P-GaN layer includes a first P-GaN layer and a second P-GaN layer, wherein the first P-GaN layer serves as a hole injection layer shared by the LED region and the intelligent display region, and the second P-GaN layer is located below the gate electrode for depleting the 2DEG under the gate to reduce the off-state current. After etching is completed, annealing is performed in a nitrogen atmosphere at a temperature of 600°C for 10 minutes to repair surface damage introduced during etching.

[0050] S4, after step S3 is completed, source, anode, gate, and drain are prepared on the epitaxial wafer in sequence; which includes photoetching, metal evaporation and sputtering, stripping, and annealing to form contacts, and the preparation of the display chip is completed.

[0051] When the source electrode is prepared, LOR10A+AZ5214E double-layer resist photoetching is adopted, Ti / Al / Ni / Au metal is evaporated by electron beam, and after stripping, ohmic contact is formed by annealing at 850℃ for 30 seconds in N2 environment. When the anode electrode is prepared, Ni / Au is evaporated by electron beam, and after stripping, ohmic contact is formed by annealing at 550℃ for 5 minutes in air environment. When the gate electrode and the drain electrode are prepared, Ni / Au is formed by magnetron sputtering to form Schottky contact. The stripping process is as follows: the sample is soaked in acetone for 15 minutes, and then is heated and soaked in NMP solution at 90℃ for 15 minutes.

[0052] The display chip for intelligent power management is prepared by the preparation method, the display chip integrates LED light emitting function and intelligent display function, high integration and high energy utilization efficiency are realized by sharing the multi-quantum well region as the basic carrier transport structure. When the prepared display chip works in the LED region, electrons are injected from the drain electrode, and light is emitted by the recombination of the holes and the electrons in the multi-quantum well region; the intelligent display region adjusts the current size by controlling the two-dimensional electron gas channel through the gate electrode, and realizes the intelligent power management function.

[0053] Therefore, the display chip and the preparation method for intelligent power management integrate LED light emitting function and intelligent display function, realize the integrated design of power management and display, and improve the functional integration and energy utilization efficiency of the display chip.

[0054] The principles and implementation manners of the present application are described by using specific examples in the present application, and the above examples are only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges will be changed. In conclusion, the content of the present application should not be understood as the limitation of the present application.

Claims

1. A display chip for intelligent power management, characterized in that: It includes a substrate and a buffer zone, a multi-quantum well zone, which are stacked in sequence, and an LED zone and an intelligent display zone which are arranged in different regions above the multi-quantum well zone; the substrate and the buffer zone serve as the base of the display chip, providing mechanical support and adjusting the lattice mismatch stress between different materials; the multi-quantum well zone provides a basic carrier transport structure for the LED zone and the intelligent display zone; the LED zone and the intelligent display zone are based on the multi-quantum well zone, and realize the coordinated light-emitting and display functions through their respective unique structures.

2. The display chip for intelligent power management according to claim 1, characterized in that: The substrate and buffer zone include a substrate layer and a buffer layer. The buffer layer is epitaxially grown on the surface of the substrate layer and is made of Fe- or C-doped GaN material. The substrate layer is a silicon substrate, a sapphire substrate or a homogeneous GaN substrate.

3. The display chip for intelligent power management according to claim 1, characterized in that: The multi-quantum well region includes an intrinsic GaN layer, an InGaN multi-quantum well structure, and an AlGaN barrier layer; the intrinsic GaN layer is deposited on the surface of the buffer layer between the substrate and the buffer zone and is directly connected to the buffer layer; the InGaN multi-quantum well structure is grown on the surface of the intrinsic GaN layer and is directly connected to the intrinsic GaN layer; the AlGaN barrier layer covers the surface of the InGaN multi-quantum well structure and is directly connected to the InGaN multi-quantum well structure; at the heterojunction between the AlGaN barrier layer and the InGaN multi-quantum well structure, a two-dimensional electron gas is formed due to spontaneous polarization and piezoelectric effect, and the inherent polarization characteristics of the group III nitride material are utilized to enhance the carrier transport capability.

4. The display chip for intelligent power management according to claim 1, characterized in that: The LED region includes: a first P-GaN layer located above the AlGaN barrier layer in the multi-quantum well region, serving as a hole injection layer; a Ni / Au composite metal layer evaporated on the surface of the first P-GaN layer, which is subjected to high-temperature alloying treatment to form a low-resistance ohmic contact; and a drain electrode prepared on the Ni / Au composite metal layer, which is used to complete the interconnection of devices in the LED region.

5. The display chip for intelligent power management according to claim 4, characterized in that: The smart display area includes: a source and a gate formed on the surface of the AlGaN barrier layer in the multi-quantum well area, both of which adopt a metal electrode structure; a SiN passivation layer covering the AlGaN barrier layer, which is used to repair interface defects introduced by the etching process and improve device stability; a second P-GaN layer located below the gate, which reduces off-state leakage current by depleting the 2DEG under the gate; a first P-GaN layer located between the AlGaN barrier layer and the anode, which serves as a hole injection layer; an anode using a Ni / Au metal stacked structure, which forms an ohmic contact with the first P-GaN layer after high-temperature annealing, and is used to realize electrical interconnection of the smart display area.

6. The display chip for intelligent power management according to claim 5, characterized in that: The first P-GaN layer is a hole injection layer shared by the LED area and the smart display area, and forms an ohmic contact with the metal electrodes of the two areas respectively; the drain is an interconnection structure shared by the LED area and the smart display area, and is deposited on the anode metal layers of the two areas respectively to complete the electrical output.

7. A method for preparing a display chip for intelligent power management according to any one of claims 1 to 6, characterized in that: The following steps are involved: S1. Prepare an epitaxial wafer including a substrate layer, a buffer layer, an intrinsic GaN layer, an InGaN multi-quantum well layer, an AlGaN barrier layer, and a P-GaN layer, and clean the epitaxial wafer using a piranha solution and a BOE solution; S2, after photolithography of the epitaxial wafer through photoresist, ICP etching is used to achieve mesa isolation, and the epitaxial wafer is cleaned again; S3, etching a light-emitting region and a photodetection region on the P-GaN layer, then cleaning it, and annealing it in an inert atmosphere to repair surface damage of the epitaxial wafer; the P-GaN layer includes a first P-GaN layer and a second P-GaN layer; S4. After completing step S3, the source, anode, gate and drain are sequentially prepared on the epitaxial wafer; this includes photolithography, metal evaporation and sputtering, stripping and annealing to form contacts, thus completing the preparation of the display chip.

8. The method for preparing a display chip for intelligent power management according to claim 7, characterized in that: In S4, when preparing the source, LOR10A+AZ5214E ​​double-layer photoresist is used, and Ti / Al / Ni / Au metal is evaporated by electron beam. After stripping, it is annealed for 30 seconds in N2 environment and 850℃ to form an ohmic contact; when preparing the anode, Ni / Au is evaporated by electron beam. After stripping, it is annealed for 5 minutes in air environment and 550℃ to form an ohmic contact.

9. The method for preparing a display chip for intelligent power management according to claim 7, characterized in that: In S4, when preparing the gate and drain, magnetron sputtering Ni / Au is used to form Schottky contacts; the stripping process is: the sample is immersed in acetone for 15 minutes, and then immersed in NMP solution heated at 90° C. for 15 minutes.

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