Preparation method of TSV-based capacitive ultrasonic transducer

Abstract

The invention relates to a preparation method of a TSV (Through Silicon Via)-based capacitive ultrasonic transducer, which comprises the following steps of: manufacturing an isolation groove (101) and a TSV conductive column (102) on an SOI (Silicon On Insulator) wafer A through a series of bulk silicon processes, manufacturing metal electrodes (103, 104 and 105) on the bottom surface of the SOI wafer A, performing high-temperature silicon-silicon bonding on a vibrating diaphragm structure layer SOI wafer B and the SOI wafer A, and preparing a first contact electrode (201), a second contact electrode (202) and a third contact electrode (203) on the wafer A. The beneficial effects of the invention are that the TSV conductive columns form a vertical conductive channel to realize electrical connection between different chip layers, and the led-out metal electrode and the movable sensitive diaphragm are not on the same surface, so that the metal electrode can be led out from the back surface by means of ball mounting and flip-chip bonding, the overall size of the device is greatly reduced, the signal transmission speed is improved, and crosstalk is reduced; and the overall performance of the CMUT is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of microsystem (MEMS) micro-nano manufacturing, in particular to a preparation method of a capacitive ultrasonic transducer based on TSV. BACKGROUND

[0002] The ultrasonic transducer plays a vital role in many fields such as medical ultrasonic imaging, non-destructive testing, industrial testing, etc. The capacitive micro-machined ultrasonic transducer (CMUT) has become a research hotspot in the field of ultrasonic transducers in recent years due to its high sensitivity, wide frequency band, and easy integration. The traditional CMUT usually adopts a planar interconnection structure to realize the electrical connection of the transducer unit and the external circuit. In this structure, the metal wiring is located on the surface of the chip, and the signal is led out through wire bonding. This planar interconnection method has many limitations. With the continuous increase of the size of the CMUT array, the wiring on the surface of the chip becomes more and more complex, which will lead to an increase in wiring resistance, an increase in signal transmission delay, and an aggravation of crosstalk problems, etc., which seriously affects the performance of the CMUT. In addition, the planar wiring also occupies a large chip area, which is not conducive to the high-density integration of the CMUT.

[0003] In order to solve the above problems, a through silicon via (TSV) technology is used to make a vertical conductive channel in the silicon substrate to realize the electrical connection between different layers of the chip, which can effectively shorten the signal transmission path, reduce the wiring resistance and signal delay, and improve the integration of the chip. Through the existing patent retrieval, Chinese patent “Capacitive micro-machined ultrasonic transducer (CMUT) device with through substrate via (TSV)” (Patent No. 201480010856.5) mainly fills the conductive metal copper in the TSV to form the electrical connection between the bottom metal electrode and the metal on the top movable diaphragm. “Capacitive micro-machined ultrasonic transducer (CMUT) with through substrate via (TSV) substrate plug” (Application No. 201480009849.3) mainly fills tungsten or copper into the TSV hole with a dielectric liner to form a TSV plug of single crystal silicon material to allow the bottom side to be electrically connected to the top plate of the CMUT element through the chip with a single crystal substrate material. The metal TSV manufacturing process is complex, the thermal stress is obvious, and it is easy to produce electromagnetic interference, which has a certain impact on the performance of the CMUT device. SUMMARY

[0004] The purpose of the present application is to solve the problems in the prior art, and to provide a preparation method of a capacitive ultrasonic transducer based on TSV. The metal electrode is formed on the back of the CMUT chip by filling polycrystalline silicon to prepare a TSV isolation ring. The signal can be led out from the back through the ball planting method, which greatly reduces the chip area and improves the signal strength.

[0005] The application adopts the technical scheme as follows:

[0006] A preparation method of a TSV-based capacitive ultrasonic transducer, comprising the following steps:

[0007] S1, selecting an SOI wafer A as a substrate, and forming a shallow cavity on a top layer silicon surface of the SOI wafer A by means of photolithography, silicon etching and sulfuric acid de-bonding;

[0008] S2, etching a first metal contact hole to a buried oxygen layer on the top layer silicon surface of the SOI wafer A by means of photolithography and deep silicon etching;

[0009] S3, performing thermal oxidation on the top layer silicon surface of the SOI wafer A by means of thermal oxidation to form a bonding surface silicon dioxide layer;

[0010] S4, removing the first connecting metal contact hole silicon dioxide on the top layer silicon surface of the SOI wafer A by means of photolithography, silicon dioxide etching and sulfuric acid de-bonding to expose the substrate silicon;

[0011] S5, preparing a third connecting metal contact hole on the top layer silicon surface of the SOI wafer A by means of photolithography, silicon dioxide etching, deep silicon etching, silicon dioxide etching and sulfuric acid de-bonding to expose the substrate silicon;

[0012] S5, bonding the substrate structure layer SOI wafer A and the diaphragm structure layer SOI wafer B through the bonding surface silicon dioxide layer at high temperature;

[0013] S6, preparing a TSV isolation groove to the buried oxygen layer on the other side of the substrate silicon of the SOI wafer A corresponding to the first connecting metal contact hole and the third connecting metal contact hole respectively by means of photolithography, silicon dioxide etching, deep silicon etching and sulfuric acid de-bonding;

[0014] S7, forming an isolation oxide layer in the TSV isolation groove by means of thermal oxidation;

[0015] S8, filling the TSV isolation groove with polycrystalline silicon by means of LPCVD deposition of polycrystalline silicon, and then removing the polycrystalline silicon by means of CMP and polycrystalline silicon wet etching to complete the preparation of the TSV isolation groove;

[0016] S9, removing the original double-sided silicon dioxide of the SOI wafer A and the SOI wafer B by means of BOE wet etching and re-performing thermal oxidation;

[0017] S9, removing the original double-sided silicon dioxide of the SOI wafer A and the SOI wafer B by means of BOE wet etching and re-performing thermal oxidation;

[0018] S10, the metal electrode contact hole pattern is formed on the substrate silicon surface of the SOI wafer A by means of photoetching, silicon dioxide etching and sulfuric acid de-gluing, and the first metal electrode contact hole, the second metal electrode contact hole and the third metal electrode contact hole are prepared;

[0019] S11, Ti / Au sputtering is performed on the substrate silicon surface of the SOI wafer A, and the metal electrode pattern is formed by means of photoetching, metal etching and organic de-gluing, and the first metal electrode, the second metal electrode and the third metal electrode are prepared in the first metal electrode contact hole, the second metal electrode contact hole and the third metal electrode contact hole respectively;

[0020] S12, the substrate silicon and the buried oxygen layer of the SOI wafer B are removed by means of mechanical thinning, TMAH etching and BOE etching, the top layer silicon of the SOI wafer B is exposed, and the vibrating diaphragm of the CMUT array is formed;

[0021] S13, the second contact electrode contact hole is prepared on the top layer silicon surface of the SOI wafer B by means of photoetching, silicon etching, silicon dioxide etching and organic de-gluing, and the top layer silicon of the SOI wafer A is etched and exposed;

[0022] S14, the silicon above the first connecting electrode contact hole and the third connecting electrode contact hole is removed on the top layer silicon surface of the SOI wafer B by means of photoetching, silicon etching and organic de-gluing, and the first connecting metal contact hole and the second connecting metal contact hole are exposed;

[0023] S15, Ti / Au sputtering is performed on the top layer silicon surface of the SOI wafer B, and the contact electrode pattern is formed by means of photoetching, metal etching and organic de-gluing, the preparation of the first contact electrode, the second contact electrode and the third contact electrode is completed, the vibrating diaphragm structure layer, the top layer silicon of the substrate structure layer and the substrate silicon of the substrate structure layer are in good contact with the first metal electrode, the second metal electrode and the third metal electrode, the electrical signals of each layer structure can be led out from the metal electrode on the back of the structure through the TSV, and finally the production of the capacitive ultrasonic transducer based on the TSV is completed.

[0024] The capacitive ultrasonic transducer based on the TSV has the advantages that the TSV filled with polycrystalline silicon is used to manufacture vertical conductive channels on the silicon wafer, the electrical connection between different chip layers is realized, the metal electrode led out by the ultrasonic transducer is not on the same surface as the movable sensitive vibrating diaphragm, the metal electrode can be led out from the back through the ball planting and flip chip welding, the overall size of the device is greatly reduced, the signal transmission speed is improved and the crosstalk is reduced, and the overall performance of the CMUT is improved. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 It is a sectional view of the capacitive ultrasonic transducer structure based on the TSV provided by the application;

[0026] Figure 2 is a schematic diagram of SOI wafer 1 after shallow cavity preparation is complete;

[0027] Figure 3 is a schematic diagram of SOI wafer 1 after first connection metal contact hole silicon etching is complete;

[0028] Figure 4 is a schematic diagram of SOI wafer 1 after thermal oxidation is complete;

[0029] Figure 5 is a schematic diagram of SOI wafer 1 after shallow cavity isolation groove preparation is complete;

[0030] Figure 6 is a schematic diagram of SOI wafer 1 after first connection metal contact hole silicon dioxide etching is complete;

[0031] Figure 7 is a schematic diagram of SOI wafer 1 after third connection metal contact hole preparation is complete;

[0032] Figure 8 is a schematic diagram of SOI wafer 1 top layer silicon surface and SOI wafer 2 top layer silicon surface after silicon-silicon bonding is complete;

[0033] Figure 9 is a schematic diagram of bonded wafer after TSV isolation groove etching is complete;

[0034] Figure 10 is a schematic diagram of bonded wafer after TSV isolation groove thermal oxidation is complete;

[0035] Figure 11 is a schematic diagram of bonded wafer after TSV isolation groove polysilicon filling and surface polysilicon removal is complete;

[0036] Figure 12 is a schematic diagram of bonded wafer after thermal oxidation is complete;

[0037] Figure 13 is a schematic diagram of bonded wafer after first metal electrode contact hole, second metal electrode contact hole, and third metal electrode contact hole preparation is complete;

[0038] Figure 14 is a schematic diagram of bonded wafer after first metal electrode, second metal electrode, and third metal electrode preparation is complete;

[0039] Figure 15 is a schematic diagram of SOI wafer 2 after substrate silicon and buried oxygen are removed, exposing the diaphragm;

[0040] Figure 16 is a schematic diagram of structure isolation groove and second contact electrode contact hole preparation is complete;

[0041] Figure 17is a schematic view of preparation of the first contact electrode contact hole and the third contact electrode contact hole;

[0042] Figure 18 is a schematic view of preparation of the first contact electrode, the second contact electrode and the third contact electrode.

[0043] DETAILED DESCRIPTION

[0044] In order to make the present application clearer, the following further describes a preparation method of a TSV-based CMUT chip structure of the present application with reference to the accompanying drawings, including the following steps:

[0045] S1, an SOI wafer A with a thickness of (380-1-2) μm is selected, and a 230 nm deep shallow cavity 109 is formed on the top layer of the SOI wafer A by means of photoetching, silicon etching and sulfuric acid degumming, as shown in Figure 2 ;

[0046] S2, as shown in Figure 3 , a 2 μm etching is performed on the top layer of the SOI wafer A by means of photoetching and deep silicon etching, and the 1 μm buried oxide layer is etched clean, and the surface photoresist is removed by sulfuric acid degumming, to complete the preparation of the first connection metal contact hole 106;

[0047] S3, as shown in Figure 4 , the SOI wafer A is subjected to thermal oxidation by means of thermal oxidation, and the thermal oxidation thickness is 250 nm;

[0048] As shown in Figure 5 , the shallow cavity isolation groove 110 is prepared on the top layer of the SOI wafer A by means of photoetching, 250 nm silicon dioxide etching, 1.75 μm deep silicon etching and sulfuric acid degumming, and the shallow cavity isolation groove is etched to the buried oxide;

[0049] S4, as shown in Figure 6 , the first connection metal contact hole 106 is subjected to silicon dioxide removal on the top layer of the SOI wafer A by means of photoetching, 250 nm silicon dioxide etching and sulfuric acid degumming, to expose the substrate silicon;

[0050] As shown in Figure 7 , the third connection metal contact hole 108 is prepared on the top layer of the SOI wafer A by means of photoetching, 250 nm silicon dioxide etching, 2 μm deep silicon etching, 1 μm silicon dioxide etching and sulfuric acid degumming, to expose the substrate silicon;

[0051] S5, as shown in Figure 8 , the substrate structure layer SOI wafer A and the diaphragm structure layer SOI wafer B are subjected to high-temperature silicon-silicon bonding through the bonding surface silicon dioxide;

[0052] S6, as shown in Figure 9As shown, a TSV isolation groove deep groove 101 is prepared on the substrate silicon surface of the SOI wafer A by means of lithography, 2 μm silicon dioxide etching, 380 μm deep silicon etching, and sulfuric acid de-bonding;

[0053] S7, as shown in Figure 10 As shown, an isolation oxide layer 101a of the TSV isolation groove is prepared by means of thermal oxidation, and the thermal oxide layer has a thickness of 250 nm;

[0054] S8, as shown in Figure 11 As shown, the TSV isolation groove is filled by means of LPCVD deposition of polysilicon 101b, and after filling, double-sided polysilicon is removed by means of CMP plus polysilicon wet etching, thereby completing the preparation of the TSV isolation groove;

[0055] S9, as shown in Figure 12 As shown, the double-sided silicon dioxide is removed by means of BOE wet etching, and thermal oxidation is performed again, and the thermal oxidation has a thickness of 2 μm;

[0056] S10, as shown in Figure 13 As shown, a metal electrode contact hole is patterned on the substrate silicon surface of the SOI wafer A by means of lithography, 2 μm silicon dioxide etching, and sulfuric acid de-bonding, thereby preparing a first metal electrode contact hole 112, a second metal electrode contact hole 113, and a third metal electrode contact hole 114, wherein the first metal electrode contact hole 112 and the third metal electrode contact hole 114 are etched to the TSV silicon pillars in the isolation grooves corresponding to the first connection metal contact hole 106 and the third connection metal contact hole 108, respectively, and the second metal electrode contact hole 113 is etched to other regions of the substrate silicon surface of the SOI wafer A;

[0057] S11, as shown in Figure 14 As shown, a 30 nm / 300 nm Ti / Au sputtering is performed on the substrate silicon surface of the SOI wafer A, a metal electrode is patterned by means of lithography, metal etching, and organic de-bonding, thereby preparing a first metal electrode 103 and a third metal electrode 105 of the TSV silicon pillars in the isolation grooves corresponding to the first connection metal contact hole 106 and the third connection metal contact hole 108, and a second metal electrode 104 corresponding to the substrate silicon in the second metal electrode contact hole 113.

[0058] S12, as shown in Figure 15 As shown, the substrate silicon 380 μm and the buried oxygen layer 1 μm of the SOI wafer B are removed by means of mechanical thinning, TMAH etching, and BOE etching, and the top layer silicon of the SOI wafer B, i.e., the diaphragm 204 of the CMUT array, is exposed;

[0059] S13, as shown in Figure 16As shown, the structure isolation groove and the second contact electrode contact hole 107 are prepared by using the process flow of photoetching, silicon etching 2 microns, silicon dioxide etching 250 nanometers and organic adhesive removal on the top layer of the SOI wafer B silicon surface, and the top layer of the SOI wafer A silicon is etched to be exposed;

[0060] S14, as shown in Figure 17 As shown, the silicon above the first contact electrode contact hole 106 and the third contact electrode contact hole 108 is removed by using the process flow of photoetching, silicon etching 2 microns and organic adhesive removal to form the corresponding cavities, and the first contact electrode contact hole 106 and the third contact electrode contact hole 108 are exposed.

[0061] S15, as shown in Figure 18 As shown, the 100nm / 500nm Ti / Au sputtering is performed on the top layer of the SOI wafer B silicon surface, the contact electrode patterning is performed by using the process flow of photoetching, metal etching and organic adhesive removal, and the first contact electrode 201, the second contact electrode 202 and the third contact electrode 203 are formed in the two cavities and the first metal contact hole 106, the second metal contact hole 107 and the third metal contact hole 108, wherein the first contact electrode 201 and the third contact electrode 203 are connected with the corresponding TSV silicon column respectively, the good contact between the top layer silicon of the diaphragm structure layer, the substrate structure layer and the first metal electrode, the second metal electrode and the third metal electrode is formed, and the electrical signals of each layer structure can be led out from the metal electrode on the back of the structure through the TSV, as shown in Figure 1 or Figure 18 As shown, the final production of the capacitive ultrasonic transducer based on TSV is completed.

[0062] The above embodiments of the present application are only examples for clearly illustrating the present application, and are not intended to limit the embodiments of the present application. Other different forms of changes or variations can be made on the basis of the above description for those skilled in the art. Here, all the embodiments are not required to be exhausted, and the obvious changes or variations extended from the essential spirit of the present application still belong to the protection scope of the present application.

Claims

1. A method for preparing a capacitive ultrasonic transducer based on TSV, comprising the following steps: S1, select SOI wafer A as substrate, and form a shallow cavity (109) on the top silicon surface of SOI wafer A by photolithography, silicon etching, and sulfuric acid stripping; S2, etching a first metal contact hole (106) from the top silicon surface of the SOI wafer A to the buried oxide layer by photolithography and deep silicon etching; S3, thermally oxidizing the top silicon surface of SOI wafer A by thermal oxidation to form a bonding surface silicon dioxide layer; A shallow cavity isolation groove (110) is prepared on the top silicon surface of the SOI wafer A by photolithography, silicon dioxide etching, deep silicon etching, and sulfuric acid degumming, and the shallow cavity isolation groove is etched to the buried oxide; S4, removing the silicon dioxide from the first connection metal contact hole (106) on the top silicon surface of the SOI wafer A by photolithography, silicon dioxide etching, and sulfuric acid degumming to expose the substrate silicon; A third connection metal contact hole (108) is prepared on the top silicon surface of the SOI wafer A by photolithography, silicon dioxide etching, deep silicon etching, silicon dioxide etching, and sulfuric acid stripping to expose the substrate silicon; S5, performing high-temperature silicon-silicon bonding between the substrate structure layer SOI wafer A and the diaphragm structure layer SOI wafer B through the bonding surface silicon dioxide layer; S6, using photolithography, silicon dioxide etching, deep silicon etching, and sulfuric acid stripping to prepare TSV isolation grooves (101) to the buried oxide layer at positions corresponding to the first connection metal contact hole (106) and the third connection metal contact hole (108) on the other side of the silicon substrate of the SOI wafer A; S7, forming an isolation oxide layer (101a) in the TSV isolation trench (101) by thermal oxidation; S8, filling the TSV isolation trench with polysilicon (101b) by depositing polysilicon using LPCVD, and removing the polysilicon by CMP plus polysilicon wet etching to complete the preparation of the TSV isolation trench; S9. Remove the original silicon dioxide on both sides of SOI wafer A and SOI wafer B by BOE wet etching and re-perform thermal oxidation; S10, patterning metal electrode contact holes on the silicon surface of the SOI wafer A substrate by photolithography, silicon dioxide etching, and sulfuric acid stripping to prepare a first metal electrode contact hole (112), a second metal electrode contact hole (113), and a third metal electrode contact hole (114); S11, performing Ti / Au sputtering on the silicon surface of the SOI wafer A substrate, and patterning the metal electrodes using a process flow of photolithography, metal etching, and organic debonding, and preparing a first metal electrode (103), a second metal electrode (104), and a third metal electrode (105) in the first metal electrode contact hole (112), the second metal electrode contact hole (113), and the third metal electrode contact hole (114), respectively; S12, removing the substrate silicon and buried oxide layer of SOI wafer B by mechanical thinning, TMAH etching, and BOE etching to expose the top silicon layer of SOI wafer B, thereby forming a diaphragm (204) of the CMUT array; S13, preparing a second contact electrode contact hole (107) on the top silicon surface of the SOI wafer B by using a process flow of photolithography, silicon etching, silicon dioxide etching, and organic stripping, and etching to expose the top silicon surface of the SOI wafer A; S14, using a process of photolithography, silicon etching, and organic stripping on the top silicon surface of the SOI wafer B to remove the silicon above the first connection electrode contact hole and the third connection electrode contact hole, thereby exposing the first connection metal contact hole (106) and the second connection metal contact hole (108); S15. Ti / Au sputtering is performed on the top silicon surface of the SOI wafer B, and contact electrodes are patterned using a process flow of photolithography, metal etching, and organic debonding to complete the preparation of the first contact electrode (201), the second contact electrode (202), and the third contact electrode (203), thereby forming good contact between the diaphragm structure layer, the top silicon of the substrate structure layer, the substrate silicon of the substrate structure layer, and the first metal electrode, the second metal electrode, and the third metal electrode. The electrical signals of each layer structure can be led out from the metal electrode on the back of the structure through TSV, and finally a capacitive ultrasonic transducer based on TSV is manufactured.

Images