Preparation method of high-reliability cross-step MEMS chip electrode layer

Abstract

The invention provides a preparation method of a high-reliability cross-step MEMS chip electrode layer. The method comprises the following steps: preparing a first silicon oxide layer on the surface of a silicon wafer; patterning the first silicon oxide layer; preparing a silicon groove structure; removing the residual first silicon oxide layer; preparing a second silicon dioxide layer for the first time; removing the second silicon oxide layer; repeatedly preparing a second silicon dioxide layer; and preparing a metal film layer on the second silicon dioxide layer. According to the method for preparing the silicon-based step-crossing MEMS chip electrode layer, the processing reliability of the electrode layer can be improved.

Description

TECHNICAL FIELD

[0001] The application relates to a preparation method of a stepped MEMS chip electrode layer and belongs to the field of micro-electro-mechanical system (MEMS) device processing. BACKGROUND

[0002] MEMS devices with resonance structures, such as MEMS inertial devices, oscillators, filters and the like, have high requirements for the air tightness of the devices. In order to realize air-tight packaging, a wafer-level vacuum packaging process with a three-layer silicon structure is usually adopted. The three-layer silicon structure comprises a substrate layer with an electrical signal connection function, a device layer with a movable function, and a cap layer with a support and protection function. A groove structure is prepared on the substrate layer and the cap layer, and the chips of the three-layer silicon structure are connected together by wafer bonding in the form of a ring, so as to realize the isolation between the inside and outside of the chip cavity, and the groove in the ring forms a cavity for the movable structure on the device layer to move.

[0003] For a process scheme in which coplanar electrodes are adopted to realize the interconnection between the device structure in the cavity and the electrode pads outside the cavity, electrode wiring needs to be performed on the substrate layer. In order to meet the isolation requirements between different electrodes, a silicon oxide dielectric material is usually prepared on the substrate layer with a groove structure before the metal electrode layer is prepared. Since the dielectric layer prepared by a thermal oxidation process has excellent compactness and insulation performance, the silicon oxide insulation dielectric layer on the substrate layer is usually prepared by a thermal oxidation process. For a surface thermal oxidation process with a groove structure, the "bird beak" effect affects the growth of silicon dioxide at the root of the groove, and further affects the thickness uniformity of the metal film layer on the silicon dioxide at the root of the groove. When the metal film layer is patterned into electrodes, the thickness non-uniformity of the metal film layer greatly increases the probability of electrode disconnection at the root of the groove, thereby increasing the risk of device failure.

[0004] The "bird beak" effect has a relatively prominent influence on the field of integrated circuits such as semiconductor field effect tubes, transistors and memories. The electric field intensity at the bird beak position is large, and breakdown is prone to occur. With the development of devices to deep submicron, in order to meet the isolation requirements between different devices in integrated circuits, the isolation technology has developed from local oxidation (LOCOS) process to shallow trench isolation (STI) technology. SMIC, Shanghai Hu Li Microelectronics and the like use the shallow trench isolation technology to improve the quality of the shallow trench isolation structure and the device performance by optimizing the growth process of the linear oxide layer and the device structure. However, no research on improving the influence of the "bird beak" effect on the performance of discrete devices has been reported. SUMMARY

[0005] The present application aims at overcoming the defects of the prior art and providing a preparation method of a MEMS chip electrode layer across steps, which can eliminate the uneven thickness of the medium layer caused by the "bird beak" effect in the thermal oxidation process, and the chip electrode layer prepared by the method has high reliability.

[0006] The technical scheme adopted by the present application is as follows:

[0007] The present application provides a preparation method of a high-reliability MEMS chip electrode layer across steps, which comprises the following steps:

[0008] (1) preparing a first silicon oxide layer on the surface of a silicon wafer; the first silicon oxide layer is prepared by using a thermal oxidation technology or a plasma chemical vapor deposition technology.

[0009] (2) patterning the first silicon oxide layer; the first silicon oxide layer on the surface of the silicon wafer is patterned by using a photoetching, exposure, etching and photoresist removal process.

[0010] (3) preparing a silicon trench structure; specifically, the anisotropic etching of silicon is performed by using a wet etching process, and the etching solution is an organic solution or an inorganic solution; the organic solution is EPW prepared by mixing ethylenediamine, o-dihydroxybenzene and water or tetramethylammonium hydroxide TMAH; and the inorganic solution is potassium hydroxide or sodium hydroxide.

[0011] The prepared silicon trench structure has no limitation on shape, lateral size and longitudinal size. The thickness t of the first silicon oxide layer and the depth d of the silicon trench structure satisfy the following relationship: t≥d / 50.

[0012] (4) removing the remaining first silicon oxide layer by using a dilute hydrofluoric acid solution or a BOE solution;

[0013] (5) preparing a second silicon oxide layer on the surface of the silicon wafer for the first time by using a thermal oxidation method;

[0014] The second silicon oxide layer prepared for the first time has a thickness of 0.1 μm to 3.0 μm, and the thermal oxidation method includes only using a dry oxygen method or a wet oxygen method, or using a combination of the two methods, and the oxidation temperature is 800°C to 1100°C.

[0015] The thickness and preparation conditions of the second silicon oxide layer prepared for the second time and the second silicon oxide layer prepared for the first time can be the same or different.

[0016] (6) removing the second silicon oxide layer by using a dilute hydrofluoric acid solution or a BOE solution;

[0017] (7) preparing a second silicon oxide layer on the surface of the silicon wafer for the second time by using a thermal oxidation method;

[0018] (8) preparing a metal film layer on the second silicon oxide layer to complete the preparation of the electrode layer of the MEMS chip across the step. The metal film layer is made of gold, chromium, nickel, platinum, titanium, tungsten, aluminum or copper.

[0019] The beneficial effects of the present application compared with the prior art are:

[0020] The electrode layer of the MEMS chip across the step prepared by the prior art has a silicon oxide groove structure introduced by the "bird beak" effect at the root of the silicon trench. The present application adopts the method of preparing the silicon oxide layer twice, which can eliminate the groove structure introduced by the "bird beak" effect at the root of the trench, and further improve the uniformity of the thickness of the metal film layer on the silicon oxide layer and the reliability of the electrode. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a process flow diagram of the prior art;

[0022] Figure 2 is a physical cross-section diagram of the electrode layer of the prior art;

[0023] Figure 3 is a process flow diagram of the present application;

[0024] Figure 4 is a physical cross-section diagram of the silicon trench structure;

[0025] Figure 5 is a physical cross-section diagram of the first preparation of the second silicon oxide layer of the present application;

[0026] Figure 6 is a physical cross-section diagram of the second preparation of the second silicon oxide layer of the present application;

[0027] Figure 7 is a physical cross-section diagram of the electrode layer of the present application. DETAILED DESCRIPTION

[0028] When preparing the electrode on the surface of the silicon wafer with a step structure, the "bird beak" effect will cause the thickness of the silicon oxide layer at the root of the trench to be obviously uneven, affecting the uniformity of the growth thickness of the silicon oxide at the root of the trench, and further introducing the failure problem of the electrode, further affecting the reliability of the electrode layer of the MEMS chip. The present application proposes a new process method for preparing the electrode, which completely eliminates the influence of the "bird beak" effect on the thermal oxidation process of the trench structure. The reasons for its poor performance are analyzed, Figure 1 is a process flow diagram of the prior art method for preparing the electrode of the MEMS chip, and the specific processing steps are as follows:

[0029] (1) preparing a first silicon oxide layer on the surface of the silicon substrate.

[0030] (2) patterning the first silicon oxide layer. The patterned first silicon oxide layer serves as a mask layer for the next etching process.

[0031] (3) Preparation of the trench structure. Anisotropic etching of silicon is performed by using a wet etching process.

[0032] (4) Removal of the remaining first silicon oxide layer.

[0033] (5) Preparation of the second silicon oxide layer. The second silicon oxide layer is prepared on the surface of the silicon wafer by using a thermal oxidation method.

[0034] (6) Preparation of the metal electrode layer on the surface of the second silicon oxide layer. Figure 2 The electrode structure is shown in the sectional view.

[0035] The electrode layer of the MEMS chip processed by using the prior art process has the following problems: Figure 2 In the red circle area at the root of the trench structure, the thickness of the metal electrode layer is obviously uneven.

[0036] In order to solve the above problems, the present application is described in detail below in combination with the drawings and specific embodiments. The flowchart of the process for preparing the electrode layer of the MEMS chip by using the process of the present application is shown in FIG. 1. Figure 3

[0037] The present application provides a preparation method of a high-reliability stepped MEMS chip electrode layer, which comprises the following steps:

[0038] (1) Preparation of the first silicon oxide layer on the surface of the silicon wafer; the first silicon oxide layer is prepared by using a thermal oxidation technology or a plasma chemical vapor deposition technology.

[0039] (2) Patterning of the first silicon oxide layer; the first silicon oxide layer on the surface of the silicon wafer is patterned by using a photoetching, exposure, etching and photoresist removal process.

[0040] (3) Preparation of the silicon trench structure; specifically, anisotropic etching of silicon is performed by using a wet etching process, and the etching solution is an organic solution or an inorganic solution; the organic solution is EPW prepared by mixing ethylenediamine, o-dihydroxybenzene and water or tetramethylammonium hydroxide TMAH; and the inorganic solution is potassium hydroxide or sodium hydroxide.

[0041] The prepared silicon trench structure has no limitation on shape, lateral size and longitudinal size. The thickness t of the first silicon oxide layer and the depth d of the silicon trench structure satisfy the following relationship: t≥d / 50.

[0042] (4) Removal of the remaining first silicon oxide layer by using a dilute hydrofluoric acid solution or a BOE solution.

[0043] (5) First preparation of the second silicon oxide layer on the surface of the silicon wafer by using a thermal oxidation method.

[0044] ​The second silicon oxide layer is prepared on the surface of the silicon wafer by a thermal oxidation method for the first time, and the thickness of the second silicon oxide layer is 0.1-3.0 μm; the thermal oxidation method includes only dry oxygen method or wet oxygen method, or a combination of the two methods, and the oxidation temperature is 800-1100 °C.

[0045] The thickness and preparation conditions of the second silicon oxide layer prepared for the second time can be the same as or different from those of the second silicon oxide layer prepared for the first time.

[0046] (6) removing the second silicon oxide layer by using a dilute hydrofluoric acid solution or a BOE solution;

[0047] (7) preparing a second silicon oxide layer on the surface of the silicon wafer by a thermal oxidation method for the second time;

[0048] (8) preparing a metal film layer on the second silicon oxide layer to complete the preparation of the electrode layer of the MEMS chip across the step; the metal film layer is made of gold, chromium, nickel, platinum, titanium, tungsten, aluminum or copper.

[0049] Embodiment:

[0050] The specific processing steps for preparing the electrode layer of the MEMS chip by the process method of the application are as follows:

[0051] (1) providing a silicon substrate with a thickness of 300 μm, and preparing a first silicon oxide layer with a thickness of 500 nm on the surface of the silicon substrate by a thermal oxidation technology.

[0052] The method for preparing the silicon oxide layer by the thermal oxidation technology is as follows: placing the silicon wafer in an oxidation furnace, setting the oxygen flow rate to 800 sccm and the oxidation temperature to 1100 °C under the condition of wet oxygen, and setting the oxidation time to 1 hour to prepare a silicon oxide layer with a thickness of 500 nm.

[0053] (2) patterning the first silicon oxide layer. Spinning photoresist AZ5214 as a mask material on the surface of the silicon wafer, and the thickness of the photoresist is about 1.5 μm; after exposure, the silicon wafer is immersed in a BOE etching solution to remove the silicon oxide material in the exposed area; and the photoresist mask is removed by using an organic solution.

[0054] (3) preparing a silicon trench structure. The silicon wafer after the surface first silicon oxide layer is patterned is placed in a potassium hydroxide etching solution with a temperature of 80 °C, the etching time is controlled to 10 min, and the etching depth is a trench with a depth of 10 μm. The structure is shown in the sectional view of the actual object. Figure 4

[0055] (4) removing the remaining first silicon oxide layer. The silicon wafer after the silicon trench processing is immersed in a dilute hydrofluoric acid solution with a concentration of 10% or a BOE solution for 5 min to remove the remaining first silicon oxide layer.

[0056] ​(5) The second silicon oxide layer with a thickness of 2 μm is prepared. The method for preparing the second silicon oxide layer by using the thermal oxidation technology is as follows: the silicon wafer is placed in an oxidation furnace, under the condition of wet oxygen, the oxygen flow is set to 800 sccm, the oxidation temperature is set to 1100 °C, and the oxidation time is set to 11 hours, so as to prepare the silicon oxide layer with a thickness of 2 μm. The structure actual section view is shown in Fig. 5, and there is an obvious groove structure caused by the "bird beak" effect in the red circle at the root of the trench. Figure 5

[0057] (6) The second silicon oxide layer is removed. The silicon wafer with the second silicon oxide layer with a thickness of 2 μm on the surface is soaked in a BOE solution or a dilute hydrofluoric acid solution with a concentration of 10% for 20 min, so as to remove the second silicon oxide layer prepared in the first time.

[0058] (7) The second silicon oxide layer is prepared for the second time. The second silicon oxide layer is prepared on the surface of the silicon wafer by using the thermal oxidation method, and the preparation method and process parameters are the same as those in step (5). The structure actual section view is shown in Fig. 6, and the thickness of the oxide layer is uniform at the corner of the root of the trench, and there is no groove structure. Figure 6

[0059] (8) The metal film layer is prepared on the surface of the silicon oxide layer. The metal film layer is prepared on the surface of the silicon wafer by using the magnetron sputtering technology, and the structure actual section view is shown in Fig. 7. The thickness of the metal film layer is uniformly distributed. Figure 7

[0060] The electrode layer prepared by using the process method in the present application has obviously improved reliability in the subsequent patterning process.

[0061] The part not described in detail in the present application is common knowledge for those skilled in the art.​​​

Claims

1. A method for preparing a high-reliability step-crossing MEMS chip electrode layer, characterized in that include: preparing a first silicon oxide layer on the surface of the silicon wafer; patterning the first silicon oxide layer; preparing a silicon trench structure; removing the remaining first silicon oxide layer; A second silicon oxide layer is first formed on the surface of the silicon wafer by using a thermal oxidation method; removing the second silicon oxide layer; preparing a second silicon oxide layer on the surface of the silicon wafer by a thermal oxidation method; A metal film layer is prepared on the second silicon oxide layer to complete the preparation of the electrode layer of the cross-step MEMS chip.

2. The method for preparing a high-reliability step-span MEMS chip electrode layer according to claim 1, characterized in that: The first silicon oxide layer is prepared by using thermal oxidation technology or plasma chemical vapor deposition technology.

3. The method for preparing a high-reliability step-span MEMS chip electrode layer according to claim 1, characterized in that: The first silicon oxide layer on the surface of the silicon wafer is patterned using photolithography, exposure, etching and photoresist removal processes.

4. The method for preparing a high-reliability step-span MEMS chip electrode layer according to claim 1, characterized in that: The preparation of the silicon trench structure specifically comprises: performing anisotropic etching of silicon using a wet etching process, wherein the etching solution is an organic solution or an inorganic solution, wherein the organic solution refers to EPW or tetramethylammonium hydroxide TMAH prepared by ethylenediamine, catechol and water; and the inorganic solution refers to potassium hydroxide or sodium hydroxide.

5. The method for preparing a high-reliability step-span MEMS chip electrode layer according to claim 4, characterized in that: The thickness t of the first silicon oxide layer and the depth d of the silicon trench structure satisfy the following relationship: t≥d / 50.

6. The method for preparing a high-reliability step-span MEMS chip electrode layer according to claim 4 or 5, characterized in that: The prepared silicon trench structure has no restrictions on shape, lateral size and vertical size.

7. The method for preparing a high-reliability step-span MEMS chip electrode layer according to claim 1, characterized in that: The second silicon oxide layer is first prepared on the surface of the silicon wafer by using a thermal oxidation method, and the thickness of the second silicon oxide layer is 0.1μm to 3.0μm; the thermal oxidation method includes using only a dry oxygen method or a wet oxygen method, or a combination of the two methods, and the oxidation temperature is 800℃ to 1100℃.

8. The method for preparing a high-reliability step-span MEMS chip electrode layer according to claim 1, characterized in that: The thickness and preparation conditions of the second silicon oxide layer prepared for the second time may be the same as or different from those of the second silicon oxide layer prepared for the first time.

9. The method for preparing a high-reliability step-span MEMS chip electrode layer according to claim 1, characterized in that: The metal film layer is made of gold, chromium, nickel, platinum, titanium, tungsten, aluminum or copper.

10. The method for preparing a high-reliability step-span MEMS chip electrode layer according to claim 1, characterized in that: When removing the first silicon oxide layer and the second silicon oxide layer, a dilute hydrofluoric acid solution or a BOE solution is used.

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