High-sensitivity broadband piezoelectric vibration sensing chip with cross-shaped annular structure and preparation method of high-sensitivity broadband piezoelectric vibration sensing chip

Abstract

The invention discloses a high-sensitivity broadband piezoelectric vibration sensing chip with a cross-shaped annular structure and a preparation method of the high-sensitivity broadband piezoelectric vibration sensing chip. A heterostructure of the high-sensitivity broadband piezoelectric vibration sensing chip is provided with a rectangular inner mass block, a middle mass ring and a frame which are sequentially arranged from the center to the outside, and the heterostructure is further provided with an inner ring cantilever beam and an outer ring cantilever beam; wherein the inner mass block, the middle mass ring and the frame are concentrically arranged, the corresponding edges of the inner mass block, the middle mass ring and the frame are parallel, the corresponding edges of the inner mass block and the middle mass ring are connected through an inner ring cantilever beam, and the corresponding edges of the middle mass ring and the frame are connected through an outer ring cantilever beam; the lower surfaces of the inner mass block, the middle mass ring, the inner ring cantilever beam and the outer ring cantilever beam are separated from the silicon substrate; the upper electrode layer is patterned with electrodes on the upper surfaces of the inner ring cantilever beam and the outer ring cantilever beam, and the surface of the passivation layer is provided with electrode leads connected with the electrodes. According to the invention, the volume of the mass block is reduced, the inherent frequency is improved, the utilization area of the piezoelectric sensitive layer is increased, and the problem of sensitivity reduction caused by high resonant frequency is compensated.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of micro-nano manufacturing and advanced sensing chip, and particularly relates to a high-sensitivity wide-band piezoelectric vibration sensing chip with a cross-ring structure and a preparation method thereof. BACKGROUND

[0002] In industrial production and scientific experiments, vibration is a key factor affecting the normal operation of equipment, reducing the stability and reliability of equipment performance. Vibration sensors are important tools for collecting vibration signals, and vibration monitoring technology based on vibration sensors has become an important means of equipment fault diagnosis and preventive maintenance.

[0003] Traditional vibration sensors have the disadvantages of large structure size, poor precision, and narrow frequency band, and are not suitable for collecting vibration signals in high-frequency and other special environments. Micro-electro-mechanical system (MEMS) technology combines micro-nano processing, semiconductor manufacturing, and sensor technology, and realizes the miniaturized manufacturing of sensors. Compared with traditional vibration sensors, MEMS vibration sensors have many incomparable advantages such as small size, high integration, high precision, high resonant frequency, and low power consumption.

[0004] Commonly used MEMS vibration sensors mainly include piezoresistive, capacitive, optical fiber, and piezoelectric types. MEMS piezoresistive vibration sensors have the advantages of strong anti-electromagnetic interference ability and easy manufacturing, but due to the inherent temperature dependence of material resistivity, they have poor temperature stability and poor noise resistance. MEMS capacitive vibration sensors have good temperature stability, high resolution, and good noise performance, but have a narrow working bandwidth and are only suitable for low-frequency monitoring fields, and are easily disturbed by parasitic capacitance. MEMS optical fiber vibration sensors have high temperature stability and strong anti-electromagnetic interference ability, but are complex to manufacture and the signal processing system is expensive. In comparison, MEMS piezoelectric vibration sensors have a wide working frequency band, high sensitivity, strong stability, and small temperature dependence. In addition, the unique sensing mechanism of piezoelectric vibration sensors allows them to work normally under passive conditions, with low power consumption, and has good application value.

[0005] The performance of a MEMS piezoelectric vibration sensor is determined by the structure of the sensor and the piezoelectric properties of the piezoelectric material. The structure of a MEMS piezoelectric vibration sensor is mainly a cantilever beam-mass block structure or a ring structure. The cantilever beam-mass block structure often has higher energy conversion efficiency than the ring structure, but has lower structural stiffness and complex processing technology. The ring structure has simple processing technology, high resonant frequency, but lower output sensitivity. MEMS piezoelectric vibration sensors usually use lead zirconate titanate (PZT), zinc oxide (ZnO) and aluminum nitride (AlN) as microstructure piezoelectric thin film materials. Among them, PZT has a large piezoelectric coefficient, but its low Curie temperature leads to process incompatibility during sensor preparation, and the heavy metal lead contained in it is not friendly to the human body and the environment; the piezoelectric coefficient of ZnO is low, which restricts the output performance of the device. Compared with PZT and ZnO, AlN is considered as the preferred material for MEMS sensor applications due to its low dielectric loss, high intrinsic signal-to-noise ratio and high Curie temperature. In addition, doping a proper amount of scandium (Sc) in AlN can significantly improve d 31 and d 33 the piezoelectric coefficient while the dielectric loss changes slightly.

[0006] At present, high-frequency vibration and strong impact are the main reasons that threaten the stable operation of large-scale equipment. The vibration monitoring technology based on MEMS piezoelectric vibration sensors requires the sensor to have high sensitivity, wide frequency band and strong impact resistance. However, the small size of micro-nano sensors limits the output performance of the device, so it is of great significance to simultaneously realize high working bandwidth and high sensitive output of the device in a limited space through structural design and material performance optimization. SUMMARY

[0007] To solve the problems in the prior art, the purpose of the present application is to provide a high-sensitivity wide-frequency-band piezoelectric vibration sensor chip with a cross-ring structure and a preparation method thereof. The mass block of the traditional cross-cantilever beam structure is divided into an inner mass block and an intermediate mass ring by structural design and four cantilever beams are added to connect them, which increases the utilization area of the piezoelectric layer of the device and compensates for the problem of reduced sensitivity caused by high resonant frequency of the device.

[0008] To achieve the above purpose, the technical scheme adopted by the present application is as follows: The application discloses a high-sensitivity wide-band piezoelectric vibration sensing chip with a cross-ring structure, which comprises a silicon substrate, and a functional heterostructure is formed on the surface of the silicon substrate by stacking an insulating layer, a lower electrode layer, a piezoelectric sensitive layer, an upper electrode layer and a passivation layer in sequence, wherein the heterostructure is provided with a rectangular inner mass block, an intermediate mass ring and a frame in sequence from the center outward, and further provided with an inner ring cantilever beam and an outer ring cantilever beam; wherein the inner mass block, the intermediate mass ring and the frame are concentrically arranged and the corresponding edges are parallel, the inner mass block and the intermediate mass ring are connected through the inner ring cantilever beam between the corresponding edges, and the intermediate mass ring and the frame are connected through the outer ring cantilever beam between the corresponding edges; the lower surfaces of the inner mass block, the intermediate mass ring, the inner ring cantilever beam and the outer ring cantilever beam are separated from the silicon substrate; the upper electrode layer is patterned with electrodes on the upper surfaces of the inner ring cantilever beam and the outer ring cantilever beam, and the surface of the passivation layer is provided with electrode leads connected with the electrodes.

[0009] Preferably, the electrodes on each inner ring cantilever beam comprise an inner ring outer electrode close to the intermediate mass ring and an inner ring inner electrode close to the inner mass block, the inner ring outer electrode and the inner ring inner electrode are respectively connected with electrode leads, and the polarization potentials of the inner ring outer electrode and the inner ring inner electrode are opposite in sign.

[0010] Preferably, the electrodes on each outer ring cantilever beam comprise an outer ring outer electrode close to the outer ring cantilever beam and an outer ring inner electrode close to the intermediate mass ring, the outer ring outer electrode and the outer ring inner electrode are respectively connected with electrode leads, and the polarization potentials of the outer ring outer electrode and the outer ring inner electrode are opposite in sign.

[0011] Preferably, the inner mass block is in a square shape, the intermediate mass ring is in a ring-shaped square frame shape, and a spacing is left between the corresponding edges of the inner mass block and the intermediate mass ring and between the corresponding edges of the intermediate mass ring and the frame.

[0012] Preferably, the inner ring cantilever beam is located at the middle of the edge of the inner mass block, and the outer ring cantilever beam is located at the middle of the edge of the intermediate mass ring.

[0013] Preferably, the lower end surfaces of the inner mass block, the intermediate mass ring, the inner ring cantilever beam and the outer ring cantilever beam are at a same level, the lower end surfaces of the inner mass block, the intermediate mass ring, the inner ring cantilever beam and the outer ring cantilever beam are higher than the lower end surface of the frame, and the height difference is not more than 0.33 mu m. Preferably, the working mode of the piezoelectric sensitive layer is d 31 Preferably, the working mode of the entire high-sensitivity wide-band piezoelectric vibration sensing chip with a cross-ring structure is d 31 Preferably, the working mode of the entire high-sensitivity wide-band piezoelectric vibration sensing chip with a cross-ring structure is

[0014] Preferably, the piezoelectric sensitive layer adopts a scandium-doped aluminum nitride piezoelectric ceramic film, the doping amount of scandium in the aluminum nitride is 10% to 30% of the mass of the aluminum nitride, and the thickness of the piezoelectric sensitive layer is 1 mu m.

[0015] Preferably, the insulating layer and passivation layer material adopts silicon dioxide, the lower electrode layer and upper electrode layer material adopts molybdenum, and the electrode lead material adopts gold.

[0016] The preparation method of the cross-ring structure high-sensitivity wide-band piezoelectric vibration sensing chip as described above comprises the following steps: Step one: clean the silicon substrate, and grow the insulating layer, deposit the lower electrode layer and the piezoelectric sensitive layer on the surface of the silicon substrate in sequence by using the plasma enhanced chemical deposition process and the magnetron sputtering process; Step two: form the alignment mark on the surface of the piezoelectric sensitive layer by using the photoetching and ion beam etching process; Step three: form the electrode on the surface of the piezoelectric sensitive layer by using the photoetching and magnetron sputtering process, and pattern the upper electrode layer to form the electrode on the surface of the inner ring cantilever beam and the outer ring cantilever beam; Step four: grow the passivation layer on the surface of the piezoelectric sensitive layer and the patterned upper electrode layer by using the plasma enhanced chemical deposition process; Step five: etch and pattern the passivation layer and the piezoelectric sensitive layer by using the photoetching and ion beam etching process to form the upper electrode lead hole and the lower electrode lead hole, wherein the upper electrode lead hole extends to the upper surface of the upper electrode layer, and the lower electrode lead hole extends to the upper surface of the lower electrode layer; Step six: deposit the lower electrode lead, the lead of the upper electrode of the inner ring cantilever beam and the lead of the upper electrode of the outer ring cantilever beam by using the photoetching and magnetron sputtering process; Step seven: deposit a layer of aluminum film as the upper masking layer and the lower masking layer on the upper and lower surfaces of the device obtained in step six by using the magnetron sputtering process; Step eight: etch and pattern the upper masking layer, the passivation layer, the piezoelectric sensitive layer, the lower electrode layer and the insulating layer in sequence by using the photoetching and ion beam etching process to form the inner ring cantilever beam and the outer ring cantilever beam; Step nine: etch and pattern the lower masking layer and the silicon substrate by using the photoetching, ion beam etching and deep reactive ion etching process to form the inner mass, the intermediate mass ring and the outer frame; Step ten: etch and pattern the upper layer of silicon and the buried oxygen layer by using the photoetching, deep reactive ion etching and wet etching process to form the outer ring through hole between the intermediate mass ring and the frame and the inner ring through hole between the inner mass and the intermediate mass ring, and complete the release of the inner mass, the inner ring cantilever beam, the intermediate mass ring and the outer ring cantilever beam; Step eleven: remove the upper masking layer and the lower masking layer by using the wet etching process to obtain the cross-ring structure high-sensitivity wide-band piezoelectric vibration sensing chip.

[0017] The present application has the following beneficial effects: The concentrated mass of the piezoelectric vibration sensing chip prepared by the application comprises an inner mass block and an intermediate mass ring, and four inner ring cantilever beams are used to connect the inner mass block and the intermediate mass ring. Compared with the traditional cross cantilever beam structure, the volume of the mass block is reduced, thereby improving the natural frequency of the device, and meanwhile, the four inner ring cantilever beams increase the utilization area of the piezoelectric sensitive layer, thereby compensating the problem of sensitivity reduction caused by high resonance frequency.

[0018] Further, the lower electrode layer, the piezoelectric sensitive layer and the upper electrode layer of the cross ring structure high-sensitivity wide-frequency band piezoelectric vibration sensing chip of the application are stacked to form a sandwich structure, the upper electrode layer is arranged at the connection end area of the inner ring cantilever beam and the outer ring cantilever beam, the upper electrode layer collects charges from the area polarized as full positive or full negative in the piezoelectric sensitive layer during the vibration of the device, and the electrodes are connected in series, thereby greatly improving the output performance of the device.

[0019] Further, in the structural design of the device, an anti-impact structure is actively designed, the lower end surface of the inner mass block and the intermediate mass ring is higher than the lower end surface of the frame, when the device vibrates within the limit impact range, the lower end surface of the frame is used as a mounting surface and is mounted on the equipment to be measured, the inner mass block and the intermediate mass ring are in a suspended state and have sufficient displacement allowance in the vibration state; when the device bears vibration exceeding the limit impact, the inner mass block and the intermediate mass ring are in contact with the surface of the equipment to be measured, thereby preventing the device from failing due to strong impact, and the device has strong anti-impact ability.

[0020] Further, during the preparation of the device, after the deposition of the gold electrode lead, a layer of metal aluminum is deposited on the upper and lower surfaces of the device as a shielding layer to protect other structure layers of the device from being affected in the etching process, thereby improving the processing precision and the yield of finished products. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments or the prior art description will be introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0022] Figure 1(a) is a schematic diagram of the overall structure of the cross ring structure high-sensitivity wide-frequency band piezoelectric vibration sensing chip of the present application; Figure 1(b) is a schematic diagram of the left lower corner of Figure 1(a) after removing the part above the silicon substrate; Figure 1(c) is an enlarged view of part A in Figure 1(b); Figure 1(d) is an enlarged view of part B in Figure 1(b); Fig. 2(a) is a front view of the cross-ring structure high-sensitivity wide-band piezoelectric vibration sensing chip of the present application; Fig. 2(b) is a top view of the upper electrode layer of the cross-ring structure high-sensitivity wide-band piezoelectric vibration sensing chip of the present application; Figure 3 Fig. 3 is a top view of the cross-ring structure high-sensitivity wide-band piezoelectric vibration sensing chip of the present application; Figure 4 Fig. 4 is a bottom view of the cross-ring structure high-sensitivity wide-band piezoelectric vibration sensing chip of the present application; Figure 5 Fig. 5 is a flow chart of the preparation process of the cross-ring structure high-sensitivity wide-band piezoelectric vibration sensing chip of the present application; Figure 6 Fig. 6 is a stress distribution diagram of the cross-ring structure high-sensitivity wide-band piezoelectric vibration sensing chip of the present application.

[0023] Figure 7 Fig. 7 is a potential distribution diagram of the cross-ring structure high-sensitivity wide-band piezoelectric vibration sensing chip of the present application; Figure 8 Fig. 8 is an impact schematic diagram of the cross-ring structure high-sensitivity wide-band piezoelectric vibration sensing chip of the present application; Figure 9 Fig. 9 is a diagram of the relationship between the amplitude and the impact of the cross-ring structure high-sensitivity wide-band piezoelectric vibration sensing chip of the present application; Fig. 10(a) is a comparison diagram of the harmonic response curves of the cross-ring structure high-sensitivity wide-band piezoelectric vibration sensing chip of the present application and the piezoelectric vibration sensor of the traditional cross-cantilever beam structure; Fig. 10(b) is a comparison diagram of the sensitivity of the cross-ring structure high-sensitivity wide-band piezoelectric vibration sensing chip of the present application and the piezoelectric vibration sensor of the traditional cross-cantilever beam structure; In the figure: 1, inner mass block, 2, middle mass ring, 3, silicon substrate, 4, buried oxygen layer, 5, upper layer silicon, 6, insulating layer, 7, lower electrode layer, 8, piezoelectric sensitive layer, 9, upper electrode layer, 9-1, inner ring outer electrode, 9-2, inner ring inner electrode, 9-3, outer ring outer electrode, 9-4, outer ring inner electrode, 10, passivation layer, 11, lower electrode lead, 12, inner ring outer electrode lead, 13, inner ring inner electrode lead, 14, outer ring outer electrode lead, 15, outer ring inner electrode lead, 16, outer ring through hole, 17, inner ring through hole, 18, inner ring cantilever beam, 19, outer ring cantilever beam, 20, frame, 21, upper electrode lead hole, 22, lower electrode lead hole, 23, upper masking layer, 24, lower masking layer. DETAILED DESCRIPTION

[0024] In order to make the purpose, characteristics and advantages of the present application more obvious and easy to understand, the technical solutions adopted in the present application will be described more clearly and in detail below in combination with the drawings and examples.

[0025] The cross-ring structure of the present invention has a high sensitivity and wide bandwidth piezoelectric vibration sensor chip, as shown in Figure 1 (a) - Figure 5 As shown, the device comprises a silicon base (also known as silicon substrate 3), an insulating layer 6, a lower electrode layer 7, a piezoelectric sensitive layer 8, an upper electrode layer 9, and a passivation layer 10, which are sequentially arranged. A MEMS process forms the inner mass block 1, four inner ring cantilever beams 18, an intermediate mass ring 2, four outer ring cantilever beams 19, and a frame 20. The inner mass block 1, four inner ring cantilever beams 18, the intermediate mass ring 2, and four outer ring cantilever beams 19 are the main functional areas of the device. The four inner ring cantilever beams 18 are arranged symmetrically around the center of a cross; the four outer ring cantilever beams 19 are also arranged symmetrically around the center of a cross. The four inner ring cantilever beams 18 are all rectangular, and each inner ring cantilever beam 18 has two connecting ends, which are respectively connected to the inner mass block 1 and the intermediate mass ring 2. The upper electrode layer 9 is patterned at the two connecting ends of the four inner ring cantilever beams 18 to form an inner ring outer electrode 9-1 and an inner ring inner electrode 9-2. There is a gap between the inner ring outer electrode 9-1 and the inner ring inner electrode 9-2, and the polarization potentials are opposite. The inner ring outer electrode 9-1 is arranged on the connecting end of the inner ring cantilever beam 18 and the intermediate mass ring 2, and the inner ring inner electrode 9-2 is arranged on the connecting end of the inner ring cantilever beam 18 and the inner mass block 1; the four outer ring cantilever beams 19 are all rectangular, and each outer ring cantilever beam 19 has two connecting ends, which are respectively connected to the intermediate mass ring 2 and the outer frame 20. The upper electrode layer 9 An outer ring outer electrode 9-3 and an outer ring inner electrode 9-4 are patterned at the two connecting ends of the four outer ring cantilever beams 19. There is a gap between the outer ring outer electrode 9-3 and the outer ring inner electrode 9-4, and the polarization potentials are opposite in positive and negative. The outer ring outer electrode 9-3 is arranged on the connecting end of the outer ring cantilever beam 19 and the outer frame 20, and the outer ring inner electrode 9-4 is arranged on the connecting end of the outer ring cantilever beam 19 and the intermediate mass ring 2; the surface of the passivation layer 10 is provided with a lower electrode lead 11 connected to the lower electrode layer 7, an inner ring outer electrode lead 12 connected to the inner ring outer electrode 9-1, an inner ring inner electrode lead 13 connected to the inner ring inner electrode 9-2, an outer ring outer electrode lead 14 connected to the outer ring outer electrode 9-3, and an outer ring inner electrode lead 15 connected to the outer ring inner electrode 9-4.

[0026] As a preferred solution of the above solution, the piezoelectric sensitive layer 8 uses aluminum nitride piezoelectric ceramic material doped with scandium, and the mass fraction of the doped scandium is 10%~30%. This not only increases the piezoelectric coefficient of the piezoelectric sensitive layer 8, but also does not cause a large change in dielectric loss, thereby significantly improving the output sensitivity of the device.

[0027] As a preferred solution of the above solution, refer to Figure 7The inner ring outer electrode 9-1, the inner ring inner electrode 9-2, the outer ring outer electrode 9-3 and the outer ring inner electrode 9-4 are located on the four inner ring cantilever beams 18 and the four outer ring cantilever beams 19 to polarize the areas into the same positive or the same negative, so as to collect the output charge and realize the potential accumulation by connecting the electrodes in series.

[0028] As a preferred scheme of the above scheme, referring to Figure 8 The inner mass block 1 and the intermediate mass ring 2 are displaced in the same direction after being subjected to the vibration impact, and the four inner ring cantilever beams 18 and the four outer ring cantilever beams 19 are simultaneously bent and deformed, so as to increase the utilization rate of the piezoelectric sensitive layer 8 and improve the output sensitivity of the device. As a preferred scheme of the above scheme, referring to Figure 9 Under the action of the 5000g impact load, the maximum displacement of the inner mass block 1 is 0.33μm. The lower end surface of the inner mass block 1 and the intermediate mass ring 2 is designed to be higher than the lower end surface of the frame 20, and the height difference is not more than 0.33μm, so that the inner mass block 1 and the intermediate mass ring 2 can be in a suspended state under the normal vibration state, and there is sufficient displacement allowance; when the impact vibration borne by the device exceeds the limit impact load, the inner mass block 1 and the intermediate mass ring 2 are in contact with the base to prevent the device from failing and being damaged.

[0029] In order to make the purpose, characteristics and advantages of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application are described clearly and completely. Obviously, the following described embodiments are only part of the embodiments of the present application, but not all the embodiments.

[0030] Embodiment As shown in FIG. 1(a) Figure 4 The cross ring structure high-sensitivity wide-band piezoelectric vibration sensing chip of the present embodiment improves the traditional cross cantilever beam structure, divides the mass block into two parts of the inner mass block 1 and the intermediate mass ring 2, and connects them by using four inner ring cantilever beams 18. The four inner ring cantilever beams 18 effectively improve the utilization rate of the piezoelectric sensitive layer 8, compensate for the sensitivity decrease problem caused by the decrease of the main mass of the device, and increase the output sensitivity.

[0031] The cross-sectional shape of the inner mass block 1 is square, and the side length is 300μm; the cross-sectional shape of the intermediate mass ring is a ring-shaped square frame, the inner ring square has a side length of 540μm, the outer ring square has a side length of 840μm, and the ring-shaped square frame has a thickness of 150μm.

[0032] The insulating layer 6 is arranged between the upper layer of silicon 5 and the lower electrode layer 7. Since the upper layer of silicon 5 has conductivity, the insulating layer 6 can effectively prevent the leakage of the charges collected by the lower electrode layer 7 during the operation of the device, thereby improving the output sensitivity of the device. Considering the insulating property of the silicon dioxide material and the easy bonding with the upper layer of silicon 4, the silicon dioxide material is preferably used as the material of the insulating layer 6, and the thickness is 0.3 μm.

[0033] The lower electrode layer 7 is arranged between the insulating layer 6 and the piezoelectric sensitive layer 8, and is connected with the lower electrode lead 11 through the lower electrode lead hole 22, for collecting the lower surface charges of the piezoelectric sensitive layer 8, and the thickness is 0.2 μm.

[0034] The piezoelectric sensitive layer 8 is arranged between the lower electrode layer 7 and the upper electrode layer 9, and is made of scandium-doped aluminum nitride piezoelectric material, as the sensitive layer of the output electric signal of the device. The thickness of the piezoelectric sensitive layer 8 is 1 μm, which is compatible with the MEMS process while maintaining high performance.

[0035] The upper electrode layer 9 includes an inner ring outer electrode 9-1, an inner ring inner electrode 9-2, an outer ring outer electrode 9-3 and an outer ring inner electrode 9-4, and the thickness is 0.2 μm. The inner ring outer electrode 9-1 is connected with the inner ring outer electrode lead 12 through the upper electrode lead hole 21, the inner ring inner electrode 9-2 is connected with the inner ring inner electrode lead 13 through the upper electrode lead hole 21, the inner ring outer electrode lead 12 and the inner ring inner electrode lead 13 are connected in series through wire bonding to realize potential accumulation, and the upper surface charges of the piezoelectric sensitive layer 8 in the four inner ring cantilever beams 18 are collected. The outer ring outer electrode 9-3 is connected with the outer ring outer electrode lead 14 through the upper electrode lead hole 21, the outer ring inner electrode 9-4 is connected with the outer ring inner electrode lead 15 through the upper electrode lead hole 21, the outer ring outer electrode lead 14 and the outer ring inner electrode lead 15 are connected in series through wire bonding to realize potential accumulation, and the upper surface charges of the piezoelectric sensitive layer 8 in the four outer ring cantilever beams 19 are collected. Considering the high efficiency of charge collection, the lengths of the inner ring outer electrode 9-1, the inner ring inner electrode 9-2, the outer ring outer electrode 9-3 and the outer ring inner electrode 9-4 arranged on the inner ring cantilever beam 18 and the outer ring cantilever beam 19 are all 50 μm.

[0036] The passivation layer 10 is arranged on the upper surface of the upper electrode layer 9, for preventing the upper electrode layer 9 from being oxidized. Considering the good passivation effect of the silicon dioxide material and the easy bonding with the upper electrode layer 9, the silicon dioxide material is preferably used as the material of the passivation layer 10, and the thickness is 0.3 μm.

[0037] The inner ring cantilever beam 18 and the outer ring cantilever beam 19 are rectangular. In order to ensure the high rigidity of the device structure, the length of the inner ring cantilever beam 18 is selected to be 120 μm, the width is 120 μm, the length of the outer ring cantilever beam 19 is selected to be 120 μm, and the width is 350 μm.

[0038] The lower electrode lead 11, the inner ring outer electrode lead 12, the inner ring inner electrode lead 13, the outer ring outer electrode lead 14 and the outer ring inner electrode lead 15 are arranged on the upper surface of the passivation layer 10, and gold is preferably used as the material of the lower electrode lead 11, the inner ring outer electrode lead 12, the inner ring inner electrode lead 13, the outer ring outer electrode lead 14 and the outer ring inner electrode lead 15, considering the high conductivity of gold, and the thickness is 0.3 μm. The lower electrode lead 11 is connected with the lower electrode layer 7 through the lower electrode lead hole 22 and is connected with the external circuit for grounding; the inner ring outer electrode lead 12, the inner ring inner electrode lead 13, the outer ring outer electrode lead 14 and the outer ring inner electrode lead 15 are respectively connected with the inner ring outer electrode 9-1, the inner ring inner electrode 9-2, the outer ring outer electrode 9-3 and the outer ring inner electrode 9-4 through the upper electrode lead hole 21, are connected in series through lead bonding and are connected with the external circuit, so as to form a closed loop as a whole.

[0039] As shown in Figure 9 The maximum amplitude of the cross ring structure high-sensitivity wide-frequency-band piezoelectric vibration sensing chip of the embodiment has an approximately linear relationship with the impact received. The maximum impact borne by the device is 5000g, and the maximum amplitude of the device is 0.33 μm. The lower end of the inner mass block 1 and the intermediate mass ring 2 is higher than the lower end of the frame 20, and the height difference is 0.33 μm, which ensures that the inner mass block 1 and the intermediate mass ring 2 can be in contact with the base under strong impact load, preventing the device from failing due to overload.

[0040] As shown in FIG. 10(a), the harmonic response curve comparison diagram of the cross ring structure high-sensitivity wide-frequency-band piezoelectric vibration sensing chip of the embodiment and the piezoelectric vibration sensor with a similar size of a traditional cross cantilever beam structure, and FIG. 10(b) is a sensitivity comparison diagram of the cross ring structure high-sensitivity wide-frequency-band piezoelectric vibration sensing chip of the embodiment and the piezoelectric vibration sensor with a similar size of a traditional cross cantilever beam structure. The resonant frequency of the cross ring structure high-sensitivity wide-frequency-band piezoelectric vibration sensing chip of the embodiment is 71 kHz, and the sensitivity is 3.62 mV / g@5 kHz. The resonant frequency of the piezoelectric vibration sensor with a similar size of a traditional cross cantilever beam structure is 65 kHz, and the sensitivity is 3.28 mV / g@5 kHz. By comparison, the cross ring structure high-sensitivity wide-frequency-band piezoelectric vibration sensing chip of the embodiment has a higher resonant frequency and sensitivity than the piezoelectric vibration sensor with a similar size of a traditional cross cantilever beam structure, and has more superior performance.

[0041] The performance index parameters of the cross ring structure high-sensitivity wide-frequency-band piezoelectric vibration sensing chip of the embodiment are as follows: a. Measurement range: 60g; b. Measurement accuracy: better than 5% FS; c. Working bandwidth: 0.5~10 kHz; d. Impact resistance: 5000g.

[0042] The working principle of the cross-ring structure high-sensitivity broadband piezoelectric vibration sensor chip of the present invention is as follows: When using this device for vibration monitoring, the lower end face of the frame is connected to the device under test, and the inner mass block 1 and the intermediate mass ring 2 are suspended. When the device under test vibrates, the device vibrates accordingly, and the up and down vibrations of the inner mass block 1 and the intermediate mass ring 2 cause the four inner ring cantilever beams 18 and the four outer ring cantilever beams 19 to bend and deform. Due to the positive piezoelectric effect of the piezoelectric material, the piezoelectric sensitive layer 8 in the cantilever beam structure will polarize under stress and generate surface charge. A potential difference will be generated between the upper and lower surfaces of the piezoelectric sensitive layer 8, and the magnitude of the potential difference is proportional to the stress it bears. Figure 6 and Figure 7 The stress concentration of the cantilever beam structure in a bent state is concentrated at the two connection ends, with one end experiencing compressive stress and the other experiencing tensile stress. Due to the piezoelectric effect, a positive and negative potential difference will be generated between the upper and lower surfaces of the piezoelectric sensitive layer at the two connection ends, with the potential difference increasing the closer to the connection ends. Lower electrode layer 7 is grounded to capture the lower surface charge of piezoelectric sensitive layer 8. Upper electrode layer 9, including inner ring outer electrode 9-1, inner ring inner electrode 9-2, outer ring outer electrode 9-3, and outer ring inner electrode 9-4, is arranged at the connection ends of inner ring cantilever beam 18 and outer ring cantilever beam 19 to capture the upper surface charge of piezoelectric sensitive layer 8 with maximum efficiency. Connecting the electrodes in series can maximize the output sensitivity of the device.

[0043] like Figure 5 The figure shows a process flow chart for preparing a high-sensitivity, wide-band piezoelectric vibration sensor chip with a cross-ring structure according to an embodiment of the present invention. First, the insulating layer 6, the lower electrode layer 7, the piezoelectric sensitive layer 8, the upper electrode layer 9 and the passivation layer 10 are completed by plasma-enhanced chemical deposition, magnetron sputtering and photolithography processes; secondly, the lower electrode lead hole 22, the upper electrode lead hole 21, the lower electrode lead 11, the inner ring outer electrode lead 12, the inner ring inner electrode lead 13, the outer ring outer electrode lead 14 and the outer ring inner electrode lead 15 are formed by photolithography, ion beam etching and magnetron sputtering processes; then, the upper masking layer 23 and the lower masking layer 24 are formed on the upper and lower sides of the device respectively by magnetron sputtering process and the upper and lower masking layers 23 and 24 are formed by magnetron sputtering process. Photolithography, ion beam etching, and deep reactive ion etching processes are used to etch the upper masking layer 23, the lower masking layer 24, the passivation layer 10, the piezoelectric sensitive layer 8, the lower electrode layer 7, the insulating layer 6, the upper silicon layer 5, and the silicon substrate 3 to complete the preliminary release of the top-layer architecture and the bottom-layer structure of the device; then, a wet etching process is used to etch the buried oxide layer 4 to form the outer ring through hole 16 and the inner ring through hole 17, completing the release of the overall structure of the device; finally, a wet etching process is used to remove the upper masking layer 23 and the lower masking layer 24 of the device to complete the processing and preparation of the device. The detailed preparation steps are as follows: Step a, preparing an SOI silicon wafer: using a 4-inch N-type 100-crystal double-sided polished SOI silicon wafer, the upper silicon layer 5 has a resistivity of 1-10 Ω·cm and a thickness of 6±0.5 μm, the buried oxide layer 4 has a thickness of 0.5±5% μm, the silicon substrate 3 has a thickness of 300±10 μm, and the total thickness of the SOI silicon wafer is 306.5±10.5 μm; using acetone, anhydrous ethanol, and deionized water for 5 minutes in sequence to remove surface impurities from the SOI silicon wafer, then using a nitrogen gun to blow dry the surface water stains of the SOI silicon wafer and drying it at 100°C for 12 minutes; Step b, depositing silicon dioxide material to form an insulating layer 6: a 0.3 μm thick silicon dioxide film is grown on the upper surface of the upper silicon layer 5 of the SOI silicon wafer using a plasma enhanced chemical deposition process as the insulating layer 6 of the device; Step c, depositing metal molybdenum to form the lower electrode layer 7: a layer of 0.2 μm thick metal molybdenum is grown on the upper surface of the insulating layer 6 by a magnetron sputtering process as the lower electrode layer 7 of the device; Step d, depositing scandium-doped aluminum nitride to form a piezoelectric sensitive layer 8 and etching to form alignment marks: A 1μm thick scandium-doped aluminum nitride material is deposited on the upper surface of the lower electrode layer 7 using a magnetron sputtering process as the device's piezoelectric sensitive layer 8. The magnetron sputtering process has an argon-nitrogen ratio of 6:24, a power of 500W, and no substrate heating. Subsequently, a layer of photoresist (positive photoresist) is spin-coated on the upper surface of the device, baked at 100°C for 12 minutes, and exposed using the first mask (positive version) for 10 seconds. The device is then immersed in a developer for 40 seconds, rinsed with deionized water, and then dried with a nitrogen gun to remove water stains on the surface of the device, and dried at 100°C for 12 minutes to complete the development pattern transfer. Finally, an ion beam etching process is used to etch the piezoelectric sensitive layer 8 to form an alignment mark. The mass fraction of doped scandium in this embodiment is 20%. Step e, depositing metal molybdenum to form the upper electrode layer 9: spin-coat a layer of photoresist (positive photoresist) on the upper surface of the device, bake at 100°C for 12 minutes, and use a second mask (positive plate) for photolithography exposure for 10 seconds; then soak in developer for 40 seconds, rinse with deionized water, blow dry the surface water stains of the device with a nitrogen gun, and dry at 100°C for 12 minutes to complete the development pattern transfer; finally, use a magnetron sputtering process to deposit a 0.2μm thick layer of metal molybdenum as the upper electrode layer 9 of the device on the upper surface of the device, and after patterning, form an inner ring outer electrode 9-1, an inner ring inner electrode 9-2, an outer ring outer electrode 9-3, and an outer ring inner electrode 9-4; Step f, depositing silicon dioxide material to form a passivation layer 10: plasma enhanced chemical deposition is used to form a 0.3 μm thick silicon dioxide film as the passivation layer 10 of the device to protect the upper electrode layer 9 from oxidation; Step g, etching to form lead hole: spin a layer of photoresist (positive) on the top surface of the device, bake at 100°C for 12 min, use the third mask (positive) to expose light for 10 s; then soak in the developer for 40 s, after cleaning with deionized water, dry the surface of the device with a nitrogen gun and bake at 100°C for 12 min to complete the development of the pattern transfer; finally, etch 0.3 μm thick silicon dioxide on the top surface of the device and patternize to form the upper electrode lead hole 21 and the preliminary lower electrode lead hole 22; Step h, etching to form lower electrode lead hole 22: spin a layer of photoresist (positive) on the top surface of the device, bake at 100°C for 12 min, use the fourth mask (positive) to expose light for 10 s; then soak in the developer for 40 s, after cleaning with deionized water, dry the surface of the device with a nitrogen gun and bake at 100°C for 12 min to complete the development of the pattern transfer; finally, etch 1 μm of the piezoelectric sensitive layer 8 on the top surface of the device and patternize to form the complete lower electrode lead hole 22; Step i, depositing gold material to form gold electrode lead: spin a layer of photoresist (positive) on the top surface of the device, bake at 100°C for 12 min, use the fifth mask (positive) to expose light for 10 s; then soak in the developer for 40 s, after cleaning with deionized water, dry the surface of the device with a nitrogen gun and bake at 100°C for 12 min to complete the development of the pattern transfer; finally, use the magnetron sputtering process to deposit 0.3 μm thick gold material (30 nm of metal chromium as an adhesion layer) on the top surface of the device and patternize to form the lower electrode lead 11, the inner ring outer electrode lead 12, the inner ring inner electrode lead 13, the outer ring outer electrode lead 14 and the outer ring inner electrode lead 15; Step j, depositing metal aluminum to form upper masking layer 23: use the magnetron sputtering process to deposit a layer of 0.4 μm thick metal aluminum on the top surface of the device as the upper masking layer 23 of the device; Step k, etching the upper masking layer 23, the passivation layer 10, the piezoelectric sensitive layer 8, the lower electrode layer 7 and the insulating layer 6: spin a layer of photoresist (positive) on the top surface of the device, bake at 100°C for 12 min, use the sixth mask (positive) to expose light for 10 s; then soak in the developer for 40 s, after cleaning with deionized water, dry the surface of the device with a nitrogen gun and bake at 100°C for 12 min to complete the development of the pattern transfer; finally, use the ion beam etching process to etch the upper masking layer 23, the passivation layer 10, the piezoelectric sensitive layer 8, the lower electrode layer 7 and the insulating layer 6 in sequence on the top surface of the device and patternize to form the inner ring cantilever beam 18 and the outer ring cantilever beam 19; Step l, depositing metal aluminum to form lower masking layer 24: use the magnetron sputtering process to deposit a layer of 0.4 μm thick metal aluminum on the lower surface of the device as the lower masking layer 24 of the device; Step m, preliminary etching of the silicon substrate 3: spin a layer of photoresist (positive resist) on the lower surface of the device, bake at 100 DEG C for 12 min, use the seventh mask (positive) to photoexpose for 10 s; then soak in the developing solution for 40 s, clean with deionized water, then use a nitrogen gun to dry the water spots on the surface of the device and bake at 100 DEG C for 12 min to complete the development pattern transfer; finally, etch the lower masking layer 24 and the silicon substrate 3 and patternize by using ion beam etching and deep reactive ion etching process on the lower surface of the device, and the etching depth of the silicon substrate 3 is 0.33 μm; Step n, secondary etching of the silicon substrate 3: spin a layer of photoresist (positive resist) on the lower surface of the device, bake at 100 DEG C for 12 min, use the eighth mask (positive) to photoexpose for 10 s; then soak in the developing solution for 40 s, clean with deionized water, then use a nitrogen gun to dry the water spots on the surface of the device and bake at 100 DEG C for 12 min to complete the development pattern transfer; finally, etch the lower masking layer 24 and the silicon substrate 3 by using ion beam etching and deep reactive ion etching process on the lower surface of the device, and the etching depth is 300 μm, forming the inner mass block 1, the intermediate mass ring 2 and the outer frame 20; Step o, etching of the upper layer of silicon 5: spin a layer of photoresist (positive resist) on the upper surface of the device, bake at 100 DEG C for 12 min, use the sixth mask (positive) to photoexpose for 10 s; then soak in the developing solution for 40 s, clean with deionized water, then use a nitrogen gun to dry the water spots on the surface of the device and bake at 100 DEG C for 12 min to complete the development pattern transfer; finally, etch the 6 μm upper layer of silicon 5 and patternize by using deep reactive ion etching process on the upper surface of the device; Step p, wet etching of the buried oxygen layer 4: the buried oxygen layer 4 is etched by using a wet etching process, forming the outer ring through hole 16 and the inner ring through hole 17, and completing the release of the inner mass block 1, the intermediate mass ring 2, the inner ring cantilever beam 18 and the outer ring cantilever beam 19; Step q, wet etching of the upper masking layer 23 and the lower masking layer 24: the upper masking layer 23 and the lower masking layer 24 are etched by using a wet etching process, and the preparation of the cross ring structure high-sensitivity wide frequency band piezoelectric vibration sensing chip is completed.

[0044] In summary, the cross ring structure high-sensitivity wide frequency band piezoelectric vibration sensing chip is prepared well by the embodiment of the application, the sensing chip has higher output sensitivity and wider working frequency band, and can accurately monitor high-frequency vibration signals. The sensing chip has strong impact resistance and temperature stability, and has very important scientific significance and application value for fault monitoring of large-scale equipment in harsh environments.

[0045] The above-described embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A high-sensitivity, wide-band piezoelectric vibration sensor chip with a cross-ring structure, characterized in that: The invention comprises a silicon substrate, wherein the surface of the silicon substrate is provided with a functional heterostructure composed of an insulating layer (6), a lower electrode layer (7), a piezoelectric sensitive layer (8), an upper electrode layer (9) and a passivation layer (10) stacked in sequence, wherein the heterostructure comprises a rectangular inner mass block (1), an intermediate mass ring (2) and a frame (20) arranged in sequence from the center to the outside, and the heterostructure further comprises an inner ring cantilever beam (18) and an outer ring cantilever beam (19); wherein the inner mass block (1), the intermediate mass ring (2) and the frame (20) are arranged concentrically and the corresponding sides are parallel, and ... The mass block (1) and the corresponding sides of the intermediate mass ring (2) are connected via an inner ring cantilever beam (18), and the corresponding sides of the intermediate mass ring (2) and the frame (20) are connected via an outer ring cantilever beam (19); the lower surfaces of the inner mass block (1), the intermediate mass ring (2), the inner ring cantilever beam (18), and the outer ring cantilever beam (19) are separated from the silicon substrate; the upper electrode layer (9) is patterned with electrodes on the upper surfaces of the inner ring cantilever beam (18) and the outer ring cantilever beam (19), and the surface of the passivation layer (10) is provided with electrode leads connected to the electrodes.

2. The high-sensitivity, wide-band piezoelectric vibration sensor chip with a cross-ring structure according to claim 1, characterized in that: The electrodes on each inner ring cantilever beam (18) include an inner ring outer electrode (9-1) close to the middle mass ring (2) and an inner ring inner electrode (9-2) close to the inner mass block (1), the inner ring outer electrode (9-1) and the inner ring inner electrode (9-2) are respectively connected to an electrode lead, and the polarization potentials of the inner ring outer electrode (9-1) and the inner ring inner electrode (9-2) are opposite in positive and negative.

3. The high-sensitivity, wide-band piezoelectric vibration sensor chip with a cross-ring structure according to claim 1, characterized in that: Each electrode includes an outer ring outer electrode (9-3) close to the outer ring cantilever beam (19) and an outer ring inner electrode (9-4) close to the middle mass ring (2), the outer ring outer electrode (9-3) and the outer ring inner electrode (9-4) are respectively connected to an electrode lead, and the polarization potentials of the outer ring outer electrode (9-3) and the outer ring inner electrode (9-4) are opposite in positive and negative.

4. The high-sensitivity, wide-band piezoelectric vibration sensor chip with a cross-ring structure according to claim 1, characterized in that: The inner mass block (1) is in the shape of a square, the middle mass ring (2) is in the shape of an annular square frame, a spacing is left between corresponding sides of the inner mass block (1) and the middle mass ring (2), and a spacing is left between corresponding sides of the middle mass ring (2) and the frame (20).

5. The high-sensitivity, wide-band piezoelectric vibration sensor chip with a cross-ring structure according to claim 1, characterized in that: The inner ring cantilever beam (18) is located in the middle of the side of the inner mass block (1), and the outer ring cantilever beam (19) is located in the middle of the side of the middle mass ring (2).

6. The high-sensitivity, wide-band piezoelectric vibration sensor chip with a cross-ring structure according to claim 1, characterized in that: The lower end surfaces of the inner mass block (1), the intermediate mass ring (2), the inner ring cantilever beam (18) and the outer ring cantilever beam (19) are at the same level, and the lower end surfaces of the inner mass block (1), the intermediate mass ring (2), the inner ring cantilever beam (18) and the outer ring cantilever beam (19) are higher than the lower end surface of the frame, and the height difference does not exceed 0.33 μm.

7. The high-sensitivity, wide-band piezoelectric vibration sensor chip with a cross-ring structure according to claim 1, characterized in that: The working mode of the piezoelectric sensitive layer is d 31 model.

8. The high-sensitivity, wide-band piezoelectric vibration sensor chip with a cross-ring structure according to claim 1, characterized in that: The piezoelectric sensitive layer (8) is made of a scandium-doped aluminum nitride piezoelectric ceramic film, the doping amount of scandium in the aluminum nitride is 10% to 30% of the mass of the aluminum nitride, and the thickness of the piezoelectric sensitive layer (8) is 1 μm.

9. The high-sensitivity, wide-band piezoelectric vibration sensor chip with a cross-ring structure according to claim 1, characterized in that: The insulating layer (6) and the passivation layer (10) are made of silicon dioxide, the lower electrode layer (7) and the upper electrode layer (9) are made of molybdenum, and the electrode lead material is gold.

10. A method for preparing a high-sensitivity, wide-band piezoelectric vibration sensor chip with a cross-ring structure according to any one of claims 1 to 9, characterized in that: The steps include: Step 1: Cleaning the silicon substrate, sequentially growing an insulating layer (6) on the surface of the silicon substrate by a plasma enhanced chemical deposition process, and depositing a lower electrode layer (7) and a piezoelectric sensitive layer (8) by a magnetron sputtering process; Step 2: forming alignment marks on the surface of the piezoelectric sensitive layer (8) using photolithography and ion beam etching processes; Step 3: forming an electrode layer (9) on the surface of the piezoelectric sensitive layer (8) by photolithography and magnetron sputtering, and patterning the electrode layer (9) to form electrodes on the surfaces of the inner ring cantilever beam (18) and the outer ring cantilever beam (19); Step 4: growing a passivation layer (10) on the surface of the piezoelectric sensitive layer (8) and the patterned upper electrode layer (9) using a plasma enhanced chemical deposition process; Step 5: etching the passivation layer (10) and the piezoelectric sensitive layer (8) using photolithography and ion beam etching processes and patterning them to form an upper electrode lead hole (21) and a lower electrode lead hole (22), wherein the upper electrode lead hole (21) extends to the upper surface of the upper electrode layer (9), and the lower electrode lead hole (22) extends to the upper surface of the lower electrode layer (7); Step 6: using photolithography and magnetron sputtering processes to deposit the lower electrode lead (11), the lead of the upper electrode of the inner ring cantilever beam (18), and the lead of the upper electrode of the outer ring cantilever beam (19); Step 7: using a magnetron sputtering process to deposit a layer of aluminum film on the upper and lower surfaces of the device obtained in step 6 as an upper masking layer (23) and a lower masking layer (24); Step eight: using photolithography and ion beam etching processes to sequentially etch and pattern the upper masking layer (23), the passivation layer (10), the piezoelectric sensitive layer (8), the lower electrode layer (7) and the insulating layer (6) to form an inner ring cantilever beam (18) and an outer ring cantilever beam (19); Step nine: etching the lower masking layer (24) and the silicon substrate (3) using photolithography, ion beam etching and deep reactive ion etching processes and patterning to form an inner mass block (1), an intermediate mass ring (2) and an outer frame (20); Step 10: etching the upper silicon layer (5) and the buried oxide layer (4) by photolithography, deep reactive ion etching and wet etching processes and patterning them to form an outer ring through hole (16) between the intermediate mass ring (2) and the frame (20), and an inner ring through hole (17) between the inner mass block (1) and the intermediate mass ring (2), thereby completing the release of the inner mass block (1), the inner ring cantilever beam (18), the intermediate mass ring (2) and the outer ring cantilever beam (19); Step 11: using a wet etching process to remove the upper masking layer (23) and the lower masking layer (24), thereby obtaining the high-sensitivity, wide-band piezoelectric vibration sensor chip of the cross-ring structure.

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