Chip testing system

Abstract

A chip testing system comprises a multipath selection unit comprising a plurality of input nodes and at least one output node, the plurality of input nodes are respectively coupled with a first type to-be-tested pin of a to-be-tested chip, and the output node is coupled with a testing unit, the first type to-be-tested pin is suitable for selectively coupling one of the input nodes with one of the output nodes according to a selection control signal, so that the corresponding first type to-be-tested pin is coupled with one of the output nodes; and the test unit is coupled with the multi-path selection unit and is suitable for testing the first type to-be-tested pin coupled with one of the output nodes of the multi-path selection unit. According to the technical scheme, test resources and test cost can be saved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of testing, and in particular, to a chip testing system. BACKGROUND

[0002] With the development of electronic technology, there are more and more types of chips. In order to ensure the quality of the chips, the chips often need to be tested for multiple times to detect the integrity of the chip functions, screen out defective products, ensure the production and manufacturing quality of the chips, and reduce redundant manufacturing costs.

[0003] Generally, a testing system includes a testing circuit board, a chip to be tested, and an automatic test equipment (ATE). The chip to be tested is placed in a test socket of the testing circuit board, and is connected to the automatic test equipment through a plurality of data interfaces of the testing circuit board, reads test instructions output by the automatic test equipment, and outputs test results from the plurality of data interfaces in parallel. The test socket of the testing circuit board can be one or more. In the case of one test socket of the testing circuit board, one testing circuit board can implement the test of one chip to be tested at a time. In the case of multiple test sockets of the testing circuit board, one testing circuit board can implement the simultaneous test of multiple chips to be tested at a time. In other words, the number of chips to be tested is consistent with the number of test sockets of one testing circuit board.

[0004] However, the current chip testing has the problems of large consumption of testing resources and high cost. SUMMARY

[0005] The problem solved by embodiments of the present application is to provide a chip testing system which can save testing resources and testing costs.

[0006] To solve the above problem, embodiments of the present application provide a chip testing system, which comprises: a multiplexing unit, comprising a plurality of input nodes, a plurality of control nodes, and at least one output node, the plurality of input nodes are respectively coupled to first type of test pins of a chip to be tested, the plurality of control nodes are used for receiving selection control signals, and the output node is coupled to a testing unit and is adapted to selectively couple one of the plurality of input nodes to one of the output nodes according to the selection control signals, so that the corresponding first type of test pin is coupled to one of the output nodes;

[0007] a testing unit, coupled to the multiplexing unit, and adapted to test the first type of test pin coupled to the output node of the multiplexing unit.

[0008] Optionally, the plurality of input nodes of the multiplexing unit are coupled to a plurality of different first-type DUT pins of the DUT, or the plurality of input nodes of the multiplexing unit are coupled to the same first-type DUT pin of a plurality of DUTs.

[0009] Optionally, the DUTs and the multiplexing units are respectively a plurality of, and the first-type DUT pins of the plurality of DUTs are divided into a plurality of groups according to test items;

[0010] If the number of the multiplexing units is respectively greater than or equal to the number of the first-type DUT pins in each group, the first-type DUT pins of the same group are respectively coupled to the same input node of the multiplexing units, and the first-type DUT pins of different groups are respectively coupled to different input nodes of the multiplexing units;

[0011] If the number of the multiplexing units is less than the number of the first-type DUT pins in the group, and the first-type DUT pins in the group are all used for output signals in the corresponding test items, the first-type DUT pins in the group are divided into a plurality of subgroups; the first-type DUT pins in each subgroup are coupled to the same input node of the plurality of multiplexing units, and the first-type DUT pins in different subgroups are coupled to different input nodes of the plurality of multiplexing units.

[0012] Optionally, the test unit comprises a switch resource module adapted to generate the selection control signal.

[0013] Optionally, the switch resource module comprises a plurality of switch channels.

[0014] The same control nodes of the plurality of multiplexing units coupled to the first-type DUT pins of the DUTs of the same group are coupled to the same switch channel of the switch resource module, and different control nodes of the plurality of multiplexing units coupled to the first-type DUT pins of the DUTs of the same group are coupled to different switch channels of the switch resource module; or,

[0015] The same control nodes of the plurality of multiplexing units coupled to the first-type DUT pins of the DUTs of the same subgroup are coupled to the same switch channel of the switch resource module, and different control nodes of the plurality of multiplexing units coupled to the first-type DUT pins of the DUTs of the same subgroup are coupled to different switch channels of the switch resource module.

[0016] Optionally, the first-type DUT pin comprises at least one of the following:

[0017] A pin only for continuity test;

[0018] a pin for performing voltage characteristic and / or current characteristic test only;

[0019] an analog pin for performing preset analog item test.

[0020] Optionally, the chip under test further comprises a second type of pin under test, which is coupled with the test unit.

[0021] Optionally, the second type of pin under test comprises at least one of:

[0022] a pin for performing test in scan test item;

[0023] a pin for performing test in built-in self-test item;

[0024] a pin for performing test in high-speed test item;

[0025] a pin for performing test in high-voltage test item;

[0026] a pin for performing test in large current test item.

[0027] Optionally, the chip test system comprises a test circuit board, and the multiplexing unit is disposed on the test circuit board.

[0028] The test circuit board comprises a test socket, and the chip under test is fixedly installed in the test socket and coupled with the test unit through the test circuit board.

[0029] Optionally, the chip test system further comprises a power supply unit adapted to provide a power supply voltage for the multiplexing unit.

[0030] Optionally, the power supply voltage comprises input voltage and / or output voltage of the first type of pin under test coupled with the input node of the multiplexing unit when test passes and / or test fails.

[0031] Optionally, the power supply unit comprises a DC-DC converter.

[0032] Optionally, the multiplexing unit comprises a decoding module and a switch corresponding to each of the plurality of input nodes.

[0033] The decoding module is adapted to receive the selection control signal and control the corresponding switch to be closed according to the selection control signal, so that the corresponding input node in the multiplexing unit is coupled with the output node through the corresponding switch.

[0034] Optionally, the multiplexing unit comprises a multiplexer.

[0035] Optionally, the chip under test comprises a SOC chip.

[0036] Optionally, the test unit comprises an automatic test machine.

[0037] Compared with the prior art, the technical scheme of the embodiment of the application has the following advantages:

[0038] The embodiment of the application provides a chip test system, which comprises: a multiplexing unit, which comprises a plurality of input nodes, a plurality of control nodes and at least one output node, the plurality of input nodes are respectively coupled with first type test pins of a chip to be tested, the plurality of control nodes are used for receiving selection control signals, and the output node is coupled with a test unit and is adapted to selectively couple one of the plurality of input nodes with one of the output nodes according to the selection control signals, so that the corresponding first type test pin is coupled with one of the output nodes; and the test unit is coupled with the multiplexing unit and is adapted to test the first type test pin coupled with one of the output nodes of the multiplexing unit.

[0039] In the chip test system provided by the embodiment of the application, the plurality of first type test pins in the chip to be tested are coupled with the test unit by using the multiplexing unit, so that the test of the plurality of first type test pins in the chip to be tested only occupies one test channel resource of the test unit coupled with the output node of the multiplexing unit, which helps to save test resources and reduce test cost. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 is a schematic diagram of the frame structure of an embodiment of the chip test system provided by the technical scheme of the application and the connection relationship between the chip test system and a chip to be tested;

[0041] Figure 2 is a structural schematic diagram of an embodiment of the multiplexing unit provided by the technical scheme of the application;

[0042] Figure 3 is a schematic diagram of two different connection relationships between the multiplexing unit and the chip to be tested. DETAILED DESCRIPTION

[0043] As known from the background art, the current chip test has the problems of large test resource consumption and high cost.

[0044] To solve the technical problem, the embodiment of the present application provides a chip testing system, comprising: a multiplexing unit, comprising a plurality of input nodes, a plurality of control nodes and at least one output node, the plurality of input nodes are respectively coupled with first type test pins of a chip to be tested, the plurality of control nodes are used for receiving selection control signals, and the output node is coupled with a testing unit and is adapted to selectively couple one of the plurality of input nodes with one of the output nodes according to the selection control signals, so that the corresponding first type test pin is coupled with the output node; and the testing unit is coupled with the multiplexing unit and is adapted to test the first type test pin coupled with one of the output nodes of the multiplexing unit.

[0045] In the chip testing system provided by the embodiment of the present application, the plurality of first type test pins in the chip to be tested are coupled with the testing unit by using the multiplexing unit, so that the testing of the plurality of first type test pins in the chip to be tested only occupies one testing channel resource of the testing unit coupled with the output node of the multiplexing unit, which helps to save testing resources and reduce testing cost.

[0046] In order to make the above-mentioned purpose, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0047] Figure 1 The framework schematic diagram of an embodiment of the chip testing system provided by the technical scheme of the present application is shown. Referring to Figure 1 , a chip testing system comprises a multiplexing unit 110 and a testing unit 120. The multiplexing unit 110 and the testing unit 120 are coupled with each other.

[0048] Referring to Figure 2 , Figure 2 is a structural schematic diagram of an embodiment of the multiplexing unit provided by the technical scheme of the present application. The multiplexing unit 110 comprises a plurality of input nodes S1-SN (N is an integer greater than 1, and as an example, N is 2 n ), a plurality of control nodes A1-AP (P is an integer greater than 1) and at least one output node D. The plurality of input nodes S1-SN are respectively coupled with first type test pins of a chip to be tested 200, the plurality of control nodes A1-AP are used for receiving selection control signals SEL[0:(M-1)], and the output node D is coupled with the testing unit 120. The multiplexing unit 110 is used for selectively coupling one of the plurality of input nodes S1-SN with the output node D according to the selection control signals SEL[0:(M-1)], so that the corresponding first type test pin is coupled with the output node D.

[0049] The multiplexing unit 110 selectively couples one of the first type of DUT pins of the DUT 200 coupled to each of the input nodes SI (I is an integer greater than or equal to 1 and less than or equal to N) to the output node D according to the selection control signal SEL[0:(M-1)], so that one of the first type of DUT pins of the DUT 200 is coupled to the test unit 120 coupled to the output node D of the multiplexing unit 110, and serial testing of the first type of DUT pins coupled to the input nodes of the multiplexing unit 110 can be realized.

[0050] Accordingly, only one test channel of the test unit 120 coupled to the output node D of the multiplexing unit 110 is used, and testing of the first type of DUT pins coupled to the input nodes S1-SN of the multiplexing unit 110 can be completed, compared with the mode in which the first type of DUT pins of the DUT 200 are directly coupled to a corresponding test channel resource of the test unit 120, only a small amount of test time is increased, test channel resources are reduced, and test costs are reduced.

[0051] The first type of DUT pins of the DUT 200 are pins used only in a small amount of testing items in a testing process of the DUT 200. For example, the first type of DUT pins of the DUT 200 include: (1) pins used only for on-off (OS) testing, such as pins for realizing a double data rate (DDR) function; (2) pins used only for voltage characteristic and / or current characteristic testing, such as open drain (OD) pins; and (3) analog pins used for preset analog item testing.

[0052] It can be understood that the first type of DUT pins can also be other types of DUT pins according to different types of the DUT 200, which is not limited herein.

[0053] In the embodiment, the selection control signal SEL[0:(M-1)] includes M-bit level signals, and each bit of the level signals can be switched between a first logic state and a second logic state, so that the selection control signal varies within a certain range. The first logic state is "1", and the second logic state is "0".

[0054] As an example, in an initial state, the M-bit level signals in the selection control signal SEL[0:(M-1)] are all in the second logic state, and the M-bit level signals in the selection control signal SEL[0:(M-1)] can be sequentially converted from the second logic state to the first logic state in order from low bits to high bits, so that the selection control signal varies within a certain range.

[0055] The length M of the selection control signal SEL[0:(M-1)] is an integer greater than or equal to 2, and the specific value of M and the number of the plurality of control nodes A1-AP can be set according to the number of the input nodes S1-SN in the multiplexing unit 110, which is not limited herein.

[0056] In a specific implementation, for a multiplexing unit 110, the plurality of input nodes S1-SN of the multiplexing unit 110 can be coupled with a plurality of different first type test pins of one DUT 200, or the plurality of input nodes S1-SN of the multiplexing unit 110 can also be coupled with the same first type test pin of a plurality of DUTs 200.

[0057] Taking a multiplexing unit 110 with four input nodes as an example, as shown in Figure 3 (a), the four input nodes of a multiplexing unit 110 can be coupled with four first type test pins Site1_PinA, Site1_PinB, Site1_PinC, Site1_PinD of one DUT 200; or, as shown in Figure 3 (b), the four input nodes of a multiplexing unit 110 can also be coupled with one of the same first type test pins Site1_PinA, Site2_PinA, Site3_PinA, Site4_PinA in four DUTs 200 respectively.

[0058] It should be noted that, compared with the mode that the plurality of input nodes S1-SN of a multiplexing unit 110 are coupled with the same first type test pin of a plurality of DUTs 200, the plurality of input nodes S1-SN of a multiplexing unit 110 are coupled with a plurality of different first type test pins of one DUT 200, which can realize parallel testing of a plurality of DUTs 200, and is helpful to save testing time.

[0059] Moreover, the plurality of input nodes S1-SN of a multiplexing unit 110 are coupled with a plurality of different first type test pins of one DUT 200, which is helpful to reduce the wiring difficulty between the first type test pin of the DUT 200 and the multiplexing unit 110, and thus is conducive to improving testing efficiency and saving testing cost.

[0060] It should be noted that for a multiplexing unit 110, the input nodes S1-SN of the multiplexing unit 110 can be coupled with different first type test pins of a DUT 200, or the input nodes S1-SN of the multiplexing unit 110 can be coupled with the same first type test pins of a plurality of DUTs 200. Correspondingly, for a DUT 200 having a plurality of first type test pins, the first type test pins of the DUT 200 can be coupled with a corresponding number of input nodes S1-SN of a multiplexing unit 110, or the first type test pins of the DUT 200 can be coupled with input nodes S1-SN of different multiplexing units 110, which can be set according to actual needs, and is not limited herein.

[0061] In this embodiment, the DUTs 200 and the multiplexing units 110 are respectively a plurality of, and the first type test pins of the plurality of DUTs 200 are divided into a plurality of groups G1-GR according to test items, and R is an integer greater than 1.

[0062] In this embodiment, the first type test pins of the plurality of DUTs 200 are divided into a plurality of groups G1-GR according to test items, that is, the first type test pins to be tested on the same test item are divided into the same group GJ (J is an integer greater than or equal to 1 and less than or equal to R), and the first type test pins to be tested on different test items are divided into different groups GJ.

[0063] Correspondingly, the first type test pins of the DUTs 200 in the same group GJ are respectively coupled with the same input nodes SI of a plurality of multiplexing units 110, and the first type test pins of the DUTs 200 in different groups are respectively coupled with different input nodes SI of a plurality of multiplexing units. In this way, the first type test pins of the DUTs 200 in each group GJ can be tested simultaneously in the same test item, which helps to further improve the test parallelism and improve the test efficiency.

[0064] It should be noted that in the case where the first type of test pins of the plurality of DUTs 200 are divided into a plurality of groups G1-GR according to test items, for a part of the number of groups, the first type of test pins in the part of the number of groups are respectively coupled to the same input nodes SI of the plurality of multiplexing units 110, and the first type of test pins of different groups are respectively coupled to different input nodes SI of the plurality of multiplexing units 110, if there are still some input nodes SI of the multiplexing units 110 used by the part of the number of groups, and the number of the remaining input nodes SI of the multiplexing units 110 is greater than or equal to the number of the first type of test pins in the remaining two or more groups, the first type of test pins in the remaining two or more groups can be respectively coupled to the remaining input nodes of the multiplexing units 110, so as to maximize the use of the multiplexing units 110 and save costs.

[0065] It should be noted that in the case where the number of multiplexing units 110 is less than the number of first type of test pins in the group GJ, and the first type of test pins in the group GJ corresponding to the test items are all used for output signals in the corresponding test items, the first type of test pins of the same group of DUTs 200 are respectively coupled to the same input nodes SI of the multiplexing units 110, and the first type of test pins of different groups of DUTs 200 are respectively coupled to different input nodes SI of the plurality of multiplexing units 110, so that the number of multiplexing units 110 used is relatively large, which is not conducive to saving the occupied layout area and test resources of the multiplexing units 110.

[0066] For example, there are 40 first type of test pins in each DUT 200, and 16 of the 40 first type of test pins are High Definition Multimedia Interface (HDMI) pins to be tested, which are only used on one HDMI test item and are only used to test the output voltage of the 16 first type of test pins. In the case where the multiplexing unit 110 has 4 input nodes and one output node, then 10 multiplexing units 110 are needed for the 40 first type of test pins of each DUT 200, which has the highest parallelism. However, since the 16 HDMI pins of the 40 first type of test pins of each DUT 200 need to be coupled to a corresponding input node SI of a corresponding multiplexing unit 110, each DUT 200 needs 16 multiplexing units 110, that is, each DUT 200 needs to additionally increase 6 multiplexing units 110, which will cause waste of the occupied layout area and test resources of the test circuit board.

[0067] Therefore, in order to balance the test parallelism and the test area and test resources, the first type of pins in the group can be re-grouped.

[0068] Specifically, when the number of the multiplexing units 110 is less than the number of the first type of pins in the group GJ, and the first type of pins in the group GJ corresponding to the test item are all used to output signals in the corresponding test item, the first type of pins in the group GJ corresponding to the test item are divided into a plurality of sub-groups GJ1-GJQ. In each sub-group GJK (K is an integer greater than or equal to 1 and less than or equal to Q), the first type of pins are coupled to the same input node SI of the plurality of multiplexing units 110, and in different sub-groups GIK, the first type of pins are coupled to different input nodes SI of the plurality of multiplexing units 110.

[0069] Still taking the 16 first type of pins in each test chip 200 as HDMI pins as an example, in addition to the on-off test, only one HDMI test item is used, and the test item is only to measure the output voltage of the 16 HDMI pins. In the case of selecting 8 multiplexing units 110, 8 of the 16 HDMI pins in each test chip 200 are coupled to the input nodes S1 of the 8 multiplexing units 110, and the remaining 8 HDMI pins are coupled to the input nodes S2 of the 8 multiplexing units 110. In this test process, the 8 HDMI pins coupled to the input nodes S1 of the 8 multiplexing units 110 are tested first, and then the 8 HDMI pins coupled to the input nodes S2 of the 8 multiplexing units 110 are tested. Only the switching time from the input nodes S1 of the 8 multiplexing units 110 to the input nodes S2 of the 8 multiplexing units 110 and the test time of the 8 HDMI pins coupled to the input nodes S2 of the 8 multiplexing units 110 need to be increased. By doing so, the number of multiplexing units 110 can be saved by half while completing the test of the 16 HDMI pins in each test chip 200.

[0070] Correspondingly, when the number of the multiplexing units 110 is less than the number of the first type of pins in the group GJ, and the first type of pins in the group GJ corresponding to the test item are all used to output signals in the corresponding test item, the number of the plurality of sub-groups GJ1-GJQ obtained by dividing the first type of pins in the group GJ can be determined according to the number of the first type of pins in the group, the increased test time, the consumed test resources, and the occupied test circuit board area. Those skilled in the art can select according to actual needs, which is not limited here.

[0071] Reference Figure 2 Fig. 1 shows a structure diagram of an embodiment of a multiplexing unit provided by the present application. As shown in the figure, in this embodiment, the multiplexing unit 110 comprises a decoder module 111 and a plurality of switches SW1-SWN corresponding to a plurality of input nodes S1-SN. The decoder module 111 is coupled to the plurality of switches SW1-SWN. Figure 2 Specifically, the decoder module 111 comprises a plurality of input nodes S1-SN and a plurality of output nodes C1-CN corresponding to the plurality of switches SW1-SWN. The plurality of input nodes S1-SN of the decoder module 111 are used to receive the selection control signals SEL[0:(M-1)], and the plurality of output nodes C1-CN of the decoder module 111 are coupled to the plurality of switches SW1-SWN, respectively. The decoder module 111 is used to receive the selection control signals SEL[0:(M-1)], and according to the selection control signals SEL[0:(M-1)], pull up the corresponding input node CI to a high level, so that the switch SWI coupled to the corresponding input node CI in the decoder module 111 is closed, thereby making the input node SI of the multiplexing unit 110 coupled to the corresponding switch SWI coupled to the output node D of the multiplexing unit 110, thereby making the first type of test pin of the DUT 200 coupled to the input node SI of the multiplexing unit 110 coupled to the output node D of the multiplexing unit 110.

[0072]

[0073] In this embodiment, the multiplexing unit 110 is a multiplexer (MUX).

[0074] It should be noted that different multiplexers have different parameter configurations. For example, the multiplexer with model ADG1608 is an 8-to-1 multiplexer, the multiplexer with model ADG1606 is a 16-to-1 multiplexer, the multiplexer with model ADG1607 is a 16-to-2 multiplexer, and so on. Accordingly, according to actual needs, multiplexers with different parameter configurations can be selected for application in the chip test system to meet different needs of chip testing.

[0075] It can be understood that the more the number of input nodes of the multiplexer, the more test resources are saved, and the lower the test parallelism is. Therefore, multiplexers with different parameter configurations can be selected according to different needs of test parallelism and test cost.

[0076] It can be understood that the more the number of input nodes of the multiplexer, the more test resources are saved, and the lower the test parallelism is. Therefore, multiplexers with different parameter configurations can be selected according to different needs of test parallelism and test cost.

[0077] ​As an example, in the case of a certain number of DUTs 200, a multiplexer with corresponding parameters can be selected according to different requirements of the number of first type DUT pins connected to the multiplexer, the test time after using the multiplexer, the test cost, etc., to achieve a better balance between the test cost and the test time.

[0078] For example, if four 8-to-1 multiplexers are selected, for the first type DUT pins and the second type DUT pins of the DUTs 200, it is assumed that 6 digital board cards and 650 test channels are needed to complete the test of a preset number of DUTs 200. If eight 4-to-1 multiplexers are selected, 6 digital board cards and 750 test channels are needed to complete the test of the preset number of DUTs 200. In the above two cases, the test cost is roughly the same in the case of the same number of digital board cards, and the increase of the test channels can achieve higher test parallelism, which helps to save test time and improve test efficiency, so it is recommended to select 4-to-1 multiplexers. Finally, the chip test scheme using 4-to-1 multiplexers is compared with the chip test scheme using 8-to-1 multiplexers in combination with the increased test time and the complexity of the test, and the optimal selection is made.

[0079] In addition, multiplexers with different bandwidths have different signal transmission speeds and transmission frequencies. For example, the signal transmission frequency of the multiplexer of model ADG1608 with a -3db bandwidth is 40MHz. Therefore, when the DUTs 200 are tested for high-speed signals, the signal amplitude attenuation caused by the multiplexer needs to be considered to avoid affecting the transmission speed of the signal.

[0080] In addition, the multiplexer has a certain internal resistance. For example, the internal resistance value of the multiplexer of model ADG1608 is 4.5 ohms at room temperature, and the maximum value is 5 ohms. The internal resistance value will become larger at high and low temperatures. Therefore, if there is a large current passing through during chip testing, the internal resistance value of the multiplexer needs to be considered to avoid the voltage drop caused by the multiplexer affecting the chip test.

[0081] In other embodiments, the multiplexing unit can also be implemented by other structures with the same function, which is not limited here.

[0082] The test unit 120 is configured to test the first type DUT pins coupled to the output nodes of the multiplexing unit 110. Specifically, the test unit 120 includes a plurality of test channels, each of which is coupled to a corresponding output node of the multiplexing unit 110, so that the test unit 120 can test the first type DUT pins coupled to the output nodes of the multiplexing unit 110.

[0083] In this embodiment, the test unit 120 is an automatic test machine. In other embodiments, the test unit can also be other structures capable of achieving the same function, which is not limited here.

[0084] In this embodiment, the test unit 120 further comprises a switch (relay) resource module (not shown) adapted to generate the selection control signal SEL[0:(M-1)].

[0085] Specifically, the switch resource module comprises a plurality of switch channels (not shown). In this embodiment, in the case that the first type of test pins of the test chips 200 in the same group GJ are respectively coupled to the same input nodes SI in the plurality of multiplexing units 110, and the first type of test pins of the test chips 200 in different groups are respectively coupled to different input nodes SI in the plurality of multiplexing units 110, the same control nodes AK (K is an integer greater than or equal to 1 and less than or equal to P) of the plurality of multiplexing units 100 coupled to the first type of test pins of the test chips 200 in the same group GJ are coupled to the same switch channels in the switch resource module, and different control nodes AK of the plurality of multiplexing units 100 coupled to the first type of test pins of the test chips 200 in the same group GJ are coupled to different switch channels in the switch resource module.

[0086] Specifically, for the multiplexing units 100 coupled to the first type of test pins of the test chips 200 in the same group, the control nodes A1, A2, …, AP of the plurality of multiplexing units 100 are respectively coupled to a corresponding switch channel in the switch resource module. In this way, the multiplexing units 100 coupled to the first type of test pins tested in the same test item can be turned on at the same time, so that simultaneous testing of the first type of test pins tested in the same test item can be realized.

[0087] Taking the multiplexing unit 110 as a multiplexer of model ADG1608 and the test unit 120 as an automatic test machine of model 93K as an example, the maximum value of the leakage current (Idd) of the multiplexer of model ADG1608 is 1 microampere (uA), and one switch channel in the switch resource module of the automatic test machine of model 93K can support a maximum current of 60 milliamperes (mA), so theoretically one switch channel can simultaneously support the connection of 60,000 multiplexers.

[0088] Therefore, in the control nodes A1-AP of the multiplexing units 100, in the case that the same control nodes A1, A2, …, AP of the plurality of multiplexing units 110 are respectively coupled with a corresponding switch channel in the switch resource module, the corresponding switch channel in the switch resource module can be simultaneously coupled with a corresponding number of multiplexing units 100, which can maximize the saving of the switch channel resources of the test unit 120, thereby helping to further save the test resources and improve the resource utilization.

[0089] In other embodiments, in the case that the number of the multiplexing units 110 is less than the number of the first type of to-be-tested pins in the group GJ, the first type of to-be-tested pins in the group GJ are all used for outputting signals in the corresponding test items, and the first type of to-be-tested pins in the group GJ are divided into a plurality of sub-groups GJ1-GJQ, the same control nodes AK of the plurality of multiplexing units 100 coupled with the first type of to-be-tested pins of the to-be-tested chip 200 in the same sub-group GJK are coupled with the same switch channel in the switch resource module, and the different control nodes AK of the plurality of multiplexing units 100 coupled with the first type of to-be-tested pins of the to-be-tested chip 200 in the same sub-group GJK are coupled with different switch channels in the switch resource module.

[0090] In the embodiment, the to-be-tested chip 200 further includes a second type of to-be-tested pin coupled with the test unit 120. Accordingly, the second type of to-be-tested pin and the test channel in the test unit 120 have a one-to-one corresponding relationship.

[0091] In specific implementations, the second type of to-be-tested pin can include at least one of the following: (1) a pin for testing in a scan test item; (2) a pin for testing in a built-in self-test item; (3) a pin for testing in a high-speed test item; (4) a pin for testing in a high-voltage test item; (5) a pin for testing in a large-current test item, etc.

[0092] In the embodiment, the to-be-tested chip 200 is a System on Chip (SoC) chip. Accordingly, the chip test system 100 further includes a test circuit board (not shown), and the multiplexing units 100 are arranged on the test circuit board, and the test circuit board includes a plurality of test sockets, and the to-be-tested chip 200 is fixedly installed in a corresponding test socket and coupled with the test unit 120 through the test circuit board.

[0093] In other embodiments, the to-be-tested chip can also be other types of chips, and the test unit can also be a test device for testing other types of chips, which is not limited herein.

[0094] In the embodiment, the chip testing system 100 further comprises a testing circuit board (not shown), and the multiplexing unit 110 is arranged on the testing circuit board. Accordingly, the chip testing system further comprises a power supply unit (not shown) adapted to provide a power supply voltage for the multiplexing unit 110.

[0095] Specifically, the power supply unit comprises a DC-DC converter, and the DC-DC converter is arranged on the testing circuit board. Taking a model 93K automatic testing machine as an example, the testing unit 120 has a fixed power supply (e.g., a voltage of 5V), and the DC-DC converter is used to convert the voltage signal output by the fixed power supply into a power supply voltage required by the multiplexing unit.

[0096] In other embodiments, the power supply unit can also be implemented by other structures capable of achieving the same function, and the power supply unit can also comprise other structures having the same function as the DC-DC converter, such as a low dropout linear regulator (LDO), etc., which are not limited herein.

[0097] In the embodiment, the power supply voltage provided by the power supply unit comprises an input voltage and / or an output voltage of a first type of to-be-tested pin coupled to the input node of the multiplexing unit 110 when the test passes and / or fails, so as to meet the testing requirement of the first type of to-be-tested pin.

[0098] In the embodiment, the power supply voltage provided by the power supply unit comprises an input voltage and / or an output voltage of a first type of to-be-tested pin coupled to the input node of the multiplexing unit 110 when the test passes and / or fails, so as to meet the testing requirement of the first type of to-be-tested pin.

[0099] As an example, the power supply voltage provided by the power supply unit comprises a positive voltage and a negative voltage, i.e., the voltage range of the output node of the multiplexing unit 110 is from the positive voltage to the negative voltage. The negative voltage can be an input or output voltage when the first type of to-be-tested pin of the to-be-tested chip is tested for continuity.

[0100] Table 1 shows a comparison between a test scheme configuration using a multiplexer and a test scheme configuration not using a multiplexer and a test cost of each to-be-tested chip:

[0101] Table 1

[0102]

[0103] In Table 1, Sites represent the number of test sockets on a test circuit board, i.e. the number of chips 200 to be tested mounted on a test circuit. As can be seen from Table 1, the output per hour is significantly increased and the chip testing cost is significantly reduced when the chip testing system in the embodiment of the present application is used to test the chips 200 to be tested, which shows that the chip testing system in the embodiment of the present application has significant advantages.

[0104] The above description of disclosed embodiments enables one skilled in the art to make or use the application. Numerous modifications to these embodiments will be apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Therefore, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0105] Although the present application has been disclosed as above, the present application is not limited to the above. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the scope of protection of the present application should be defined by the scope defined by the claims.

Claims

1. A chip testing system, characterized in that: include: a multi-way selection unit, comprising a plurality of input nodes, a plurality of control nodes, and at least one output node, wherein the plurality of input nodes are respectively coupled to first-type pins to be tested of the chip to be tested, the plurality of control nodes are used to receive a selection control signal, and the output node is coupled to the test unit and is adapted to selectively couple one of the plurality of input nodes to one of the output nodes according to the selection control signal, so that the corresponding first-type pin to be tested is coupled to one of the output nodes; The testing unit is coupled to the multi-way selection unit and is adapted to test a first-type pin to be tested coupled to one of the output nodes of the multi-way selection unit.

2. The chip testing system according to claim 1, wherein: The multiple input nodes of the multiple selection unit are coupled to multiple different first-type pins under test of the chip under test, or the multiple input nodes of the multiple selection unit are coupled to the same first-type pins under test of multiple chips under test.

3. The chip testing system according to claim 1, wherein: There are a plurality of chips to be tested and a plurality of multiplexer units, and the first type of pins to be tested of the plurality of chips to be tested are divided into a plurality of groups according to test items; If the number of the multiplexer units is greater than or equal to the number of the first type pins to be tested in each group, the first type pins to be tested in the same group are coupled to the same input node in the multiplexer unit, and the first type pins to be tested in different groups are coupled to different input nodes in the multiplexer unit; If the number of the multi-way selection units is less than the number of the first type of pins to be detected in the group, and the first type of pins to be detected in the group are all used to output signals in the corresponding test items, the first type of pins to be detected in the group are divided into multiple sub-groups; the first type of pins to be detected in each sub-group are coupled to the same input node in multiple multi-way selection units, and the first pins to be detected in different sub-groups are coupled to different input nodes in multiple multi-way selection units.

4. The chip testing system according to claim 3, wherein: The test unit includes: a switch resource module, adapted to generate the selection control signal.

5. The chip testing system according to claim 4, wherein: The switch resource module includes a plurality of switch channels; The same control node of the multiple multiplexer units coupled to the first type of pins to be tested of the chips to be tested in the same group is coupled to the same switch channel in the switch resource module, and different control nodes of the multiple multiplexer units coupled to the first type of pins to be tested of the chips to be tested in the same group are coupled to different switch channels in the switch resource module; or, The same control node of multiple multi-way selection units coupled to the first type of pins to be tested of the chip to be tested in the same sub-group is coupled to the same switch channel in the switch resource module, and the different control nodes of multiple multi-way selection units coupled to the first type of pins to be tested of the chip to be tested in the same sub-group are coupled to different switch channels in the switch resource module.

6. The chip testing system according to claim 1, wherein: The first type of pins to be tested include at least one of the following: Pins that are tested for continuity only; Pins that are only tested for voltage characteristics and / or current characteristics; Analog pins for testing preset analog items.

7. The chip testing system according to claim 1, wherein: The chip under test further includes a second type of pins under test, and the second type of pins under test are coupled to the test unit.

8. The chip testing system according to claim 7, wherein: The second type of pin to be tested includes at least one of the following: Pins tested in scan test items; Pins tested in built-in self-test items; Pins tested in high-speed test items; Pins tested in high voltage test items; Pins tested in the high current test item.

9. The chip testing system according to claim 1, wherein: The chip testing system includes a testing circuit board, and the multi-way selection unit is arranged on the testing circuit board; The test circuit board includes a test socket. The chip to be tested is fixedly installed in the test socket and is coupled to the test unit through the test circuit board.

10. The chip testing system according to claim 1, wherein: The chip testing system further includes: a power supply unit adapted to provide a power supply voltage to the multiplexer unit.

11. The chip testing system according to claim 10, wherein: The supply voltage includes an input voltage and / or an output voltage of a first-type pin to be tested coupled to an input node of the multiplexer unit when the test passes and / or fails.

12. The chip testing system according to claim 10, wherein: The power supply unit includes a DC-DC converter.

13. The chip testing system according to claim 1, wherein: The multiplex selection unit includes a decoding module and switches corresponding to the multiple input nodes one by one; The decoding module is adapted to receive the selection control signal and control the corresponding switch to close according to the selection control signal, so that the corresponding input node in the multi-way selection unit is coupled to the output node through the corresponding switch.

14. The chip testing system according to claim 1, wherein: The multiplexing unit includes a multiplexer.

15. The chip testing system according to claim 1, wherein: The chip to be tested includes a SOC chip.

16. The chip testing system according to claim 1, wherein: The testing unit includes an automatic testing machine.

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