Signal conditioning circuit, conditioning equipment and test system

Abstract

The invention relates to the technical field of vehicle-mounted signal testing, in particular to a signal conditioning circuit, conditioning equipment and a testing system. The circuit comprises a first processing module, a first protection module, a second processing module, a second protection module, a power supply module and a third protection module, and the first processing module is used for modulating an initial PWM signal output by an NI case into a target PW signal conforming to the voltage acquisition range of an ECU; the first protection module is used for performing overvoltage protection on the first processing module; the second processing module is used for converting the control signal output by the ECU into a target control signal conforming to the voltage acquisition range of the NI case; the second protection module is used for performing overcurrent protection on the second processing module; the power supply module is used for providing respective corresponding working voltages for the first processing module and the second processing module; and the third protection module is used for performing overvoltage and overcurrent protection on the power supply module. By adopting the scheme of the invention, the stability of the digital signal in the HIL test process can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of vehicle-mounted signal testing, and in particular to a signal conditioning circuit, a conditioning device and a testing system. BACKGROUND

[0002] At present, in the field of vehicle-mounted testing, HIL (Hardware-in-the-loop) testing is a widely used technology. The HIL testing usually adopts a NI chassis and a test board card group; the NI chassis is used to simulate a vehicle-mounted device or a vehicle-mounted electrical system and can output corresponding state signals, and the test board card group is used to transmit various signals between the NI chassis and an ECU (Hardware-in-the-loop, electronic control unit). The NI chassis is a chassis produced by the United States National Instruments (NI) for integrating and managing various modular instruments and data acquisition devices.

[0003] The interaction between the NI chassis and the ECU involves both digital signals and analog signals; for the interaction process of the digital signals, the voltage ranges of the input signals corresponding to the NI chassis and the ECU are different; this requires the digital processing module in the test board card group to be able to implement corresponding processing on the digital signals interacted between the NI chassis and the ECU, so that the NI chassis and the ECU can both receive signals within their voltage acquisition ranges. However, due to the complex environment in the vehicle-mounted testing environment, there may be many interference factors, which may cause overvoltage or overcurrent in the circuit, which will seriously affect the quality of the digital signals.

[0004] Therefore, how to improve the stability of the digital signals in the HIL testing process is a problem to be solved. SUMMARY

[0005] Therefore, it is necessary to provide a signal conditioning circuit, a conditioning device and a testing system capable of improving the quality of digital signals in the HIL testing process.

[0006] In a first aspect, the present application provides a signal conditioning circuit, which comprises a first processing module, a first protection module, a second processing module, a second protection module, a power supply module and a third protection module, wherein:

[0007] The first processing module is configured to receive an initial PWM signal output by the NI chassis and modulate the initial PWM signal into a target PWM signal within a first threshold range, wherein the first threshold range is the voltage acquisition range of the ECU; and the first protection module is configured to perform overvoltage protection on the first processing module.

[0008] The second processing module is configured to receive the control signal in digital form output by the ECU and convert the control signal into a target control signal within a second threshold range, which is a voltage collection range of the NI chassis; and the second protection module is configured to perform overcurrent protection on the second processing module.

[0009] The power module is configured to provide respective working voltages for the first processing module and the second processing module; and the third protection module is configured to perform overvoltage and overcurrent protection on the power module.

[0010] In one of the embodiments, the first processing module includes an inverter, a first N-channel MOS tube, a second P-channel MOS tube, and a third N-channel MOS tube, wherein:

[0011] The gate of the first MOS tube is connected to the NI chassis for inputting an initial PWM signal; the drain of the first MOS tube is connected to an output end of the power module for inputting a working voltage VDD; and the source of the first MOS tube is grounded.

[0012] The input end of the inverter is connected to the drain of the first MOS tube; and the output end of the inverter is connected to the gate of the second MOS tube and the gate of the third MOS tube.

[0013] The drain of the second MOS tube is connected to the working voltage VDD provided by the power module; the source of the third MOS tube is grounded; the source of the second MOS tube and the drain of the third MOS tube are connected to an output end of the first processing module; and the output end of the first processing module is connected to an input end of the ECU.

[0014] In one of the embodiments, the input end of the first processing module is further connected to a voltage stabilizing module, wherein:

[0015] The voltage stabilizing module includes a first voltage stabilizing diode and a Schottky diode; the first voltage stabilizing diode and the Schottky diode are connected in anti-series; the anode of the first voltage stabilizing diode is connected to the gate of the first MOS tube; and the anode of the Schottky diode is grounded.

[0016] In one of the embodiments, the drain of the second MOS tube is connected to the power module, and the power module provides a variable voltage VDD-SW for the drain of the second MOS tube.

[0017] In one of the embodiments, the first protection module includes a first voltage dividing resistor and a second voltage dividing resistor, wherein:

[0018] The first voltage dividing resistor is connected in series between the output end of the NI chassis and the gate of the first MOS tube; one end of the second voltage dividing resistor is connected to the gate of the first MOS tube, and the other end is grounded.

[0019] In one of the embodiments, the second processing module comprises a non-inverting buffer, the second protection module is connected between the output end of the ECU and the input end of the non-inverting buffer, and the output end of the non-inverting buffer is connected to the NI chassis.

[0020] In one of the embodiments, the second protection module comprises a protection resistor and a second zener diode, wherein:

[0021] The protection resistor is connected in series between the output end of the NI chassis and the input end of the non-inverting buffer, the cathode of the second zener diode is connected to the input end of the non-inverting buffer, and the anode of the second zener diode is grounded.

[0022] In one of the embodiments, the third protection module comprises a fuse protector and a varistor, and the initial voltage is input to the input end of the power supply module through the fuse protector.

[0023] One end of the varistor is connected to the input end of the power supply module, and the other end is grounded.

[0024] In a second aspect, the application provides a conditioning device, which comprises a power supply board card and a conditioning board card, wherein the signal conditioning circuit as described in any one of the above first aspects is configured in the power supply board card and the conditioning board card.

[0025] In a third aspect, the application provides a test system, which comprises an NI chassis, an ECU, and the conditioning device as described in the second aspect, wherein the conditioning device is used for signal interaction between the NI chassis and the ECU.

[0026] In the above signal conditioning circuit, conditioning device, and test system, the first processing module can modulate the initial PWM signal output by the NI chassis into a target PWM signal within a first threshold range, and since the first threshold range is the voltage collection range of the ECU, the target PWM signal obtained through the first processing module can be received by the ECU. The second processing module can convert the control signal output by the ECU into a target control signal within a second threshold range, and since the second threshold range is the voltage collection range of the NI chassis, the target control signal obtained through the second processing module can be received by the NI chassis.

[0027] The initial voltage and initial current inputted from outside to the power module can have unstable fluctuations, and the short circuit of the first processing module and / or the second processing module can also cause a large voltage or current in the power module, thereby causing the risk of damage to the power module; the third protection module can perform overvoltage and overcurrent protection on the power module, thereby enabling the working voltage provided by the power module for the first processing module and the second processing module to remain stable, and also reducing the probability of damage to the power module itself; the first protection module can perform overcurrent protection on the first processing module, thereby reducing the impact of large current on each component in the first processing module, enabling the target PWM signal output by the first processing module to be stable; the second protection module can perform overvoltage protection on the second processing module, thereby reducing the probability of damage to the second processing module by overvoltage, thereby improving the stability of the second processing module. The scheme of the present application improves the stability of the conditioning circuit during operation through two-stage overvoltage and overcurrent protection, thereby enabling the signals transmitted between the NI case and the ECU to remain stable. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0029] Figure 1 Structure schematic diagram of a signal conditioning circuit in an embodiment;

[0030] Figure 2 Structure schematic diagram of a first processing module in an embodiment;

[0031] Figure 3 Structure schematic diagram of a second processing module in an embodiment;

[0032] Figure 4 Structure schematic diagram of a power module in an embodiment;

[0033] Figure 5 Structure schematic diagram of a conditioning device in an embodiment. DETAILED DESCRIPTION

[0034] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the related drawings. The drawings show embodiments of the present application. However, the present application can be implemented in many different forms, and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0036] It is to be understood that the terms "first", "second", and the like, used herein do not connote any hierarchy or order, but are used to distinguish one element from another. For example, a first element can be termed a second element, and, similarly, a second element can be termed a first element, without departing from the scope of the present application.

[0037] It is to be understood that, in the following embodiments, "connected" or "coupled" or "linked" or the like means that the circuit, module, unit, or the like connected or coupled or linked between each other can transmit electrical signal or data.

[0038] It is to be understood that "at least one" means one or more, "multiple" means two or more. "At least part of the element" means part or all of the element.

[0039] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" or "comprising", or "includes" or "including" when used herein, specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

[0040] In one exemplary embodiment, the present application provides a signal conditioning circuit, which can be applied to signal conditioning and transmission between two devices or two systems; wherein the signal conditioning means that the output signal of the output party is conditioned to be within the voltage and / or current range of the receiving party, so that the output party can realize normal signal transmission with the receiving party.

[0041] In a typical scenario, the signal conditioning circuit provided by the present application can be used for vehicle testing of a car; in the vehicle testing of the car, the NI chassis is used to simulate a vehicle-mounted device or a vehicle-mounted electrical system, and can output corresponding state signals, and the interaction between the NI chassis and the ECU (Electronic Control Unit) will involve both digital signals and analog signals; for the interaction process of the digital signals, the voltage ranges of the input signals corresponding to the NI chassis and the ECU are different; this requires the digital processing module in the test board card group to be able to implement corresponding processing on the digital signals exchanged between the NI chassis and the ECU, so that the NI chassis and the ECU can both receive signals within their voltage acquisition ranges. Moreover, due to the complex environment in the vehicle testing environment, there may be many interference factors; for example, which may cause overvoltage or overcurrent conditions, which will seriously affect the quality of the digital signals.

[0042] In an exemplary embodiment, as shown in Figure 1 The present application provides a signal conditioning circuit, which comprises a first processing module, a second processing module and a power module; wherein the first processing module is configured to receive an initial PWM signal output by the NI chassis and modulate the initial PWM signal into a target PWM signal within a first threshold range, wherein the first threshold range is the voltage acquisition range of the ECU; the second processing module is configured to receive a digital control signal output by the ECU and convert the control signal into a target control signal within a second threshold range, wherein the second threshold range is the voltage acquisition range of the NI chassis; and the power module is configured to provide respective working voltages for the first processing module and the second processing module.

[0043] In the embodiments of the present application, the first processing module can modulate the initial PWM signal output by the NI chassis into a target PWM signal within the first threshold range, and since the first threshold range is the voltage acquisition range of the ECU, the target PWM signal obtained after modulation by the first processing module can be received by the ECU. The second processing module can convert the control signal output by the ECU into a target control signal within the second threshold range, and since the second threshold range is the voltage acquisition range of the NI chassis, the target control signal obtained after processing by the second processing module can be received by the NI chassis.

[0044] Further, in order to improve the stability of signal transmission between the NI chassis and the ECU, the signal conditioning circuit in the embodiments of the present application further comprises a first protection module, a second protection module and a third protection module. Referring to Figure 1The first protection module is connected to the output end of the NI case and the input end of the first processing module, and is used for overvoltage protection of the first processing module. The second protection module is connected to the output end of the ECU and the input end of the second processing module, and is used for overcurrent protection of the second processing module. The third protection module is connected to the input end of the power module, and is used for overvoltage and overcurrent protection of the power module.

[0045] In the embodiment of the present application, the initial voltage and the initial current input to the power module from outside may fluctuate unstably, and the short circuit of the first processing module and / or the second processing module may cause a large voltage or current in the power module, thereby causing a risk of damage to the power module. The third protection module can perform overvoltage and overcurrent protection on the power module, thereby keeping the working voltage provided by the power module for the first processing module and the second processing module stable and reducing the probability of damage to the power module itself. The first protection module can perform overcurrent protection on the first processing module, thereby reducing the impact of large current on each component in the first processing module and keeping the target PWM signal output by the first processing module stable. The second protection module can perform overvoltage protection on the second processing module, thereby reducing the probability of damage to the second processing module by overvoltage and improving the stability of the second processing module. The scheme of the present application improves the stability of the conditioning circuit during operation through two-stage overvoltage and overcurrent protection, thereby keeping the signals transmitted between the NI case and the ECU stable.

[0046] In one of the embodiments, as shown in Figure 2 The first processing module includes an inverter NF, a first N-channel MOS tube Q1, a second P-channel MOS tube Q2, and a third N-channel MOS tube Q3. The gate (G) of the first MOS tube A1 is connected to the output end of the NI case for inputting an initial PWM signal. The high-level voltage of the initial PWM signal is VCC. The drain (D) of the first MOS tube Q1 is connected to the output end of the power module for inputting a working voltage VDD. The voltage VCC is greater than the first voltage VDD. The source (S) of the first MOS tube Q1 is grounded. The input end of the inverter NF is connected to the drain (D) of the first MOS tube Q1. The output end of the inverter NF is connected to the gate (G) of the second MOS tube Q2 and the gate (G) of the third MOS tube Q3. The drain (D) of the second MOS tube Q2 is connected to the working voltage VDD provided by the power module, and the source (S) of the third MOS tube Q3 is grounded. The source (S) of the second MOS tube Q2 and the drain (D) of the third MOS tube Q3 are connected to the output end of the first processing module, and the output end of the first processing module is connected to the input end of the ECU.

[0047] The operating principle of the first processing module is as follows: when the initial PWM signal is in a high-level state, the gate (G) input of the first MOS transistor Q1 is high, thereby causing conduction between the drain (D) and source (S) of the first MOS transistor Q1. At this time, the input of the inverter NF is low, and the output of the inverter NF is high, which is then simultaneously input to the gates (G) of the second and third MOS transistors Q2 and Q3. When the gate (G) input of the second MOS transistor Q2 is high, conduction between the drain (D) and source (S) of the second MOS transistor Q2 is blocked. However, when the gate (G) input of the third MOS transistor Q3 is high, conduction between the drain (D) and source (S) of the third MOS transistor Q3 is enabled. Because the source (S) of the first MOS transistor Q1 is grounded, the output of the first processing module is low at this time.

[0048] When the initial PWM signal is low, the gate (G) input of the first MOS transistor Q1 is low, and therefore the drain (D) and source (S) of the first MOS transistor Q1 are not conductive. At this time, the input of the inverter NF is high (VDD), and the output of the inverter NF is low, which is then simultaneously input to the gates (G) of the second and third MOS transistors Q2 and Q3. When the gate (G) input of the second MOS transistor Q2 is low, the drain (D) and source (S) of the second MOS transistor Q2 are conductive. When the gate (G) input of the third MOS transistor Q3 is low, the drain (D) and source (S) of the third MOS transistor Q3 are not conductive. Because the drain (D) of the second MOS transistor Q2 is connected to the operating voltage VDD, the output of the first processing module is high, and the voltage value of the high level is the operating voltage VDD. That is, the initial PWM signal is a high-level waveform signal with a voltage of VCC. After modulation by the first processing module, a high-level waveform signal with a voltage of VDD is obtained, i.e., the target PWM signal. In one example, the operating voltage VCC is +12V and the operating voltage VDD is +5V.

[0049] Further, if Figure 2 As shown, the input end of the first processing module is also connected to a voltage stabilization module, wherein the voltage stabilization module includes a first voltage stabilization diode D1 and a Schottky diode D2. The first voltage stabilization diode D1 and the Schottky diode D2 are connected in anti-series, with the anode of the first voltage stabilization diode D1 connected to the gate (G) of the first MOS transistor Q1, and the anode of the Schottky diode D2 connected to ground. The first voltage stabilization diode D1 and the Schottky diode are connected between the gate (G) of the first MOS transistor Q1 and the reference ground. The interaction between the first voltage stabilization diode D1 and the Schottky diode provides a voltage stabilization effect, thereby maintaining a stable voltage input to the gate (G) of the first MOS transistor Q1.

[0050] Further, refer to Figure 2The second MOS tube Q2 is further connected with a filter capacitor C1, one end of the filter capacitor C1 is connected to the drain (D) of the second MOS tube Q2, and the other end is grounded. The filter capacitor C1 can filter the working voltage VDD input to the first processing module, so that the input working voltage VDD is kept stable.

[0051] Further, referring to Figure 2 A current source is further connected in series between the drain (D) of the first MOS tube Q1 and the working voltage VDD, and a voltage source is further connected between the drain (D) of the first MOS tube Q1 and the input end of the inverter NF.

[0052] In one example, as Figure 2 shown, the first protection module includes a first voltage dividing resistor R1 and a second voltage dividing resistor R2, wherein: the first voltage dividing resistor R1 is connected in series between the output end of the NI case and the gate (G) of the first MOS tube Q1; one end of the second voltage dividing resistor R2 is connected to the gate (G) of the first MOS tube Q1, and the other end is grounded. The first voltage dividing resistor R1 and the second voltage dividing resistor can achieve voltage division, and the effective voltage division ratio is R1 / (R1+R2). Since the high level voltage of the initial PWM signal is VCC, the high level input to the gate (G) of the first MOS tube Q1 is VCC*R1 / (R1+R2).

[0053] Since the first voltage dividing resistor R1 and the second voltage dividing resistor achieve the function of voltage division, the voltage input to the first MOS tube Q1 is reduced, which can also reduce the current in the circuit, thereby achieving the function of overcurrent protection for the first processing module.

[0054] Further, as Figure 2 shown, the drain (D) of the second MOS tube is connected to a power supply module, and the power supply module provides a variable voltage VDD-SW to the drain (D) of the second MOS tube. Since the voltage value of the high level of the target PWM signal output by the first processing module is determined by the input voltage of the drain (D) of the second MOS tube Q2, by inputting a variable voltage VDD-SW to the drain (D) of the second MOS tube Q2, the voltage value of the high level of the target PWM signal actually output by the first processing module can be adjusted.

[0055] It can be understood that the structure of the above-mentioned first processing module can also adopt other forms, which are not limited to the forms mentioned in the above-mentioned embodiments; for example, the first MOS tube Q1 in the structure of the above-mentioned first processing module can be replaced by an NPN type triode, the second MOS tube Q2 can be replaced by a PNP type triode, and the third MOS tube Q3 can also be replaced by an NPN type triode.

[0056] Further, the gate of the first MOS Q1 is connected with a diode D0 and a working voltage VDD, wherein the anode of the diode D0 is connected with the gate of the first MOS Q1, and the cathode is connected with one end of the input working voltage VDD.

[0057] More further, the first processing module can be replaced by an existing integrated chip, for example, MCP1404T-E / SN can be used to replace the first processing module; wherein the MCP1404T-E / SN chip includes two independent input and output paths, and each input and output path can be equivalent to replace the first processing module.

[0058] In one embodiment, referring to Figure 3 , the second processing module includes a non-inverting buffer H1, the second protection module is connected between the output end of the ECU and the input end of the non-inverting buffer H1, and the output end of the non-inverting buffer H1 is connected with the NI case.

[0059] Specifically, the non-inverting buffer H1 can improve the driving ability of the signal so that the signal can drive a larger load; isolate the front stage (ECU) and the rear stage load (NI case) to prevent the front stage from being overloaded. The non-inverting buffer H1 can also perform level conversion so that its output can adapt to signals of different voltage systems; in the scheme of the present application, the non-inverting buffer H1 can convert the voltage of the control signal output by the ECU into a target control signal within a second threshold range, so that the target control signal can meet the voltage acquisition range of the NI case. Further, the non-inverting buffer H1 can also reduce signal attenuation and suppress noise interference, that is, the target control signal output to the NI case by the non-inverting buffer H1 is more stable.

[0060] In one embodiment, referring to Figure 3 , the second protection module includes a protection resistor R1 and a second zener diode D3; wherein the protection resistor R1 is connected in series between the output end of the NI case and the input end of the non-inverting buffer H1, the cathode of the second zener diode D3 is connected with the input end of the non-inverting buffer H1, and the anode of the second zener diode D3 is grounded.

[0061] Specifically, the protection resistor R1 can limit the size of the current input to the non-inverting buffer H1, thereby playing a role of overcurrent protection for the non-inverting buffer H1; and the second zener diode D3 can stabilize the control signal input to the input end of the non-inverting buffer H1, so that the high level in the input control signal remains stable.

[0062] In one of the embodiments, the power module is configured to convert the input initial voltage into respective working voltages for the first processing module and the second processing module, and to supply power to the first processing module and the second processing module. In this case, the working voltages of the first processing module and the second processing module are different, and the power module can include at least two voltage conversion modules, i.e., a first voltage conversion module and a second voltage conversion module. The first voltage conversion module is configured to convert the initial voltage into the working voltage VDD corresponding to the first processing module, and the second voltage conversion module is configured to convert the initial voltage into the working voltage corresponding to the second processing module.

[0063] Further, referring to Figure 4 , the initial voltage is first input to the third protection module and then distributed to each voltage conversion module by the third protection module. The first voltage conversion module and the second voltage conversion module can both be implemented by using an integrated voltage conversion chip. In this case, the first voltage conversion module corresponds to the voltage conversion chip U1, and the second voltage conversion module corresponds to the voltage conversion chip U2.

[0064] Specifically, referring to Figure 4 , the third protection module includes a fuse protector FU and a voltage-dependent resistor RV. In this case, the first end of the fuse protector FU is configured to input the initial voltage, the second end of the fuse protector FU is connected to the input end of the first voltage conversion module and the second voltage conversion module, respectively, one end of the voltage-dependent resistor RV is connected to the second end of the fuse protector FU, and the other end is grounded. Further, the power module further includes a connector configured to receive an external variable voltage VCC-SW and to provide the variable voltage VCC-SW to the first processing module.

[0065] In one of the exemplary embodiments, referring to Figure 5 , the present application provides a conditioning device including a power board card, a conditioning board card, and a backboard. In this case, the conditioning board card is configured with the first processing module and the second processing module as disclosed in the above signal conditioning circuit embodiments. The conditioning board card is configured with multiple input and output, i.e., the conditioning board card is configured with multiple first processing modules and second processing modules, and the number of the first processing modules and the second processing modules is the same. The power board card is configured with the power module as disclosed in the above signal conditioning circuit embodiments. The backboard is configured to connect the power board card and the conditioning board card. On one hand, the backboard provides input and output signals from the NI chassis and / or the ECU to the conditioning board card through the set input and output terminals. On the other hand, the power module supplies power to each first processing module and each second processing module in the conditioning board card through the pre-set wiring of the backboard.

[0066] In one exemplary embodiment, the present application provides a test system; the test system comprises a first object device, a second object device and a conditioning device as disclosed in the above conditioning device embodiments; the conditioning device is configured to interact signals between the first object device and the second object device. In one typical example scenario, the first object device can be a NI chassis in HIL test, and the second object device can be an ECU on vehicle in HIL test.

[0067] In the description of the present specification, the description referring to the terms "some embodiments", "other embodiments", and the like, means that the particular feature, structure, material or characteristic being described is included in at least one embodiment or example of the present application. The illustrative description of these terms in this specification is not necessarily referring to the same embodiment or example.

[0068] The technical features of the above embodiments can be combined in any manner. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combinations of the technical features do not contradict, they should be considered as the scope of the present application.

[0069] The above embodiments only express several implementation manners of the present application, the description is specific and detailed, however, it should not be understood as the limitation to the scope of the present application. It should be pointed out that, for the ordinary skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A signal conditioning circuit, characterized in that: The circuit includes a first processing module, a first protection module, a second processing module, a second protection module, a power supply module and a third protection module, wherein: The first processing module is configured to receive an initial PWM signal output by the NI chassis and modulate the initial PWM signal into a target PWM signal within a first threshold range, wherein the first threshold range is a voltage acquisition range of the ECU; the first protection module is configured to provide overvoltage protection for the first processing module; The second processing module is configured to receive a digital control signal output by the ECU and convert the control signal into a target control signal within a second threshold range, where the second threshold range is a voltage acquisition range of the NI chassis; the second protection module is configured to provide overcurrent protection for the second processing module; The power supply module is used to provide the first processing module and the second processing module with their respective corresponding operating voltages; the third protection module is used to provide overvoltage and overcurrent protection for the power supply module.

2. The signal conditioning circuit according to claim 1, wherein: The first processing module includes an inverter, a first N-channel MOS transistor, a second P-channel MOS transistor, and a third N-channel MOS transistor, wherein: The gate of the first MOS transistor is connected to the NI chassis for inputting an initial PWM signal; the drain of the first MOS transistor is connected to the output end of the power module for inputting an operating voltage VDD; the source of the first MOS transistor is grounded; The input end of the inverter is connected to the drain of the first MOS transistor; the output end of the inverter is connected to the gate of the second MOS transistor and the gate of the third MOS transistor at the same time; The drain of the second MOS transistor is connected to the operating voltage VDD provided by the power module, and the source of the third MOS transistor is grounded; the source of the second MOS transistor and the drain of the third MOS transistor are connected to the output end of the first processing module, and the output end of the first processing module is connected to the input end of the ECU.

3. The signal conditioning circuit according to claim 2, wherein: The input end of the first processing module is further connected to a voltage stabilizing module, wherein: The voltage stabilizing module includes a first voltage stabilizing diode and a Schottky diode; the first voltage stabilizing diode and the Schottky diode are connected in anti-series, the anode of the first voltage stabilizing diode is connected to the gate of the first MOS tube, and the anode of the Schottky diode is grounded.

4. The signal conditioning circuit according to claim 3, wherein: The drain of the second MOS transistor is connected to the power module, and the power module provides a variable voltage VDD-SW for the drain of the second MOS transistor.

5. The signal conditioning circuit according to claim 4, wherein: The first protection module includes a first voltage-dividing resistor and a second voltage-dividing resistor, wherein: The first voltage-dividing resistor is connected in series between the output end of the NI chassis and the gate of the first MOS transistor; one end of the second voltage-dividing resistor is connected to the gate of the first MOS transistor, and the other end is grounded.

6. The signal conditioning circuit according to claim 1, wherein: The second processing module includes a non-inverting buffer. The second protection module is connected to the output end of the ECU and the input end of the non-inverting buffer. The output end of the non-inverting buffer is connected to the NI chassis.

7. The signal conditioning circuit according to claim 6, wherein: The second protection module includes a protection resistor and a second voltage stabilizing diode, wherein: The protection resistor is connected in series between the output end of the NI chassis and the input end of the non-inverting buffer, the cathode of the second voltage regulator diode is connected to the input end of the non-inverting buffer, and the anode of the second voltage regulator diode is grounded.

8. The signal conditioning circuit according to claim 7, wherein: The third protection module includes a fuse protector and a varistor, and the initial voltage is input to the input end of the power module after passing through the fuse protector; One end of the varistor is connected to the input end of the power module, and the other end is grounded.

9. A conditioning device, characterized in that: The device includes a power supply board and a conditioning board, wherein the power supply board and the conditioning board are configured with a signal conditioning circuit as described in any one of claims 1 to 8.

10. A testing system, characterized in that: The apparatus comprises an NI chassis, an ECU, and the conditioning device according to claim 9, wherein: The conditioning device is used for performing signal interaction between the NI chassis and the ECU.

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