LDO overcurrent detection and current limiting circuit
Through the LDO overcurrent detection and current limiting circuit, the current comparator and constant current output clamp circuit are used to solve the problems of LDO overcurrent detection accuracy and high power consumption in the existing technology, and achieve high-precision current limiting output without shutting down the LDO, saving circuit area.
Patent Information
- Application Number
- CN202510964898.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-14
- Publication Date
- 2025-10-17
AI Technical Summary
Existing LDO overcurrent detection solutions have the problem of high accuracy but large area and power consumption. In addition, the LDO needs to be shut down after OCP is triggered, which increases design costs.
The LDO overcurrent detection and current limiting circuit is adopted, including an overcurrent detection circuit and a constant current output clamp circuit. The output current is detected by a current comparator and clamped at the power tube control end to limit the output current and avoid LDO shutdown.
High-precision overcurrent detection is achieved to avoid LDO shutdown, saving power consumption and circuit area. At the same time, it automatically switches to normal state after the load returns to normal.
Smart Images
Figure CN120803178A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of power management chip, and particularly relates to an LDO overcurrent detection and current limiting circuit. BACKGROUND
[0002] In the design of LDO (Low-Dropout Regulator), it is necessary to protect the chip from being burned out when the load current is too large. The current mainstream method is to detect the output current of the LDO, and when the output current reaches a set threshold, an output control signal is sent to a system control module to control the LDO to be turned off or the load to be turned off, so as to protect the LDO and the load from being burned out by large current. Figure 1 An existing overcurrent detection architecture is shown, and the detection principle is as follows: M1 and M2 form a current mirror, the output current is scaled down in proportion, and then a voltage VSE_OCP is generated by flowing through a resistor R2, and then a comparator is used to compare with a reference voltage VREF_OCP. When the output load increases, the M2 mirror current also increases, resulting in the rise of VSE_OCP, and when it exceeds VREF_OCP, the comparator output flips as an OCP indication signal. After triggering OCP, the LDO is turned off. In order to prevent false triggering during transient load, an RC is often added to the output stage to do delay.
[0003] This detection scheme has the following problems: 1. The accuracy of using the comparator is high, but the area and power consumption are large; 2. In order to prevent false triggering, a capacitor C1 is needed to generate a delay as an overcurrent delay; 3. After triggering OCP, the LDO is generally turned off, so a restart circuit is needed, which increases the design cost. SUMMARY
[0004] In view of the problems in the prior art, an LDO overcurrent detection and current limiting circuit is provided, which limits the output current after detecting the triggering of overcurrent and does not cause power down. After the load returns to normal, it can automatically switch to the normal state without the need for an additional overcurrent recovery circuit.
[0005] The technical scheme adopted by the present application is as follows: an LDO overcurrent detection and current limiting circuit, comprising an LDO circuit, an overcurrent detection circuit and a constant current output clamping circuit, wherein, The LDO circuit is used to control the output stable voltage according to the control end voltage of the power tube; The overcurrent detection circuit is used to detect the output current of the LDO circuit and generate an overcurrent detection signal; The constant current output clamping circuit is used to clamp the control end voltage of the power tube in the LDO circuit according to the overcurrent detection signal, and then limit the output current of the LDO circuit.
[0006] As a preferred solution, the constant current output clamping circuit comprises a fifth resistor, a fifth power transistor and a sixth power transistor, wherein the first end of the fifth resistor receives an input voltage, the second end of the fifth resistor is connected to the first end of the fifth power transistor and the first end of the sixth power transistor respectively, the second end of the fifth power transistor is connected to the control end of the sixth power transistor and the overcurrent detection circuit respectively, for receiving the overcurrent detection signal generated by the overcurrent detection circuit; the second end of the sixth power transistor is connected to the control end of the fifth power transistor and the LDO circuit respectively, for clamping the gate voltage of the power transistor in the LDO circuit.
[0007] As a preferred solution, the overcurrent detection circuit is implemented by using a current comparator circuit, and the overcurrent detection signal is generated by comparing the relationship between the current threshold and the LDO output current.
[0008] As a preferred solution, the overcurrent detection circuit comprises a third resistor, a fourth resistor, a third power transistor, a fourth power transistor, a first bias current source and a second bias current source; wherein the first end of the third resistor receives an input voltage, the second end of the third resistor is connected to the first end of the third power transistor, the second end of the third power transistor is connected to the ground through the second bias current source, and the common node of the third resistor and the third power transistor is connected to the LDO circuit; the first end of the fourth resistor receives an input voltage, the second end of the fourth resistor is connected to the first end of the fourth power transistor, and the second end of the fourth power transistor is connected to the ground through the first bias current source; the control end of the third power transistor is connected to the second end of the third power transistor and the control end of the fourth power transistor respectively.
[0009] As a preferred solution, the first bias current source and the second bias current source provide the same bias current, and the bias current is related to the current threshold.
[0010] As a preferred solution, the bias current provided by the first bias current source and the second bias current source is adjustable by a digital circuit.
[0011] As a preferred solution, the LDO circuit comprises a first power tube, a second power tube, a first resistor, a second resistor, a first capacitor, a load resistor and a comparator; a first end of the first power tube is connected to the overcurrent detection circuit, and a second end of the first power tube is connected to the ground in sequence through the first resistor and the second resistor; a first end of the second power tube receives an input voltage, and a second end of the second power tube is connected to a common node of the first power tube and the first resistor; a first end of the first capacitor is connected to the common node of the first power tube and the first resistor, and a second end of the first capacitor is connected to the ground; a first end of the load resistor is connected to the common node of the first power tube and the first resistor, and a second end of the load resistor is connected to the ground; a first input end of the comparator receives a reference voltage, a second input end of the comparator is connected to a common node of the first resistor and the second resistor, an output end of the comparator is connected to control ends of the first power tube and the second power tube, and a voltage end of the comparator receives the input voltage; and the common node connected to the first power tube and the first resistor provides an output voltage.
[0012] As a preferred solution, in the LDO circuit, the sampling ratio is adjusted by controlling the ratio of the first power tube and the second power tube, and then the power tube area and the detection power consumption are controlled.
[0013] As a preferred solution, by adjusting the resistance values of the third resistor and the fourth resistor in the overcurrent detection circuit, it is ensured that the constant current output clamping circuit can generate a stable clamping voltage for clamping the control end of the power tube in the LDO circuit.
[0014] As a preferred solution, by adjusting the fifth resistor in the constant current output clamping circuit and the corresponding pull-down circuit, the clamping voltage is adjusted, and then the current limiting value is determined.
[0015] Compared with the prior art, the beneficial effects of the above technical solutions are: 1. After triggering the overcurrent protection, the LDO will not be turned off, and the current limiting output can be realized.
[0016] 2. The current limiting circuit does not increase additional power consumption, and at the same time, the circuit area for generating delay can be saved.
[0017] 3. The current limiting threshold is determined by the bias current and the sampling ratio, and the sampling accuracy is high.
[0018] 4. The current limiting threshold can be improved and modified by adjusting the bias current. BRIEF DESCRIPTION OF DRAWINGS
[0019] Figure 1 It is a traditional overcurrent detection circuit.
[0020] Figure 2 It is an LDO overcurrent detection and current limiting circuit proposed by the embodiment of the application. DETAILED DESCRIPTION
[0021] Embodiments of the present application are described below in detail with reference to the accompanying drawings, wherein the same or similar components or components having the same or similar functions are denoted by the same or similar reference numerals throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and cannot be understood as a limitation of the present application. On the contrary, the embodiments of the present application include all changes, modifications and equivalents falling within the spirit and scope of the appended claims.
[0022] To solve the problem of the conventional over-current detection scheme, please refer to Figure 2 The embodiment of the present application proposes an LDO over-current detection and current limiting circuit, which mainly includes an LDO circuit, an over-current detection circuit and a constant current output clamping circuit. Among them, the LDO circuit is mainly used to control the output stable voltage according to the control end voltage of the power tube, which can be realized by a conventional circuit. The over-current detection circuit is mainly used to detect the output current of the LDO circuit and generate an over-current detection signal. The constant current output clamping circuit is mainly used to clamp the control end voltage of the power tube in the LDO circuit according to the over-current detection signal, thereby limiting the output current of the LDO circuit.
[0023] The over-current detection circuit proposed in this embodiment can realize high-precision OCP detection. On this basis, the constant current output clamping circuit is used to realize the current limiting of the LDO without increasing additional power consumption. At the same time, due to the introduction of the constant current output clamping circuit, after the over-current protection occurs, the LDO will not be turned off, only the gate voltage of the power tube is clamped, and after the load returns to normal, it can automatically switch to the normal state without the need for an additional over-current recovery circuit.
[0024] Specifically, please refer to Figure 2 The constant current output clamping circuit includes a fifth resistor R5, a fifth power tube M5 and a sixth power tube M6. The first end of the fifth resistor R5 receives an input voltage. The second end of the fifth resistor R5 is connected to the first end of the fifth power tube M5 and the first end of the sixth power tube M6. The second end of the fifth power tube M5 is connected to the control end of the sixth power tube M6 and the over-current detection circuit, for receiving the over-current detection signal generated by the over-current detection circuit. The second end of the sixth power tube M6 is connected to the control end of the fifth power tube M5 and the LDO circuit, for clamping the gate voltage of the power tube in the LDO circuit.
[0025] The over-current detection circuit in this embodiment is realized by a current comparator circuit, which generates an over-current detection signal by comparing the relationship between the current limiting threshold and the LDO output current. Specifically, please refer to Figure 2, the over-current detection circuit comprises a third resistor R3, a fourth resistor R4, a third power transistor M3, a fourth power transistor M4, a first bias current source and a second bias current source; wherein the first end of the third resistor R3 receives an input voltage, the second end of the third resistor R3 is connected to the first end of the third power transistor M3, the second end of the third power transistor M3 is connected to the ground GND through the second bias current source, and the common node of the third resistor R3 and the third power transistor M3 is connected to the LDO circuit; the first end of the fourth resistor R4 receives an input voltage, the second end of the fourth resistor R4 is connected to the first end of the fourth power transistor M4, and the second end of the fourth power transistor M4 is connected to the ground GND through the first bias current source; the control end of the third power transistor M3 is connected to the second end of the third power transistor M3 and the control end of the fourth power transistor M4 respectively.
[0026] It should be noted that in the over-current detection circuit, the first bias current source and the second bias current source provide the same bias current, and the size of the bias current is related to the current limit threshold. In one embodiment, the size of the bias current provided by the first bias current source and the second bias current source is supported by digital circuit tuning, so that the adjustment of the current limit threshold can be realized.
[0027] Please continue to refer to Figure 2 In the embodiment, the LDO circuit comprises a first power transistor M1, a second power transistor M2, a first resistor R1, a second resistor R2, a first capacitor Cout, a load resistor Rload and a comparator; the first end of the first power transistor M1 is connected to the over-current detection circuit, and the second end of the first power transistor M1 is connected to the ground GND through the first resistor R1 and the second resistor R2 in sequence; the first end of the second power transistor M2 receives an input voltage, and the second end of the second power transistor M2 is connected to the common node of the first power transistor M1 and the first resistor R1; the first end of the first capacitor Cout is connected to the common node of the first power transistor M1 and the first resistor R1, and the second end of the first capacitor Cout is connected to the ground GND; the first end of the load resistor Rload is connected to the common node of the first power transistor M1 and the first resistor R1, and the second end of the load resistor Rload is connected to the ground GND; the first input end of the comparator receives a reference voltage VREF, the second input end of the comparator is connected to the common node of the first resistor R1 and the second resistor R2, the output end of the comparator is connected to the control end of the first power transistor M1 and the second power transistor M2, and the voltage end of the comparator receives an input voltage; the common node connected to the first power transistor M1 and the first resistor R1 provides an output voltage.
[0028] It should be noted that in the LDO circuit, the ratio of the first power transistor M1 and the second power transistor M2 controls the sampling ratio of the LDO power transistor, and in the embodiment, the current limit threshold is determined by controlling the size ratio and bias current of the first power transistor M1 and the second power transistor M2, and the power transistor area and detection power consumption can be balanced.
[0029] In addition, in the LDO overcurrent detection and current limiting circuit, once the ratio of the bias current to the first power tube M1 and the second power tube M2 is determined, the DC operating point of the overcurrent detection circuit can be adjusted by adjusting the resistance values of the third resistor R3 and the fourth resistor R4, so that after triggering the overcurrent, the voltage clamping to the control end of the power tube in the LDO is ensured, and the fifth power tube M5 will not be turned on, that is, the common node of the fourth power tube M4 and the first bias current source will not provide an overcurrent detection signal to be pulled up, so that the constant current output clamping circuit can generate a stable clamping voltage to clamp the control end of the power tube in the LDO circuit.
[0030] Since the LDO overcurrent detection and current limiting circuit realizes current limiting output by clamping the voltage of the control end of the power tube, the sixth power tube M6 is turned on during current limiting output, and therefore the fifth resistor R5 and the corresponding pull-down current can be adjusted to determine the clamping voltage of the power tube, thereby determining the current limiting value.
[0031] It should be noted that in the embodiment, the first power tube M1, the second power tube M2, the third power tube M3, the fourth power tube M4, the fifth power tube M5 and the sixth power tube M6 are all controllable switching devices, and any suitable semiconductor switching device can be selected, such as a metal oxide semiconductor field effect transistor (MOSFET) or a bipolar junction transistor (BJT) or a junction field effect transistor (JFET).
[0032] In order to more clearly illustrate the LDO overcurrent detection and current limiting circuit proposed in the embodiment of the application, the working principle of the LDO overcurrent detection and current limiting circuit will be further described below with reference to the accompanying drawings. Figure 2 The working principle will be further described.
[0033] Among them, the third resistor R3, the fourth resistor R4, the first power tube M1, the second power tube M2, the third power tube M3, the first bias current source and the second bias current source realize the sampling and detection of the output current, and the working principle can be equivalent to: (IB+K1*Iload)*R3=IB*R4 Where K1 is the ratio of the first power tube M1 to the second power tube M2. Therefore, by setting the bias current, the ratio K1, the third resistor R3 and the fourth resistor R4, the corresponding threshold value can be determined.
[0034] When the LDO output current increases, the current flowing through the second power transistor M2 also increases, causing the third resistor R3 voltage drop to increase, the VSE voltage to drop, and the fourth power transistor M4 to increase the current flowing out. When the output current increases to the fourth power transistor M4 flowing out current is greater than the bias current IB provided by the first bias current source, the OCP_OUT point voltage will be pulled high, causing the fifth power transistor M5 to turn off and the sixth power transistor M6 to turn on. At this time, due to the limited pull-down capability (the maximum pull-down current is denoted as I_CMP) of the operational amplifier output, the power transistor control end voltage V_GATE at this time is determined by the maximum pull-down current I_CMP The voltage drop of the impedance composed of the fifth resistor R5 and the sixth power transistor M6. Since the on-state impedance of the sixth power transistor M6 is much smaller than that of the fifth resistor R5, its main voltage drop is determined by the fifth resistor R5. Therefore, after the overcurrent occurs, the power transistor control end voltage V_GATE is clamped at VDD-I_CMP*R5, where VDD is the input voltage of the circuit. When the power transistor control end voltage V_GATE is clamped, the Vgs voltage of the power transistor is fixed, and its output current capability is clamped, realizing constant current output.
[0035] The LDO overcurrent detection and current limiting circuit provided by the present application can realize non-shutdown of the LDO after overcurrent and realize current limiting output. Moreover, the constant current output clamping circuit does not increase additional power consumption, and can save circuit area for generating delay.
[0036] For those skilled in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances; the drawings in the embodiments are used to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations.
[0037] Although the embodiments of the present application have been shown and described above, it should be understood that the above embodiments are exemplary and cannot be understood as limiting the present application. Those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application.
Claims
1. An LDO overcurrent detection and current limiting circuit, characterized in that: It includes LDO circuit, overcurrent detection circuit and constant current output clamp circuit, among which, The LDO circuit is used to control the output stable voltage according to the control terminal voltage of the power tube; An overcurrent detection circuit is used to detect the output current of the LDO circuit and generate an overcurrent detection signal; The constant current output clamp circuit is used to clamp the control terminal voltage of the power tube in the LDO circuit according to the overcurrent detection signal, thereby limiting the output current of the LDO circuit.
2. The LDO overcurrent detection and current limiting circuit according to claim 1, wherein: The constant current output clamping circuit includes a fifth resistor, a fifth power tube, and a sixth power tube, wherein the first end of the fifth resistor receives an input voltage, the second end of the fifth resistor is connected to the first end of the fifth power tube and the first end of the sixth power tube, respectively, the second end of the fifth power tube is connected to the control end of the sixth power tube and the overcurrent detection circuit, respectively, for receiving an overcurrent detection signal generated by the overcurrent detection circuit; the second end of the sixth power tube is connected to the control end of the fifth power tube and the LDO circuit, respectively, for clamping the gate voltage of the power tube in the LDO circuit.
3. The LDO overcurrent detection and current limiting circuit according to claim 1 or 2, characterized in that: The overcurrent detection circuit is implemented using a current comparator circuit, and generates an overcurrent detection signal by comparing the relationship between the current limit threshold and the LDO output current.
4. The LDO overcurrent detection and current limiting circuit according to claim 3, characterized in that: The overcurrent detection circuit includes a third resistor, a fourth resistor, a third power transistor, a fourth power transistor, a first bias current source, and a second bias current source. The first end of the third resistor receives an input voltage, the second end of the third resistor is connected to the first end of the third power transistor, the second end of the third power transistor is grounded via the second bias current source, and a common node between the third resistor and the third power transistor is connected to the LDO circuit. The first end of the fourth resistor receives an input voltage, the second end of the fourth resistor is connected to the first end of the fourth power transistor, and the second end of the fourth power transistor is grounded via the first bias current source. The control end of the third power transistor is connected to the second end of the third power transistor and the control end of the fourth power transistor, respectively. The common node between the fourth power transistor and the first bias current source provides an overcurrent detection signal.
5. The LDO overcurrent detection and current limiting circuit according to claim 4, characterized in that: The first bias current source and the second bias current source provide the same bias current, and the magnitude of the bias current is related to the current limiting threshold.
6. The LDO overcurrent detection and current limiting circuit according to claim 5, characterized in that: The bias currents provided by the first bias current source and the second bias current source can be adjusted by a digital circuit.
7. The LDO overcurrent detection and current limiting circuit according to claim 1 or 2, characterized in that: The LDO circuit includes a first power tube, a second power tube, a first resistor, a second resistor, a first capacitor, a load resistor, and a comparator. The first end of the first power tube is connected to the overcurrent detection circuit, and the second end of the first power tube is connected to the ground via the first resistor and the second resistor in sequence. The first end of the second power tube receives an input voltage, and the second end of the second power tube is connected to the common node of the first power tube and the first resistor. The first end of the first capacitor is connected to the common node of the first power tube and the first resistor, and the second end is grounded. The first end of the load resistor is connected to the common node of the first power tube and the first resistor, and the second end is grounded. The first input end of the comparator receives a reference voltage, the second input end of the comparator is connected to the common node of the first resistor and the second resistor, the output end of the comparator is connected to the control ends of the first power tube and the second power tube, and the voltage end of the comparator receives the input voltage. The common node connected to the first power tube and the first resistor provides an output voltage.
8. The LDO overcurrent detection and current limiting circuit according to claim 7, characterized in that: In the LDO circuit, the sampling ratio is adjusted by controlling the ratio of the first power tube to the second power tube, thereby controlling the power tube area and the detection power consumption.
9. The LDO overcurrent detection and current limiting circuit according to claim 4, characterized in that: By adjusting the resistance values of the third resistor and the fourth resistor in the overcurrent detection circuit, it is ensured that the constant current output clamping circuit can generate a clamping voltage that stably clamps the control end of the power tube in the LDO circuit.
10. The LDO overcurrent detection and current limiting circuit according to claim 2, characterized in that: The clamping voltage is adjusted by adjusting the fifth resistor and the corresponding pull-down circuit in the constant current output clamping circuit, thereby determining the current limiting value.