Linear voltage regulator and power management system

Abstract

The invention provides a linear voltage regulator and a power supply management system. The linear voltage regulator comprises an error amplification module, a buffer module, a voltage regulation module and a power supply rejection ratio enhancement module, one input end of the error amplification module is used for receiving reference voltage; the input end of the buffer module is connected with the output end of the error amplification module and is used for outputting driving voltage; the driving end of the voltage regulation module is connected with the output end of the buffer module, the power supply end of the voltage regulation module is connected with a power supply and used for receiving input voltage output by the power supply, and the output end of the voltage regulation module is connected with the other input end of the error amplification module; the input end of the power supply rejection ratio enhancement module is connected with the output end of the buffer module, the output end of the voltage regulation module and the power supply, and the output end of the power supply rejection ratio module is connected with the buffer module. The power supply rejection ratio can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of voltage regulation, in particular to a linear voltage regulator and a power management system. BACKGROUND

[0002] Linear voltage regulators are widely used in electronic systems, which are mainly used to convert a higher input voltage into a lower stable voltage as a power rail to power various load components and circuits in the system. In high-performance systems, it is particularly important to use linear voltage regulators with high power supply rejection ratio to power sensitive components such as radio frequency amplifiers, voltage-controlled oscillators, timing integrated circuits, image sensors, etc.

[0003] The conventional linear voltage regulator couples the input voltage to the output voltage due to the inherent output resistance of the pass transistor, and when the input voltage changes, the output current and the output voltage will be disturbed accordingly, resulting in poor power supply rejection ratio of the conventional linear voltage regulator. SUMMARY

[0004] The present application provides a linear voltage regulator and a power management system, aiming to solve the problem of poor power supply rejection ratio of the current linear voltage regulator.

[0005] In a first aspect, the present application provides a linear voltage regulator, comprising an error amplification module, a buffer module, a voltage regulation module, and a power supply rejection ratio enhancement module; an input end of the error amplification module is used to receive a reference voltage; an input end of the buffer module is connected with an output end of the error amplification module, and is used to output a driving voltage; a driving end of the voltage regulation module is connected with an output end of the buffer module, a power supply end of the voltage regulation module is connected with a power supply, and is used to receive an input voltage output by the power supply, and an output end of the voltage regulation module is connected with another input end of the error amplification module; an input end of the power supply rejection ratio enhancement module is connected with the output end of the buffer module, the output end of the voltage regulation module, and the power supply respectively, and an output end of the power supply rejection ratio module is connected with the buffer module; wherein the power supply rejection ratio enhancement module is used to generate a correction signal according to the driving voltage output by the buffer module, the input voltage output by the power supply, and the output voltage output by the voltage regulation module, and output the correction signal to the buffer module to offset the influence of the input voltage on the output voltage.

[0006] Further, the power supply rejection ratio enhancement module comprises a reference current circuit, a disturbed current circuit and a filter module; an input end of the reference current circuit is connected with the power supply, the buffer module and the voltage regulation module through the filter module respectively, and an output end of the reference current circuit is connected with the buffer module; an input end of the disturbed current circuit is connected with the power supply, and the disturbed current circuit is further connected with the buffer module and the voltage regulation module through the filter module respectively, and an output end of the disturbed current circuit is connected with the buffer module.

[0007] Further, the reference current circuit comprises a first reference device and a first current sensor; a controlled electrode of the first reference device is connected with the buffer module through the filter module, a first electrode of the first reference device is connected with the power supply through the filter module, a second electrode of the first reference device is connected with an input end of the first current sensor, another input end of the first current sensor is connected with the voltage regulation module through the filter module, and an output end of the first current sensor is connected with the buffer module.

[0008] Further, the disturbed current circuit comprises a first disturbed device and a second current sensor; a controlled electrode of the first disturbed device is connected with the buffer module through the filter module, a first electrode of the first disturbed device is connected with the power supply, a second electrode of the first disturbed device is connected with an input end of the second current sensor, another input end of the second current sensor is connected with the voltage regulation module through the filter module, and an output end of the second current sensor is connected with the buffer module.

[0009] Further, the filter module comprises a first low-pass filter, a second low-pass filter and a third low-pass filter; one end of the first low-pass filter is connected with the power supply, and another end of the first low-pass filter is connected with the first electrode of the first reference device; one end of the second low-pass filter is connected with the buffer module, and another end of the second low-pass filter is connected with the controlled electrode of the first reference device and the controlled electrode of the first disturbed device respectively; one end of the third low-pass filter is connected with the voltage regulation module, and another end of the third low-pass filter is connected with the first current sensor and the second current sensor respectively.

[0010] Further, the power supply rejection ratio enhancement module comprises a second reference device, a second disturbed device, a first current replication circuit, a second current replication circuit, an amplification circuit and a first filter circuit; the controlled electrode of the second reference device is connected with the buffer module, the first electrode of the second reference device is connected with the first current replication circuit, and the second electrode of the second reference device is connected with the amplification circuit respectively; the controlled electrode of the second disturbed device is connected with the amplification circuit, the first electrode of the second disturbed device is connected with the second current replication circuit, and the second electrode of the second disturbed device is connected with the amplification circuit; the first current replication circuit and the second current replication circuit are connected with the amplification circuit and the first filter circuit respectively, the amplification circuit is connected with the first filter circuit, and the first filter circuit is further connected with the buffer module.

[0011] Further, the first current replication circuit comprises a third current sensor and a second filter circuit; the input end of the third current sensor is connected with the second reference device, the output end of the third current sensor is connected with the second filter circuit, and the second filter circuit is connected with the amplification circuit and the first filter circuit respectively.

[0012] Further, the second current replication circuit comprises a fourth current sensor, the input end of the fourth current sensor is connected with the second disturbed device, and the output end of the fourth current sensor is connected with the amplification circuit and the first filter circuit respectively.

[0013] Further, the amplification circuit comprises a first field effect transistor and a first resistor, the controlled electrode of the first field effect transistor is connected with the first current replication circuit and the second current replication circuit respectively, the first electrode of the first field effect transistor is connected with a power supply rail, the second electrode of the first field effect transistor is connected with one end of the first resistor, and the other end of the first resistor is connected with the second disturbed device, the second reference device and the voltage regulation module respectively.

[0014] In a second aspect, the present application further provides a power management system, wherein the power management system comprises the linear voltage regulator according to any one of the above.

[0015] The power management system comprises a linear voltage regulator, the linear voltage regulator comprises an error amplification module, a buffer module, a voltage regulation module and a power supply rejection ratio enhancement module, the error amplification module is used for comparing an output voltage and a reference voltage and amplifying a difference between the two to generate a control signal, the buffer module is used for isolating the error amplification module and the voltage regulation module and providing a driving voltage for the voltage regulation module, the voltage regulation module is used for adjusting a voltage drop from an input voltage to an output voltage to realize voltage stabilization, and the power supply rejection ratio enhancement module is used for generating a correction signal according to the driving voltage, the input voltage and the output voltage, to offset the influence of the input voltage on the output voltage to improve the power supply rejection ratio. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0017] Figure 1 is a block schematic diagram of the linear voltage regulator provided by an embodiment of the present application;

[0018] Figure 2 is a circuit diagram of the linear voltage regulator provided by an embodiment of the present application;

[0019] Figure 3 is a block schematic diagram of the power supply rejection ratio enhancement module provided by an embodiment of the present application;

[0020] Figure 4 is a circuit diagram of the power supply rejection ratio enhancement module provided by an embodiment of the present application;

[0021] Figure 5 is a block schematic diagram of the power supply rejection ratio enhancement module provided by another embodiment of the present application;

[0022] Figure 6 is a circuit diagram of the power supply rejection ratio enhancement module provided by another embodiment of the present application. DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0024] It should be understood that the terms "comprises" and "comprising," when used in this specification and accompanying claims, indicate the presence of the described features, integers, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, operations, elements, components, and / or groups thereof.

[0025] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in this specification and the appended claims, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, operations, elements, components, and / or groups thereof.

[0026] In addition, directional terms as used in this disclosure, such as "upper," "lower," "front," "back," "left," "right," "inner," "outer," "lateral," and the like, are made only with reference to the positions of the components as shown in the attached drawings and as understood by a person of ordinary skill in the art, and are not intended to be limiting of the present application. Furthermore, like reference numerals are intended to refer to like and / or similar elements throughout this disclosure.

[0027] Referring to Figures 1 to 6 , Figure 1 is a block diagram of a linear voltage regulator 100 according to an embodiment of the present application; Figure 2 is a circuit diagram of the linear voltage regulator 100 according to an embodiment of the present application; Figure 3 is a block diagram of a power supply rejection ratio enhancement module 40 according to an embodiment of the present application; Figure 4 is a circuit diagram of the power supply rejection ratio enhancement module 40 according to an embodiment of the present application; Figure 5 is a block diagram of a power supply rejection ratio enhancement module 40 according to another embodiment of the present application; Figure 6 is a circuit diagram of the power supply rejection ratio enhancement module 40 according to another embodiment of the present application. As Figure 1As shown, the linear voltage regulator 100 includes an error amplification module 10, a buffer module 20, a voltage regulation module 30 and a power supply rejection ratio enhancement module 40; an input end of the error amplification module 10 is used to receive a reference voltage; the input end of the buffer module 20 is connected to the output end of the error amplification module 10 for outputting a driving voltage; the driving end of the voltage regulation module 30 is connected to the output end of the buffer module 20, the power supply end of the voltage regulation module 30 is connected to the power supply 200 for receiving the input voltage output by the power supply 200, and the output end of the voltage regulation module 30 is connected to the error amplification module 10 for outputting a driving voltage; The other input end of the amplification module 10 is connected; the input end of the power supply rejection ratio enhancement module 40 is respectively connected to the output end of the buffer module 20, the output end of the voltage regulation module 30 and the power supply 200, and the output end of the power supply rejection ratio module is connected to the buffer module 20; wherein, the power supply rejection ratio enhancement module 40 is used to generate a correction signal according to the driving voltage output by the buffer module 20, the input voltage output by the power supply 200 and the output voltage output by the voltage regulation module 30, and output the correction signal to the buffer module 20 to offset the influence of the input voltage on the output voltage.

[0028] Specifically, the linear voltage regulator 100 may include an error amplification module 10, a buffer module 20, a voltage regulation module 30, and a power supply rejection ratio enhancement module 40. The error amplification module 10 may include two input terminals, one of which is connected to a reference terminal for receiving a reference voltage, and the other is connected to the voltage regulation module 30 for receiving an output voltage, comparing the reference voltage with the output voltage, and then amplifying the difference between the two to generate a control signal. Furthermore, the error amplification module 10 may provide gain for the feedback system to ensure that the output voltage is stable at a target value.

[0029] The input end of the buffer module 20 is connected to the output end of the error amplification module 10, and its output end is respectively connected to the voltage regulation module 30 and the power supply rejection ratio enhancement module 40. It is used to isolate the error amplification module 10 from the voltage regulation module 30 to prevent load changes from affecting the stability of the error amplification module 10. At the same time, it is also used to provide a driving signal.

[0030] The driving end of the voltage regulation module 30 is connected to the output end of the buffer module 20, its power supply end is connected to the power supply 200, and its output end is respectively connected to the error amplification module 10 and the power supply rejection ratio enhancement module 40, and is used to adjust the voltage drop between the input voltage and the output voltage to achieve the voltage stabilization function.

[0031] like Figure 2 As shown, the error amplification module 10 may include an error amplifier EA, and the buffer module 20 may include a buffer BUF. Figure 2A circuit diagram of the linear voltage regulator 100 provided by the embodiment of the present application is shown in FIG. 1. Figure 2 The EA is an error amplifier, the BUF is a buffer, the Mp is a field effect transistor, and the PSRR boost is a power supply rejection ratio enhancement module 40. Figure 2 As can be seen, the reference signal Vref is input to the positive electrode of the error amplifier EA, the feedback signal Vfb is input to the negative electrode of the error amplifier, the error amplifier generates a control signal according to the reference signal Vref and the feedback signal Vfb and outputs the control signal to the buffer, the buffer outputs a driving signal Vg, which is output to the gate of the field effect transistor on one hand and to the power supply rejection ratio enhancement module 40 on the other hand. The input voltage Vin is input to the drain of the field effect transistor and to the power supply rejection ratio enhancement module 40, and the output voltage of the source of the field effect transistor is output to the power supply rejection ratio enhancement module 40 on one hand and forms a feedback voltage after passing through the feedback network composed of the resistor R1 and the resistor R2, which is output to the negative electrode of the error amplifier, forming a negative feedback. The power supply rejection ratio enhancement module 40 generates a correction signal corr according to the input signal Vin, the driving signal Vg and the output signal Vout, which is input to the buffer to offset the disturbance of the input signal, thereby enhancing the power supply rejection ratio, wherein the correction signal corr can be in the form of voltage or current.

[0032] The power supply rejection ratio enhancement module 40 provided by the present application specifically includes two different embodiments, which will be described below.

[0033] Embodiment one: referring to FIG. 2, Figure 3 As a further embodiment, the power supply rejection ratio enhancement module 40 includes a reference current circuit 41, a disturbed current circuit 42 and a filter module 43; the input end of the reference current circuit 41 is connected with the power supply 200, the buffer module 20 and the voltage regulation module 30 through the filter module 43, and the output end of the reference current circuit 41 is connected with the buffer module 20; the input end of the disturbed current circuit 42 is connected with the power supply 200, and the disturbed current circuit 42 is also connected with the buffer module 20 and the voltage regulation module 30 through the filter module 43, and the output end of the disturbed current circuit 42 is connected with the buffer module 20.

[0034] The power supply rejection ratio enhancement module 40 can include a reference current circuit 41, a disturbed current circuit 42, and a filter module 43. The input end of the reference current circuit 41 is connected to the power supply 200, the buffer module 20, and the voltage regulation module 30 through the filter circuit, respectively, for receiving the input signal, the output signal, and the driving signal after filtering out the high-frequency part by the filter module 43 as an interference-free reference to form a reference current. The disturbed current circuit 42 is directly connected to the power supply 200 for receiving the input voltage after filtering out the interference by the filter module 43 to form an interference current. The current difference between the reference current and the interference current is converted into a voltage signal, i.e., a correction signal, which is input to the buffer module 20 for offsetting the disturbance of the input signal.

[0035] Referring to Figure 4As a further embodiment, the reference current circuit 41 comprises a first reference device Mr2 and a first current sensor CS1; the controlled electrode of the first reference device Mr2 is connected with the buffer module 20 through the filter module 43, the first electrode of the first reference device Mr2 is connected with the power supply 200 through the filter module 43, the second electrode of the first reference device Mr2 is connected with an input terminal of the first current sensor CS1, another input terminal of the first current sensor CS1 is connected with the voltage regulation module 30 through the filter module 43, and the output terminal of the first current sensor CS1 is connected with the buffer module 20. As a further embodiment, the disturbed current circuit 42 comprises a first disturbed device Mr1 and a second current sensor CS2; the controlled electrode of the first disturbed device Mr1 is connected with the buffer module 20 through the filter module 43, the first electrode of the first disturbed device Mr1 is connected with the power supply 200, the second electrode of the first disturbed device Mr1 is connected with an input terminal of the second current sensor CS2, another input terminal of the second current sensor CS2 is connected with the voltage regulation module 30 through the filter module 43, and the output terminal of the second current sensor CS2 is connected with the buffer module 20. As a further embodiment, the filter module 43 comprises a first low-pass filter LPF1, a second low-pass filter LPF2 and a third low-pass filter LPF3; one end of the first low-pass filter LPF1 is connected with the power supply 200, and the other end of the first low-pass filter LPF1 is connected with the first electrode of the first reference device Mr2; one end of the second low-pass filter LPF2 is connected with the buffer module 20, and the other end of the second low-pass filter LPF2 is connected with the controlled electrode of the first reference device Mr2 and the controlled electrode of the first disturbed device Mr1 respectively; one end of the third low-pass filter LPF3 is connected with the voltage regulation module 30, and the other end of the third low-pass filter LPF3 is connected with the first current sensor CS1 and the second current sensor CS2 respectively.

[0036] The first reference device Mr2 and the first disturbed device Mr1 are both copied devices of the field effect tube Mp, and each can be a field effect tube. The gate of the first reference device Mr2 and the gate of the first disturbed device Mr1 are connected with the buffer BUF through the second low-pass filter LPF2, the drain of the first reference device Mr2 is connected with the power supply 200 through the first low-pass filter LPF1, the source of the first reference device Mr2 is connected with the first current sensor CS1, the drain of the first disturbed device Mr1 is connected with the power supply 200, and the source of the first disturbed device Mr1 is connected with the second current sensor CS2. Through the above setting, the gate, the drain and the source of the field effect tube Mp are input to the first reference device Mr2 after being filtered by the filter, the first current sensor CS1 collects the current to obtain the reference current iref_pb, and the drain of the first disturbed device Mr1 is directly connected with the power supply 200, and the second current sensor CS2 collects the current containing the interference to obtain the interference current ir1. The difference between the reference current iref_pb and the interference current ir1 drives the first disturbed device Mr1 through the resistance RC, forms a negative feedback loop, makes the interference current ir1 equal to the reference current iref_pb, and generates the correction signal corr_v in the process. The correction signal corr_v is input to the buffer, and when the correction signal corr_v is subtracted from the output of the buffer, the interference of the input signal can be offset.

[0037] Embodiment two: refer to Figure 5 As a further embodiment, the power supply rejection ratio enhancement module 40 comprises a second reference device Mr3, a second disturbed device Mr4, a first current replication circuit 44, a second current replication circuit 45, an amplification circuit 46 and a first filter circuit 47; the controlled electrode of the second reference device Mr3 is connected with the buffer module 20, the first electrode of the second reference device Mr3 is connected with the first current replication circuit 44, and the second electrode of the second reference device Mr3 is connected with the amplification circuit 46 respectively; the controlled electrode of the second disturbed device Mr4 is connected with the amplification circuit 46, the first electrode of the second disturbed device Mr4 is connected with the second current replication circuit 45, and the second electrode of the second disturbed device Mr4 is connected with the amplification circuit 46; the first current replication circuit 44 and the second current replication circuit 45 are connected with the amplification circuit 46 and the first filter circuit 47 respectively, the amplification circuit 46 is connected with the first filter circuit 47, and the first filter circuit 47 is further connected with the buffer module 20.

[0038] The power supply rejection ratio enhancement module 40 can include a second reference device Mr3, a second disturbed device Mr4, a first current replication circuit 44, a second current replication circuit 45, an amplification circuit 46, and a first filter circuit 47. The second reference device Mr3 is connected to the first current replication circuit 44, so that the first current replication circuit 44 replicates the current of the second reference device Mr3 to form an undisturbed reference current. The second disturbed device Mr4 is connected to the second current replication circuit 45, so that the second current replication circuit 45 replicates the current of the second disturbed device Mr4 to form a disturbed current. The reference current and the disturbed current are combined before the amplification circuit 46 to form an interference current, which is amplified by the amplification circuit 46 and then fed back to the gate of the second disturbed device Mr4 to balance the current difference. At the same time, the first filter circuit 47 filters out the direct current component to generate a correction signal containing only alternating current components, which is then input to the buffer to offset the disturbance of the input voltage.

[0039] Referring to Figure 6 As a further embodiment, the first current replication circuit 44 includes a third current sensor and a second filter circuit. The input end of the third current sensor is connected to the second reference device Mr3, and the output end of the third current sensor is connected to the second filter circuit. The second filter circuit is connected to the amplification circuit 46 and the first filter circuit 47, respectively. As a further embodiment, the second current replication circuit 45 includes a fourth current sensor. The input end of the fourth current sensor is connected to the second disturbed device Mr4, and the output end of the fourth current sensor is connected to the amplification circuit 46 and the first filter circuit 47, respectively. As a further embodiment, the amplification circuit 46 includes a first field effect transistor and a first resistor. The controlled electrode of the first field effect transistor is connected to the first current replication circuit 44 and the second current replication circuit 45, respectively. The first electrode of the first field effect transistor is connected to the power supply rail. The second electrode of the first field effect transistor is connected to one end of the first resistor. The other end of the first resistor is connected to the second disturbed device Mr4, the second reference device Mr3, and the voltage regulation module 30.

[0040] As shown in Figure 6As shown, Vcp is the power rail for powering the power supply rejection ratio enhancement module 40. The third current sensor is composed of seven field effect transistors, M1-M7, which replicate the current of the second reference device Mr3. The second filter circuit includes a resistor Rf1 and a capacitor Cf1, which form a low pass filter to generate an undisturbed reference current iref_pb. The fourth current sensor is composed of five field effect transistors, M8-M12, which replicate the current of the second disturbed device Mr4 to generate a disturbed current ir1. The reference current iref_pb and the disturbed current ir1 are subtracted in Figure 6 The resulting disturbance current is amplified by the amplifier circuit 46, which includes a first resistor Zc1 and a first field effect transistor M13, to feed back the disturbance current output to drive the second disturbed device Mr4, so as to force the disturbed current of the second disturbed device Mr4 to follow the reference current. The first filter circuit 47 includes field effect transistors M14-M17, a resistor Rf2 and a capacitor Cf2, which form a filter to filter out the corresponding DC component and generate a current correction signal corr_i containing only AC component. In addition, the difference between the buffer in Figure 4 The difference between the buffer in Figure 6 The buffer in is designed as a super source follower (MS1-MS2 and I1-I2), with a matching impedance Zc2 added as the injection point of the correction signal. The correction signal corr_i flows through the impedance Zc2 to offset the effect of the input voltage disturbance.

[0041] The application further provides a power management system, which comprises the linear voltage regulator 100 in any of the above embodiments, the linear voltage regulator 100 comprising an error amplification module 10, a buffer module 20, a voltage regulation module 30 and a power supply rejection ratio enhancement module 40; an input end of the error amplification module 10 is used for receiving a reference voltage; an input end of the buffer module 20 is connected with an output end of the error amplification module 10, and is used for outputting a driving voltage; a driving end of the voltage regulation module 30 is connected with an output end of the buffer module 20, a power supply end of the voltage regulation module 30 is connected with a power supply 200, and is used for receiving an input voltage output by the power supply 200, and an output end of the voltage regulation module 30 is connected with another input end of the error amplification module 10; input ends of the power supply rejection ratio enhancement module 40 are respectively connected with the output end of the buffer module 20, the output end of the voltage regulation module 30 and the power supply 200, and an output end of the power supply rejection ratio module is connected with the buffer module 20; wherein the power supply rejection ratio enhancement module 40 is used for generating a correction signal according to the driving voltage output by the buffer module 20, the input voltage output by the power supply 200 and the output voltage output by the voltage regulation module 30, and outputting the correction signal to the buffer module 20 to offset the influence of the input voltage on the output voltage.

[0042] Specifically, the linear voltage regulator 100 can comprise the error amplification module 10, the buffer module 20, the voltage regulation module 30 and the power supply rejection ratio enhancement module 40. The error amplification module 10 can comprise two input ends, one input end is connected with a reference end and is used for receiving a reference voltage, and the other input end is connected with the voltage regulation module 30 and is used for receiving an output voltage, and then the reference voltage and the output voltage are compared, and then the difference between the two is amplified to generate a control signal, and at the same time, the gain for the feedback system is provided to ensure that the output voltage is stable at the target value.

[0043] The input end of the buffer module 20 is connected with the output end of the error amplification module 10, and the output end thereof is connected with the voltage regulation module 30 and the power supply rejection ratio enhancement module 40 respectively, which is used for isolating the error amplification module 10 and the voltage regulation module 30 to avoid the influence of load change on the stability of the error amplification module 10, and at the same time, is used for providing a driving signal.

[0044] The driving end of the voltage regulation module 30 is connected with the output end of the buffer module 20, the power supply end thereof is connected with the power supply 200, and the output end thereof is connected with the error amplification module 10 and the power supply rejection ratio enhancement module 40 respectively, which is used for regulating the voltage drop between the input voltage and the output voltage to realize the voltage stabilization function.

[0045] As Figure 2As shown, the error amplification module 10 can include an error amplifier EA, and the buffer module 20 can include a buffer BUF, Figure 2 A circuit diagram of the linear voltage regulator 100 provided by the embodiment of the present application is shown in FIG. 2, Figure 2 EA is an error amplifier, BUF is a buffer, Mp is a field effect transistor, and PSRR boost is a power supply rejection ratio enhancement module 40. Figure 2 As shown, the reference signal Vref is input to the positive electrode of the error amplifier EA, the feedback signal Vfb is input to the negative electrode of the error amplifier, the error amplifier generates a control signal according to the reference signal Vref and the feedback signal Vfb and outputs the control signal to the buffer, the buffer outputs a driving signal Vg, which is output to the gate of the field effect transistor on one hand and to the power supply rejection ratio enhancement module 40 on the other hand. The input voltage Vin is input to the drain of the field effect transistor and to the power supply rejection ratio enhancement module 40, and the output voltage of the source of the field effect transistor is output to the power supply rejection ratio enhancement module 40 on one hand and to the feedback network composed of the resistor R1 and the resistor R2 to form a feedback voltage on the other hand, which is output to the negative electrode of the error amplifier to form a negative feedback. The power supply rejection ratio enhancement module 40 generates a correction signal corr according to the input signal Vin, the driving signal Vg and the output signal Vout, which is input to the buffer to offset the disturbance of the input signal, thereby enhancing the power supply rejection ratio, wherein the correction signal corr can be in the form of voltage or current.

[0046] The linear voltage regulator and the power management system disclosed by the present application can generate a correction signal according to the input signal, the output signal and the driving signal, and eliminate the disturbance of the input voltage to the output voltage through the correction signal, thereby improving the power supply rejection ratio.

[0047] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of various equivalent modifications or replacements within the technical range disclosed by the present application, and these modifications or replacements should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A linear voltage regulator, characterized in that: include: an error amplification module, wherein an input terminal of the error amplification module is used to receive a reference voltage; a buffer module, wherein an input end of the buffer module is connected to an output end of the error amplification module and is used to output a driving voltage; a voltage regulating module, wherein a driving end of the voltage regulating module is connected to the output end of the buffer module, a power supply end of the voltage regulating module is connected to a power supply and is configured to receive an input voltage output by the power supply, and an output end of the voltage regulating module is connected to another input end of the error amplification module; a power supply rejection ratio enhancement module, wherein the input end of the power supply rejection ratio enhancement module is respectively connected to the output end of the buffer module, the output end of the voltage regulation module and the power supply, and the output end of the power supply rejection ratio module is connected to the buffer module; Among them, the power supply rejection ratio enhancement module is used to generate a correction signal according to the driving voltage output by the buffer module, the input voltage output by the power supply and the output voltage output by the voltage regulation module, and output the correction signal to the buffer module to offset the influence of the input voltage on the output voltage.

2. The linear voltage regulator according to claim 1, wherein The power supply rejection ratio enhancement module includes a reference current circuit, a disturbed current circuit and a filtering module; The input end of the reference current circuit is connected to the power supply, the buffer module and the voltage regulation module respectively through the filter module, and the output end of the reference current circuit is connected to the buffer module; The input end of the disturbed current circuit is connected to the power supply, and the disturbed current circuit is also connected to the buffer module and the voltage regulation module respectively through the filter module, and the output end of the disturbed current circuit is connected to the buffer module.

3. The linear voltage regulator according to claim 2, wherein: The reference current circuit includes a first reference device and a first current sensor; The controlled pole of the first reference device is connected to the buffer module through the filtering module, the first pole of the first reference device is connected to the power supply through the filtering module, the second pole of the first reference device is connected to an input end of the first current sensor, the other input end of the first current sensor is connected to the voltage regulation module through the filtering module, and the output end of the first current sensor is connected to the buffer module.

4. The linear voltage regulator according to claim 3, wherein: The disturbed current circuit includes a first disturbed device and a second current sensor; The controlled pole of the first victim device is connected to the buffer module through the filtering module, the first pole of the first victim device is connected to the power supply, the second pole of the first victim device is connected to an input end of the second current sensor, the other input end of the second current sensor is connected to the voltage regulation module through the filtering module, and the output end of the second current sensor is connected to the buffer module.

5. The linear voltage regulator according to claim 4, wherein: The filtering module includes a first low-pass filter, a second low-pass filter and a third low-pass filter; One end of the first low-pass filter is connected to the power supply, and the other end of the first low-pass filter is connected to the first pole of the first reference device; One end of the second low-pass filter is connected to the buffer module, and the other end of the second low-pass filter is respectively connected to the controlled pole of the first reference device and the controlled pole of the first victim device; One end of the third low-pass filter is connected to the voltage regulation module, and the other end of the third low-pass filter is connected to the first current sensor and the second current sensor respectively.

6. The linear voltage regulator according to claim 1, wherein: The power supply rejection ratio enhancement module includes a second reference device, a second disturbed device, a first current replication circuit, a second current replication circuit, an amplifier circuit and a first filtering circuit; The controlled electrode of the second reference device is connected to the buffer module, the first electrode of the second reference device is connected to the first current replication circuit, and the second electrodes of the second reference device are respectively connected to the amplification circuits; The controlled electrode of the second victim device is connected to the amplifying circuit, the first electrode of the second victim device is connected to the second current replicating circuit, and the second electrode of the second victim device is connected to the amplifying circuit; The first current replication circuit and the second current replication circuit are respectively connected to the amplifier circuit and the first filter circuit. The amplifier circuit is connected to the first filter circuit, and the first filter circuit is also connected to the buffer module.

7. The linear voltage regulator according to claim 6, wherein: The first current replication circuit includes a third current sensor and a second filtering circuit; An input end of the third current sensor is connected to the second reference device, an output end of the third current sensor is connected to the second filter circuit, and the second filter circuit is connected to the amplifying circuit and the first filter circuit respectively.

8. The linear voltage regulator according to claim 6, wherein: The second current replication circuit includes a fourth current sensor, an input end of the fourth current sensor is connected to the second victim device, and an output end of the fourth current sensor is connected to the amplification circuit and the first filtering circuit respectively.

9. The linear voltage regulator according to claim 6, wherein: The amplification circuit includes a first field-effect transistor and a first resistor, the controlled electrode of the first field-effect transistor is respectively connected to the first current replication circuit and the second current replication circuit, the first electrode of the first field-effect transistor is connected to the power rail, the second electrode of the first field-effect transistor is connected to one end of the first resistor, and the other end of the first resistor is respectively connected to the second disturbed device, the second reference device and the voltage regulation module.

10. A power management system, characterized in that: The device comprises a linear voltage regulator as claimed in any one of claims 1 to 9.

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