Loading method for peripheral settings of processor and server system

Abstract

The invention discloses a method for loading peripheral settings of a processor and a server system, and relates to the technical field of servers, the method comprises the following steps: reading a base address of a bidirectional two-wire system serial bus, writing memory read-write capability enabling and transmission configuration enabling into a preset offset address space of a corresponding base address, and then, loading the peripheral settings of the processor into a preset offset address space of the corresponding base address; and reading data of a specific address from the memory by using a multi-byte reading mode of a bidirectional two-wire system serial bus protocol, verifying the read data, updating mainboard variable information when verification succeeds, comparing the model of a processor actually installed on the server with the model of the processor read from the memory, and if the models are matched, updating the mainboard variable information. If not, the processor is correct, and the server correctly loads and configures the peripheral settings of the processor according to the specified processor model in the memory, so that the problem that some mainboard functions cannot be normally used due to the fact that wrong configuration is executed when the server is started due to the fact that the processor models are not matched is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of servers, and in particular to a loading method of peripheral device settings of a processor and a server system. BACKGROUND

[0002] The mainboard of the prior art does not perform EEPROM (Electrically Erasable Programmable Read-Only Memory, a special type of non-volatile memory, the main feature of which is that it can be erased and reprogrammed through electrical signals within the operating voltage range) security verification at startup, so that the CPU (Central Processing Unit, a main hardware of a computer) model does not match during startup, which easily leads to the server system executing incorrect configurations at startup, and further easily causes part of the mainboard functions to be unable to be normally used or the mainboard to be damaged, thereby affecting the normal use of the subsequent mainboard.

[0003] That is, the prior art cannot avoid the situation that the server executes incorrect configurations at startup due to the CPU model mismatch, which causes part of the mainboard functions to be unable to be normally used. SUMMARY

[0004] The present application provides a loading method of peripheral device settings of a processor and a server system to at least solve the problem of how to avoid the situation that the server executes incorrect configurations at startup due to the processor model mismatch, which causes part of the mainboard functions to be unable to be normally used.

[0005] The present application provides a loading method of peripheral device settings of a processor, which comprises the following steps: storing a mainboard mapping relationship into a memory based on a bidirectional two-wire serial bus protocol, the mainboard mapping relationship being a mapping relationship of a mainboard model, a mainboard type, and each processor model supported by the mainboard type; in the case that a server system is started, assigning a mainboard variable information to an undefined type, the mainboard variable information comprising a current mainboard model, a current mainboard type, and a current processor model; reading a peripheral parallel bus base address of the bidirectional two-wire serial bus, and writing memory read-write capability and transmission configuration capability into a space with a sum of the peripheral parallel bus base address and a preset offset address; reading address data to be verified from the memory based on a multi-byte reading mode of the bidirectional two-wire serial bus protocol, and performing verification and processing on the address data to be verified; and based on a first verification result, performing a crash processing, or updating the mainboard variable information according to the mainboard mapping relationship, and determining whether to load peripheral device settings of the current processor according to the updated mainboard variable information and an actual processor model.

[0006] The application further provides a server system, comprising a mainboard controller, a processor and a memory, the mainboard controller and the processor communicate with each other, the processor and the memory are electrically connected through a bidirectional two-wire serial bus, and the mainboard controller is used for executing the loading method of the peripheral setting of the processor.

[0007] Through the application, the base address of the bidirectional two-wire serial bus is read, the memory read-write capability is enabled and the transmission configuration is written into the preset offset address space of the corresponding base address, then the data of a specific address is read from the memory by using the multi-byte reading mode of the bidirectional two-wire serial bus protocol, the read data is verified, the mainboard variable information is updated when the verification is successful, the processor model actually installed on the server is compared with the processor model read from the memory, if they match, it is proved that the processor is correct, the server will correctly load and configure the peripheral setting of the processor according to the processor model specified in the memory, thereby solving the problem that the server executes incorrect configuration when starting due to the mismatch of the processor model, and the problem that part of the mainboard functions cannot be normally used. BRIEF DESCRIPTION OF DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0009] Figure 1 A flowchart of a loading method of a peripheral setting of a processor provided by the embodiments of the application;

[0010] Figure 2 A flowchart of another loading method of a peripheral setting of a processor provided by the embodiments of the application;

[0011] Figure 3 A structure block diagram of a mainboard controller provided by the embodiments of the application;

[0012] Figure 4 A structure diagram of a server system provided by the embodiments of the application.

[0013] Among them, the above drawings include the following reference signs:

[0014] 100, mainboard controller; 200, processor; 300, memory. DETAILED DESCRIPTION

[0015] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0016] It should be noted that, in the description of the present application, the terms "comprising", "containing" or any other variants thereof are intended to cover non-exclusive containing, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms "first", "second" and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0017] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0018] The embodiments of the present application provide a loading method of peripheral device settings of a processor, as shown in the method, the method comprises the following steps: Figure 1 As shown in the method, the method comprises the following steps:

[0019] In step S101, the motherboard mapping relationship is stored into the memory based on the bidirectional two-wire serial bus protocol, and the motherboard mapping relationship is the mapping relationship of the motherboard model, the motherboard type and the corresponding supported processor model;

[0020] BIOS, the full name of Basic Input Output System, is a set of programs running when the server starts, which is usually fixed in a read-only memory (ROM) chip on the computer motherboard.

[0021] In step S102, the motherboard variable information is assigned as an undefined type in the case of server system startup, and the motherboard variable information includes the current motherboard model, the current motherboard type and the current processor model;

[0022] The current motherboard model refers to the specific model of the motherboard of the server; the current motherboard type refers to the category or form factor of the motherboard, and each motherboard type includes a plurality of motherboard models; and the current processor model refers to the specific model of the central processing unit of the server.

[0023] In step S103, the peripheral parallel bus base address of the bidirectional two-wire serial bus is read, and the memory read-write capability enable and the transmission configuration enable are written into the space of the sum of the peripheral parallel bus base address and the preset offset address;

[0024] The preset offset address can be 0x20.

[0025] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard.

[0026] When referring to reading the PCI (Peripheral Component Interconnect, also known as Peripheral Parallel Bus, which is a standard bus architecture for fixed computer internal components) base address space of the I2C bus (Inter-Integrated Circuit is a two-wire serial bus used for data transmission between microcontrollers and passive elements) through BUS number, DEV number, and FUN number, the specific meanings are as follows:

[0027] BUS number: refers to the number of the PCI bus, there may be multiple PCI buses in the server, each bus has its own independent number, and the BUS number is used to identify the target PCI bus.

[0028] DEV number (Device number): on a specified PCI bus (BUS), each slot or device also has its own independent number, called Device number. There can be multiple devices on a PCI bus, usually numbered from 0.

[0029] FUN number (Function number): in a PCI device, there may be multiple functions (or multiple logical devices) supported by a physical device, for example, a PCIe network card may support both network function and management function, and each function also has its own independent number, called Function number. Generally, the basic function number of the device is 0.

[0030] Through the BUS number, DEV number, and FUN number, a device in the PCI configuration space can be uniquely located. The configuration space contains various configuration information of the device, including the Base Address Register (BAR) location of its I2C controller. Reading the PCI base address of the I2C bus is to read the BAR of the I2C controller of the corresponding PCI device, thereby determining the starting address of the I2C controller in the memory mapping. This address is the interface for the CPU to communicate with the I2C controller, through which the CPU can control the read and write operations of the I2C bus.

[0031] Enabling I2C memory read capability means that the I2C device can be accessed directly through memory mapping, rather than just through I / O ports. This can improve the efficiency of data transfer, as memory access is usually faster than I / O access, and under certain architectures, memory access can use cache, further speeding up the read-write process. Enabling the host function of the I2C bus (i.e. the function of transmission configuration) means that the CPU or master controller can actively control the communication on the I2C bus, rather than just passively responding. This enables the host to more flexibly manage the slave device, such as performing fast read-write operations, configuring slave device parameters, or performing bus fault detection and management.

[0032] In step S104, the address data to be verified is read from the memory based on the multi-byte read mode of the bidirectional two-wire serial bus protocol, and the address data to be verified is verified and processed. Based on the first checksum result, a crash handling is performed, or the motherboard variable information is updated according to the motherboard mapping relationship, and whether to load the peripheral settings of the current processor is determined according to the updated motherboard variable information and the actual processor model.

[0033] Checksum is a method for detecting errors in data transmission or storage. It works by performing some mathematical operation (usually summation) on the data, and then attaching the result of the calculation to the data after transmission or storage. The receiving party or the party reading the data will apply the same mathematical operation to the original data again, and compare the result with the received checksum. If they match, the data is considered to have not changed during transmission or storage; if they do not match, it means that the data may have been damaged or tampered with.

[0034] In the above steps, the motherboard model, motherboard type and the mapping relationship of the corresponding supported processor model are stored in the memory (such as EEPROM) of the server using the bidirectional two-wire serial bus (i.e. I2C bus) protocol. This means that each motherboard will record the list of CPU models that it can perfectly match and run, thereby establishing the relevance between the motherboard and the CPU. When the server system starts to start, the BIOS will set the motherboard model, motherboard type, processor model and other key variable information as "undefined type", which means that before formally reading the memory information, the server has no knowledge of the characteristics of its own motherboard. Next, the BIOS reads the base address of the I2C bus and activates the function of the I2C bus by writing the memory read-write capability and transmission configuration enable to the preset offset address space of the corresponding base address. Subsequently, the data at a specific address is read from the memory using the multi-byte read mode of the I2C protocol, and these data contain the mapping relationship information of the motherboard. The BIOS will verify the read data, and if the verification fails (for example, the checksum verification fails), it means that the data in the memory may have been tampered with or damaged, and the server will directly execute a downtime process to prevent potential security risks. If the verification is successful, the BIOS will parse the data and update the motherboard variable information to reflect the correct motherboard model, type and processor model information. Most importantly, the BIOS will also read the actual installed processor model on the server and compare it with the processor model read from the memory. If the two do not match, it means that the current motherboard and CPU (current processor) do not match, and the server will continue to execute a downtime process to avoid incorrect peripheral configuration; if they match, it means that the CPU is correct, and the server will correctly load and configure the peripheral settings of the CPU according to the processor model specified in the EEPROM, such as PCI Lane quantity (Peripheral Component Interconnect lane refers to the number of data transmission channels in the PCI Express interface), USB port (Universal Serial Bus port is a standard interface on a computer system, used to connect external devices such as keyboards, mice, printers, external hard drives, USB flash drives, mobile phones and other electronic devices), network port, etc., thereby ensuring that all functions can operate normally and avoiding the loss or abnormality of functions caused by the incompatibility of the CPU and the motherboard, thereby solving the problem of how to avoid the problem of the server executing incorrect configuration when starting due to the mismatch of the processor model, causing part of the motherboard functions to be unable to be used normally.

[0035] The application can confirm the actual settings of peripherals of the mainboard by reading the information of the EEPROM, and needs to be consistent with the peripherals supported by the CPU. If the EEPROM is artificially damaged or the type of the installed CPU is inconsistent with the CPU supported by the mainboard, the system will be down, ensuring the safety, reliability and stability of the CPU and the mainboard, avoiding the technical problem that the incorrect installation of the CPU causes some interfaces of the mainboard to be unavailable, ensuring the consistency of the peripheral information of the mainboard and the CPU, improving the use efficiency of the mainboard, and having outstanding beneficial effects and obvious technical advantages.

[0036] In an embodiment of the application, based on the first checksum result, a down processing is performed, or the mainboard variable information is updated according to the mainboard mapping relationship, including: pre-processing the first checksum result to obtain a first sum value, wherein the pre-processing includes: taking the first checksum result as a remainder to obtain a first remainder, and determining the first sum value as the sum of the first remainder and the last byte data of the address data to be checked; in the case that the first sum value is 0, the down processing is performed; in the case that the first sum value is not 0, byte data at a preset offset address of the address of the storage is read, and checksum processing is performed on the byte data to obtain a second checksum result, and based on the second checksum result, the down processing is performed, or the mainboard variable information is updated according to the mainboard mapping relationship.

[0037] The application also provides a specific use scenario for performing a down processing, or updating mainboard variable information according to a mainboard mapping relationship: in a data center environment, operation and maintenance personnel need to regularly maintain and upgrade the server, including updating the BIOS and the CPU. In this process, misoperation or insufficient compatibility check may cause incompatible CPUs to be installed on the server mainboard, or the BIOS image to be incorrectly written to the unsupported mainboard. For example, a B type CPU is mistakenly installed on a server mainboard supporting an A type CPU, and the number of PCI lanes, USB interfaces, etc. of the B type CPU are significantly different from those of the A type. In this case, if the server continues to start, there may be instability, peripheral compatibility problems, and even the risk of data loss.

[0038] Preprocessing and verification logic: When reading the data in the EEPROM for verification, the first sum is obtained by calculating the checksum and preprocessing, which includes the remainder calculation of the first checksum result, and then the sum calculation of the obtained remainder and the last byte. Such preprocessing can ensure the integrity of the data, so that even in the case of slight interference, the system can be shut down in time to prevent system abnormalities caused by data errors. Multiple verification mechanism: In addition to the preliminary checksum check, there is further verification based on the second checksum result. This multiple verification mechanism increases the fault tolerance of the system, ensuring that even in complex environments, the server can accurately determine the compatibility of the hardware and the correctness of the configuration, preventing false positives or system risks caused by single-point verification failure.

[0039] The specific use scenarios of the hang-up processing or updating the mainboard variable information according to the mainboard mapping relationship have the beneficial effects that the compatibility of the CPU and the mainboard can be determined at the initial stage of server startup, avoiding the startup attempt of non-compatible hardware, and significantly improving the stability and reliability of the system. The hang-up processing can immediately prevent potential problems from occurring, preventing the server from running in an unstable state and protecting the safety of the server and data. In a data center, quickly identifying and isolating problem hardware can significantly reduce troubleshooting time. The present application can determine the problem at the startup stage, and the operation and maintenance personnel can quickly locate whether it is a CPU installation error or a BIOS writing error, so that appropriate repair measures can be taken, avoiding subsequent complex fault diagnosis processes and saving a lot of manpower and time cost. In the security strategy of the server and the data center, hardware compatibility and configuration control are crucial. The present application ensures that only the correct CPU and BIOS configuration can enable the server to start, preventing potential security vulnerabilities caused by configuration errors, such as illegal access or data leakage. Hang-up processing as a last line of defense can prevent unauthorized or non-compliant hardware from starting, enhancing the overall security of the system. For customers using servers, the stability and security of the hardware are key factors in determining whether they will rely on a certain brand in the long term. The present application ensures the reliability and security of the server at the hardware level through strict verification mechanisms, improving user trust in the server and the management strategy behind it.

[0040] In an embodiment of the present application, based on the second checksum result, performing a hang-up process, or updating the motherboard variable information according to the motherboard mapping relationship, comprises: preprocessing the second checksum result to obtain a second sum value; in the case that the second sum value is 0, performing the hang-up process; in the case that the second sum value is not 0, determining a target product as a product of data at a preset offset address and 2 raised to the power of n, and determining a target read address as a sum of the target product and a preset byte, n being an integer and n≥0; reading data at the target read address from the memory, preprocessing the data at the target read address to obtain a third sum value, and based on the third sum value, performing the hang-up process, or updating the motherboard variable information according to the motherboard mapping relationship.

[0041] By calculating the checksum and preprocessing, it can effectively detect whether the data in the EEPROM is tampered or damaged. If the second sum value is 0, it usually means that the data fails the check, which may be due to the data in the EEPROM being maliciously modified or damaged for other reasons, at which time the hang-up process can prevent the server from starting, preventing the use of damaged or incorrect configuration information, thereby avoiding potential system failure or security risks. In actual operation, if the data format stored in the EEPROM is incorrect or data is missing, direct reading may not immediately trigger a hang-up, but subsequent system initialization and configuration may fail due to data errors, causing the server to run unstable. By checking the checksum before reading the data, such problems can be detected in advance, and the hang-up process is immediately executed, avoiding unnecessary misoperations and system abnormalities. Determining the target product as the product of the data at the preset offset address and 2 raised to the power of n, and determining the target read address based thereon, can accurately locate the specific information about the motherboard model, type and CPU model stored in the EEPROM. Through this process, it is ensured that the data read is the key information about the compatibility of the motherboard and CPU, thereby avoiding the failure of part of the peripheral functions due to the use of incompatible CPUs, improving the stability and reliability of the server. Determining the target read address as the sum of the product of the data at the preset offset address and 2 raised to the power of n and the preset byte, the key data in the EEPROM can be read in a targeted manner, avoiding unnecessary data reading and improving reading efficiency. At the same time, based on this reading strategy, even if a large amount of data is stored in the EEPROM, the required information can be quickly located and read, reducing the system startup time. Based on the result of the third sum value, the motherboard variable information can be selectively updated. If the third sum value is correct, it means that the data read is valid, at which time the motherboard variable information can be safely updated according to the read motherboard mapping relationship, ensuring that the configuration is accurate and correct when the server starts; if the check fails, the hang-up process is performed, which is simple and clear, avoiding complex data comparison and error handling logic.

[0042] In an embodiment of the present application, the method further comprises: preprocessing the second checksum result to obtain a second sum value; in the case that the second sum value is 0, performing a shutdown process; in the case that the second sum value is not 0, performing an AND operation on the data at the preset offset address to obtain an AND operation result, and setting the target read address to be the sum of the AND operation result and a preset value; reading the data at the target read address from the memory, preprocessing the data at the target read address to obtain a fourth sum value, and performing a shutdown process based on the fourth sum value, or updating the motherboard variable information according to the motherboard mapping relationship.

[0043] Specifically, preprocessing the checksum stored in the EEPROM can further check whether the data has been tampered with or damaged. If the second sum value is 0, it usually means that the check fails, and the data may be invalid, so performing a shutdown process can prevent the server from running in an error or unexpected configuration, thereby protecting the stability and security of the system. By performing an AND operation on the result, combining the preset offset address and the value to calculate a new target read address, this method can accurately locate the position of the motherboard model, type and CPU model information stored in the EEPROM, ensuring that the read data is correct and has not been changed by external interference. In the case that the second sum value is not 0, it means that the data stored in the EEPROM has passed the preliminary integrity check. Next, preprocessing the data at the target read address to obtain a fourth sum value, if the fourth sum value also passes the check, then the motherboard variable information in the BIOS can be safely updated according to the read motherboard information, ensuring that the server can correctly identify and configure hardware resources when starting. These preprocessing steps actually increase the complexity of accessing sensitive information in the EEPROM, making it difficult for unauthorized users to modify this information without leaving traces. This helps to prevent malicious attackers from gaining control of the server by modifying the BIOS image or data in the EEPROM. Automatically performing such a check when the server starts can quickly detect problems caused by the motherboard variable information not matching the actual installed hardware, avoiding subsequent compatibility problems and maintenance difficulties, reducing the complaint rate and operation and maintenance cost of the server. Comparing the CPU model information in the EEPROM with the actual installed CPU model ensures consistency between the two. If inconsistency is detected, the server is immediately shut down, avoiding functional abnormalities or performance degradation that may be caused by using incompatible CPUs, improving the overall stability and performance of the server.

[0044] In an embodiment of the present application, based on the fourth sum value, performing a shutdown process, or updating the motherboard variable information according to the motherboard mapping relationship, comprises: in the case that the fourth sum value is 0, performing a shutdown process; in the case that the fourth sum value is not 0, determining a target processor model based on the motherboard mapping relationship and the data at the target read address; and updating at least the current processor model of the motherboard variable information to the target processor model.

[0045] Specifically, if the data in the EEPROM is tampered with or accidentally deleted, resulting in the fourth and value being 0, it indicates that the data integrity of the EEPROM may be compromised. The crash handling can prevent the server from starting up with incomplete or incorrect configurations, thus protecting the security of the system and avoiding potential security threats such as the startup image being replaced or the CPU model information being maliciously changed. By verifying whether the CPU model is consistent with the model recorded in the EEPROM, this mechanism ensures that the server uses the correct BIOS configuration and peripheral settings. This is crucial because different CPU models (e.g., A, B, C, D versions) may support different numbers of PCI lanes, USB ports, etc. If the CPU model does not match, even if the server can start up, there may be cases where peripherals do not work properly or do not work at all, leading to data loss, performance degradation, or users being unable to access certain functions. The crash handling avoids these problems in such cases, ensuring the correctness of the functions and the reliability of the system. The crash handling immediately interrupts the startup when it detects that the CPU model does not match the EEPROM information, which helps to quickly locate the problem and reduce debugging time and cost. For users of the server, such a mechanism can provide clear fault information, guiding them to check whether the wrong CPU is installed or whether there is an EEPROM data error, so that appropriate corrective measures can be taken quickly. When the current processor model of the motherboard variable information is correctly updated to the target processor model, the BIOS will initialize the correct peripheral settings according to the actual specifications of the CPU. This means that all hardware resources will be fully utilized, and no peripherals will be idle due to incorrect configurations, thus improving the overall performance and resource utilization of the server.

[0046] In an embodiment of the present application, according to the updated motherboard variable information and the actual processor model, it is determined whether to load the peripheral settings of the current processor, comprising: in the case where the current processor model of the updated motherboard variable information and the actual processor model are the same, loading the peripheral settings of the current processor; in the case where the current processor model of the updated motherboard variable information and the actual processor model are different, determining that the peripheral settings of the current processor do not need to be loaded.

[0047] By verifying the consistency of the processor model, it can be ensured that the BIOS loaded peripheral settings are matched with the actual installed CPU, thereby avoiding system instability, function loss or performance degradation caused by mismatched peripheral settings. Different CPUs may support different numbers and types of peripherals, such as PCI Lane, USB ports, etc. After the processor model verification, the correct peripheral settings are loaded to ensure the compatibility and functionality of all hardware components, avoiding startup failure or system running abnormally caused by hardware incompatibility. This mechanism can prevent illegal modification of BIOS image or startup with incorrect CPU, thereby protecting the server from security threats caused by reverse engineering, malware or hardware incompatibility. The execution of the shutdown process when the mismatch occurs strengthens the physical and logical security of the server. When the server fails to start, the shutdown process can immediately prompt the user that the CPU model is mismatched, which helps to quickly locate the problem and avoid long troubleshooting and possible misdiagnosis, reducing the operation and maintenance cost and customer complaint rate. By accurately loading the processor peripheral settings, the peripheral resources of the CPU can be maximized, avoiding the use of part of the resources due to improper settings, and ensuring the full and reasonable use of server hardware resources.

[0048] In an embodiment of the present application, after updating the mainboard variable information, the method further comprises: closing the memory read-write capability and transmission configuration function of the bidirectional two-wire serial bus.

[0049] Specifically, after completing the necessary information reading, the advanced functions of the I2C bus are immediately closed, which can prevent potential attackers from further illegal access or tampering through the I2C bus. For example, an attacker may try to modify other devices (such as sensors, power management units, etc.) stored on the bus through the I2C bus, and closing these functions can effectively prevent such attacks. Closing unnecessary functions can reduce the energy consumption of the system, especially in high-performance computing environments such as servers, every milliwatt saved can have a significant impact in large-scale deployment. In addition, this also reduces the competition for I2C bus resources, making other devices that need to use the bus work more smoothly. Long-term opening of the advanced functions of I2C may introduce instability factors, such as communication errors due to external interference, or bus deadlocks caused by software errors. Timely closing of these functions helps to maintain the stable operation of the system, reducing the risk of server failure during startup.

[0050] In an embodiment of the present application, the mainboard mapping relationship is stored in the memory based on the bidirectional two-wire serial bus protocol, comprising: storing the mainboard mapping relationship in the form of binary in the memory based on the bidirectional two-wire serial bus protocol.

[0051] Specifically, the bidirectional two-wire serial bus (such as I2C) uses only two lines for data transmission (one for data and the other for clock), which greatly reduces the number of signal lines on the motherboard, simplifies hardware design, reduces production costs, and reduces the risk of electromagnetic interference. Binary format can compactly and efficiently store motherboard mapping relationships, including configuration information of various peripherals (such as the number of PCI lanes supported by the CPU, the number of USB ports, etc.). This approach not only saves storage space, but also makes the reading and parsing process faster, which is beneficial for fast startup and system configuration.

[0052] In an embodiment of the present application, determining the peripheral settings of the current processor includes: according to the processor model in the memory, setting the corresponding number of interfaces of the peripheral parallel bus of the current processor.

[0053] Specifically, by verifying the processor model, it is ensured that the BIOS loaded configuration matches the actual installed processor, avoiding system instability or security vulnerabilities caused by incorrect BIOS image refresh, such as incorrect peripheral interface configuration, which may be maliciously exploited to gain system control. The peripheral support of each processor (such as the number of PCI lanes, USB ports, etc.) may be different, and the correct processor model information ensures that the system can initialize the correct peripheral link, avoiding loss of hardware functionality or performance degradation due to mismatched configuration. For server manufacturers, using a unified BIOS image can greatly reduce management and maintenance complexity, especially when supporting multiple CPUs. By storing the processor model information in EEPROM, the BIOS configuration can be automatically adjusted without the need to prepare a separate BIOS version for each processor model.

[0054] As shown in Figure 2 The specific steps of the method of the present application include:

[0055] The server motherboard burns the mapping relationship of the motherboard model, motherboard type, and CPU (processor) model into the EEPROM (memory) image connected physically by the I2C bus;

[0056] The server starts, and first assigns the motherboard model, motherboard type, and processor model of the motherboard to the Unknown type, i.e., the undefined type;

[0057] Continue to start and execute the information reading of EEPROM, which needs to be obtained through the I2C bus. First, read the peripheral parallel bus base address space of the bidirectional two-wire serial bus through the BUS number, DEV number, and FUN number of the I2C bus;

[0058] The memory read-write capability and transmission configuration capability are written into the sum of the peripheral parallel bus base address and the preset offset address, that is, the data of the offset address of the PCI base address space of the I2C bus is read and stored, at this time, it is the PCI address space of the I2C bus, the I2C bus address mounted by the EEPROM is written into the address space of the PCI, that is, the I / O read-write capability of the I2C bus is initialized, then the memory read capability of the I2C bus is enabled by adding the IO enable offset 0x04 address to the PCI base address of the I2C bus, finally, the host function of the I2C bus is enabled by adding the address offset register of the I2C bus to the PCI base address + 0x40 of the I2C bus;

[0059] The multi-byte reading mode based on the bidirectional two-wire serial bus protocol is used to read the address data to be verified from the memory, and the address data to be verified is verified and processed, that is, the address of the EEPROM and the address of the I2C bus, the start offset address 0x00 and the multi-byte length (8 bytes) are read by the I2C protocol multi-byte reading mode, the preset condition is used to perform checksum verification on the read 8 bytes, that is, the read 8 bytes are verified, if the verification value 256 is taken modulo and added to the eighth byte data to judge whether it is 0;

[0060] If the result is 0, it is considered that the value format of the EEPROM is incorrect, and the system is directly crashed (here, the EEPROM data format is verified); if it is not 0, the offset address is continued to be used to read the processor model information, that is, one byte data at the offset 0x03 of the EEPROM address is continued to be read and judged whether it is 0, if it is 0, the system is directly crashed, if it is not 0, the value of the offset address data of 0x03 is left shifted by 3 bits and added by 6 bytes of offset to read the CPU model information supported by the motherboard, if it is 0, the system is crashed, if it is not 0, the content of the offset address data at 0x03 is continued to be processed with 0x3F data (that is, the AND operation is performed) and added by 1 as the offset address, the motherboard type information of the EEPROM is read according to the single-byte reading, if the return value is 0, the system is crashed, if it is not 0, the content of the offset address data at 0x03 is read based on the above offset address added by 1 and the length of 0x3F data, if the return value is 0, the system is crashed, if it is not 0, the I2C bus I / O read-write capability is closed, the stored data is written back, and the I2C bus host function is closed;

[0061] The motherboard model, motherboard type and CPU model read by the I2C are actually assigned values, at the same time, the BIOS directly reads the model information actually installed by the CPU and compares, if the CPU signal EEPROM read is inconsistent with the actual CPU model read, a shutdown process is performed; if the comparison result is consistent, the PCI link peripheral is set according to the CPU model in the EEPROM.

[0062] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and necessary general hardware platform, of course, it can also be realized by hardware, but in many cases, the former is a better embodiment.

[0063] The embodiment of the present application also provides a motherboard controller, as shown in the figure, Figure 3 The motherboard controller comprises:

[0064] The first processing unit 31 is used for storing the motherboard mapping relationship into the memory based on the bidirectional two-wire serial bus protocol, and the motherboard mapping relationship is the mapping relationship of the motherboard model, the motherboard type and each processor type supported by the corresponding processor;

[0065] The second processing unit 32 is used for assigning the motherboard variable information as an undefined type in the case of starting the server system, and the motherboard variable information includes the current motherboard model, the current motherboard type and the current processor model;

[0066] The third processing unit 33 is used for reading the peripheral parallel bus base address of the bidirectional two-wire serial bus, and writing the memory read-write capability enable and the transmission configuration enable into the space of the sum of the peripheral parallel bus base address and the preset offset address respectively;

[0067] The fourth processing unit 34 is used for reading the to-be-verified address data from the memory based on the multi-byte reading mode of the bidirectional two-wire serial bus protocol, and performing verification and processing on the to-be-verified address data, and based on the first verification result, performing a shutdown process, or updating the motherboard variable information according to the motherboard mapping relationship, and determining whether to load the peripheral settings of the current processor according to the updated motherboard variable information and the actual processor model.

[0068] The motherboard controller stores the motherboard model, motherboard type and the mapping relationship of the corresponding supported processor model in the memory (such as EEPROM) of the server using the bidirectional two-wire serial bus (i.e. I2C bus) protocol. This means that each motherboard will record the list of CPU models that it can perfectly match and run, thereby establishing the relevance between the motherboard and the CPU. When the server system starts, the BIOS sets the motherboard model, motherboard type, processor model and other key variable information as "undefined type", which means that before formally reading the memory information, the server has no knowledge of the characteristics of its own motherboard. Next, the BIOS reads the base address of the I2C bus and activates the function of the I2C bus by writing the memory read-write capability and transmission configuration enable to the preset offset address space of the corresponding base address. Then, the data at a specific address is read from the memory using the multi-byte read mode of the I2C protocol, and these data contain the mapping relationship information of the motherboard. The BIOS checks the read data, and if the check fails (for example, the checksum check fails), it means that the data in the memory may have been tampered with or damaged, and the server will directly execute a downtime process to prevent potential security risks. If the check is successful, the BIOS will parse the data and update the motherboard variable information to reflect the correct motherboard model, type and processor model information. Most importantly, the BIOS also reads the actual installed processor model on the server and compares it with the processor model read from the memory. If they do not match, it means that the current motherboard and CPU (current processor) do not match, and the server will continue to execute a downtime process to avoid incorrect peripheral configuration; if they match, it means that the CPU is correct, and the server will correctly load and configure the peripheral settings of the CPU according to the processor model specified in the EEPROM, such as the number of PCI lanes (Peripheral Component Interconnect lane refers to the number of data transmission channels within the PCI Express interface), USB ports (Universal Serial Bus port is a standard interface on a computer system used to connect external devices such as keyboards, mice, printers, external hard drives, USB flash drives, mobile phones and other electronic devices), network ports, etc., thereby ensuring that all functions can operate normally and avoiding the loss or abnormality of functions caused by CPU and motherboard incompatibility, thereby solving the problem of how to avoid the server executing incorrect configuration when starting due to the mismatch of the processor model, causing part of the motherboard functions to be unable to use normally.

[0069] In an embodiment of the present application, the fourth processing unit comprises: a first processing module configured to pre-process the first checksum result to obtain a first sum value, wherein the pre-processing comprises: taking the first checksum result modulo to obtain a first remainder, and determining the first sum value as a sum of the first remainder and a last byte of data of the address to be checked; a second processing module configured to perform a hang-up processing in a case where the first sum value is 0; and a third processing module configured to read byte data at a preset offset address of the address of the memory in a case where the first sum value is not 0, perform checksum processing on the byte data to obtain a second checksum result, and perform the hang-up processing based on the second checksum result, or update the motherboard variable information according to a motherboard mapping relationship.

[0070] In an embodiment of the present application, the third processing module comprises: a first processing submodule configured to pre-process the second checksum result to obtain a second sum value; a second processing submodule configured to perform the hang-up processing in a case where the second sum value is 0; and a third processing submodule configured to determine a target product as a product of data at the preset offset address and 2 raised to the power of n, and determine a target read address as a sum of the target product and a preset byte, n being an integer and n≥0, read data at the target read address from the memory, pre-process the data at the target read address to obtain a third sum value, and perform the hang-up processing based on the third sum value, or update the motherboard variable information according to the motherboard mapping relationship.

[0071] In an embodiment of the present application, the motherboard controller further comprises: a fifth processing unit configured to pre-process the second checksum result to obtain a second sum value; and a sixth processing unit configured to perform the hang-up processing in a case where the second sum value is 0; and a seventh processing unit configured to perform an AND operation on data at the preset offset address to obtain an AND operation result, determine the target read address as a sum of the AND operation result and a preset numerical value, read data at the target read address from the memory, pre-process the data at the target read address to obtain a fourth sum value, and perform the hang-up processing based on the fourth sum value, or update the motherboard variable information according to the motherboard mapping relationship.

[0072] In an embodiment of the present application, the seventh processing unit comprises: a fourth processing module configured to perform the hang-up processing in a case where the fourth sum value is 0; a fifth processing module configured to determine a target processor model based on the motherboard mapping relationship and the data at the target read address in a case where the fourth sum value is not 0; and a sixth processing module configured to update the current processor model of the motherboard variable information to the target processor model.

[0073] In an embodiment of the present application, the fourth processing unit comprises: a loading module configured to load the peripheral device settings of the current processor in the case that the current processor type of the updated mainboard variable information is the same as the actual processor type.

[0074] In an embodiment of the present application, the mainboard controller comprises: an eighth processing unit configured to close the memory read-write capability and the transmission configuration function of the bidirectional two-wire serial bus after updating the mainboard variable information.

[0075] In an embodiment of the present application, the first processing unit comprises: a storage module configured to store the mainboard mapping relationship in the form of binary into the memory based on the bidirectional two-wire serial bus protocol.

[0076] In an embodiment of the present application, the fourth processing unit comprises: a setting module configured to set the corresponding number of interfaces of the link peripheral device settings of the peripheral device parallel bus of the current processor according to the processor type in the memory.

[0077] The features of the embodiments of the mainboard controller can be referred to the related descriptions of the embodiments of the loading method of the peripheral device settings of the processor, which will not be repeated here.

[0078] The embodiments of the present application further provide an electronic device comprising a memory and a processor, the memory storing a computer program, and the processor being configured to run the computer program to execute the steps in any of the embodiments of the loading method of the peripheral device settings of the processor.

[0079] The embodiments of the present application further provide a computer readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the embodiments of the loading method of the peripheral device settings of the processor when running.

[0080] The present application further provides a server system, which comprises a server and a plurality of electronic devices, wherein the server is configured to execute the steps in any of the embodiments of the loading method of the peripheral device settings of the processor. Figure 4As shown, it comprises: a mainboard controller 100, a processor 200 and a memory 300, the mainboard controller and the processor communicate with each other, the processor and the memory are electrically connected through a bidirectional two-wire serial bus, and the mainboard controller is used for executing any one of the loading methods of the peripheral device settings of the processor. The base address of the bidirectional two-wire serial bus is read, and the memory read-write capability is enabled and the transmission configuration is enabled to be written into the preset offset address space of the corresponding base address. Then, the data of a specific address in the memory is read by using the multi-byte reading mode of the bidirectional two-wire serial bus protocol, the read data is verified, the mainboard variable information is updated when the verification is successful, the processor model actually installed on the server is compared with the processor model read from the memory, and if they match, it means that the processor is correct, and the server will correctly load and configure the peripheral device settings of the processor according to the processor model specified in the memory, thereby solving the problem of how to avoid the problem that part of the mainboard functions cannot be normally used due to the incorrect configuration of the server when starting because the processor model does not match.

[0081] In an example embodiment, the computer readable storage medium described above can include, but is not limited to: a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0082] Embodiments of the present application also provide a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement the steps in any one of the loading methods of the peripheral device settings of the processor.

[0083] Embodiments of the present application also provide another computer program product, which comprises a non-volatile computer readable storage medium, and the non-volatile computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps in any one of the loading methods of the peripheral device settings of the processor.

[0084] The skilled person can further realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized by electronic hardware, computer software or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in the above description in general terms. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0085] The foregoing describes in detail a loading method of peripheral device settings of a processor and a server system provided by the present application. The principles and implementation manners of the present application are described by using specific examples in the present application. The foregoing description of the examples is only applicable to helping understand the method of the present application and its core idea. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, the present application can be improved and modified in several ways, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A method for loading peripheral settings of a processor, characterized in that: include: Storing a motherboard mapping relationship in a memory based on a bidirectional two-wire serial bus protocol, the motherboard mapping relationship being a mapping relationship between a motherboard model, a motherboard type, and corresponding supported processor models; When the server system is started, all motherboard variable information is assigned an undefined type, wherein the motherboard variable information includes the current motherboard model, the current motherboard type and the current processor model; Reading a peripheral parallel bus base address of a bidirectional two-wire serial bus, and writing a memory read / write capability enable and a transmission configuration enable into a space of a sum of the peripheral parallel bus base address and a preset offset address; The address data to be checked is read from the memory in a multi-byte reading manner based on the bidirectional two-wire serial bus protocol, and the address data to be checked is checked and processed, and based on the first checksum result, a downtime process is performed, or the motherboard variable information is updated according to the motherboard mapping relationship, and based on the updated motherboard variable information and the actual processor model, it is determined whether to load the peripheral settings of the current processor.

2. The method for loading peripheral settings of a processor according to claim 1, characterized in that: Based on the first checksum result, performing downtime processing, or updating the motherboard variable information according to the motherboard mapping relationship, includes: Preprocessing the first checksum result to obtain a first sum value, wherein the preprocessing includes: taking a remainder of the first checksum result to obtain a first remainder, and determining the first sum value as a sum of the first remainder and the last byte data of the address data to be checked; When the first sum value is 0, executing downtime processing; When the first sum value is not 0, the byte data at the preset offset address of the address of the memory is read, and the byte data is checked and processed to obtain a second checksum result, and based on the second checksum result, downtime processing is performed, or the motherboard variable information is updated according to the motherboard mapping relationship.

3. The method for loading peripheral settings of a processor according to claim 2, characterized in that: Based on the second checksum result, performing downtime processing, or updating the motherboard variable information according to the motherboard mapping relationship, includes: Preprocessing the second checksum result to obtain a second sum value; When the second sum value is 0, the system performs downtime processing; When the second sum is not 0, determining a target product as a product of the data of the preset offset address and 2 to the power of n, and determining a target read address as a sum of the target product and a preset byte, where n is an integer and n≥0; The data of the target read address is read from the memory, and the data of the target read address is preprocessed to obtain a third sum value, and based on the third sum value, downtime processing is performed, or the motherboard variable information is updated according to the motherboard mapping relationship.

4. The method for loading peripheral settings of a processor according to claim 2, characterized in that: The method further comprises: Preprocessing the second checksum result to obtain a second sum value; When the second sum value is 0, the system performs downtime processing; When the second sum value is not 0, performing AND processing on the data of the preset offset address to obtain an AND processing result, and setting the target read address to the sum of the AND processing result and the preset value; The data of the target read address is read from the memory, and the data of the target read address is preprocessed to obtain a fourth sum value, and based on the fourth sum value, downtime processing is performed, or the motherboard variable information is updated according to the motherboard mapping relationship.

5. The method for loading peripheral settings of a processor according to claim 4, characterized in that: Based on the fourth sum value, executing downtime processing, or updating the motherboard variable information according to the motherboard mapping relationship, includes: When the fourth sum is 0, executing downtime processing; When the fourth sum value is not 0, determining a target processor model based on the motherboard mapping relationship and the data of the target read address; At least the current processor model of the motherboard variable information is updated to the target processor model.

6. The method for loading peripheral settings of a processor according to claim 1, characterized in that: Based on the updated motherboard variable information and the actual processor model, determine whether to load the peripheral settings of the current processor, including: When the current processor model of the updated motherboard variable information is the same as the actual processor model, loading the peripheral settings of the current processor; When the current processor model in the updated motherboard variable information is different from the actual processor model, it is determined that there is no need to load the peripheral settings of the current processor.

7. The method for loading peripheral settings of a processor according to claim 1, characterized in that: After updating the motherboard variable information, the method further includes: Disable the memory read and write capability and the transmission configuration function of the bidirectional two-wire serial bus.

8. The method for loading peripheral settings of a processor according to claim 1, characterized in that: The motherboard mapping relationship is stored in the memory based on the bidirectional two-wire serial bus protocol, including: Based on the bidirectional two-wire serial bus protocol, the mainboard mapping relationship is stored in the memory in binary form.

9. The method for loading peripheral settings of a processor according to any one of claims 1 to 8, characterized in that: Determine the peripheral settings for loading the current processor, including: A corresponding number of interfaces are set on the link peripherals of the peripheral parallel bus of the current processor according to the processor model in the memory.

10. A server system, characterized in that: include: A motherboard controller, a processor and a memory, wherein the motherboard controller and the processor communicate with each other, the processor and the memory are electrically connected using a bidirectional two-wire serial bus, and the motherboard controller is used to execute the loading method for peripheral settings of the processor according to any one of claims 1 to 9.

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