Host configurable reservation

Abstract

The invention relates to host configurable reservation. A system includes: a memory device; and a processing device operably coupled with the memory device, the processing device to perform operations including exposing a plurality of values of a reserved parameter of the memory device to a host system; receiving, from the host system, a selection of a value of the plurality of values; and based on the selection, updating a value of an operating parameter specifying a reserved capacity of the memory device.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to host adjustment of preconfigured reservations of memory devices. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally speaking, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, the present disclosure provides a system comprising: a memory device; and a processing device operably coupled to the memory device, the processing device configured to perform operations comprising: exposing a plurality of values ​​for a reservation parameter of the memory device to a host system; receiving a selection of a value from the host system from the plurality of values; and updating a value of an operating parameter specifying a reserved capacity of the memory device based on the selection.

[0004] In another aspect, the present disclosure provides a method comprising: exposing, by a processing device, a plurality of values ​​of a reservation parameter of a memory device to a host system; receiving a selection of a value from the host system; and updating a value of an operating parameter specifying a reserved capacity of the memory device based on the selection.

[0005] In another aspect, the present disclosure provides a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: exposing a plurality of values ​​for a reservation parameter of the memory device to a host system; receiving a selection of a value from the host system from the plurality of values; and updating a value of an operating parameter that specifies a reserved capacity of the memory device based on the selection. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example computing environment including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 2A and 2B Example registers for implementing host adjustments of preconfigured reservations of a memory device according to some embodiments of the present disclosure are described.

[0009] Figures 3 to 4is a flowchart of an example method of a host adjustment implementing preconfigured reservations of a memory device, in accordance with some embodiments of the present disclosure.

[0010] Figure 5 is a block diagram of an example computer system in which embodiments of the present disclosure can operate. DETAILED DESCRIPTION

[0011] Aspects of the present disclosure relate to host adjustment of preconfigured reservations of a memory device. A memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Example storage devices and memory modules are described below in connection with Figure 1 An example storage device and memory module are described. Generally, a host system can utilize a memory sub-system including one or more components of a memory device, such as storing data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

[0012] A memory sub-system can include a high-density non-volatile memory device in which it is desirable to retain data in the absence of a supply of electrical power to the memory device. For example, a NAND memory provides storage in a compact, high-density configuration. A non-volatile memory device is a package of one or more dies, each die including one or more planes. For some types of non-volatile memory devices (e.g., NAND memory), each plane includes a set of physical blocks. Each block includes a set of pages. Each page includes a set of memory cells (“cells”). A cell is an electronic circuit that stores information. A block refers to a unit of a memory device for storing data below and can include a group of memory cells, a group of word lines, a word line, or an individual memory cell. Each block can include a number of sub-blocks, where each sub-block is defined by an associated pillar (e.g., a vertical conductive trace) extending from a shared bit line. A memory page (also referred to herein as a “page”) stores binary data corresponding to one or more bits of data received from a host system.

[0013] A reservation refers to a physical capacity of a memory device that exceeds a logical capacity (“user capacity”) presented by an operating system as available to a host system. Thus, due to a reservation, a ratio of the physical capacity of the memory device to the user capacity of the memory device will exceed 1; the difference between the physical capacity and the user capacity is a reservation capacity, which can be measured in terms of a number of reserved valid blocks, memory pages, sub-blocks, half-blocks, or any other management unit (MU) in the memory device. The reservation capacity can be used, for example, for garbage collection, wear leveling, and / or dynamic caching.

[0014] In some memory sub-systems, such as managed NAND flash memory, embedded multimedia cards (eMMC) memory devices can include a controller to manage processes and improve performance. Firmware running on the controller can use reserved capacity to support garbage collection, wear leveling, bad block replacement, or other background processes that maintain and optimize performance. The efficiency of such processes can depend on the reserved capacity. The reserved capacity can be preconfigured at a manufacturing or post-production stage without consideration of a host system's specific usage pattern for the memory device.

[0015] Aspects of the present disclosure address the above and other deficiencies by enabling a host system to select one of the reserved parameter values that can be exposed by a memory device, such as via a reserved option register, which can be a read-only register of a configuration space of the memory device. In some implementations, a controller, such as a memory sub-system or local controller of the memory device, can store a list of valid reserved parameter values in the reserved option register from which the host system can select one or more values to be used by the controller to configure the reserved capacity of the memory device. Thus, the host system can read the reserved option register of the configuration space of the memory device and can further select a reserved parameter value that represents less reserved capacity, which can result in less efficient background processes, and more user capacity, or a reserved parameter value that represents more reserved capacity, which can result in more efficient background processes, and less user capacity. Accordingly, the host system can select a desired value of a particular reserved parameter from the list and send the selected value to the controller.

[0016] The controller can validate the received value, such as by comparing the received value to the list of valid reserved parameter values. Upon failing to find the received value in the list, the controller can notify the host system of an error. Conversely, upon successfully validating the received value, the controller can store the reserved parameter value in a reserved configuration register according to the received value, which can be a read / write or write-only register of the configuration space in the memory device. The memory device can check the reserved configuration register and update values of operational parameters of the memory device according to the reserved configuration register to adjust memory space allocated as reserved capacity. For example, the controller can update an operational parameter stored in a register of the memory device, such as a SEC_COUNT field in an extended device specific data (CSD) register, where the field SEC_COUNT defines the user capacity of the memory device, to adjust memory space allocated as reserved capacity.

[0017] Advantages of the present disclosure include enabling a host system to efficiently adjust a preconfigured reserved capacity of a memory device in order to flexibly balance performance with user capacity. The present disclosure meets the need of a host system to adjust a preconfigured reserved capacity according to the needs of the host system’s usage. In some usage of a memory device, a host system can need a larger reserved capacity to obtain better performance. A larger reserved capacity can provide additional available memory to firmware to optimize internal data management, resulting in performance improvement or endurance improvement. For example, firmware can engage in “light” garbage collection due to the number of free blocks in a larger reserved capacity, and light garbage collection can increase effective reserved, resulting in write amplification reduction, minimizing performance degradation, and causing less device wear over the lifetime of the memory device. In some usage of a memory device, a host system can need a larger user capacity to store user data.

[0018] Figure 1 An example computing system 100 including a memory sub-system 110 according to some embodiments of the present disclosure is described. The memory sub-system 110 can include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0019] The memory sub-system 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash memory drives, universal serial bus (USB) flash drives, embedded Multi-Media Controllers (eMMC) drives, Universal Flash Storage (UFS) drives, Secure Digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0020] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation vehicle), an Internet of Things (IoT) capable device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such computing device including memory and a processing device.

[0021] The computing system 100 can include a host system 120 coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to different types of memory sub-systems 110. Figure 1An example of a host system 120 coupled to a memory sub-system 110 is described. As used herein, “coupled to” or “coupled with” generally refers to a connection between components that can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0022] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, memory controllers (e.g., NVDIMM controllers), and storage protocol controllers (e.g., PCIe controllers, SATA controllers, CXL controllers). The host system 120 uses the memory sub-system 110, for example, to write data to and read data from the memory sub-system 110.

[0023] The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a compute express link (CXL) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, Fibre Channel, serial attached SCSI (SAS), double data rate (DDR) memory bus, a small computer system interface (SCSI), a dual in-line memory module (DIMM) interface (e.g., a DIMM slot interface that supports double data rate (DDR)), etc. The physical host interface can be used to transfer data between the host system 120 and the memory sub-system 110. When the memory sub-system 110 is coupled with the host system 120 by a physical host interface (e.g., a PCIe or CXL bus), the host system 120 can further access a memory device (e.g., memory device 130) utilizing an NVM express (NVMe) interface. The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system 110 and the host system 120. Figure 1 The memory sub-system 110 is illustrated as an example. In general, the host system 120 can access multiple memory sub-systems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0024] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory devices 140) can be, but are not limited to, random access memories (RAMs), such as dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs).

[0025] Some examples of non-volatile memory devices, such as memory devices 130, include negative-and (NAND)-type flash memory and in-situ write memory, such as three-dimensional cross-point (“3D cross-point”) memory. Cross-point arrays of non-volatile memory can perform bit storage based on bulk resistance changes along with a stackable cross-grid data access array. Further, in contrast to many flash-based memories, cross-point non-volatile memory can perform in-situ write operations, where a non-volatile memory cell can be programmed without previously erasing the non-volatile memory cell. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0026] Each of memory devices 130 can include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), can store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), and penta-level cells (PLC), can store multiple bits per cell. In some embodiments, each of memory devices 130 can include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device can include SLC, MLC, TLC, QLC, and PLC portions of memory cells. The memory cells of memory devices 130 can be grouped into pages, which can refer to a logical unit of a memory device for storing data. For some types of memory, such as NAND, pages can be grouped to form blocks.

[0027] Although 3D cross-point arrays of non-volatile memory cells and NAND-type flash memory, such as 2D NAND, 3D NAND, have been described, memory devices 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or negative-or (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM).

[0028] The memory sub-system controller 115 (or simply the controller 115) can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130, and other such operations. The memory sub-system controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0029] The memory sub-system controller 115 can include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory sub-system controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120.

[0030] In some embodiments, the local memory 119 can include memory registers that store memory pointers, fetched data, and the like. The local memory 119 can also include read-only memory (ROM) for storing microcode. While the example memory sub-system 110 has been illustrated as including the memory sub-system controller 115, in another embodiment of the disclosure, the memory sub-system 110 does not include the memory sub-system controller 115, but can rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory sub-system). Figure 1

[0031] In general, the memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. The memory sub-system controller 115 can be responsible for other operations associated with the memory devices 130 such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical address (e.g., a logical block address (LBA), a namespace) and a physical address (e.g., a physical block address). The memory sub-system controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert the commands received from the host system into command instructions for accessing the memory devices 130, and convert responses associated with the memory devices 130 into information for the host system 120.​

[0032] Memory sub-system 110 can also include additional circuitry or components not shown. In some embodiments, memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row and column decoders) that can receive an address from memory sub-system controller 115 and decode the address to access memory devices 130.

[0033] In some embodiments, memory devices 130 include a local media controller 135 that operates in conjunction with memory sub-system controller 115 to perform operations on one or more memory cells of memory devices 130. An external controller (e.g., memory sub-system controller 115) can externally manage memory devices 130 (e.g., perform media management operations on memory devices 130). In some embodiments, memory devices 130 are managed memory devices, which are raw memory devices combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0034] Memory sub-system 110 includes a reserved capacity manager 113 that can enable host adjustment of preconfigured reservations of memory devices. Memory sub-system 110 can include configuration space registers 123 to support the operations and functionality of reserved capacity manager 113 described herein. Regarding Figures 2A to 5 Further details regarding the operations of reserved capacity manager 113 and registers 123 are described.

[0035] Figure 2A And 2B An example register (e.g., registers 123) for implementing host adjustment of preconfigured reservations of memory devices according to some embodiments of the present disclosure is described. Figure 2A A read-only register (i.e., a reserved options register) that can be used to store a list of valid reserved parameter values, such as register 200A, is described. Figure 2B A read / write (R / W) register (i.e., a reserved configuration register) that can be used to store valid reserved parameter values (e.g., from the values shown in register 201B to the values shown in register 203B) that can be used by a memory device to update preconfigured reservations of the memory device is described.

[0036] Reference is made to Figure 2AIn an illustrative example, each entry of the list can include a value of a reservation parameter represented by a user capacity (e.g., measured in terms of a number of MUs). In an illustrative example, each entry of the list can include a value of a reservation parameter represented by a reservation ratio (e.g., measured in terms of a ratio of a physical capacity to a user capacity). In some implementations, each entry of the list can include values of two or more reservation parameters (e.g., a reservation ratio and a corresponding user capacity). In some implementations, each entry of the list can also specify a corresponding predicted improvement in a performance of the memory device or a durability aspect of the memory device. The predicted improvement can be measured in terms of a ratio of a particular parameter associated with the corresponding reservation parameter (referred to as a new setting of the reservation parameter) to the same parameter associated with a default reservation parameter (referred to as a default setting of the reservation parameter). The default setting of the reservation parameter can be a reservation parameter (e.g., a reservation ratio, a user capacity, etc.) that is set during a post-fabrication and / or production phase.

[0037] For example, the predicted improvement can be measured in terms of a ratio of a performance parameter in the new setting to a performance parameter in the default setting. In some implementations, the performance parameter can include a performance metric. As another example, the predicted improvement can be measured in terms of a ratio of a durability parameter in the new setting to a durability parameter in the default setting. In some implementations, the durability parameter can include a terabytes written (TBW) capability, which refers to an amount of data that can be written to the memory device during a lifetime of the memory device. The list in the register 200A can be pre-populated during a post-fabrication or production phase.

[0038] In some implementations, each entry of the list can be represented by a record identifier or indexed in the list. For example, an entry (e.g., record ID 00h) can indicate a default setting corresponding to a user capacity U0 and a reservation ratio O0. For example, assume a physical capacity is PC, a user capacity is U0, and a reservation ratio is O0 = PC / U0. A performance parameter is PP0, and a durability parameter is EP0. An improvement metric M0 is 0% because it corresponds to the default setting.

[0039] In some implementations, a predicted improvement metric can be measured in terms of a percentage of a performance parameter in the new setting relative to a performance parameter in the default setting. For example, record ID 01h can indicate a new setting corresponding to a user capacity U1 and a reservation ratio O1. Assume a physical capacity is PC, a user capacity is U1, a reservation ratio is O1 = PC / U1, and a performance parameter is PP1. An improvement metric M1 is (PP1-PP0) / PP0.

[0040] In some implementations, the prediction improvement metric can be measured as a percentage of the endurance parameter in the new setting relative to the performance parameter in the default setting. For example, record ID 02h can indicate a new setting corresponding to user capacity U2 and reservation ratio O2. Assume that the physical capacity is PC, the user capacity is U2, the reservation ratio is O2 = PC / U2, and the endurance parameter is EP2. The improvement metric M2 is (EP2-EP0) / EP0.

[0041] Reference Figure 2B The reservation capacity manager 113 can modify the register (i.e., the reservation configuration register) from a value in the default setting (e.g., shown as register 201B) to a value in the new setting (e.g., shown as register 203B). The register 201B can store a value of a reservation parameter corresponding to the default setting. For example, the reservation parameter value can be preset to a value corresponding to the user capacity of record ID 00h. As another example, the reservation parameter value can be preset to a value corresponding to the reservation ratio of record ID 00h. As yet another example, the reservation parameter value can be preset to record ID 00h, which can be used to read a specific value of the user capacity or the reservation ratio of an entry in the register 200A.

[0042] The register 203B can store a value of a reservation parameter corresponding to the new setting. For example, the reservation parameter value can be modified to a value corresponding to the user capacity of record ID 02h. As another example, the reservation parameter value can be modified to a value corresponding to the reservation ratio of record ID 02h. As yet another example, the reservation parameter value can be modified to record ID 02h, which can be used to read a specific value of the user capacity or the reservation ratio of an entry in the register 200A.

[0043] Figures 3 to 4 is an example method of a host adjusting implementation of a preconfigured reservation of a memory device according to some embodiments of the present disclosure. Methods 300-400 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, method 300 is performed by the host system 120 (e.g., a controller or CPU in the host system 120), and method 400 is performed by the memory device 110 (e.g., a controller or CPU in the memory device 110). Figure 1The operations of the method 300 can be performed by a host system (e.g., the host system 120) or a memory sub-system (e.g., the memory sub-system 110). In some embodiments, the operations of the method 300 are performed by the reservation capacity manager 113 (or a controller of the memory sub-system 110 or a local controller in the memory device 130). Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0044] Reference is made to Figure 3 At operation 310, processing logic in a host system (e.g., the host system 120) can send a request to a memory device (e.g., the memory device 130) to read a first register (e.g., the register 200A in the register 123) in the memory device in the memory sub-system. In some implementations, the first register stores a list of one or more values of a reservation parameter characterizing at least one of: a reservation ratio associated with the memory device, a user capacity of the memory device, and an improvement of the memory device. In some implementations, the first register is in a configuration space of the memory device. In some implementations, the first register is a read-only register.

[0045] At operation 320, in response to sending the request, the processing logic in the host system can receive (e.g., via the reservation capacity manager 113) from the memory device a value of a reservation parameter characterizing at least one of: a reservation ratio associated with the memory device, a user capacity of the memory device, and an improvement of the memory device. In some implementations, the value of the reservation parameter is preset in the first register (e.g., set by a vendor of the memory device during a post-manufacturing or production phase of the memory device).

[0046] At operation 330, the processing logic in the host system can determine a reservation parameter value from the received value. In some implementations, the processing logic can determine the reservation parameter value by selecting at least a subset of the one or more values of the reservation parameter (e.g., selecting one of the entries in 200A). For example, one subset of the one or more values of the reservation parameter includes a value indicating a user capacity, a value indicating a reservation ratio, and a value indicating a predicted improvement, and the processing logic can select the subset including the desired improvement and determine the reservation parameter value to be the value indicating the user capacity or the value indicating the reservation ratio in the subset. Using the example illustrated in Figure 2A Using the example illustrated in 200A, the processing logic can select the record ID 03h, since the entry includes the desired improvement M3, and thus determine the reservation parameter value to be the user capacity U3 or the reservation ratio O3 associated with the record ID 03h.

[0047] At operation 340, processing logic in the host system can send the determined reservation parameter values to the memory device (e.g., memory device 130). In some implementations, the processing logic can send a selected at least one subset of the one or more values of the reservation parameter. For example, one subset of the one or more values of the reservation parameter includes a value indicative of a user capacity, a value indicative of a reservation ratio, and a value identifying the subset, and the processing logic can send one or more of these values. Using Figure 2A Using the example described in FIG. 3, the processing logic can send the record ID 03h, or the user capacity U3 or the reservation ratio O3 associated with the record ID 03h.

[0048] Referring to Figure 4 At operation 410, processing logic (e.g., reservation capacity manager 113) can expose one or more values of a reservation parameter to a host system (e.g., host system 120), the reservation parameter characterizing at least one of: a reservation ratio associated with a memory device (e.g., memory device 130), a user capacity of the memory device, and an improvement of the memory device. In some implementations, the processing logic can expose the one or more values of the reservation parameter in response to receiving a request from the host system (e.g., operation 310), such that operation 410 can correspond to operation 320. In some implementations, a first register (e.g., register 200A in register 123) stores a list including the one or more values of the reservation parameter, the reservation parameter characterizing at least one of: a reservation ratio associated with a memory device, a user capacity of the memory device, and an improvement of the memory device. In some implementations, the first register is in a configuration space of the memory device (e.g., memory device 130). In some implementations, the first register is a read-only register. In some implementations, the one or more values of the reservation parameter are preset from historical data.

[0049] In some implementations, the improvement of the memory device is measured by at least one of: a performance metric or a terabyte write capacity. In some implementations, a value of the reservation parameter characterizing the improvement of the memory device is a percentage of a performance or endurance parameter in a new setting of the reservation of the memory device relative to a default setting of the reservation of the memory device.

[0050] At operation 420, the processing logic can receive, from the host system, a selection of at least a subset of one or more values of the reservation parameter. In some implementations, the selection includes the second value (e.g., operation 340), and the processing logic can determine whether the second value is valid according to the one or more values of the reservation parameter. In some implementations, the processing logic can search the first register (e.g., register 200A in register 123) for a match of the second value, determine that the second value is valid when a match of the second value is found, and determine that the second value is invalid when no match of the second value is found. In some implementations, the processing logic determines that the second value matches one of the one or more values of the reservation parameter. In some implementations, in response to determining that the second value is valid, the processing logic can write the second value to the second register. In some implementations, in response to determining that the second value is invalid, the processing logic can send an error notification to the host system in response to receiving the second value (or selection).

[0051] Using the example described in Figure 2A and 2B the processing logic can receive the second value as record ID 02h or a user capacity U2 or a reservation ratio 02 associated with record ID 02h, and search the first register 220A for a match of the second value, and determine that the second value is valid when a match is found. In some implementations, in response to determining that the second value is valid, the processing logic can write the second value to the second register 200B by modifying from a value 00h (O0 or U0) of the second register 201B to a value 02h (O2 or U2) of the second register 203B.

[0052] In some implementations, the second value is selected from the one or more values of the reservation parameter. In some implementations, writing the second value to the second register is performed once during a lifetime of the memory device. In some implementations, the second value indicates at least one of: a reservation ratio or a user capacity.

[0053] At operation 430, the processing logic can update a value of an operational parameter of the memory device based on the selection. In some implementations, the processing logic can update the value of the operational parameter of the memory device by firmware running on the processing device. In some implementations, the firmware runs on a controller of the memory device, and the firmware uses the reservation capacity of the memory device.

[0054] In some implementations, the processing logic can update the value of the operational parameter of the memory device by first writing the second value to the second register (e.g., register 200B in register 123), and then updating the value of the operational parameter according to the second value written to the second register. Using the example described in Figure 2BIn the illustrated example, the second value is a user capacity U2 or a reservation ratio O2, and the processing logic can update the value of the operating parameter of the memory device to align it with the user capacity U2 or the reservation ratio O2.

[0055] In some implementations, the operating parameter can specify at least one of: a reservation capacity of the memory device, a user capacity of the memory device, or a reservation ratio of the memory device. In some implementations, a value of the operating parameter (e.g., the SEC_COUNT parameter) is stored in a third register (e.g., an extended device specific data (CSD) register), and wherein the operating parameter specifies a user capacity of the memory device. In some implementations, the processing logic can update the value of the operating parameter of the memory device by decreasing the user capacity of the memory device, wherein the physical capacity of the memory device is unchanged.

[0056] In some implementations, a value of the operating parameter is stored in another register, and wherein the operating parameter specifies a reservation capacity of the memory device. In some implementations, the processing logic can update the value of the operating parameter of the memory device by increasing the reservation capacity of the memory device, wherein the physical capacity of the memory device is unchanged.

[0057] In some implementations, a value of the operating parameter is stored in another register, and wherein the operating parameter specifies a reservation ratio of the memory device. In some implementations, the processing logic can update the value of the operating parameter of the memory device by increasing the reservation ratio of the memory device, wherein the physical capacity of the memory device is unchanged.

[0058] Figure 5 An example machine of a computer system 500 is illustrated, within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein can be executed. In some embodiments, the computer system 500 can correspond to a host system (e.g., the host system 120 of Figure 1 that includes, is coupled to, or utilizes a memory sub-system (e.g., the memory sub-system 110 of Figure 1 ), or can be used to perform operations of a controller (e.g., execute an operating system to perform operations corresponding to the reservation capacity manager 113 of Figure 1 ). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environments, as a peer machine in peer-to-peer (or distributed) network environments, or as a server or a client machine in cloud computing infrastructure or environments.

[0059] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0060] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0061] Processing device 502 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device can be complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device 502 can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. The computer system 500 can further include a network interface device 508 to communicate over the network 520.

[0062] The data storage system 518 can include a machine-readable storage medium 524 (also known as a computer-readable medium) on which is stored one or more sets of instructions 526 or software embodying any one or more of the methodologies or functions described herein. The instructions 526 can also reside, completely or at least partially, within the main memory 504 and / or within the processing device 502 during execution thereof by the computer system 500, the main memory 504 and the processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, data storage system 518, and / or main memory 504 can correspond to memory subsystem 110 of FIG. 1. Figure 1

[0063] In one embodiment, the instructions 526 include instructions to implement a reservation capacity manager (e.g., the reservation capacity manager 104 of FIG. 1) that is configured to perform the operations described herein. Figure 1 ​instructions to perform the functionality of the reservation capacity manager 113. While the machine-readable storage medium 524 is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

[0064] Certain portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. This description and representation have been extremely well-understood by those skilled in the art, for whom these

[0065] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0066] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0067] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct more specialized apparatus to perform the methods. The structure for a variety of these systems will appear as follows description. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

[0068] The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions, which can be used to program a computer (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form accessible by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium, such as a read only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0069] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific examples thereof. It will be evident that various modifications can be made thereto without departing from the broader spirit and scope of embodiments of the present disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims

1. A system comprising: memory device; and A processing device operatively coupled to the memory device, the processing device configured to perform operations comprising: exposing a plurality of values ​​of a reservation parameter of the memory device to a host system; receiving, from the host system, a selection of a value from the plurality of values; and Based on the selection, a value of an operating parameter specifying a reserved capacity of the memory device is updated.

2. The system of claim 1, wherein the reservation parameter characterizes at least one of: a reservation ratio associated with the memory device, a user capacity of the memory device, or an improvement in a performance metric of the memory device. 3 . The system of claim 1 , wherein the plurality of values ​​for the reserved parameter are stored in a first register of a configuration space of the memory device, wherein the first register is read-only.

4. The system of claim 1 , wherein receiving the selection of a value from the plurality of values ​​further comprises: receiving a second value from the host system; determining whether the second value is valid based on the multiple values ​​of the reserved parameter; and In response to determining that the second value is valid, the second value is written to a second register of a configuration space of the memory device, wherein updating the value of the operating parameter is performed according to the second value written to the second register.

5. The system of claim 4, wherein determining whether the second value is valid further comprises: A determination is made as to whether the second value matches one of the plurality of values ​​of the reservation parameter.

6. The system of claim 4, wherein the operations further comprise: In response to determining that the second value is invalid, an error notification is sent to the host system in response to receiving the second value.

7. The system of claim 1, wherein the value of the operating parameter is stored in a third register.

8. The system of claim 1, wherein the operating parameter specifying the reserved capacity comprises at least one of: a parameter specifying a user capacity of the memory device, or a parameter specifying a reservation ratio of the memory device.

9. The system of claim 1 , wherein updating the value of the operating parameter further comprises: The user capacity of the memory device is reduced, wherein the physical capacity of the memory device is unchanged.

10. A method comprising: exposing, by a processing device, a plurality of values ​​of a reserved parameter of the memory device to a host system; receiving, from the host system, a selection of a value from the plurality of values; and Based on the selection, a value of an operating parameter specifying a reserved capacity of the memory device is updated.

11. The method of claim 10, wherein the reservation parameter characterizes at least one of: a reservation ratio associated with the memory device, a user capacity of the memory device, or an improvement in a performance metric of the memory device.

12. The method of claim 10, wherein the plurality of values ​​of the reserved parameter are stored in a first register of a configuration space of the memory device, wherein the first register is read-only, and wherein the plurality of values ​​of the reserved parameter are preset.

13. The method of claim 10, wherein receiving the selection of a value from the plurality of values ​​further comprises: receiving a second value from the host system; determining whether the second value is valid based on the multiple values ​​of the reserved parameter; and In response to determining that the second value is valid, the second value is written to a second register of a configuration space of the memory device, wherein updating the value of the operating parameter is performed according to the second value written to the second register. The method of claim 10 , wherein the value of the operating parameter is stored in a third register.

15. The method of claim 10, wherein the operating parameter specifying the reserved capacity comprises at least one of: a parameter specifying a user capacity of the memory device, or a parameter specifying a reservation ratio of the memory device.

16. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: exposing a plurality of values ​​of a reservation parameter of the memory device to a host system; receiving, from the host system, a selection of a value from the plurality of values; and Based on the selection, a value of an operating parameter specifying a reserved capacity of the memory device is updated.

17. The non-transitory computer-readable storage medium of claim 16, wherein the reservation parameter characterizes at least one of: a reservation ratio associated with the memory device, a user capacity of the memory device, or an improvement in a performance metric of the memory device.

18. The non-transitory computer-readable storage medium of claim 16, wherein the plurality of values ​​for the reserved parameter are stored in a first register of a configuration space of the memory device, wherein the first register is read-only.

19. The non-transitory computer-readable storage medium of claim 16, wherein receiving the selection of a value from the plurality of values ​​further comprises: receiving a second value from the host system; determining whether the second value is valid based on the multiple values ​​of the reserved parameter; and In response to determining that the second value is valid, the second value is written to a second register of a configuration space of the memory device, wherein updating the value of the operating parameter is performed according to the second value written to the second register.

20. The non-transitory computer-readable storage medium of claim 16, wherein the value of the operating parameter is stored in a third register.

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