Domestic CPU main and backup flash starting system and method

Abstract

The application discloses a domestic CPU main and standby Flash starting system and method, and the system comprises a domestic CPU, a CPLD device, a main Flash, at least one standby Flash and a GPIO signal line. The CPLD device expands a single SPI interface of the CPU into a multi-way SPI interface through logic programming, the main Flash stores a main starting firmware, and the standby Flash stores an independent standby firmware. During starting, the CPLD device preferentially connects the main Flash; if starting fails, the CPU sends a failure signal to the CPLD device through the GPIO, the CPLD device triggers CPU reset and switches an SPI signal to the standby Flash, and the CPU reloads the standby firmware to start. The application dynamically manages the SPI signal through the CPLD device, realizes intelligent switching control, breaks through the hardware limitation, and significantly improves the system starting reliability and stability.

Description

Technical Field

[0001] This invention relates to the field of computer boot technology, specifically a domestically produced CPU main and backup Flash boot system and method. Background Technology

[0002] In motherboard designs based on domestically produced CPUs (such as the Loongson 3A6000), boot reliability is crucial for ensuring stable system operation. However, some domestic CPUs (such as the Loongson 3A6000) only support a single SPI interface. This hardware limitation leads to numerous technical challenges. The following explanation uses the Loongson 3A6000 CPU as an example:

[0003] 1. Physical limitations of a single-channel SPI interface

[0004] The Loongson 3A6000 CPU's single-channel SPI interface design cannot directly support simultaneous connection to both primary and backup Flash memories at the hardware level. This means that during the boot process, the CPU can only access the primary Flash memory through a single SPI interface. If the primary Flash memory fails (e.g., due to firmware corruption, poor chip contact, or memory aging), the CPU will be unable to obtain valid boot firmware, directly causing system boot failure and potentially leading to system crashes.

[0005] 2. Heavy reliance on startup reliability

[0006] Traditional solutions rely entirely on the proper functioning of a single Flash memory. If any fault occurs in the main Flash memory, the CPU will freeze because it cannot load the boot program, and system stability cannot be guaranteed. This absolute dependence on a single Flash memory makes the system extremely vulnerable to hardware failures.

[0007] 3. Functional limitations of dedicated switching devices

[0008] While using dedicated SPI signal switching devices can enable the connection of multiple Flash memories, these devices have significant limitations. They lack programmability, cannot implement intelligent switching control logic based on boot failure signals, and cannot dynamically adjust signal flow according to the CPU's boot state. Summary of the Invention

[0009] The purpose of this invention is to overcome the above-mentioned technical problems and provide a domestic CPU master-slave Flash boot system.

[0010] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0011] A domestic CPU main and backup Flash boot system includes a domestic CPU, a CPLD device, a main Flash memory, at least one backup Flash memory, and GPIO signal lines;

[0012] The domestically produced CPU has a single SPI interface, which is electrically connected to the CPLD device. The CPLD device is used to expand the single SPI interface of the domestically produced CPU into a multi-channel SPI interface and to realize the switching control between the main Flash memory and the backup Flash memory. The main Flash memory is electrically connected to the domestically produced CPU through one SPI interface of the CPLD device and is used to store the main boot firmware.

[0013] The backup Flash memory is electrically connected to the domestic CPU through other SPI interfaces of the CPLD device. Each backup Flash memory is used to store independent backup boot firmware. The GPIO signal line is used to transmit boot failure signals and reset control signals between the domestic CPU and the CPLD device to realize automatic switching between the primary and backup Flash memories.

[0014] Furthermore, the CPLD device expands the single-channel SPI interface of the domestic CPU into a multi-channel SPI interface through logic programming using programmable logic code.

[0015] Furthermore, the CPLD device internally performs logic programming processing through programmable logic code, including switching logic processing of the SPI signal clock signal, chip select signal, data input signal, and data output signal.

[0016] Furthermore, the domestically produced CPU is a Loongson processor.

[0017] Furthermore, the number of the multiple SPI interfaces is equal to the total number of the main Flash memory and all spare Flash memories.

[0018] This invention also provides a domestic CPU primary / backup Flash boot method, the steps of which are as follows:

[0019] S1: When the domestic CPU is powered on, the CPLD device prioritizes switching the SPI signal to the main Flash memory;

[0020] S2: The domestically produced CPU boots by loading the firmware in the main Flash memory;

[0021] S3: If the main Flash memory fails to boot, the domestic CPU sends a boot failure signal to the CPLD device through the GPIO signal line;

[0022] S4: After receiving the startup failure signal, the CPLD device operates on the reset signal of the domestic CPU to trigger the CPU reset and switches the SPI signal to a backup Flash memory.

[0023] S5: The CPLD device releases the reset signal of the domestic CPU, which restarts and boots by loading the firmware of the switched backup Flash memory through the CPLD device.

[0024] Furthermore, in step S4, the CPLD device achieves the switching of SPI signals through logic programming processing using programmable logic code, including the switching logic of clock signals, chip select signals, data input signals, and data output signals.

[0025] Furthermore, the specific method of step S4 is as follows:

[0026] S41: After the CPLD device receives the startup failure signal sent by the domestic CPU, the internal logic circuit first generates a control signal according to the preset switching logic, and prepares to switch the output target of the clock signal.

[0027] S42: The CPLD device switches the output target of the clock signal from the main Flash memory to the selected backup Flash memory to ensure that the clock signal can be correctly transmitted to the backup Flash memory;

[0028] S43: The chip select signal is switched synchronously according to the switched SPI_CLK signal. The CPLD device controls the level of the chip select signal through internal logic to ensure that only the selected spare Flash memory can respond to the SPI bus command, while other spare Flash memories are in an unselected state.

[0029] S44: The CPLD device adjusts the level of the data input signal and the data output signal according to the switching logic to ensure the stability and reliability of the communication between the SPI bus and the backup Flash memory, and to prevent data writing errors or communication interruptions.

[0030] S45: The CPLD device completes all SPI signal switching logic to ensure a stable communication connection between the SPI bus and the backup Flash memory.

[0031] Furthermore, in step S5, after the domestic CPU restarts, if the switched backup Flash memory starts successfully, the system operates normally; if the domestic CPU fails to load the firmware of the switched backup Flash memory, the domestic CPU sends a startup failure signal to the CPLD device again through the GPIO signal line, and the CPLD device triggers the domestic CPU to reset again and switches the SPI signal to the next backup Flash memory.

[0032] Furthermore, it also includes step S6: verifying through the simulation verification module whether the CPLD device can correctly receive the startup failure signal of the domestic CPU and switch to the backup Flash memory for startup when the main Flash memory fails to start.

[0033] Beneficial effects of this invention:

[0034] 1. This invention's CPLD device, through internal logic programming, expands the original single-channel SPI interface of a domestic CPU into a multi-channel SPI interface. This expansion enables the CPU to simultaneously connect to primary and backup Flash memories for booting. During CPU power-on, the CPLD prioritizes switching the SPI signal to the primary Flash; if the primary Flash boot fails, the CPU notifies the CPLD via a GPIO signal, and the CPLD then controls the reset signal and switches the SPI signal to the backup Flash, ensuring the CPU can restart. This design significantly improves the reliability of CPU booting, avoids system boot failure due to a single Flash failure, achieves flexible expansion of the SPI interface, and greatly enhances system reliability.

[0035] 2. Compared to traditional dedicated SPI signal switching devices, the CPLD device of this invention utilizes a more flexible and intelligent logic control method implemented through internal code. The CPLD device can precisely control the signal flow according to actual needs, effectively handling the logical interaction and boot process between the CPU and Flash. This innovative logic control method not only simplifies hardware design but also optimizes the boot process, improving the overall performance and stability of the system. Attached Figure Description

[0036] Figure 1 : System architecture block diagram of Embodiment 1 of the present invention.

[0037] Figure 2 : A schematic diagram of the workflow of Embodiment 1 of the present invention.

[0038] Figure 3 The simulation timing diagram of the switching from the main Flash memory to the auxiliary Flash memory in this invention. Detailed Implementation

[0039] The present invention will now be described in detail with reference to the accompanying drawings and embodiments. To more intuitively and clearly describe the technical solution of the present invention, the following embodiments use the Loongson 3A6000 domestic CPU as an example. Example 1

[0040] A domestically produced CPU master-slave Flash boot system, such as Figure 1 As shown, it includes a Loongson 3A6000 CPU, a CPLD device, a main Flash memory, a backup Flash memory, and GPIO signal lines; the Loongson 3A6000 CPU has a single SPI interface, which is electrically connected to the CPLD device.

[0041] The CPLD device internally performs logical programming processing on the signal flow through code, including switching logic processing of the SPI signal clock signal (SPI_CLK), chip select signal (SPI_CSN), data input signal (SPI_DI), and data output signal (SPI_DO), thereby expanding the single SPI interface of the Loongson 3A6000 CPU into a two-channel SPI interface and realizing the switching control between the main Flash memory and the backup Flash memory.

[0042] The following is the core code for implementing SPI signal switching using a CPLD device:

[0043] / * Assigns the CPU_SPI_SDO signal of the CPU to the CPLD_QSPI_MOSI signal. Inside the CPLD, the signal level is converted by logic circuitry before being connected together. * /

[0044] assign CPLD_QSPI_MOSI = CPU_SPI_SDO;

[0045] / * Assign the CPLD_QSPI_MISO signal to CPU_SPI_SDI. Inside the CPLD, the signal level is converted by logic circuitry before being connected together. * /

[0046] assign CPU_SPI_SDI = CPLD_QSPI_MISO;

[0047] *The spi_cs signal is defined as high (disabled) when the current state is standby, chip select, or not in S0 state. When the current state is startup, the chip select signal is active.* /

[0048] wire spi_cs_High =

[0049] current_state==S0_WAIT

[0050] ||current_state==SPI_SEL

[0051] ||current_state>S4_CPU_S0;

[0052] / * Defines the SPI clock idle state as high to maintain consistency with the idle state of the master and backup Flash devices, ensuring signal compatibility. * /

[0053] localparam SPI_CLK_IDLE_STATE = 1;

[0054] / * Assign the CPU_SPI_SCK signal to CPLD_QSPI_SCK. Inside the CPLD, the signal is level-shifted by logic circuitry before being connected together. * /

[0055] assign CPLD_QSPI_SCK = CPU_SPI_SCK;

[0056] / * Defines the SPI chip select signal as high in the idle state, keeping it unselected to prevent accidental data transmission on the bus. * /

[0057] localparam SPI_CSN_IDLE_STATE = 1;

[0058] / *If spi_cs_High=1 or flash1_sel=1, then pull it high (disable); otherwise, assign the CPU's CPU_SPI_CSN signal to the CPLD_QSPI_CS0N signal, and select master Flash boot.* /

[0059] assign CPLD_QSPI_CS0N = spi_cs_High|(flash1_sel? CPU_SPI_CSN:1'h1);

[0060] / *If spi_cs_High=1 or flash1_sel=0, pull it high (disable); otherwise, assign the CPU's CPU_SPI_CSN signal to the CPLD_QSPI_CS1N signal, selecting Flash boot as the backup.* /

[0061] assign CPLD_QSPI_CS1N = spi_cs_High|(flash1_sel? 1'h1:CPU_SPI_CSN).

[0062] The main Flash memory is electrically connected to the Loongson 3A6000 CPU via one SPI interface of the CPLD device and stores the main boot firmware. The backup Flash memory is connected to the Loongson 3A6000 CPU via another SPI interface of the CPLD device and stores an independent backup boot firmware. The GPIO signal lines are used to transmit boot failure signals and reset control signals between the Loongson 3A6000 CPU and the CPLD device to realize automatic switching between the main and backup Flash memories.

[0063] The working principle of this embodiment is briefly described below:

[0064] The Loongson 3A6000 CPU sends a boot command to the CPLD device via its single-channel SPI interface. The CPLD device prioritizes switching the SPI signal to the main Flash memory. If the main Flash memory boot fails, the Loongson 3A6000 CPU sends a boot failure signal to the CPLD device via the GPIO signal line. Upon response, the CPLD device pulls down the CPU reset signal and switches the SPI signal to any backup Flash memory. After the CPLD device releases the CPU reset signal, the Loongson 3A6000 CPU restarts and accesses the switched backup Flash memory through the CPLD device to boot.

[0065] To better understand the technical solution of this embodiment, its working method is explained in detail below:

[0066] like Figure 2 As shown, a method for booting a domestically produced CPU using primary and backup Flash memory includes the following steps:

[0067] S1: When the Loongson 3A6000 CPU is powered on and started, the CPLD device prioritizes switching the SPI signal to the main Flash memory;

[0068] S2: The Loongson 3A6000 CPU boots by loading firmware from the main Flash memory;

[0069] S3: If the main Flash memory fails to boot, the Loongson 3A6000 CPU sends a boot failure signal to the CPLD device through the GPIO signal line;

[0070] S4: After receiving the startup failure signal, the CPLD device operates on the reset signal of the Loongson 3A6000 CPU to trigger the CPU reset and switch the SPI signal to the backup Flash memory.

[0071] S5: The CPLD device releases the reset signal of the Loongson 3A6000 CPU, the Loongson 3A6000 CPU restarts and boots by loading the firmware of the switched backup Flash memory through the CPLD device.

[0072] like Figure 3 To obtain the switching timing diagram for the switchover from the main Flash memory to the backup Flash memory captured by the simulation platform, from... Figure 3 As we can see, the left side of the red line La (time markers -100 to 3545) is the timing signal of the main Flash memory. Starting from the node with time marker 3545, the system switches to the backup Flash memory, that is, the right side of the red line La (time markers 3545 to 3950) is the timing signal of the backup Flash memory.

[0073] Preferably, in step S4, the CPLD device switches the SPI signal by performing logical programming of the signal flow through internal code, including the switching logic of the clock signal (SPI_CLK), chip select signal (SPI_CSN), data input signal (SPI_DI), and data output signal (SPI_DO). The specific method is as follows:

[0074] S41: After the CPLD device receives the start failure signal sent by the Loongson 3A6000 CPU, the internal logic circuit first generates a control signal according to the preset switching logic, and prepares to switch the output target of the clock signal (SPI_CLK);

[0075] S42: The CPLD device switches the output target of the clock signal (SPI_CLK) from the main Flash memory to the selected backup Flash memory to ensure that the clock signal can be correctly transmitted to the backup Flash memory;

[0076] S43: The chip select signal (SPI_CSN) is switched synchronously according to the switched SPI_CLK signal. The CPLD device controls the level of the chip select signal (SPI_CSN) through internal logic to ensure that only the selected spare Flash memory can respond to SPI bus commands, while other spare Flash memories are in an unselected state.

[0077] S44: The CPLD device adjusts the level of the data input signal (SPI_DI) and the data output signal (SPI_DO) according to the switching logic to ensure the stability and reliability of communication between the SPI bus and the backup Flash memory, and to prevent data write errors or communication interruptions.

[0078] S45: The CPLD device completes all SPI signal switching logic to ensure a stable communication connection between the SPI bus and the backup Flash memory.

[0079] In this embodiment, the CPLD device expands the original single-channel SPI interface of the Loongson 3A6000 CPU into a dual-channel SPI interface through internal logic programming. This expansion allows the Loongson 3A6000 CPU to simultaneously connect to the primary and backup Flash memories for booting. During CPU power-on, the CPLD device prioritizes switching the SPI signal to the primary Flash; if the primary Flash boot fails, the CPU notifies the CPLD device via a GPIO signal. The CPLD device then controls the reset signal and switches the SPI signal to the backup Flash, ensuring the Loongson 3A6000 CPU can restart. This design significantly improves the reliability of CPU booting, avoids system boot failure due to a single Flash failure, enables flexible expansion of the SPI interface, and greatly enhances system reliability.

[0080] Furthermore, compared to traditional dedicated SPI signal switching devices, the CPLD device in this embodiment utilizes a more flexible and intelligent logic control method implemented through internal code. The CPLD device can precisely control the signal flow according to actual needs, effectively handling the logical interaction and boot process between the CPU and Flash. This innovative logic control method not only simplifies hardware design but also optimizes the boot process, improving the overall system performance and stability. Example 2

[0081] The only difference from Embodiment 1 is that the CPLD device expands the single SPI interface of the Loongson 3A6000 CPU to more than two SPI interfaces, allowing for multiple backup Flash memories, thus improving stability and reliability. Specifically, in operation, if the switched backup Flash memory successfully boots, the system runs normally; if the switched backup Flash memory also fails to boot, the Loongson 3A6000 CPU sends a boot failure signal again via GPIO, triggering a reset on the CPLD device and switching to the next backup Flash memory, until all backup Flash memories have successfully booted. Example 3

[0082] This embodiment, based on the system described in Embodiment 1, adds a simulation verification module for the primary / standby Flash memory switching function, used to verify the system's fault switching robustness before hardware deployment. The specific verification process is as follows:

[0083] 1. Simulation platform setup

[0084] Using EDA tools to build a digital simulation environment for a CPU-CPLD-Flash system specifically includes:

[0085] The Loongson 3A6000 CPU behavior model is used to simulate the SPI interface and GPIO signal output.

[0086] The CPLD programmable logic code is the same as in Example 1;

[0087] The main Flash memory and backup Flash memory model supports firmware loading status feedback;

[0088] The fault injection module is used to simulate main Flash memory failure scenarios;

[0089] 2. Fault Injection and Switching Trigger

[0090] Step 1: Simulation platform initialization, CPLD devices route SPI signals to main Flash memory;

[0091] Step 2: Force the main Flash memory to return to a boot failure state (such as a firmware verification error signal) through the fault injection module.

[0092] Step 3: Monitor whether the CPU behavior model sends a startup failure signal to the CPLD via the GPIO signal line;

[0093] Step 4: Verify whether the CPLD device pulls the CPU reset signal low within the preset clock cycle after receiving the failure signal.

[0094] 3. SPI signal switching verification

[0095] Monitor the timing of key SPI signals output by the CPLD to verify the following logic:

[0096] Clock signal (SPI_CLK) switching: The CPLD device switches the clock output target from the main Flash to the backup Flash, and the switching process is glitch-free;

[0097] Chip select signal (SPI_CSN) synchronization: The chip select signal completes a level transition on the next rising edge of the clock after SPI_CLK switching, ensuring that the spare Flash is selected (in this embodiment, it is set to active low).

[0098] Data input signal (SPI_DI) and data output signal (SPI_DO) status: The signal level is immediately adjusted to the default operating state of the spare Flash after switching (set to high level in this embodiment).

[0099] 4. Criteria for successful switchover

[0100] After the CPU is reset and released, if the startup firmware first instruction in the spare Flash memory is successfully read via the SPI bus, the simulation verification is successful; otherwise, the simulation verification fails.

[0101] Through simulation verification in this embodiment, it was confirmed that the CPLD device can intelligently trigger a switching action based on the CPU's GPIO signal when the main Flash memory fails. This verification process ensures the high availability of the system in a real hardware environment.

[0102] It should be noted that the domestically produced CPU, CPLD device, Flash memory, etc. of the present invention are all through devices, and can be flexibly selected in practical applications. The above embodiments are only illustrative examples.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the present invention and are not intended to limit the technical solutions described in the present invention. Therefore, although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the present invention. All technical solutions and improvements that do not depart from the spirit and scope of the present invention should be covered within the scope of the claims of the present invention.

Claims

1. A domestically produced CPU master / slave Flash boot system, characterized in that: Includes domestically produced CPU, CPLD device, main Flash memory, at least one spare Flash memory, and GPIO signal lines; The domestically produced CPU has a single SPI interface, which is electrically connected to the CPLD device. The CPLD device is used to expand the single SPI interface of the domestically produced CPU into a multi-channel SPI interface and to realize the switching control between the main Flash memory and the backup Flash memory. The main Flash memory is electrically connected to the domestic CPU through one SPI interface of the CPLD device and is used to store the main boot firmware; The backup Flash memory is electrically connected to the domestic CPU through other SPI interfaces of the CPLD device. Each backup Flash memory is used to store independent backup boot firmware. The GPIO signal lines are used to transmit boot failure signals and reset control signals between the domestic CPU and the CPLD device to realize automatic switching between the primary and backup Flash memories. The CPLD device internally expands the single SPI interface of the domestic CPU into a multi-channel SPI interface through programmable logic code. The logic programming process includes switching logic processing of the SPI signal clock signal, chip select signal, data input signal and data output signal.

2. The domestically produced CPU primary / backup Flash boot system according to claim 1, characterized in that: The domestically produced CPU mentioned is the Loongson processor.

3. The domestically produced CPU primary / backup Flash boot system according to claim 1, characterized in that: The number of the multiple SPI interfaces is equal to the total number of the main Flash memory and all spare Flash memories.

4. A method for booting a domestically produced CPU using primary and backup Flash memory, characterized in that, The steps of applying the domestic CPU primary / backup Flash boot system as described in claim 1 are as follows: S1: When the domestic CPU is powered on, the CPLD device prioritizes switching the SPI signal to the main Flash memory; S2: The domestically produced CPU boots by loading the firmware in the main Flash memory; S3: If the main Flash memory fails to boot, the domestic CPU sends a boot failure signal to the CPLD device through the GPIO signal line; S4: After receiving the startup failure signal, the CPLD device operates on the reset signal of the domestic CPU to trigger the CPU reset and switches the SPI signal to a backup Flash memory. S5: The CPLD device releases the reset signal of the domestic CPU, which restarts and boots by loading the firmware of the switched backup Flash memory through the CPLD device.

5. The domestic CPU primary / backup Flash boot method according to claim 4, characterized in that: The specific method for step S4 is as follows: S41: After the CPLD device receives the start failure signal sent by the domestic CPU, the internal logic circuit first generates a control signal according to the preset switching logic, and prepares to switch the output target of the clock signal. S42: The CPLD device switches the output target of the clock signal from the main Flash memory to the selected backup Flash memory to ensure that the clock signal can be correctly transmitted to the backup Flash memory; S43: The chip select signal is switched synchronously according to the switched SPI_CLK signal. The CPLD device controls the level of the chip select signal through internal logic to ensure that only the selected spare Flash memory can respond to the SPI bus command, while other spare Flash memories are in an unselected state. S44: The CPLD device adjusts the level of the data input signal and the data output signal according to the switching logic to ensure the stability and reliability of the communication between the SPI bus and the backup Flash memory, and to prevent data writing errors or communication interruptions. S45: The CPLD device completes all SPI signal switching logic to ensure a stable communication connection between the SPI bus and the backup Flash memory.

6. The domestic CPU primary / backup Flash boot method according to any one of claims 4-5, characterized in that: In step S5, after the domestic CPU restarts, if the switched backup Flash memory starts successfully, the system runs normally; if the domestic CPU fails to start by loading the firmware of the switched backup Flash memory, the domestic CPU sends a startup failure signal to the CPLD device again through the GPIO signal line, and the CPLD device triggers the domestic CPU to reset again and switches the SPI signal to the next backup Flash memory.

7. The domestic CPU primary / backup Flash boot method according to claim 4, characterized in that: It also includes step S6: verifying through the simulation verification module whether the CPLD device can correctly receive the startup failure signal of the domestic CPU and switch to the backup Flash memory for startup when the main Flash memory fails to start.

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