Performance detection method and device of chip simulation system and medium

Abstract

The invention discloses a performance detection method and device for a chip simulation system and a medium, and relates to the technical field of chip development, and the method comprises the steps: executing a performance self-test of a target hardware simulation model, and obtaining a first test result identifier; according to the target hardware simulation model and the target chip firmware, a simulation system comprehensive test is executed, and a second test result identifier is obtained; determining and outputting a target system test result according to the first test result identifier and the second test result identifier; according to the method, the overall performance of the hardware simulation model and the overall performance of the chip simulation system can be evaluated respectively through performance self-testing and simulation system comprehensive testing, separated testing of hardware and firmware can be indirectly achieved, and the accuracy of performance detection of the chip simulation system is guaranteed; and the performance state of the chip simulation system can be automatically analyzed and determined based on the identifiers output by the two tests, so that the abnormal condition of performance reduction can be captured in time, and the chip development efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip development, and in particular to a performance detection method and device of a chip simulation system and a medium. BACKGROUND

[0002] At present, the system simulation environment building for chip development usually includes a hardware simulation model and a CPU (Central Processing Unit) model, and the chip firmware is loaded and run in the CPU model. The hardware simulation model and the CPU model work together to determine the overall performance of the system simulation environment. During the chip development stage, the development of the chip firmware and the chip hardware simulation model is often in a state of rapid iteration, and the frequent changes of the two may lead to fluctuations or even a decline in the performance of the simulation system. If the performance decline can be detected as early as possible, it will help to locate the problem source faster and speed up the development process; however, the performance changes of the simulation environment currently mainly depend on the subjective perception of the platform user, and this kind of user feedback-dependent way has obvious limitations: the user perception is usually not accurate enough and often lags behind the actual occurrence time of the system performance decline. This lag may lead to the problem not being discovered for a long time, thereby affecting the development efficiency.

[0003] Therefore, how to accurately and automatically detect the performance of the chip simulation system so as to timely capture the abnormal situation of performance decline and improve the chip development efficiency is a problem that needs to be solved at present. SUMMARY

[0004] The purpose of the present application is to provide a performance detection method and device of a chip simulation system and a computer readable storage medium, so as to accurately and automatically detect the performance of the chip simulation system, thereby timely capturing the abnormal situation of performance decline and improving the chip development efficiency.

[0005] To solve the above technical problems, the present application provides a performance detection method of a chip simulation system, comprising:

[0006] performing performance self-test of a target hardware simulation model to obtain a first test result identifier; wherein the target hardware simulation model is any preset hardware simulation model, and the first test result identifier is any preset self-test result identifier;

[0007] performing simulation system comprehensive test according to the target hardware simulation model and a target chip firmware to obtain a second test result identifier; wherein the target chip firmware is any preset chip firmware, and the second test result identifier is any preset comprehensive test result identifier;

[0008] According to the first test result identifier and the second test result identifier, a target system test result is determined and output; wherein the target system performance test result is any preset performance test result.

[0009] In another aspect, the performance self-test of the target hardware simulation model is executed, and a first test result identifier is obtained, including:

[0010] The performance self-test of the target hardware simulation model is executed, and a current self-test index of the performance self-test is obtained; wherein the performance self-test is used for firmware patching of the target hardware simulation model;

[0011] According to the current self-test index and a preset self-test index, the first test result identifier is obtained.

[0012] In another aspect, the preset self-test result identifier includes a self-test failure identifier, a self-test performance decline identifier, a self-test performance stability identifier, and a self-test performance improvement identifier;

[0013] The performance self-test of the target hardware simulation model is executed, and a current self-test index of the performance self-test is obtained, including:

[0014] The performance self-test of the target hardware simulation model is executed, and it is judged whether the performance self-test is successfully completed;

[0015] If successfully completed, a current self-test index of the performance self-test is obtained;

[0016] If not successfully completed, the first test result identifier is determined as the self-test failure identifier;

[0017] According to the current self-test index and a preset self-test index, the first test result identifier is obtained, including:

[0018] If the current self-test index is not greater than a self-test low threshold, the first test result identifier is determined as the self-test performance decline identifier; wherein the self-test low threshold is a product of the preset self-test index and a first parameter, and the first parameter is less than 1;

[0019] If the current self-test index is greater than the self-test low threshold and not greater than a self-test high threshold, the first test result identifier is determined as the self-test performance stability identifier; wherein the self-test low threshold is a product of the preset self-test index and a second parameter, and the second parameter is greater than 1;

[0020] If the current self-test index is greater than the self-test high threshold, the first test result identifier is determined as the self-test performance improvement identifier.

[0021] In another aspect, the second test result identifier is obtained by performing a simulation system comprehensive test according to the target hardware simulation model and the target chip firmware.

[0022] If the first test result identifier is the self-test performance stable identifier or the self-test performance improvement identifier, the second test result identifier is obtained by performing the simulation system comprehensive test according to the target hardware simulation model and the target chip firmware.

[0023] If the first test result identifier is the self-test failure identifier, a hardware simulation model self-test failure result is output.

[0024] If the first test result identifier is the self-test performance decline identifier, a hardware simulation model variation causing performance decline result is output.

[0025] In another aspect, the current self-test indicator is a performance score and / or a number of read-write operations per second; wherein the performance score is a quotient of a preset constant and a simulation test time.

[0026] In another aspect, the second test result identifier is obtained by performing a simulation system comprehensive test according to the target hardware simulation model and the target chip firmware.

[0027] The simulation system comprehensive test is performed according to the target hardware simulation model and the target chip firmware, and a log is recorded, to obtain the second test result identifier; wherein the simulation system comprehensive test comprises a communication interaction process of the target hardware simulation model and the target chip firmware under a preset business scenario, and the log is used to record a key node timestamp of each business logic sub-process in the simulation system comprehensive test.

[0028] In another aspect, the preset self-test result identifier comprises a self-test performance stable identifier and a self-test performance improvement identifier; and the preset comprehensive test result identifier comprises a comprehensive test failure identifier, a comprehensive test performance decline identifier, a comprehensive test performance stable identifier, and a comprehensive test performance improvement identifier.

[0029] The target system test result is determined and output according to the first test result identifier and the second test result identifier, comprising:

[0030] If the first test result identifier is the self-test performance stable identifier or the self-test performance improvement identifier, and the second test result identifier is the comprehensive test failure identifier, the target system test result is determined as a simulation system comprehensive performance test failure result, and the target system test result is output.

[0031] If the first test result is identified as the self-test performance stable identifier or the self-test performance improvement identifier, and the second test result is identified as the comprehensive test performance stable identifier, the target system test result is determined as a simulation system performance state stable result, and the target system test result is outputted.

[0032] If the first test result is identified as the self-test performance stable identifier or the self-test performance improvement identifier, and the second test result is identified as the comprehensive test performance improvement identifier, the target system test result is determined as a simulation system performance state improvement result, and the target system test result is outputted.

[0033] If the first test result is identified as the self-test performance stable identifier or the self-test performance improvement identifier, and the second test result is identified as the comprehensive test performance decline identifier, the target system test result is determined as a simulation system comprehensive performance decline result, and the target system test result is outputted.

[0034] In another aspect, the determination of the target system test result as a simulation system comprehensive performance decline result and the output of the target system test result comprise:

[0035] After the determination of the target system test result as a simulation system comprehensive performance decline result, a performance self-test of a preset historical hardware simulation model is performed to obtain a third test result identifier.

[0036] According to the preset historical hardware simulation model and the target chip firmware, a simulation system comprehensive test is performed to obtain a fourth test result identifier.

[0037] According to the third test result identifier and the fourth test result identifier, a historical system test result is determined.

[0038] If the historical system test result is a target simulation system performance state stable result, the target system test result and a first comprehensive performance decline reason are outputted; wherein the target simulation system performance state stable result is a simulation system performance state stable result corresponding to the self-test performance stable identifier and the comprehensive test performance stable identifier; and the first comprehensive performance decline reason is a comprehensive performance decline caused by a model interaction change.

[0039] If the historical system test result is the simulation system comprehensive performance decline result, the target system test result and a second comprehensive performance decline reason are outputted; wherein the second comprehensive performance decline reason is a comprehensive performance decline caused by a chip firmware logic change.

[0040] The application further provides a performance detection device of a chip simulation system, which comprises:

[0041] a self-test unit configured to perform performance self-test on a target hardware simulation model to obtain a first test result identifier, wherein the target hardware simulation model is any preset hardware simulation model, and the first test result identifier is any preset self-test result identifier;

[0042] a comprehensive test unit configured to perform simulation system comprehensive test according to the target hardware simulation model and a target chip firmware to obtain a second test result identifier, wherein the target chip firmware is any preset chip firmware, and the second test result identifier is any preset comprehensive test result identifier;

[0043] a performance analysis unit configured to determine and output a target system test result according to the first test result identifier and the second test result identifier, wherein the target system performance test result is any preset performance test result.

[0044] In addition, the application further provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of the performance detection method of the chip simulation system.

[0045] The performance detection method of the chip simulation system comprises the following steps: performing performance self-test on a target hardware simulation model to obtain a first test result identifier, wherein the target hardware simulation model is any preset hardware simulation model, and the first test result identifier is any preset self-test result identifier; performing simulation system comprehensive test according to the target hardware simulation model and a target chip firmware to obtain a second test result identifier, wherein the target chip firmware is any preset chip firmware, and the second test result identifier is any preset comprehensive test result identifier; and determining and outputting a target system test result according to the first test result identifier and the second test result identifier, wherein the target system performance test result is any preset performance test result.

[0046] It can be seen that, by means of performance self-test and simulation system comprehensive test, the performance of the hardware simulation model and the overall performance of the chip simulation system are respectively evaluated, the separation test of the hardware and the firmware is indirectly realized, the accuracy of the performance detection of the chip simulation system is ensured, the performance state of the chip simulation system is automatically analyzed and determined based on the first test result identifier and the second test result identifier, the performance of the chip simulation system is automatically detected, abnormal conditions of performance decline can be captured in time, and the chip development efficiency is improved. BRIEF DESCRIPTION OF DRAWINGS

[0047] In order to make the technical solutions of the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only aim at the embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative effort based on the provided drawings.

[0048] Figure 1 A flow chart of a performance detection method of a chip simulation system provided by an embodiment of the present application;

[0049] Figure 2 A structural schematic diagram of a performance detection device of a chip simulation system provided by an embodiment of the present application;

[0050] Figure 3 A schematic diagram of a performance self-test flow of a hardware simulation model provided by an embodiment of the present application;

[0051] Figure 4 A schematic diagram of a simulation system comprehensive test flow provided by an embodiment of the present application;

[0052] Figure 5 A structural block diagram of a performance detection device of a chip simulation system provided by an embodiment of the present application;

[0053] Figure 6 A structural schematic diagram of a performance detection device of a chip simulation system provided by an embodiment of the present application;

[0054] Figure 7 A structural schematic diagram of a computer readable storage medium provided by an embodiment of the present application. DETAILED DESCRIPTION

[0055] In order to make the technical solutions of the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only aim at the embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative effort based on the provided drawings.

[0056] Please refer to Figure 1 , Figure 1 A flow chart of a performance detection method of a chip simulation system provided by an embodiment of the present application. The method can include:

[0057] Step 101: Execute a performance self-test of a target hardware simulation model to obtain a first test result identifier; wherein the target hardware simulation model is any preset hardware simulation model, and the first test result identifier is any preset self-test result identifier.

[0058] It is understandable that the target hardware simulation model in this embodiment can be the hardware simulation model used by the chip simulation system whose performance needs to be tested, such as the latest version of the hardware simulation model currently running. Each preset hardware simulation model in this embodiment can be a pre-set version of a hardware simulation model; the specific number and content of the preset hardware simulation models in this embodiment can be set by the designer according to the usage scenario and user needs. For example, the preset hardware simulation model can include the latest version of the hardware simulation model currently used by the chip simulation system and the previous version of the hardware simulation model (or the preset version of the hardware simulation model) used last time, and can also include other versions of hardware simulation models. This embodiment does not impose any restrictions on this.

[0059] Correspondingly, the specific selection of the target hardware simulation model in this embodiment can be set by the designer according to the usage scenario and user needs. For example, the target hardware simulation model can be the latest version of the hardware simulation model, that is, the hardware simulation model currently used by the chip simulation system that needs to test performance; for example, in this step, the performance self-test of the target hardware simulation model can be performed at a preset time interval to obtain the first test result identifier to periodically trigger the performance test process. Figure 2 As shown, the trigger interface can serve as a process trigger interface of the periodic performance test module, which is responsible for triggering the performance test process according to the preset time interval; that is, the trigger interface can trigger the performance test process regularly according to the repetition period value (i.e., the preset time interval, such as 24 hours) set in the initialization configuration module; for example, if the preset time interval is set to 24 hours, a performance test will be automatically triggered every 24 hours to trigger the execution of the performance self-test of the latest version of the hardware simulation model (i.e., the target hardware simulation model) to obtain a first test result identifier. The target hardware simulation model can also be any preset hardware simulation model selected by the user according to demand. For example, in this step, the performance self-test of the target hardware simulation model can be executed according to the obtained manual trigger instruction to obtain a first test result identifier; that is, the target hardware simulation model can be a preset hardware simulation model selected by the manual trigger instruction or a hardware simulation model of the latest version; as Figure 2 As shown, the trigger interface can retain the manual trigger function, allowing users to trigger the performance test process once when releasing a new version or meeting other special requirements, to ensure that the test can adapt to different development scenarios and requirements.

[0060] For example, if Figure 2As shown, the initialization configuration module can be responsible for configuring the data storage module, applied to the first cycle performance test or other manual configuration scenarios; for example, the initialization configuration module can obtain the latest version of the hardware simulation model, store it as the preset hardware simulation model as the historical version of the hardware simulation model for subsequent testing; obtain the latest version of the chip firmware, store it as the preset chip firmware as the historical version of the chip firmware for subsequent testing.

[0061] It should be noted that the performance self-test of the target hardware simulation model in the embodiment can be used for firmware spiking of the target hardware simulation model to shield the logical execution of the chip firmware (such as the target chip firmware) and only evaluate the performance of the target hardware simulation model, so that the test result (i.e., the first test result identifier) can completely reflect the performance level of the target hardware simulation model and is irrelevant to the chip firmware.

[0062] Further, in the embodiment, a first keyword can be set at the end of the performance self-test to facilitate the determination of whether the performance self-test is successfully completed, i.e., if the first keyword is detected during the execution of the performance self-test or after the end of the performance self-test, it is determined that the performance self-test is successfully completed. In order to facilitate subsequent performance analysis, in the embodiment, the business flow logic of the performance self-test can be divided into multiple sub-flows to record the time stamp at the key node, so that the key node time stamp of each sub-flow can be recorded in the log during the performance self-test execution process.

[0063] Correspondingly, the performance self-test of the target hardware simulation model can be performed and a self-test log can be recorded to obtain a first test result identifier; wherein the self-test log is used to record the key node time stamp of each business logic sub-flow in the performance self-test to facilitate subsequent performance analysis.

[0064] Correspondingly, the first test result identifier in the embodiment can be any preset self-test result identifier, and the preset self-test result identifier can include at least two of a self-test failure identifier, a self-test performance decline identifier, a self-test performance stability identifier, and a self-test performance improvement identifier. For the performance self-test of the target hardware simulation model in this step, the specific manner of obtaining the first test result identifier can be set by the designer according to the practical scene and user demand, such as performing the performance self-test of the target hardware simulation model to obtain the current self-test index of the performance self-test; wherein the performance self-test is used to perform firmware splicing on the target hardware simulation model; and the first test result identifier is obtained according to the current self-test index and a preset self-test index. The preset self-test index can be a preset self-test index, such as the index of the last performance self-test (i.e., the historical self-test index), so as to determine the first test result identifier by comparing the current self-test index with the preset self-test index. The first test result identifier can also be determined by directly comparing the current self-test index with a fixed threshold. The embodiment does not make any limitation in this regard.

[0065] For example, when the preset self-test result identifier includes the self-test performance decline identifier, the self-test performance stability identifier, and the self-test performance improvement identifier, the process of obtaining the first test result identifier according to the current self-test index and the preset self-test index can include: if the current self-test index is not greater than a self-test low threshold (such as the low threshold L1 in the above table), the first test result identifier is determined as the self-test performance decline identifier (such as the marking result 1-2 in the above table); wherein the self-test low threshold is the product of the preset self-test index and a first parameter, and the first parameter is less than 1; if the current self-test index is greater than the self-test low threshold and not greater than a self-test high threshold (such as the low threshold H1 in the above table), the first test result identifier is determined as the self-test performance stability identifier (such as the marking result 1-3 in the above table); wherein the self-test low threshold is the product of the preset self-test index and a second parameter, and the second parameter is greater than 1; and if the current self-test index is greater than the self-test high threshold, the first test result identifier is determined as the self-test performance improvement identifier (such as the marking result 1-4 in the above table). Figure 3 Figure 3 Figure 3 Figure 3 Figure 3

[0066] Correspondingly, when the preset self-test result identifier also includes the self-test failure identifier, the process of performing the performance self-test of the target hardware simulation model to obtain the current self-test index of the performance self-test can include: performing the performance self-test of the target hardware simulation model, judging whether the performance self-test is successfully completed, such as detecting whether the first keyword exists in the log corresponding to the performance self-test; if the performance self-test is successfully completed, the current self-test index of the performance self-test is obtained; and if the performance self-test cannot be successfully completed, the first test result identifier is determined as the self-test failure identifier (such as the marking result 1-1 in the above table).​​​​​Figure 3

[0067] Wherein, the embodiment does not limit the specific data type of the current self-test index, for example, the current self-test index can be IOPS (the number of read and write operations per second), for example, in the embodiment, FIO (a kind of open source disk IO stress test tool) test can be carried out in performance self-test process, and the obtained IOPS is taken as the current self-test index;For example, the IOPS of this test is 10, and the storage current self-test index P1=10.If the simulation test time is taken as the performance test result of performance self-test, for the convenience of unified comparison, the simulation test time is converted into performance score as the current self-test index, for example, performance score=C / simulation test time, C is a preset constant, for adjusting the numerical range of performance score;That is, the current self-test index can also be performance score, and the performance score is the quotient of the preset constant and the simulation test time of performance self-test.

[0068] Correspondingly, the embodiment does not limit the specific parameter value of the first parameter and the second parameter, for example, the first parameter can be the difference between 1 and the parameter factor (α), that is, the self-test low threshold L1=P2(1-α), P2 is a preset self-test index;The second parameter can be the sum of 1 and the parameter factor, that is, the self-test high threshold H1=P2(1+α);For example, FIO test is adopted, and IOPS is taken as the current self-test index, the IOPS of the historical self-test index (that is, the preset self-test index) is 10, that is, P2=10, the performance index is allowed to float by 10%, that is, α=10%, the self-test high threshold is set to 11, and the self-test low threshold is set to 9.

[0069] Correspondingly, as shown in Figure 2 The initialization configuration module can also be used to configure the parameter factor (α), so that the configuration unit can obtain the parameter factor and the preset self-test index (P2) from the data storage module, complete the configuration of the self-test low threshold (L1) and the self-test high threshold (H1), and facilitate the performance self-test of the subsequent self-test unit (hardware simulation model performance self-test unit).

[0070] Step 102: according to the target hardware simulation model and the target chip firmware, performing simulation system comprehensive test, obtaining the second test result identifier;Wherein, the target chip firmware is any preset chip firmware, and the second test result identifier is any preset comprehensive test result identifier.

[0071] ​It can be understood that the target chip firmware in this embodiment can be a chip firmware used by a chip simulation system that needs to detect performance, such as a latest version of chip firmware currently running. Each preset chip firmware in this embodiment can be a preset version of chip firmware; the specific number and content of the preset chip firmware in this embodiment can be set by the designer according to the use scenario and user demand, such as the preset hardware simulation model can include the latest version of chip firmware currently used by the chip simulation system and the last version of chip firmware (or a preset version of chip firmware) used last time, and can also include other versions of chip firmware. This embodiment does not make any limitation on this.

[0072] Correspondingly, the specific selection of the target chip firmware in this embodiment can be set by the designer according to the use scenario and user demand, such as the target chip firmware can be the latest version of hardware chip firmware, that is, the chip firmware currently used by the chip simulation system that needs to detect performance; for example, the performance of the current chip simulation system can be periodically detected at a preset time interval in this step. The target chip firmware can also be any chip firmware selected by the user according to the demand, such as the target chip firmware and the target hardware simulation model corresponding to the manual trigger instruction can be executed in this step to perform simulation system comprehensive testing to obtain a second test result identifier, so that the test can adapt to different development scenarios and demands.

[0073] It should be noted that the simulation system comprehensive testing in this embodiment can be used to perform overall performance evaluation on the target hardware simulation model and the target chip firmware, and can be based on a preset typical business scenario (i.e., a preset business scenario); during the testing process, the target hardware simulation model and the target chip firmware will communicate and interact with each other, so as to comprehensively reflect the comprehensive performance of the chip simulation system; that is, the simulation system comprehensive testing includes the communication and interaction process between the target hardware simulation model and the target chip firmware.

[0074] Further, a second keyword can be set at the end of the execution of the simulation system comprehensive testing in this embodiment to facilitate the determination of whether the simulation system comprehensive testing is successfully completed, that is, if the second keyword is detected during the execution process or after the end of the simulation system comprehensive testing, it is determined that the simulation system comprehensive testing is successfully completed. In order to facilitate subsequent performance analysis, the business flow logic of the simulation system comprehensive testing can be divided into a plurality of sub-flows (i.e., business logic sub-flows) in this embodiment, so as to record the time stamp at the key node, so that the key node time stamp of each sub-flow can be recorded in the log during the execution process of the simulation system comprehensive testing.

[0075] Correspondingly, the step can perform a simulation system comprehensive test according to the target hardware simulation model and the target chip firmware, and record a log to obtain a second test result identifier; wherein the simulation system comprehensive test comprises a communication interaction process of the target hardware simulation model and the target chip firmware under a preset business scenario, and the log is used to record a key node timestamp of each business logic sub-process in the simulation system comprehensive test, so as to facilitate subsequent performance analysis.

[0076] Correspondingly, the second test result identifier in the embodiment can be any preset comprehensive test result identifier, and the preset comprehensive test result identifier can comprise at least two of a comprehensive test failure identifier, a comprehensive test performance decline identifier, a comprehensive test performance stability identifier, and a comprehensive test performance improvement identifier. For the specific manner of performing a simulation system comprehensive test according to the target hardware simulation model and the target chip firmware to obtain a second test result identifier in the step, a designer can set it according to practical scenarios and user needs, such as performing a simulation system comprehensive test by using the target hardware simulation model and the target chip firmware to obtain a current comprehensive test index of the simulation system comprehensive test; and obtaining the second test result identifier according to the current comprehensive test index and a preset comprehensive test index. The preset comprehensive test index can be a preset comprehensive test index, such as a last simulation system comprehensive test index (i.e. a historical comprehensive test index), so as to determine the second test result identifier by comparing the current comprehensive test index with the preset comprehensive test index. The second test result identifier can also be determined by directly comparing the current comprehensive test index with a fixed threshold. The embodiment does not make any limitation on this.

[0077] For example, when the preset comprehensive test result identifier comprises a comprehensive test performance decline identifier, a comprehensive test performance stability identifier, and a comprehensive test performance improvement identifier, the process of obtaining the second test result identifier according to the current comprehensive test index and the preset comprehensive test index can comprise: if the current comprehensive test index is not greater than a comprehensive test low threshold (such as a low threshold L2 in Figure 4 ), it is determined that the second test result identifier is the comprehensive test performance decline identifier (such as a marking result 2-2 in Figure 4 ); wherein the comprehensive test low threshold is a product of the preset comprehensive test index and a third parameter, and the third parameter is less than 1; if the current comprehensive test index is greater than the comprehensive test low threshold and not greater than a comprehensive test high threshold (such as a high threshold H2 in Figure 4 ), it is determined that the second test result identifier is the comprehensive test performance stability identifier (such as a marking result 2-3 in Figure 4 ); wherein the comprehensive test low threshold is a product of the preset comprehensive test index and a fourth parameter, and the fourth parameter is greater than 1; and if the current comprehensive test index is greater than the comprehensive test high threshold, it is determined that the second test result identifier is the comprehensive test performance improvement identifier (such as a marking result 2-4 in Figure 4 ).

[0078] Correspondingly, when the preset comprehensive test result identifier further includes a comprehensive test failure identifier, the process of executing the simulation system comprehensive test by using the target hardware simulation model and the target chip firmware to obtain the current comprehensive test index of the simulation system comprehensive test can include: executing the simulation system comprehensive test by using the target hardware simulation model and the target chip firmware, and determining whether the simulation system comprehensive test is successfully completed, such as whether the second keyword exists in the log corresponding to the simulation system comprehensive test; if the simulation system comprehensive test is successfully completed, obtaining the current comprehensive test index of the simulation system comprehensive test; if the simulation system comprehensive test cannot be successfully completed, determining that the second test result identifier is a comprehensive test failure identifier (such as Figure 4 the marking result 2-1 in FIG. 1B).

[0079] Similarly, the present embodiment does not limit the specific data type of the current comprehensive test index. For example, the current comprehensive test index can use IOPS (the number of read and write operations per second) and / or performance score. The present embodiment does not limit the specific parameter values of the third parameter and the fourth parameter. For example, the third parameter can be the difference between 1 and the parameter factor (a), that is, the comprehensive test low threshold L2=P4(1-a), and P4 is the preset comprehensive test index; the fourth parameter can be the sum of 1 and the parameter factor, that is, the comprehensive test high threshold H2=P4(1+a).

[0080] Correspondingly, when the preset self-test result identifier includes a self-test failure identifier or a self-test performance decline identifier, the first test result identifier can be a self-test failure identifier or a self-test performance decline identifier, and the corresponding performance detection result can be directly output without executing the simulation system comprehensive test, thereby avoiding waste of processing resources. For example, when the preset self-test result identifier includes a self-test failure identifier, a self-test performance decline identifier, a self-test performance stable identifier, and a self-test performance improvement identifier, if the first test result identifier is a self-test performance stable identifier or a self-test performance improvement identifier, the second test result identifier is obtained by executing the simulation system comprehensive test according to the target hardware simulation model and the target chip firmware; if the first test result identifier is a self-test failure identifier, a hardware simulation model self-test failure result is output; and if the first test result identifier is a self-test performance decline identifier, a hardware simulation model change causes performance decline result is output.

[0081] Step 103: determining and outputting a target system test result according to the first test result identifier and the second test result identifier; wherein the target system performance test result is any preset performance test result.

[0082] It can be understood that the performance detection result of the chip simulation system (i.e., the target system test result) can be determined and output according to the two test result identifiers (i.e., the first test result identifier and the second test result identifier) obtained from the performance self-test of the target hardware simulation model and the simulation system comprehensive test, so as to realize the automatic detection of the performance of the chip simulation system.

[0083] Correspondingly, the target system test result in the embodiment can be one preset performance test result corresponding to the first test result identifier and the second test result identifier. The specific number and content of the preset performance test result in the embodiment can be set by the designer according to the practical scene and user demand, for example, the preset performance test result can include at least two of the simulation system comprehensive performance test failure result, the simulation system performance state stability result, the simulation system performance state improvement result, the simulation system comprehensive performance decline result, the hardware simulation model self-test failure result, and the hardware simulation model change caused performance decline result.

[0084] For example, when the preset self-test result identifier includes the self-test performance stability identifier and the self-test performance improvement identifier, and the preset comprehensive test result identifier includes the comprehensive test failure identifier, the comprehensive test performance decline identifier, the comprehensive test performance stability identifier, and the comprehensive test performance improvement identifier, the step can determine the target system test result as the simulation system comprehensive performance test failure result and output the target system test result when the first test result identifier is the self-test performance stability identifier or the self-test performance improvement identifier and the second test result identifier is the comprehensive test failure identifier; determine the target system test result as the simulation system performance state stability result and output the target system test result when the first test result identifier is the self-test performance stability identifier or the self-test performance improvement identifier and the second test result identifier is the comprehensive test performance stability identifier; determine the target system test result as the simulation system performance state improvement result and output the target system test result when the first test result identifier is the self-test performance stability identifier or the self-test performance improvement identifier and the second test result identifier is the comprehensive test performance improvement identifier; and determine the target system test result as the simulation system comprehensive performance decline result and output the target system test result when the first test result identifier is the self-test performance stability identifier or the self-test performance improvement identifier and the second test result identifier is the comprehensive test performance decline identifier.

[0085] Further, in the case that the target system test result is a simulation system comprehensive performance decline result, the embodiment can also output the reason for the simulation system comprehensive performance decline, such as the comprehensive performance decline caused by the change of interaction between models (i.e., between the hardware simulation model and the CPU model loading and running the chip firmware) or the comprehensive performance decline caused by the change of chip firmware logic. For example, the process of determining that the target system test result is a simulation system comprehensive performance decline result and outputting the target system test result can include: after determining that the target system test result is a simulation system comprehensive performance decline result, performing a performance self-test of a preset historical hardware simulation model to obtain a third test result identifier; performing a simulation system comprehensive test according to the preset historical hardware simulation model and the target chip firmware to obtain a fourth test result identifier; determining a historical system test result according to the third test result identifier and the fourth test result identifier; if the historical system test result is a target simulation system performance state stable result, outputting the target system test result and a first comprehensive performance decline reason; wherein the target simulation system performance state stable result is a simulation system performance state stable result corresponding to the self-test performance stable identifier and the comprehensive test performance stable identifier; the first comprehensive performance decline reason is the comprehensive performance decline caused by the change of interaction between models; if the historical system test result is a simulation system comprehensive performance decline result, outputting the target system test result and a second comprehensive performance decline reason; wherein the second comprehensive performance decline reason is the comprehensive performance decline caused by the change of chip firmware logic. That is, in the embodiment, the performance detection result (i.e., the historical system test result) obtained by using the hardware simulation model of the last performance detection (i.e., the preset historical hardware simulation model) and the latest chip firmware (i.e., the target chip firmware) can be used to determine the cause of the performance decline: when the historical system test result is a simulation system comprehensive performance decline result, the cause of the performance decline is the change of chip firmware logic; and when the historical system test result is a simulation system performance state stable result corresponding to the self-test performance stable identifier and the comprehensive test performance stable identifier, the cause of the performance decline is the change of interaction between the hardware simulation model and the CPU model.

[0086] For example, as Figure 3 and Figure 4As shown, the preset self-test result identifier can include a marked result 1-1 (i.e., a self-test failure identifier), a marked result 1-2 (i.e., a self-test performance decline identifier), a marked result 1-3 (i.e., a self-test performance stability identifier), and a marked result 1-4 (a self-test performance improvement identifier); the marked result 1-1 is used to indicate that the hardware simulation model performance self-test fails; the marked result 1-2 is used to indicate that, based on the performance self-test, the hardware simulation model performance declines; the marked result 1-3 is used to indicate that, based on the performance self-test, the hardware simulation model performance is relatively stable; and the marked result 1-4 is used to indicate that, based on the performance self-test, the hardware simulation model performance improves. The preset comprehensive test result identifier can include a marked result 2-1 (i.e., a comprehensive test failure identifier), a marked result 2-2 (i.e., a comprehensive test performance decline identifier), a marked result 2-3 (i.e., a comprehensive test performance stability identifier), and a marked result 2-4 (a comprehensive test performance improvement identifier); the marked result 2-1 is used to indicate that the simulation system comprehensive performance test fails; the marked result 2-2 is used to indicate that, based on the simulation system comprehensive test, the chip simulation system performance declines; the marked result 2-3 is used to indicate that, based on the simulation system comprehensive test, the chip simulation system performance is relatively stable; and the marked result 2-4 is used to indicate that, based on the simulation system comprehensive test, the chip simulation system performance improves.

[0087] Since the two tests of the target hardware simulation model performance self-test and the simulation system comprehensive test are directed to different test subjects, i.e., the hardware simulation model and the chip simulation system including the hardware simulation model and the CPU model. Table 1 shows a performance test result marking combination table, which has a total of 10 possible combination situations, which to some extent reflects the current performance change of the hardware simulation model and the chip simulation system.

[0088] Table 1 Performance test result marking combination table

[0089]

[0090] As shown in Table 1, flag1 can be a hardware simulation model self-test failure result, used to indicate that the performance self-test of the target hardware simulation model fails, and the subsequent simulation system comprehensive test can not be performed. The hardware simulation model self-test failure result can be output to a log (such as the self-test log described above), so that the key node timestamps of each business logic sub-flow in the performance self-test are recorded, facilitating subsequent problem positioning. Flag2 can be a hardware simulation model change causing performance degradation result, used to indicate that the hardware simulation model change causes performance degradation, and the subsequent simulation system comprehensive test can not be performed. The self-test log can be output to facilitate subsequent users to use the key node timestamps of each business logic sub-flow in the performance self-test to mark and analyze sub-flows with relatively high time consumption, helping to troubleshoot the cause of the performance reduction of the hardware simulation model. Flags 3 and 7 can be simulation system comprehensive performance test failure results, used to indicate that the simulation system comprehensive test fails, and the simulation system comprehensive performance test failure result can be output to a log to facilitate subsequent problem positioning. Flags 5 and 9 can be simulation system performance state stable results, used to indicate that the performance state of the chip simulation system is relatively stable. Flags 6 and 10 can be simulation system performance state improvement results, used to indicate that the performance state of the chip simulation system has improved.

[0091] Correspondingly, flags 4 and 8 in Table 1 can be simulation system comprehensive performance degradation results, used to indicate that the performance state of the simulation system comprehensive test has degraded, that is, the performance indicators of the performance self-test are relatively stable or have improved, while the performance indicators of the simulation system comprehensive test have degraded. There are two possible causes for this situation: (1) logic change of the chip firmware (2) interaction change between the hardware simulation model and the CPU model. When the target system test result is flag4 and flag8, the embodiment can use the hardware simulation model of the last performance test (i.e., the preset historical hardware simulation model) and the latest chip firmware (i.e., the target chip firmware) to perform re-detection, and when the performance detection result (i.e., the historical system test result) obtained is flag4 or flag8, it is determined that the cause of the performance degradation is the logic change of the chip firmware. When the historical system test result is flag5, it is determined that the cause of the performance degradation is the interaction change between the hardware simulation model and the CPU model, thereby outputting the target system test result and the corresponding comprehensive performance degradation cause, which can more accurately determine the cause of the performance degradation problem.

[0092] Correspondingly, for the specific output mode of the target system test result in this step, the designer can set it himself, such as directly displaying the target system test result, or outputting the target system test result to a corresponding log, such as a performance analysis unit (such as Figure 2The performance preliminary analysis unit in the performance self-test unit 10) can determine the target system test result according to the first test result identifier and the second test result identifier, and output the target system test result to the corresponding work log. Correspondingly, the method provided in the embodiment can also include a log output process, such as outputting the log of the performance self-test, the log of the comprehensive performance test of the simulation system, and / or the work log of the performance analysis unit according to user demand.

[0093] Further, the target hardware simulation model, the target chip firmware, the current self-test index, and the current comprehensive test index can also be stored in the embodiment to facilitate subsequent performance detection. For example, when the target system test result is the simulation system performance state stable result or the simulation system performance state improvement result (such as the flag 5, 6, 9, or 10 described above), the target hardware simulation model, the target chip firmware, the current self-test index, and the current comprehensive test index are used to update the stored historical hardware simulation model, the historical chip firmware, the historical self-test index, and the historical comprehensive test index. For example, Figure 2 As shown in the figure, the data storage updating unit can be used to update the storage data of the data storage magic armor, and the updating is performed only when the target system test result is the flag 5, 6, 9, or 10.

[0094] In the embodiment, the performance self-test and the comprehensive performance test of the simulation system are used to respectively evaluate the performance of the hardware simulation model and the chip simulation system, which can indirectly realize the separation test of the hardware and the firmware, and ensure the accuracy of the performance detection of the chip simulation system. The target system test result is determined and output according to the first test result identifier and the second test result identifier, which can automatically analyze and determine the performance state of the chip simulation system based on the identifiers output by the two tests, realize the automatic detection of the performance of the chip simulation system, and thus can timely capture the abnormal situation of performance decline and improve the chip development efficiency.

[0095] Corresponding to the method embodiment above, the embodiment of the application also provides a chip simulation system performance detection device. The chip simulation system performance detection device described below can be correspondingly referred to the chip simulation system performance detection method described above.

[0096] Please refer to Figure 5 , Figure 5 The structure block diagram of the chip simulation system performance detection device provided in the embodiment of the application. The device can include:

[0097] The self-test unit 10 is configured to perform the performance self-test of the target hardware simulation model, and obtain the first test result identifier; wherein the target hardware simulation model is any preset hardware simulation model, and the first test result identifier is any preset self-test result identifier.

[0098] The comprehensive test unit 20 is configured to perform a simulation system comprehensive test according to the target hardware simulation model and the target chip firmware, and obtain a second test result identifier; the target chip firmware is any preset chip firmware, and the second test result identifier is any preset comprehensive test result identifier.

[0099] The performance analysis unit 30 is configured to determine and output a target system test result according to the first test result identifier and the second test result identifier; the target system performance test result is any preset performance test result.

[0100] In some embodiments, the self-test unit 10 can include:

[0101] The execution subunit is configured to perform a performance self-test of the target hardware simulation model, and obtain a current self-test index of the performance self-test; the performance self-test is used for firmware splicing of the target hardware simulation model.

[0102] The determination subunit is configured to obtain the first test result identifier according to the current self-test index and a preset self-test index.

[0103] In some embodiments, the preset self-test result identifier includes a self-test failure identifier, a self-test performance decline identifier, a self-test performance stability identifier, and a self-test performance improvement identifier.

[0104] The execution subunit can be specifically configured to perform the performance self-test of the target hardware simulation model, determine whether the performance self-test is successfully completed, obtain the current self-test index of the performance self-test if the performance self-test is successfully completed, and determine that the first test result identifier is the self-test failure identifier if the performance self-test cannot be successfully completed.

[0105] The determination subunit can be specifically configured to determine that the first test result identifier is the self-test performance decline identifier if the current self-test index is not greater than a self-test low threshold value, determine that the first test result identifier is the self-test performance stability identifier if the current self-test index is greater than the self-test low threshold value and not greater than a self-test high threshold value, and determine that the first test result identifier is the self-test performance improvement identifier if the current self-test index is greater than the self-test high threshold value; the self-test low threshold value is a product of the preset self-test index and a first parameter, and the first parameter is less than 1; the self-test low threshold value is a product of the preset self-test index and a second parameter, and the second parameter is greater than 1.

[0106] In some embodiments, the comprehensive test unit 20 can include:

[0107] The comprehensive execution subunit is configured to perform a simulation system comprehensive test according to the target hardware simulation model and the target chip firmware if the first test result identifier is the self-test performance stability identifier or the self-test performance improvement identifier, and obtain a second test result identifier.

[0108] a failure output subunit configured to output a hardware simulation model self-test failure result if the first test result identifier is a self-test failure identifier;

[0109] a performance decline output subunit configured to output a hardware simulation model performance decline result caused by variation if the first test result identifier is a self-test performance decline identifier.

[0110] In some embodiments, the current self-test indicator is a performance score and / or a number of read-write operations per second; wherein the performance score is a quotient of a preset constant and a simulation test time.

[0111] In some embodiments, the comprehensive test unit 20 can be specifically configured to perform a simulation system comprehensive test and record a log according to the target hardware simulation model and the target chip firmware to obtain a second test result identifier; wherein the simulation system comprehensive test comprises a communication interaction process of the target hardware simulation model and the target chip firmware under a preset business scenario, and the log is used to record a key node timestamp of each business logic sub-process in the simulation system comprehensive test.

[0112] In some embodiments, the preset self-test result identifier comprises a self-test performance stable identifier and a self-test performance improvement identifier; and the preset comprehensive test result identifier comprises a comprehensive test failure identifier, a comprehensive test performance decline identifier, a comprehensive test performance stable identifier, and a comprehensive test performance improvement identifier.

[0113] The performance analysis unit 30 can comprise:

[0114] a first determination subunit configured to determine that the target system test result is a simulation system comprehensive performance test failure result and output the target system test result if the first test result identifier is a self-test performance stable identifier or a self-test performance improvement identifier, and the second test result identifier is a comprehensive test failure identifier;

[0115] a second determination subunit configured to determine that the target system test result is a simulation system performance state stable result and output the target system test result if the first test result identifier is a self-test performance stable identifier or a self-test performance improvement identifier, and the second test result identifier is a comprehensive test performance stable identifier;

[0116] a third determination subunit configured to determine that the target system test result is a simulation system performance state improvement result and output the target system test result if the first test result identifier is a self-test performance stable identifier or a self-test performance improvement identifier, and the second test result identifier is a comprehensive test performance improvement identifier;

[0117] The fourth determination subunit is configured to determine that the target system test result is a simulation system comprehensive performance decline result and output the target system test result if the first test result identifier is the self-test performance stability identifier or the self-test performance improvement identifier and the second test result identifier is the comprehensive test performance decline identifier.

[0118] In some embodiments, the fourth determination subunit can be specifically configured to perform performance self-test on the preset historical hardware simulation model after determining that the target system test result is the simulation system comprehensive performance decline result, obtain a third test result identifier; perform simulation system comprehensive test according to the preset historical hardware simulation model and the target chip firmware, obtain a fourth test result identifier; determine a historical system test result according to the third test result identifier and the fourth test result identifier; output the target system test result and a first comprehensive performance decline reason if the historical system test result is a target simulation system performance state stability result; output the target system test result and a second comprehensive performance decline reason if the historical system test result is the simulation system comprehensive performance decline result; wherein the target simulation system performance state stability result is a simulation system performance state stability result corresponding to the self-test performance stability identifier and the comprehensive test performance stability identifier; the first comprehensive performance decline reason is a comprehensive performance decline caused by model interaction change; and the second comprehensive performance decline reason is a comprehensive performance decline caused by chip firmware logic change.

[0119] In this embodiment, the performance self-test of the self-test unit 10 and the simulation system comprehensive test of the comprehensive test unit 20 can respectively evaluate the performance of the hardware simulation model and the chip simulation system as a whole, indirectly realize the separation test of the hardware and the firmware, and ensure the accuracy of the performance detection of the chip simulation system; and the performance analysis unit 30 can determine and output the target system test result according to the first test result identifier and the second test result identifier, automatically analyze and determine the performance state of the chip simulation system based on the identifiers output by the two tests, realize the automatic detection of the performance of the chip simulation system, and thus can timely capture the abnormal situation of performance decline and improve the chip development efficiency.

[0120] Corresponding to the above method embodiments, the embodiments of the present application also provide a chip simulation system performance detection device. The chip simulation system performance detection device described below can be mutually corresponding to the chip simulation system performance detection method described above.

[0121] Please refer to Figure 6 , Figure 6 The chip simulation system performance detection device provided by the embodiments of the present application is shown in the structure diagram. The device can include:

[0122] The memory D1 is configured to store a computer program.

[0123] Processor D2, configured to implement the steps of the chip simulation system performance detection method provided by the above method embodiments when executing the computer program.

[0124] In this embodiment, the chip simulation system performance detection device can be a computer or a server, such as a server running a chip simulation system.

[0125] Corresponding to the above method embodiments, the embodiments of the present application also provide a computer readable storage medium, and the computer readable storage medium described below can be mutually corresponding to the chip simulation system performance detection method described above.

[0126] Please refer to Figure 7 , Figure 7 The structure of a computer readable storage medium provided by the embodiments of the present application is shown in the figure. The computer readable storage medium 40 stores a computer program 41, and the computer program 41 is executed by a processor to implement the steps of the chip simulation system performance detection method provided by the above method embodiments.

[0127] The computer readable storage medium can be a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various readable storage media that can store program codes.

[0128] Corresponding to the above method embodiments, the embodiments of the present application also provide a computer program product, and the computer program product described below can be mutually corresponding to the chip simulation system performance detection method described above.

[0129] A computer program product, comprising a computer program / instruction, which is executed by a processor to implement the steps of the chip simulation system performance detection method provided by the above method embodiments.

[0130] The embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts of each embodiment can be mutually referred to. For the device, equipment, computer readable storage medium and computer program product disclosed in the embodiments, since they correspond to the method disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method part.

[0131] The performance detection method, device and computer readable storage medium of the chip simulation system provided by the present application are described in detail above. The principles and implementation modes of the present application are described by applying specific examples in this paper, and the above description of the embodiments is only used to help understand the method of the present application and its core idea. It should be pointed out that, for ordinary skilled persons in the technical field, some improvements and modifications can be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the protection scope of the present application.

Claims

1. A performance detection method for a chip simulation system, characterized in that: include: Execute a performance self-test of a target hardware simulation model to obtain a first test result identifier; wherein the target hardware simulation model is any preset hardware simulation model, and the first test result identifier is any preset self-test result identifier; Performing a simulation system comprehensive test according to the target hardware simulation model and the target chip firmware to obtain a second test result identifier; wherein the target chip firmware is any preset chip firmware, and the second test result identifier is any preset comprehensive test result identifier; According to the first test result identifier and the second test result identifier, a target system test result is determined and output; wherein the target system performance test result is any preset performance test result.

2. The performance detection method of the chip simulation system according to claim 1, characterized in that: The performing of the performance self-test of the target hardware simulation model to obtain a first test result identifier includes: Executing a performance self-test of the target hardware simulation model to obtain a current self-test indicator of the performance self-test; wherein the performance self-test is used to perform firmware stubbing on the target hardware simulation model; The first test result identifier is obtained according to the current self-test indicator and the preset self-test indicator.

3. The performance detection method of the chip simulation system according to claim 2, characterized in that: The preset self-test result identifiers include: self-test failure identifier, self-test performance degradation identifier, self-test performance stability identifier, and self-test performance improvement identifier; The performing of the performance self-test of the target hardware simulation model to obtain a current self-test indicator of the performance self-test includes: Executing a performance self-test of the target hardware simulation model to determine whether the performance self-test is successfully completed; If completed successfully, obtaining the current self-test indicator of the performance self-test; If the test cannot be completed successfully, determining the first test result identifier as the self-test failure identifier; The obtaining of the first test result identifier according to the current self-test indicator and the preset self-test indicator includes: If the current self-test indicator is not greater than a self-test low threshold, determining that the first test result identifier is the self-test performance degradation identifier; wherein the self-test low threshold is the product of the preset self-test indicator and a first parameter, and the first parameter is less than 1; If the current self-test indicator is greater than the self-test low threshold and not greater than the self-test high threshold, determining that the first test result identifier is the self-test performance stable identifier; wherein the self-test low threshold is the product of the preset self-test indicator and a second parameter, and the second parameter is greater than 1; If the current self-test indicator is greater than the self-test high threshold, the first test result identifier is determined to be the self-test performance improvement identifier.

4. The performance detection method of the chip simulation system according to claim 3, characterized in that: The step of performing a comprehensive test of the simulation system according to the target hardware simulation model and the target chip firmware to obtain a second test result identifier includes: If the first test result identifier is the self-test performance stable identifier or the self-test performance improved identifier, performing the simulation system comprehensive test according to the target hardware simulation model and the target chip firmware to obtain the second test result identifier; If the first test result identifier is the self-test failure identifier, outputting a hardware simulation model self-test failure result; If the first test result identifier is the self-test performance degradation identifier, a performance degradation result caused by a change in the hardware simulation model is output.

5. The performance detection method of the chip simulation system according to claim 2, characterized in that: The current self-test indicator is a performance score and / or the number of read and write operations performed per second; wherein the performance score is the quotient of a preset constant and the simulation test time.

6. The performance detection method of the chip simulation system according to claim 1, characterized in that: The step of performing a comprehensive test of the simulation system according to the target hardware simulation model and the target chip firmware to obtain a second test result identifier includes: According to the target hardware simulation model and the target chip firmware, the simulation system comprehensive test is executed and a log is recorded to obtain the second test result identifier; wherein, the simulation system comprehensive test includes the communication interaction process between the target hardware simulation model and the target chip firmware under a preset business scenario, and the log is used to record the key node timestamps of each business logic sub-process in the simulation system comprehensive test.

7. The performance detection method of a chip simulation system according to any one of claims 1 to 6, characterized in that: The preset self-test result identifiers include: a self-test performance stable identifier and a self-test performance improvement identifier; the preset comprehensive test result identifiers include: a comprehensive test failure identifier, a comprehensive test performance degradation identifier, a comprehensive test performance stable identifier, and a comprehensive test performance improvement identifier; The determining and outputting the target system test result according to the first test result identifier and the second test result identifier includes: If the first test result identifier is the self-test performance stable identifier or the self-test performance improved identifier, and the second test result identifier is the comprehensive test failure identifier, then determining that the target system test result is a simulation system comprehensive performance test failure result, and outputting the target system test result; If the first test result identifier is the self-test performance stable identifier or the self-test performance improvement identifier, and the second test result identifier is the comprehensive test performance stable identifier, then determining that the target system test result is a simulation system performance state stable result, and outputting the target system test result; If the first test result identifier is the self-test performance stabilization identifier or the self-test performance improvement identifier, and the second test result identifier is the comprehensive test performance improvement identifier, then determining that the target system test result is a simulation system performance status improvement result, and outputting the target system test result; If the first test result identifier is the self-test performance stability identifier or the self-test performance improvement identifier, and the second test result identifier is the comprehensive test performance degradation identifier, then the target system test result is determined to be a simulation system comprehensive performance degradation result, and the target system test result is output.

8. The performance detection method of the chip simulation system according to claim 7, characterized in that: Determining that the target system test result is a result of degradation of the comprehensive performance of the simulation system and outputting the target system test result includes: After determining that the target system test result is a result of degradation of the comprehensive performance of the simulation system, executing a performance self-test of a preset historical hardware simulation model to obtain a third test result identifier; Performing a simulation system comprehensive test according to the preset historical hardware simulation model and the target chip firmware to obtain a fourth test result identifier; Determining a historical system test result according to the third test result identifier and the fourth test result identifier; If the historical system test result is a target simulation system performance state stability result, the target system test result and the first comprehensive performance degradation reason are output; wherein the target simulation system performance state stability result is the simulation system performance state stability result corresponding to the self-test performance stability flag and the comprehensive test performance stability flag; the first comprehensive performance degradation reason is the comprehensive performance degradation caused by the interaction change between models; If the historical system test result is a result of a degradation in the comprehensive performance of the simulation system, the target system test result and a second reason for the degradation in comprehensive performance are output; wherein the second reason for the degradation in comprehensive performance is a degradation in comprehensive performance caused by a change in chip firmware logic.

9. A performance detection device for a chip simulation system, characterized in that: include: A self-test unit, configured to perform a performance self-test of a target hardware simulation model and obtain a first test result identifier; wherein the target hardware simulation model is any preset hardware simulation model, and the first test result identifier is any preset self-test result identifier; A comprehensive test unit, configured to perform a simulation system comprehensive test based on the target hardware simulation model and the target chip firmware, and obtain a second test result identifier; wherein the target chip firmware is any preset chip firmware, and the second test result identifier is any preset comprehensive test result identifier; The performance analysis unit is used to determine and output a target system test result based on the first test result identifier and the second test result identifier; wherein the target system performance test result is any preset performance test result.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the performance detection method of the chip simulation system according to any one of claims 1 to 8.

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