Queue circuit, processor, computer device, chip product and method

Abstract

The invention discloses a queue circuit, a processor, computer equipment, a chip product and a method, and relates to the technical field of electronics. The queue circuit comprises a signal receiving unit, an index queue and a storage unit, indexes of N requests are stored in the index queue, and information carried by the N requests respectively is stored in the storage unit; the signal receiving unit is used for receiving a queue updating signal, and the queue updating signal carries a first index; the storage unit is used for outputting information carried by a first request under the condition that the first request in the N requests meets an output condition; wherein the output condition comprises that the first request is a first index request of which the carried information is firstly written into a storage unit in M first index requests contained in the N requests, and the first index request refers to a request of which the index is a first index. According to the scheme, the information carried by each request aiming at the same object is returned to the upstream (the receiving party of the output of the queue circuit) according to the write-in sequence.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of electronics, and particularly relate to a queue circuit, a processor, a computer device, a chip product and a method. BACKGROUND

[0002] In some chip products (such as a processor chip), after a request initiator (hereinafter referred to as an upstream) initiates a request to a request responder (hereinafter referred to as a downstream), the upstream will temporarily store data carried by the request in a queue circuit of the chip, and only when the data carried by a certain request in the queue circuit is returned to the upstream, the request processing is marked as completed.

[0003] Therefore, the order of the data returned by the queue circuit will affect the processing logic of the upstream, and how to reasonably design the queue circuit needs further research. SUMMARY

[0004] Embodiments of the present application provide a queue circuit, a processor, a computer device, a chip product and a method. The technical solutions provided by the embodiments of the present application are as follows: According to an aspect of the embodiments of the present application, a queue circuit is provided, the queue circuit comprising a signal receiving unit, an index queue and a storage unit, wherein the index queue stores indexes of N requests, the index of the request is used to indicate an object to which the request is directed, and the storage unit stores information carried by the N requests respectively, N being a positive integer; The signal receiving unit is configured to receive a queue update signal, the queue update signal carrying a first index, the first index belonging to an index of a processed request; The storage unit is configured to output information carried by a first request in the N requests in a case where the first request meets an output condition, wherein the output condition comprises that the first request is a first index request in M first index requests included in the N requests, and information carried by the first index request is written into the storage unit first, the first index request being a request with the first index, and M being a positive integer less than or equal to N.

[0005] According to an aspect of the embodiments of the present application, a processor is provided, the processor comprising the above queue circuit.

[0006] According to an aspect of the embodiments of the present application, a computer device is provided, the computer device comprising a processor, the processor comprising the above queue circuit.

[0007] According to an aspect of the embodiments of the present application, a chip product is provided, the chip product comprising the above queue circuit.

[0008] According to an aspect of an embodiment of the present application, a queue circuit-based information processing method is provided. The queue circuit includes a signal receiving unit, an index queue, and a storage unit. The index queue stores N request indexes, the request indexes being used to indicate objects to which the requests are directed. The storage unit stores information carried by the N requests respectively. N is a positive integer. The method includes: The signal receiving unit receives a queue update signal. The queue update signal carries a first index. The first index belongs to the indexes of processed requests. The storage unit outputs information carried by a first request in the N requests when the first request meets an output condition. The output condition includes that the first request is a first index request in which information carried by M first index requests included in the N requests is written into the storage unit first. The first index request refers to a request with the first index. M is a positive integer less than or equal to N.

[0009] The technical scheme provided by the embodiment of the present application has at least the following beneficial effects: For a queue circuit that stores N request indexes (in an index queue of the queue circuit) and information carried by the N requests respectively (in a storage unit of the queue circuit), the signal receiving unit of the queue circuit is designed to output information carried by a first request when the first request is a first index request in which information carried by M first index requests included in the N requests is written into the storage unit first. The data carried by requests with the same index in the queue circuit is output in sequence. Since the request index is used to indicate an object to which the request is directed, the above scheme ensures that information carried by requests directed to the same object is returned to an upstream (a receiver of an output of the queue circuit) in writing order, thereby ensuring the correctness of the processing logic of the upstream. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 FIG. 1 is a schematic diagram of a circuit structure including an upstream and a downstream provided by an embodiment of the present application; Figure 2 FIG. 2 is a structural schematic diagram of a queue circuit provided by an embodiment of the present application; Figure 3 FIG. 3 is a schematic diagram of a first preparation signal generation process provided by an embodiment of the present application; Figure 4 FIG. 4 is a schematic diagram of a second preparation signal generation process provided by an embodiment of the present application; Figure 5is a schematic diagram of a shift process of a pointer stored in a pointer queue provided by an embodiment of the present application; Figure 6 is a flow chart of an information processing method based on a queue circuit provided by an embodiment of the present application; Figure 7 is a flow chart of an information processing method based on a queue circuit provided by another embodiment of the present application. DETAILED DESCRIPTION

[0011] In order to make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0012] In some chips with upstream and downstream structures (i.e. request initiator and request responder), a queue circuit is usually arranged. The queue circuit functions to record information carried by a request in a request execution process. When a downstream completes processing of a request and returns a response to an upstream, the queue circuit also needs to return the information carried by the request to the upstream so as to indicate to the upstream that the request processing is completed and the next action can be executed.

[0013] Reference is made to Figure 1 which shows a schematic diagram of a circuit structure including upstream and downstream structures provided by an embodiment of the present application. The circuit structure includes an upstream structure 10, a downstream structure 20 and a queue circuit 30.

[0014] The upstream structure 10 can include any device with a request sending function, such as different logic units in a chip. The downstream structure 20 can include any device for processing a request, such as logic units, memories (such as cache) in a chip, etc. The devices included in the upstream structure 10 and the downstream structure 20 can each be one or more, which is not limited by the present application.

[0015] In some embodiments, the upstream structure 10 sends a request to the downstream structure 20, in the case that the request is received by a logic unit in the downstream structure 20, the request can be a request for the logic unit to perform a certain logic action, accordingly, the response returned by the downstream structure 20 for the request can include data generated by the logic action. In the case that the request is received by a memory in the downstream structure 20, the request can be a read / write request, accordingly, the response returned by the downstream structure 20 for the request can include read data / successful write response, etc. In some embodiments, the data in the response returned by the downstream structure 20 will be stored in the SRAM (Static Random-Access Memory) of the upstream structure. In some embodiments, when the upstream structure 10 sends a request to the downstream structure 20, the index of the request (indicating the object to which the request is directed) and the information carried by the request are recorded in the queue circuit 30 synchronously, and when the downstream structure 20 processes the request and returns a response for the request, the index of the request is given to the queue circuit 30, and the queue circuit 30 will return the information carried by the request to the upstream structure 10 according to the index.

[0016] In related technologies, there are two implementation modes for the queue circuit 30. One is to determine the output order of the queue circuit 30 according to the order returned by the downstream structure 20. When the downstream structure 20 returns out of order, the queue circuit 30 first outputs the information carried by the request corresponding to the index returned first by the downstream structure 20. In this way, the output order of the queue circuit 30 is equivalent to the order returned by the downstream structure 20, and when one index returned by the downstream structure 20 corresponds to multiple requests (the information carried by these multiple requests is all recorded in the queue circuit 30), a polling mode is usually selected to select the output of the queue circuit 30.

[0017] The other implementation mode is to output all requests in order. That is, when the downstream structure 20 returns an index, the queue circuit 30 must wait until the information carried by each earlier request (the information carried by these requests is earlier than the information carried by the request with the index) is output before outputting the information carried by the request with the index.

[0018] In the above first implementation mode, the queue circuit 30 cannot achieve the same index output in order, and in many scenarios, it cannot meet the design requirements. For example, program execution in a processor can depend on the order of memory access, in which case, for multiple requests with the same index (directed to the same object), if the queue circuit 30 returns the information carried by the request out of order, it can cause the program execution to fail.

[0019] In the second implementation manner, the completely order-preserving queue circuit 30 sorts all requests together, and when the index of a late-arriving request has met the output condition, the index of a previous-arriving request (information carried by the corresponding request) also needs to continue to wait for output. In this case, the utilization efficiency of the queue is reduced, the probability of upstream back pressure due to queue full is increased, and the best performance cannot be achieved.

[0020] Based on the above problems, the present application provides a new queue circuit 30, which can return information carried by a request in order for requests with the same index, and can achieve higher performance and higher utilization efficiency of the queue circuit 30.

[0021] Please refer to Figure 2 which shows a structure diagram of the queue circuit provided by an embodiment of the present application. The queue circuit 30 includes a signal receiving unit 31, an index queue 32, and a storage unit 33.

[0022] The index queue 32 stores indexes of N requests, and the index of a request is used to indicate an object to which the request is directed. For example, in the case of a read request, the index of the request is used to indicate a device accessed by the read request, or to indicate a storage location of data to be read by the read request. For another example, in the case of a request for triggering a device to perform a logical operation, the index of the request is used to indicate the device.

[0023] In some embodiments, the index queue 32 is composed of registers.

[0024] In some embodiments, the index queue 32 includes at least two registers.

[0025] In some embodiments, the index queue 32 includes Q entries, Q being an integer greater than N. One of the Q entries is used to store an index of a request, and when an index is stored in one of the Q entries, the entry is occupied, and when no index is stored in the entry, the entry is in an idle state.

[0026] The storage unit 33 stores information respectively carried by N requests, N being a positive integer. Those skilled in the art can understand that information carried by requests with different functions is different, for example, a read request needs to carry information such as the address and length of data to be read, a write request needs to carry data to be written, and a request for implementing a logical operation needs to carry data participating in the operation and an indication of the type of operation, and therefore the present application does not limit the specific content of information carried by a request.

[0027] In some embodiments, the storage unit 33 includes a RAM (Random Access Memory).

[0028] The signal receiving unit 31 is configured to receive a queue updating signal, and the queue updating signal carries a first index, and the first index belongs to the index of a processed request.

[0029] The queue updating signal is configured to indicate to update the content stored in the queue circuit 30.

[0030] The processed request refers to a request that has been processed, that is, when the downstream structure 20 processes a request, the queue updating signal carrying the index of the processed request is sent to the queue circuit 30.

[0031] The storage unit 33 is configured to output the information carried by the first request in the case that the first request in the N requests meets an output condition.

[0032] The output condition includes that the first request is a first index request in M first index requests included in the N requests, the information carried by the first index request is written into the storage unit 33 first, the first index request refers to a request with the first index, and M is a positive integer less than or equal to N.

[0033] In some embodiments, the M first index requests are all the first index requests included in the N requests.

[0034] For example, the storage unit 33 stores the information carried by the request a, the information carried by the request b, and the information carried by the request c. The index of the request a is 1, the indexes of the request b and the request c are both 2, the time when the request a is written into the storage unit 33 is earlier than the time when the request b is written into the storage unit 33, and the time when the request b is written into the storage unit 33 is earlier than the time when the request c is written into the storage unit 33. In the case that the queue updating signal received by the signal receiving unit 31 carries the index 2, the storage unit 33 outputs the information carried by the request b.

[0035] The technical scheme provided by the embodiments of the present application is for a queue circuit that stores N request indexes (stored in the index queue of the queue circuit) and information carried by the N requests respectively (stored in the storage unit of the queue circuit). By designing the signal receiving unit in the queue circuit to output the information carried by the first request in the case that the first request belongs to a request with the first index (first index request) in the N requests, the information carried by the first request is written into the storage unit first, the order of the data carried by the requests with the same index stored in the queue circuit is guaranteed to be output (output according to the order of writing), since the index of the request is used to indicate the object to which the request is directed, the above scheme guarantees that the information carried by the requests directed to the same object is returned to the upstream (the receiving party of the output of the queue circuit) in the order of writing, and further guarantees the correctness of the processing logic of the upstream.

[0036] In some embodiments, please refer to Figure 2 The queue circuit 30 further comprises a pointer queue 34, in which N pointers corresponding to the N requests are stored, and the pointer corresponding to a request is used to indicate the storage location of the information carried by the request in the storage unit 33.

[0037] In some embodiments, the pointer queue 34 is composed of registers. In some embodiments, the pointer queue 34 comprises at least two registers.

[0038] In some embodiments, the storage space of the storage unit 33 is divided into R entries, each of which is used to store the information carried by a request, and R is an integer greater than or equal to N. When an entry of the R entries stores the information carried by a request, the entry is occupied, and when the entry does not store the information carried by a request, the entry is said to be in an idle state.

[0039] Exemplarily, when the depth of the storage unit 33 (i.e. the value of R) is 128, the pointer corresponding to a request can be a 7-bit number, so as to indicate any one of the 128 entries.

[0040] The pointer queue 34 is used to provide the pointer corresponding to the first request to the storage unit 33 in the case that the first request is the first index request in which the pointer corresponding to the request is first written into the pointer queue 34, wherein the order of writing the information carried by the N requests into the storage unit 33 is consistent with the order of writing the N pointers corresponding to the N requests into the pointer queue 34.

[0041] The storage unit 33 is used to output the information carried by the first request according to the pointer corresponding to the first request.

[0042] Exemplarily, the M first index requests comprise request b and request c, the pointer corresponding to request b is 2, and the pointer corresponding to request c is 3. In the case that the pointer 2 is written into the pointer queue 34 earlier than the pointer 3, the pointer queue 34 provides the pointer 2 to the storage unit 33, and the storage unit 33 can find the entry in which the information carried by request b is stored according to the pointer 2, and then output the information carried by request b stored in the entry.

[0043] In some embodiments, the pointer corresponding to a request is also used to indicate the storage location of the index of the request in the index queue 32. In some embodiments, R=Q.

[0044] In the above embodiment, the N pointers corresponding to the N requests are recorded in the pointer queue 34 of the queue circuit 30. Since the order of writing the information carried by the N requests into the storage unit 33 is consistent with the order of writing the N pointers corresponding to the N requests into the pointer queue 34, in the above scheme, the queue circuit 30 only needs to provide the correct pointer to the storage unit 33 according to the order of storing the pointer itself, and through the simple way of providing the pointer to the storage unit 33, the storage unit 33 can be ensured to output the information carried by the request with the same index in order.

[0045] In some embodiments, the pointer queue 34 includes P entries, P being an integer greater than or equal to N.

[0046] In the case that the pointer corresponding to the first request is the i th pointer of the N pointers corresponding to the N requests written into the pointer queue 34, the pointer corresponding to the first request is stored in the i th entry of the P entries, i being a positive integer less than or equal to N.

[0047] For example, if the pointer queue 34 includes 10 entries, the N requests are request a, request b and request c, the pointer corresponding to request a is 1, the pointer corresponding to request b is 2, and the pointer corresponding to request c is 3. In the case that the pointer 1 is stored in the first entry of the 10 entries, the pointer 2 is stored in the second entry of the 10 entries, and the pointer 3 is stored in the third entry of the 10 entries, the pointer 1 of request a is first written into the pointer queue 34, the pointer 2 of request b is second written into the pointer queue 34, and the pointer 3 of request c is third written into the pointer queue 34.

[0048] In the above embodiment, the arrangement order of the entries in which the N pointers corresponding to the N requests are located in the pointer queue 34 reflects the writing order of the N pointers, and no additional storage resource is needed to record the writing order, thereby saving the chip area and reducing the implementation cost.

[0049] In some embodiments, referring to Figure 2 , the queue circuit 30 further includes a write management unit 35.

[0050] The write management unit 35 is configured to determine the pointer corresponding to the second request in the case that the index of the second request and the information carried by the second request are received.

[0051] In some embodiments, the write management unit 35 is connected with the index queue 32, the storage unit 33 and the pointer queue 34 respectively.

[0052] In some embodiments, the write management unit 35 is configured to receive the index of the second request and the information carried by the second request. In some embodiments, the index of the second request and the information carried by the second request are contained in the same information or signal.

[0053] In some embodiments, the pointer corresponding to the second request is used to indicate the storage location of the index of the second request in the index queue 32, and is used to indicate the storage location of the information carried by the second request in the storage unit 33. That is, the pointer corresponding to the second request is both a write pointer for writing the index of the second request into the index queue 32, and is a write pointer for writing the information carried by the second request into the storage unit 33, and is a read pointer for reading the information carried by the second request from the storage unit 33.

[0054] Therefore, the write management unit 35 can determine the pointer corresponding to the second request in any one of the following two ways.

[0055] Way 1, the write management unit 35 is configured to, in a case where the index of the second request and the information carried by the second request are received, find an entry in an idle state from the Q entries of the index queue 32 (for example, sequentially find down from the first entry of the Q entries), and determine the pointer indicating the entry as the pointer corresponding to the second request.

[0056] Way 2, the write management unit 35 is configured to, in a case where the index of the second request and the information carried by the second request are received, find an entry in an idle state from the R entries of the storage unit 33 (for example, sequentially find down from the first entry of the R entries), and determine the pointer indicating the entry as the pointer corresponding to the second request.

[0057] For each request, the information carried by the request and the corresponding index are always stored in the storage unit 33 and the index queue 32, and after the information carried by the request is read, the information carried by the request and the corresponding index are deleted synchronously, so that the position of the entry in an idle state in the index queue 32 and the position of the entry in an idle state in the storage unit 33 are the same. Therefore, the pointer determined based on the way 1 or the way 2 can indicate the storage location of the information in the storage unit 33 and the storage location of the index in the index queue 32 at the same time.

[0058] The write management unit 35 is further configured to write the pointer corresponding to the second request into the pointer queue 34, and write the index of the second request into the index queue 32 and write the information carried by the second request into the storage unit 33 according to the pointer corresponding to the second request.

[0059] In some embodiments, the second request is a request other than the N requests, and the write management unit 35 is configured to, in a case where P is greater than N, write the pointer corresponding to the second request into the N+1th entry of the P entries of the pointer queue 34.

[0060] In the above embodiment, the write management unit 35 records the synchronization of the index of the second request and the pointer used when the information carried by the second request is written, on one hand, the write order of the pointers corresponding to the N requests in the pointer queue 34 can reflect the write order of the information carried by the N requests to the storage unit 33 (and the order of the indexes of the N requests written to the index queue 32), on the other hand, the index of the write request and the write pointer used when the information carried by the request is written are ingeniously used as the read pointer used when the information is output from the storage unit 33, so that the pointer in the present scheme is highly multiplexed, and only a small amount of data needs to be recorded additionally in the queue circuit 30 to achieve the order-preserving output of the index request.

[0061] In some embodiments, the arrangement order of the storage positions of the pointers corresponding to the N requests in the pointer queue 34 is consistent with the order of the pointers corresponding to the N requests written to the pointer queue.

[0062] For example, in the case that the pointer corresponding to the first request is the i th pointer of the N requests written to the pointer queue 34, the pointer corresponding to the first request is stored in the i th entry of the P entries.

[0063] In some embodiments, the signal receiving unit 31 is also connected with the index queue 32.

[0064] The signal receiving unit 31 is also configured to compare the first index with the indexes stored in the index queue 32 to generate first preparation signals corresponding to the M first index requests, the first preparation signal corresponding to the first index request being used to mark the storage position of the index of the first index request in the index queue 32.

[0065] In some embodiments, the first preparation signal corresponding to the first index request is used to mark the entry of the index of the first index request in the Q entries of the index queue 32.

[0066] In addition, from the above embodiment, it can be known that the pointer corresponding to the request can indicate the storage position of the index of the request in the index queue 32 and the storage position of the information carried by the request in the storage unit 33. Similarly, the first preparation signal corresponding to the first index request can be used to mark the storage position of the information carried by the first index request in the index queue 32 in addition to marking the storage position of the index of the first index request in the index queue 32.

[0067] In some embodiments, the first preparation signal corresponding to the first index request is used to mark the entry of the information carried by the first index request in the R entries of the storage unit 33.

[0068] In some embodiments, please refer to Figure 2The queue circuit 30 further comprises a preparation signal recording unit 36, one end of the preparation signal recording unit 36 being connected to the signal receiving unit 31, and the other end of the preparation signal recording unit 36 being connected to the pointer queue 34. The preparation signal recording unit 36 is configured to record the first preparation signals corresponding to the M first index requests respectively.

[0069] In some embodiments, the preparation signal recording unit 36 is composed of registers. In some embodiments, the preparation signal recording unit comprises at least two registers.

[0070] In some embodiments, the signal receiving unit 31 is further configured to write the first preparation signals corresponding to the M first index requests respectively into the preparation signal recording unit 36.

[0071] In some embodiments, referring to Figure 3 The preparation signal recording unit 36 comprises T entries 361, T being an integer greater than N, and one entry 361 in the preparation signal recording unit 36 is configured to mark whether the index of the first index request is stored in the corresponding entry in the index queue 32. For example, when one entry in the preparation signal recording unit 36 is set to 1, it means that the index of the first index request is stored in the corresponding entry in the index queue 32 (at this time, the 1 in the entry can be regarded as the first preparation signal corresponding to the first index request), and when one entry in the preparation signal recording unit 36 is set to 0, it means that the index of the first index request is not stored in the corresponding entry in the index queue 32. That is, the pointer corresponding to the first index request can also be used to indicate the entry in the T entries 361 in the preparation signal recording unit 36 where the first preparation signal corresponding to the first index request is located. In some embodiments, R = Q = T.

[0072] Exemplarily, referring to Figure 3 The signal receiving unit 31 compares the received first index 2 with the indexes recorded in the index queue 32, and it can be known that the indexes 2 corresponding to the first index requests are stored in the 3rd entry and the 4th entry in the index queue 32. Accordingly, the signal receiving unit 31 sets the values in the 3rd entry and the 4th entry in the preparation signal recording unit 36 to 1, that is, the 1 in the 3rd entry and the 4th entry in the preparation signal recording unit 36 can be regarded as the first preparation signal.

[0073] In some embodiments, the pointer queue 34 is further configured to read the first preparation signals corresponding to the M first index requests from the signal receiving unit 31.

[0074] In the above embodiment, the preparation signal recording unit 36 is arranged between the signal receiving unit 31 and the pointer queue 34, so as to provide corresponding storage space to support the signal receiving unit 31 to record the first preparation signal in real time, and support the pointer queue 34 to complete the conversion from the first preparation signal to the second preparation signal.

[0075] The pointer queue 34 is configured to convert the first preparation signal corresponding to the M first index requests into the second preparation signal corresponding to the M first index requests respectively, wherein the second preparation signal corresponding to the first index request is used to mark the storage position of the pointer corresponding to the first index request in the pointer queue 34.

[0076] In some embodiments, the pointer queue 34 is further configured to write the second preparation signal corresponding to the M first index requests back to the preparation signal recording unit 36.

[0077] In some embodiments, for any one of the M first index requests, the pointer queue 34 is configured to determine, as the pointer corresponding to the first index request, the pointer stored in the pointer queue 34 and indicating the storage position marked by the first preparation signal corresponding to the first index request (see above, the storage position can be the storage position of the index of the first index request in the index queue 32, or the storage position of the information carried by the first index request in the storage unit 33) among the N pointers corresponding to the N requests, and generate a signal used to mark the storage position of the pointer in the pointer queue 34 as the second preparation signal corresponding to the first index request.

[0078] In some embodiments, see above, the pointer corresponding to the first index request can also be used to indicate the entry in which the first preparation signal corresponding to the first index request is located among the T entries 361 included in the preparation signal recording unit 36. Therefore, for any one of the M first index requests, the pointer queue 34 can also be configured to determine, as the pointer corresponding to the first index request, the pointer stored in the pointer queue 34 and indicating the entry in which the first preparation signal corresponding to the first index request is located (in the preparation signal recording unit 36) among the N pointers corresponding to the N requests, and generate a signal used to mark the storage position of the pointer in the pointer queue 34 as the second preparation signal corresponding to the first index request.

[0079] Exemplarily, please refer to Figure 4, the first index request corresponds to index 2, and the signal receiving unit 31 sets the values in the third and fourth entries of the preparation signal recording unit 36 to 1, and sets the values in the other entries to 0. In this case, the pointer 2 stored in the second entry of the pointer queue 34 can indicate the third entry of the index queue 32 (or the preparation signal recording unit 36), and the pointer 3 stored in the third entry of the pointer queue 34 can indicate the fourth entry of the index queue 32 (or the preparation signal recording unit 36). Therefore, the pointer queue 34 sets the values in the second and third entries of the preparation signal recording unit 36 to 1 (which can be regarded as the second preparation signal), and sets the values in the other entries to 0, so as to convert the first preparation signals corresponding to the M first index requests into the second preparation signals corresponding to the M first index requests, and further mark the second and third entries of the pointer queue 34.

[0080] In some embodiments, the pointer queue 34 includes a storage subunit and a logic subunit (not shown in FIG. 4). The storage subunit is configured to store the pointers corresponding to the N requests, and the logic subunit is configured to convert the first preparation signals corresponding to the M first index requests into the second preparation signals corresponding to the M first index requests, and to implement other logical functions performed by the pointer queue 34. Figure 2

[0081] The pointer queue 34 is further configured to provide the pointer corresponding to the first request to the storage unit 33 when the pointer corresponding to the first request is located in the first storage location of the M storage locations marked by the second preparation signals corresponding to the M first index requests, where M is a positive integer less than or equal to N.

[0082] For example, referring to FIG. 4, Figure 4 The second and third entries of the pointer queue 34 are marked by the second preparation signals, and therefore the M storage locations are the second and third entries of the pointer queue 34. Since the second entry of the pointer queue 34 is located before the third entry, the pointer queue 34 can directly provide the pointer 2 stored in the second entry to the storage unit 33.

[0083] ​In the above embodiment, in the first aspect, the first index request corresponding first preparation signal is converted into a second preparation signal, which can be used to maintain the pointer write order in the pointer queue 34 (so that the arrangement order of the storage positions of the N request corresponding pointers in the pointer queue 34 is consistent with the order of the N request corresponding pointers writing into the pointer queue), so that the storage position of the first index request in the index queue 32 and the storage position of the first index request corresponding pointer in the pointer queue 34 cannot be strictly corresponding, and the storage position of the first index request corresponding pointer in the pointer queue 34 is correctly marked, thereby facilitating the extraction of the corresponding pointer. In the second aspect, the above scheme only marks the index / pointer position of the first index request, without considering the writing order of the index / information carried by other requests in the N requests, so that the request return can be realized with lower delay and lower power consumption. In the third aspect, in the above scheme, the pointer queue 34 directly provides the earlier storage position of the M first index request corresponding pointers, without recording the corresponding storage time, and has lower implementation complexity.

[0084] In some embodiments, the pointer queue 34 is used to delete the pointer (i.e., the first request corresponding pointer) stored in the ith entry after providing the first request corresponding pointer to the storage unit 33, and in the case that i is less than N, the pointers stored in the (i+1)th entry to the Nth entry in the pointer queue are sequentially moved one entry, that is, the pointer stored in the (i+1)th entry is moved to the ith entry, the pointer stored in the (i+2)th entry is moved to the (i+1)th entry, and so on, and the pointer stored in the Nth entry is moved to the (N-1)th entry.

[0085] Exemplarily, please refer to Figure 5 In period 0, there are 4 occupied entries in the pointer queue 34, which correspond to 4 writing processes of the queue circuit 30, that is, 4 requests in sequence. The first request corresponding pointer is pointer 0, index = 0, the second request corresponding pointer is pointer 1, index = 0, the third request corresponding pointer is pointer 2, index = 1, and the fourth request corresponding pointer is pointer 3, index = 0. At the same time, in period 0, the position of pointer 2 in the pointer queue 34 is marked by the second preparation signal in the preparation signal recording unit 36. Then the pointer queue 34 outputs pointer 2 as the pointer provided to the storage unit 33. In the next period (period 1), the pointer queue 34 will move pointer 3 from the original entry (the next entry of the entry where pointer 2 is located) to the entry where pointer 2 is deleted.

[0086] In the above embodiment, after the pointer queue 34 provides the pointer corresponding to the first request to the storage unit 33, the pointer corresponding to the first request is not only removed by the pointer queue 34, but the pointer located after the pointer is also moved forward accordingly, so that there is no idle entry (i.e., an entry not storing a pointer) between any two occupied entries (i.e., entries storing pointers) of the pointer queue 34, thereby ensuring that the arrangement order of the pointers in the pointer queue 34 can always accurately reflect the writing order of the pointers when new pointers are subsequently written.

[0087] In some embodiments, the storage unit 33 is further configured to delete the information carried by the first request after outputting the information.

[0088] In some embodiments, the index queue 32 is further configured to delete the index of the first request after the pointer queue 34 provides the pointer corresponding to the first request to the storage unit 33.

[0089] The following is an embodiment of the method of the present application. For details not described in detail in the embodiment of the method of the present application, please refer to the above embodiments of the queue circuit.

[0090] Please refer to Figure 6 which shows a flowchart of a queue circuit-based information processing method provided by an embodiment of the present application. The queue circuit includes a signal receiving unit, an index queue, and a storage unit. The index queue stores indexes of N requests, and the indexes of the requests are used to indicate objects to which the requests are directed. The storage unit stores information respectively carried by the N requests, and N is a positive integer. The method includes at least one of the following steps 610-620.

[0091] In step 610, the signal receiving unit receives a queue update signal, and the queue update signal carries a first index. The first index belongs to the indexes of the processed requests.

[0092] In step 620, the storage unit outputs the information carried by the first request under the condition that the first request among the N requests satisfies an output condition.

[0093] The output condition includes that the first request is a first index request among M first index requests included in the N requests, and the information carried by the first index request is written into the storage unit first. The first index request refers to the request with the first index, and M is a positive integer less than or equal to N.

[0094] In some embodiments, the queue circuit further includes a pointer queue, and the pointer queue stores pointers respectively corresponding to the N requests. The pointer corresponding to the request is used to indicate the storage position of the information carried by the request in the storage unit.

[0095] The method further includes: in a case that the first request is a first index request among the M first index requests, the pointer queue providing the pointer corresponding to the first request to the storage unit, wherein the order of writing the information carried by the N requests into the storage unit is consistent with the order of writing the pointers corresponding to the N requests into the pointer queue.

[0096] The step 620 includes: the storage unit outputting the information carried by the first request according to the pointer corresponding to the first request.

[0097] The technical scheme provided by the embodiments of the present application is applied to a queue circuit which stores N requests (stored in an index queue of the queue circuit) and information carried by the N requests (stored in a storage unit of the queue circuit). In a case that, after the signal receiving unit receives the first index (which belongs to the index of the processed request), the first request among the N requests is a first index request among the M first index requests, the information carried by the first index request is first written into the storage unit, the storage unit outputs the information carried by the first request. The data carried by the requests with the same index stored in the queue circuit is output in sequence (according to the writing order), and the index of the request is used to indicate the object to which the request is directed, so that the information carried by the requests directed to the same object is returned to the upstream (the receiving side of the output of the queue circuit) in the writing order, and the correctness of the processing logic of the upstream is ensured.

[0098] In some embodiments, the arrangement order of the storage positions of the pointers corresponding to the N requests in the pointer queue is consistent with the order of writing the pointers corresponding to the N requests into the pointer queue. In this case, refer to Figure 7 FIG. 7 is a flowchart of a method for processing information based on a queue circuit according to another embodiment of the present application. The method includes at least one of the following steps 710-750.

[0099] In step 710, the signal receiving unit receives a queue update signal, and the queue update signal carries a first index which belongs to the index of the processed request.

[0100] In step 720, the signal receiving unit compares the first index with the indexes stored in the index queue to generate first preparation signals corresponding to the M first index requests respectively.

[0101] The first preparation signal corresponding to the first index request is used to mark the storage position of the index of the first index request in the index queue.

[0102] The pointer queue converts the first preparation signals corresponding to the M first index requests into second preparation signals corresponding to the M first index requests respectively.

[0103] The second preparation signal corresponding to the first index request is used to mark the storage position of the pointer corresponding to the first index request in the pointer queue.

[0104] The pointer queue provides the pointer corresponding to the first request to the storage unit in the case that the pointer corresponding to the first request is located at the first storage position of the M storage positions.

[0105] The M storage positions are marked by the second preparation signals corresponding to the M first index requests, and M is a positive integer less than or equal to N.

[0106] The storage unit outputs the information carried by the first request according to the pointer corresponding to the first request.

[0107] In some embodiments, the queue circuit further includes a preparation signal recording unit, one end of the preparation signal recording unit is connected to the signal receiving unit, and the other end of the preparation signal recording unit is connected to the pointer queue; the preparation signal recording unit is used to record the first preparation signals corresponding to the M first index requests.

[0108] In some embodiments, the pointer queue includes P entries, and P is an integer greater than or equal to N; in the case that the pointer corresponding to the first request is the i th write pointer corresponding to the N requests, the pointer corresponding to the first request is stored in the i th entry of the P entries, and i is a positive integer less than or equal to N.

[0109] In some embodiments, please refer to Figure 7 The method further includes step 760.

[0110] After the pointer queue provides the pointer corresponding to the first request to the storage unit, the pointer stored in the i th entry is deleted, and in the case that i is less than N, the pointers stored in the pointer queue from the i+1 th entry to the N th entry are sequentially moved by one entry.

[0111] In some embodiments, the queue circuit further includes a write management unit; the method further includes: 1. The write management unit determines the pointer corresponding to the second request in the case that the index of the second request and the information carried by the second request are received.

[0112] 2. The write management unit writes the pointer corresponding to the second request into the pointer queue, and writes the index of the second request into the index queue, writes the information carried by the second request into the storage unit according to the pointer corresponding to the second request.

[0113] For the convenience of understanding, an application example based on the above embodiments is given as follows.

[0114] The upstream structure sends the request a, the request b, and the request c (equivalent to the second request in the above) to the downstream structure in turn, wherein the indexes of the request a and the request b are both index 1, and the index of the request c is index 2.

[0115] Suppose that when the write management unit 35 receives the request a (receives the index of the request a and the information carried by the request a), the first, the second, and the third free locations of the index queue 32 and the storage unit 33 are all the second entry, the third entry, and the fourth entry, the write management unit 35 can determine the pointers corresponding to the respective requests according to the entries of the free state of the index queue 32 (or the storage unit 33). Among them, the pointer 1 corresponding to the request a points to the second entry of the index queue 32 and the storage unit 33, the pointer 2 corresponding to the request b points to the third entry of the index queue 32 and the storage unit 33, and the pointer 3 corresponding to the request c points to the fourth entry of the index queue 32 and the storage unit 33. The pointer 1, the pointer 2, and the pointer 3 are stored in the first entry, the second entry, and the third entry of the pointer queue 34 in turn. For the sake of simplicity of description, it is assumed that the pointer queue 34 is empty, and thus the pointer 1, the pointer 2, and the pointer 3 are stored in the first entry, the second entry, and the third entry of the pointer queue 34 in turn.

[0116] According to the positions indicated by the pointer 1, the pointer 2, and the pointer 3, the second entry, the third entry, and the fourth entry of the index queue 32 store the index 1, the index 1, and the index 2 in turn. The second entry, the third entry, and the fourth entry of the storage unit 33 store the information carried by the request a, the request b, and the request c in turn.

[0117] The signal receiving unit 31 receives the queue update information from the downstream structure. Suppose that the index of the processed request carried by the queue update information is index 1 (i.e., the first index in the above), the signal receiving unit 31 compares the first index with the indexes stored in the index queue 32, and obtains the first preparation signal 01100…, i.e., the second entry and the third entry where the index 1 is located are marked as 1, and the others are marked as 0.

[0118] Next, the pointers pointing to the second entry and the third entry of the index queue 32, i.e., the pointer 1 and the pointer 2, are found in the pointer queue 34, and the first preparation signal is converted into the second preparation signal 1100…, i.e., the first entry and the second entry where the pointer 1 and the pointer 2 are located are marked as 1, and the others are marked as 0.

[0119] According to the storage location indicated by the second preparation signal, it can be determined that the pointer 1 writes in sequence earlier than the pointer 2, and thus, according to the storage location indicated by the pointer 1, the information carried by the request a is read in the storage unit 33 and output to the upstream structure.

[0120] The pointer 1, the information carried by the request a, and the index corresponding to the request a (i.e., the index 1 stored in the second entry) are deleted. The storage locations of the pointer 2 and the pointer 3 are changed to the first entry and the second entry in the pointer queue 34.

[0121] An exemplary embodiment of the present application further provides a processor, which comprises the queue circuit introduced in the above embodiments.

[0122] The processor can comprise one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor can be implemented in at least one of a hardware form of a DSP (Digital Signal Processing), an FPGA (Field Programmable Gate Array), and a PLA (Programmable Logic Array). The processor can also comprise a main processor and a coprocessor. The main processor is a processor for processing data in a wake-up state, also referred to as a CPU (Central Processing Unit). The coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor can be a GPU (Graphics Processing Unit) for being responsible for rendering and drawing of content to be displayed on a display screen. In some embodiments, the processor can further comprise an AI processor for processing a computing operation related to machine learning.

[0123] An exemplary embodiment of the present application further provides a computer device, which comprises the processor comprising the queue circuit introduced in the above embodiments.

[0124] Optionally, the computer device can be a server, or a terminal device such as a mobile phone, a tablet computer, a vehicle-mounted terminal, a wearable device, a smart home device, etc., or can be a robot, a base station, or any device applied to the processor, and the present application does not limit this.

[0125] An exemplary embodiment of the present application further provides a chip product, which comprises the queue circuit introduced in the above embodiments.

[0126] An embodiment of the present application further provides a GPU, which comprises the queue circuit of the above embodiment.

[0127] An embodiment of the present application further provides a graphic card, which comprises a processor, and the processor comprises the queue circuit of the above embodiment.

[0128] It should be understood that "multiple" mentioned herein refers to two or more than two. The "and / or" describes the association between the associated objects, which means that there can be three relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone. The character " / " generally represents that the associated objects before and after are in an "or" relationship. In addition, the step numbers described herein only exemplarily show a possible execution order between steps. In some other embodiments, the above steps can also be executed in a non-numbered order, such as two steps with different numbers are executed at the same time, or two steps with different numbers are executed in an order opposite to the illustration, and the embodiments of the present application are not limited in this regard.

[0129] The above only exemplarily illustrates the embodiments of the present application, and does not limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A queue circuit, characterized in that: The queue circuit includes a signal receiving unit, an index queue, and a storage unit, wherein the index queue stores indexes of N requests, the index of the request being used to indicate an object targeted by the request, and the storage unit stores information carried by the N requests, where N is a positive integer; The signal receiving unit is configured to receive a queue update signal, wherein the queue update signal carries a first index, where the first index belongs to an index of a processed request; The storage unit is used to output the information carried by the first request when the first request among the N requests meets the output condition; wherein the output condition includes: the first request is the first index request among the M first index requests included in the N requests, and the information carried is first written into the storage unit, the first index request refers to the request with the first index as the index, and M is a positive integer less than or equal to N.

2. The queue circuit according to claim 1, characterized in that The queue circuit further includes a pointer queue, wherein the pointer queue stores pointers corresponding to the N requests respectively, and the pointers corresponding to the requests are used to indicate the storage location of the information carried by the requests in the storage unit; The pointer queue is configured to provide the storage unit with a pointer corresponding to the first request when the first request is the first index request among the M first index requests and the corresponding pointer is first written into the pointer queue, wherein an order in which information carried by the N requests is written into the storage unit is consistent with an order in which the pointers corresponding to the N requests are written into the pointer queue; The storage unit is configured to output information carried in the first request according to a pointer corresponding to the first request.

3. The queue circuit according to claim 2, characterized in that The arrangement order of the storage positions of the pointers corresponding to the N requests in the pointer queue is consistent with the order in which the pointers corresponding to the N requests are written into the pointer queue; The signal receiving unit is further configured to compare the first index with an index stored in the index queue to generate first preparation signals corresponding to the M first index requests, respectively, wherein the first preparation signals corresponding to the first index requests are used to mark a storage position of the index of the first index request in the index queue; The pointer queue is used to convert the first ready signals corresponding to the M first index requests into second ready signals corresponding to the M first index requests, wherein the second ready signals corresponding to the first index request are used to mark the storage position of the pointer corresponding to the first index request in the pointer queue; The pointer queue is also used to provide the pointer corresponding to the first request to the storage unit when the pointer corresponding to the first request is located at the first storage position among M storage locations, wherein the M storage locations are marked by the second ready signals corresponding to the M first index requests respectively, and M is a positive integer less than or equal to N.

4. The queue circuit according to claim 3, characterized in that The queue circuit further comprises a preparation signal recording unit, one end of the preparation signal recording unit is connected to the signal receiving unit, and the other end of the preparation signal recording unit is connected to the pointer queue; The preparation signal recording unit is configured to record the first preparation signals respectively corresponding to the M first index requests.

5. The queue circuit according to any one of claims 2 to 4, characterized in that: The pointer queue includes P entries, where P is an integer greater than or equal to N; when the pointer corresponding to the first request is the i-th pointer written into the pointer queue among the pointers corresponding to the N requests, the pointer corresponding to the first request is stored in the i-th entry among the P entries, where i is a positive integer less than or equal to N.

6. The queue circuit according to claim 5, characterized in that The pointer queue is also used to delete the pointer stored in the i-th entry after providing the pointer corresponding to the first request to the storage unit, and, when i is less than N, move the pointers stored in the pointer queue from the i+1-th entry to the N-th entry forward one entry respectively.

7. The queue circuit according to any one of claims 2 to 4, characterized in that: The queue circuit further includes a write management unit; The write management unit is configured to determine a pointer corresponding to the second request upon receiving the index of the second request and the information carried by the second request; The write management unit is further configured to write the pointer corresponding to the second request into the pointer queue, and, based on the pointer corresponding to the second request, write the index of the second request into the index queue, and write the information carried by the second request into the storage unit.

8. A processor, characterized in that: The processor comprises the queue circuit according to any one of claims 1 to 7.

9. A computer device, characterized in that: The computer device comprises a processor comprising the queue circuit according to any one of claims 1 to 7.

10. A chip product, characterized in that: The chip product includes the queue circuit according to any one of claims 1 to 7.

11. An information processing method based on a queue circuit, characterized in that: The queue circuit includes a signal receiving unit, an index queue, and a storage unit, wherein the index queue stores indexes of N requests, where the indexes of the requests are used to indicate objects targeted by the requests, and the storage unit stores information carried by the N requests, where N is a positive integer. The method includes: The signal receiving unit receives a queue update signal, wherein the queue update signal carries a first index, and the first index belongs to an index of a processed request; The storage unit outputs the information carried by the first request when the first request among the N requests meets the output condition; wherein the output condition includes: the first request is the first index request among the M first index requests included in the N requests, and the information carried is first written into the storage unit, the first index request refers to the request with the first index as the index, and M is a positive integer less than or equal to N.

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