Interface buffer device, integrated circuit communication system and method

Abstract

The invention discloses an interface buffer device, an integrated circuit communication system and an integrated circuit communication method. The interface buffer device comprises an uplink interface which communicates with a main device; the plurality of integrated circuit I2C master interfaces are respectively communicated with the I2C slave interfaces of the plurality of corresponding slave devices; the control unit is used for controlling the uplink interface and the plurality of I2C main interfaces and processing data received from the uplink interface and data received from the plurality of I2C main interfaces; and the storage unit is used for storing the data received from the uplink interface, the data received from the plurality of I2C main interfaces and the processing data processed by the control unit for processing the received data. According to the method and the device, the technical problem that the communication speed is relatively low due to the fact that the number of I2C master interfaces of the master device is limited and communication is selected with I2C slave interfaces of a plurality of slave devices in related technologies is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication, in particular to an interface buffering device, an integrated circuit communication system and method. BACKGROUND

[0002] In modern electronic devices, an Inter-Integrated Circuit (I2C for short) bus is a widely used bidirectional two-wire serial bus, which is used to connect an I2C master interface of a master device (for example, a controller) and I2C slave interfaces of various peripheral devices, so as to realize communication between the master device and a plurality of slave devices (for example, various peripheral devices). With the increase in the number of peripheral devices, the limited I2C master interface of the master device cannot meet the needs of the peripheral devices, resulting in slow communication speed between the master device and various peripheral devices.

[0003] At present, no effective solution has been proposed for the above problems. SUMMARY

[0004] Embodiments of the present application provide an interface buffering device, an integrated circuit communication system and method, to at least solve the technical problem of slow communication speed caused by the limited number of I2C master interfaces of the master device and the selection of communication with the I2C slave interfaces of the plurality of slave devices in the related art.

[0005] According to an aspect of an embodiment of the present application, an interface buffering device is provided, comprising: an uplink interface, which is used to communicate with a master device; a plurality of I2C master interfaces, which are respectively used to communicate with a plurality of I2C slave interfaces of corresponding slave devices; a control unit, which is used to control the uplink interface and the plurality of I2C master interfaces, and process data received from the uplink interface and data received from the plurality of I2C master interfaces; and a storage unit, which is used to store the data received from the uplink interface, the data received from the plurality of I2C master interfaces, and processing data of the received data processed by the control unit.

[0006] Optionally, the uplink interface is an interface with a transmission rate exceeding a predetermined threshold.

[0007] Optionally, the types of the plurality of I2C master interfaces include at least one of the following: a hardware I2C master interface of the interface buffering device, and an interface through which the interface buffering device implements an I2C master interface function in a software manner.

[0008] Optionally, the plurality of I2C master interfaces are further used to communicate with an I2C gating expansion device, and the I2C gating expansion device is used to select communication with the I2C slave interfaces of the plurality of slave devices.

[0009] Optionally, the interface buffering device further comprises a plurality of GPIO extension interfaces respectively in communication with the corresponding plurality of slave devices.

[0010] Optionally, the control unit is further configured to process other data received from the uplink interface and data received from the plurality of I2C master interfaces based on the rule data received from the uplink interface, and to actively control the uplink interface and the plurality of I2C master interfaces based on the processed data.

[0011] According to yet another aspect of the present application, there is provided an integrated circuit communication system comprising a master device, a plurality of slave devices, and the interface buffering device as described in any of the preceding aspects.

[0012] Optionally, the integrated circuit communication system further comprises an I2C gating extension device in communication with the plurality of I2C master interfaces, the I2C gating extension device being configured to selectively communicate with I2C slave interfaces of the plurality of slave devices.

[0013] According to yet another aspect of the present application, there is provided an integrated circuit communication method comprising: receiving data transmitted by a master device through an uplink interface; processing the data transmitted by the master device to obtain processed data; selecting a target I2C master interface from a plurality of I2C master interfaces; transmitting the processed data to an I2C slave interface of a corresponding slave device through the target I2C master interface; receiving response data fed back by the corresponding slave device through the target I2C master interface; processing the response data to obtain processed response data; and transmitting the processed response data to the master device through the uplink interface.

[0014] Optionally, the transmitting the processed data to the I2C slave interface of the corresponding slave device through the target I2C master interface comprises: transmitting the processed data to an I2C gating extension device through the target I2C master interface; and transmitting the processed data to the I2C slave interface of the corresponding slave device based on the corresponding slave device selected by the I2C gating extension device.

[0015] According to still another aspect of the present application, there is provided an integrated circuit communication device, comprising: a first receiving module configured to receive data transmitted by a master device through an uplink interface; a first processing module configured to process the data transmitted by the master device to obtain processed data; a selecting module configured to select a target I2C master interface from a plurality of I2C master interfaces; a first transmitting module configured to transmit the processed data to a corresponding I2C slave interface of a slave device through the target I2C master interface; a second receiving module configured to receive response data fed back by the slave device through the target I2C master interface; a second processing module configured to process the response data to obtain processed response data; and a second transmitting module configured to transmit the processed response data to the master device through the uplink interface.

[0016] According to still another aspect of the present application, there is provided a computer readable storage medium comprising a stored executable program, wherein the executable program, when executed, controls a device in which the computer readable storage medium is located to perform the integrated circuit communication method according to any one of the preceding aspects.

[0017] According to still another aspect of the present application, there is provided an electronic device comprising: a memory storing an executable program; and a processor configured to execute the program, wherein the program, when executed, performs the integrated circuit communication method according to any one of the preceding aspects.

[0018] According to still another aspect of the present application, there is provided a computer program product comprising a computer program which, when executed by a processor, implements the steps of the integrated circuit communication method according to any one of the preceding aspects.

[0019] In the embodiment of the present application, the interface buffer circuit is adopted to communicate with the master device through the uplink interface, the plurality of integrated circuit I2C master interfaces are respectively used to communicate with the corresponding plurality of integrated circuit I2C slave interfaces of the slave devices, the control unit is used to control the uplink interface and the plurality of I2C master interfaces, and process the data received from the uplink interface and the data received from the plurality of I2C master interfaces, and the storage unit is used to store the data received from the uplink interface, the data received from the plurality of I2C master interfaces, and the processed data obtained by processing the received data by the control unit, so that the I2C master interface of the master device and the plurality of I2C slave interfaces of the slave devices are connected, thereby realizing the expansion of the I2C interface and accelerating the communication speed between the master device and the plurality of slave devices, and further solving the technical problem of slow communication speed caused by the limited number of I2C master interfaces of the master device and the selection of the I2C slave interfaces of the plurality of slave devices for communication in the related art. BRIEF DESCRIPTION OF DRAWINGS

[0020] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0021] Figure 1 is a structural block diagram of an interface buffer device according to an embodiment of the application;

[0022] Figure 2 is a structural block diagram of an integrated circuit communication system according to an embodiment of the application;

[0023] Figure 3 is a flow chart of an integrated circuit communication method according to an embodiment of the application;

[0024] Figure 4 is a structural block diagram of a single Master multi-I2C Slaver system capable of fast response according to an alternative embodiment of the application;

[0025] Figure 5 is a structural block diagram of an integrated circuit communication device according to an embodiment of the application. DETAILED DESCRIPTION

[0026] In order to make the technical personnel of the present application better understand the present application, the following will be combined with the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application are described clearly and completely, obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the scope of protection of the present application.

[0027] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily limit to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0028] First, some of the nouns or terms appearing in the description of the embodiments of the present application are applicable to the following explanations:

[0029] Inter-Integrated Circuit (I2C) bus, a two-wire serial bus, is used for lightweight inter-integrated circuit communication, a serial data line (SDA) and a serial clock line (SCL). Through the two lines, I2C allows a controller or other master device to communicate with multiple slave devices in full duplex, without having to set up a data line and a clock line for each device, greatly simplifying the hardware wiring. Based on the master-slave architecture, the master controls the bus timing and initiates data transmission, and is responsible for the generation of start and stop signals. The slave responds to the request of the master and receives or sends data. Each slave has a unique address on the I2C bus, and the master selects the slave to be communicated through the address. During data transmission, the device address is broadcast first, and then the read or write operation can be performed. In I2C communication, data is transmitted in the form of bytes, and an acknowledgement signal is sent after each byte to confirm whether the data is correctly received.

[0030] The I2C interface includes an I2C master interface and an I2C slave interface, wherein the I2C master interface belongs to the master, and the I2C slave interface belongs to the slave. The master with the I2C master interface and the slave with the I2C slave interface can communicate through the I2C bus.

[0031] For network communication electronic devices such as switches, the Master has access requirements for a plurality of Slavers with I2C slave interfaces, and there can be a plurality of Slavers with the same address in the plurality of Slavers with I2C slave interfaces. The Master can be a Central Processing Unit (CPU) chip in the network communication electronic device such as a switch, and the number of I2C master interfaces provided by the CPU chip is limited. When the number of Slavers to be accessed is large, an interface expansion circuit needs to be introduced to selectively communicate with the Slavers to be accessed. For example, when the CPU chip can provide 3 I2C master interfaces and 9 Slavers need to be accessed, through the interface expansion circuit, the CPU chip can only select to communicate with 3 Slavers at the same time, and the remaining 6 Slavers wait for the previous communication to end and then communicate in batches. The selection and switching increase the additional time overhead and the calculation overhead of the CPU chip, resulting in a longer time for the CPU chip to complete communication with all the Slavers to be accessed. The complex Slaver and register addressing process between the CPU chip and the interface expansion circuit is equivalent to indirect addressing of the Slavers by the CPU chip, which actually further increases the communication load of the CPU chip.

[0032] Furthermore, due to limitations in the I2C protocol specification, the I2C master and slave interfaces can only transmit data at a relatively low communication rate. For example, when operating in standard mode, the I2C master and slave interfaces transmit data at a rate of 100kHz, resulting in low communication efficiency. For multiple slaves requiring interaction, the CPU chip can only meet communication needs by increasing the access frequency of the I2C master interface, which increases the CPU chip load.

[0033] According to an embodiment of the present invention, an interface buffer device is provided. Figure 1 is a structural block diagram of an interface buffer device according to an embodiment of the present invention. Figure 1 As shown, the interface buffer device includes: an uplink interface 11, a plurality of integrated circuit I2C master interfaces 12, a control unit 13 and a storage unit 14.

[0034] Uplink interface 11, communicating with the master device.

[0035] As an optional embodiment, the uplink interface can be an interface with a transmission rate exceeding a predetermined threshold. Through the uplink interface, the interface buffer device can communicate with the master device, and the number of uplink interfaces can be one or more. By configuring the uplink interface as an interface with a transmission rate exceeding a predetermined threshold, high-speed transmission of data between the interface buffer device and the master device can be guaranteed, thereby giving full play to the performance of the master device, so that the master device can send data about multiple slave devices to the interface buffer circuit at one time. Among them, the predetermined threshold can be determined based on a variety of methods, for example, it can be determined based on the data throughput requirements, data processing capabilities and / or response time requirements of the master device. For example, the uplink interface can be a serial peripheral interface (Serial Peripheral Interface, abbreviated as SPI), a universal serial bus interface (Universal Serial Bus, abbreviated as USB) or a peripheral component interconnect express interface (Peripheral Component Interconnect Express, abbreviated as PCIe). Among them, the SPI interface is a full-duplex, synchronous serial communication interface with a transmission rate of up to several megahertz, such as 20MHz; the USB interface can also provide higher transmission rates, such as 480MHz for USB 2.0 and 5GHz for USB 3.0; the PCIe interface is an interface that complies with the high-speed serial computer expansion bus standard, and its transmission rate can reach 2GHz.

[0036] The plurality of integrated circuit I2C master interfaces 12 communicate with the corresponding I2C slave interfaces of the plurality of slave devices respectively.

[0037] As an optional embodiment, the types of the plurality of I2C master interfaces can include at least one of: a hardware I2C master interface of the interface buffer device, and an interface that implements the I2C master interface function by software. Through the plurality of I2C master interfaces, the interface buffer device can communicate with the I2C slave interfaces of the corresponding plurality of slave devices respectively, and the plurality of I2C master interfaces can work in parallel, so that the interface buffer device can simultaneously communicate with the I2C slave interfaces of the plurality of slave devices, thereby reducing the time for waiting and switching connections, and greatly improving the data transmission speed. The hardware I2C master interface of the interface buffer device can be a hardware module integrated in the interface buffer device and specially used for I2C communication, and the timing of I2C communication, including the driving and receiving logic of the SCL and SDA lines, can be controlled according to the dedicated hardware logic, to provide more stable communication between the interface buffer device and the I2C slave interfaces of the corresponding plurality of slave devices. The interface buffer device can take a micro controller unit (MCU) as the core, and the MCU can provide more I2C master interfaces for the master device through the hardware I2C master interface and the rich GPIO interface. When the number of hardware I2C master interfaces of the interface buffer device is insufficient to meet the communication needs of the plurality of slave devices, the interface buffer device can be extended with I2C master interfaces, for example, the interface that implements the I2C master interface function by software. The other interfaces of the interface buffer device can be modified by software to obtain an interface with the I2C master interface function, achieving the effect of I2C master interface extension with high cost-effectiveness and strong programmability.

[0038] As an optional embodiment, the plurality of I2C master interfaces can also be used for communication with an I2C gating expansion device, and the I2C gating expansion device selects communication with the I2C slave interfaces of the plurality of slave devices. Through the communication between the I2C master interface and the I2C gating expansion device, one I2C master interface can communicate with the I2C slave interfaces of the plurality of slave devices. On the one hand, when the addresses of the plurality of slave devices are the same, in order to avoid the problem of addressing failure caused by address conflict, the plurality of slave devices with the same address can be connected to one I2C master interface through the I2C gating expansion device, so as to ensure that only one of the plurality of slave devices with the same address communicates with the interface buffer device at the same time. On the other hand, the I2C gating expansion device can further expand the number of slave devices that can be managed by the plurality of I2C master interfaces, and increase the flexibility and scalability of the interface buffer device.

[0039] The control unit 13 is configured to control the uplink interface and the plurality of I2C master interfaces, and process the data received from the uplink interface and the data received from the plurality of I2C master interfaces.

[0040] As an optional embodiment, the control unit can control the operation of the entire interface buffer device, including controlling the uplink interface and the plurality of I2C master interfaces, and processing the data received from the uplink interface and the data received from the plurality of I2C master interfaces. The control unit can also process other data received from the uplink interface and data received from the plurality of I2C master interfaces based on the rule data received from the uplink interface, and actively control the uplink interface and the plurality of I2C master interfaces based on the processed data. By managing the uplink interface connection with the master device, the correct transmission and reception of data is ensured, and by controlling the working state and data transmission process of the plurality of I2C master interfaces, efficient communication with the plurality of slave devices is achieved. The control unit can also process the data received from the uplink interface and the data received from the plurality of I2C master interfaces, for example, parse the data received from the uplink interface, understand the instructions or requests sent by the master device, and convert them into appropriate control signals for driving the I2C master interface. For another example, process the data received from the plurality of slave devices by the plurality of I2C master interfaces, integrate, verify, filter and format convert as necessary, so as to efficiently and accurately feed back to the master device through the uplink interface. Through the control unit, the interface buffer device can have certain data processing and error correction capabilities, thereby allowing the master device to only send high-level instructions without worrying about the specific I2C communication details, thereby improving the speed and accuracy of data access between the master device, the interface buffer device and the plurality of slave devices. In addition, in the case of master device failure, the control unit can temporarily take over the control of the plurality of I2C master interfaces, reducing the impact of the failure on the slave devices.

[0041] The storage unit 14 is configured to store the data received from the uplink interface, the data received from the plurality of I2C master interfaces, and the processed data obtained by processing the data received from the uplink interface by the control unit.

[0042] As an optional embodiment, the storage unit can store the data generated during the operation of the interface buffer device, including the data received by the uplink interface, the data received by the plurality of I2C master interfaces, and the processed data obtained by processing the data received by the uplink interface and the data received by the plurality of I2C master interfaces, thereby supporting efficient operation and data processing of the interface buffer device. Among them, by storing the data received by the uplink interface and the data received by the plurality of I2C master interfaces, subsequent processing or forwarding of the received data is facilitated. By storing the processed data obtained by processing the data received by the uplink interface and the data received by the plurality of I2C master interfaces, such as intermediate data or final data generated after processing, the processing process and processing result can be recorded, facilitating subsequent tracing or error correction based on the record.

[0043] As an optional embodiment, the interface buffer device can further include a plurality of GPIO extension interfaces respectively in communication with the corresponding plurality of slave devices. The GPIO extension interface can directly read the state information of the slave device, such as power state, fault indication, and other simple signals not covered by the I2C protocol, and can also be used to directly control some functions of the device, such as switch operation, reset signal, and the like. The GPIO extension interface can also serve as auxiliary communication and control for I2C communication. For example, in some scenarios, I2C communication may not be sufficient to meet the comprehensive device management requirements, and the GPIO extension interface can assist I2C communication by sending a wake-up signal or a configuration signal to prepare the slave device to enter an I2C communication state, or to reset the device or manage the power supply after communication. Since the interface buffer device itself has a large number of GPIO interfaces, some of the GPIO interfaces can be used as GPIO extension interfaces to expand the number of such interfaces in the case of insufficient GPIO interfaces on the host device.

[0044] By using the interface buffer circuit, the host device is communicated through the uplink interface, the plurality of integrated circuit I2C master interfaces are respectively in communication with the I2C slave interfaces of the plurality of slave devices, the control unit is used to control the uplink interface and the plurality of I2C master interfaces, and to process the data received from the uplink interface and the data received from the plurality of I2C master interfaces, and the storage unit is used to store the data received from the uplink interface, the data received from the plurality of I2C master interfaces, and the processing data of the control unit processing the received data, achieving the purpose of connecting the I2C master interface of the host device and the I2C slave interfaces of the plurality of slave devices, thereby realizing the expansion of the I2C interface and accelerating the communication speed of the host device and the plurality of slave devices, and further solving the technical problem of slow communication speed caused by the limited number of I2C master interfaces of the controller in the related art and the selection of communication with the I2C slave interfaces of the peripheral devices.

[0045] According to the embodiments of the present application, an integrated circuit communication system is provided. Figure 2 is a structural block diagram of an integrated circuit communication system according to the embodiments of the present application, as shown in Figure 2 The integrated circuit communication system includes a host device, a plurality of slave devices, and the interface buffer device described above.

[0046] As an optional embodiment, the master device can be a CPU with powerful processing capability, which can be responsible for the overall control of initialization of communication, sending of instructions and receiving of data, and can establish connection with the interface buffer device through the high-speed uplink interface, send instructions or data, and receive processed and integrated information at the same time. The slave device is the final target of communication of the master device, and can be various types of sensors, actuors, storage devices or other functional modules. By adding the interface buffer device between the master device and the plurality of slave devices, the interface buffer device can be responsible for communication management, data processing and integration, and resource allocation and optimization, so as to significantly improve the speed and accuracy of data transmission between the master device and the plurality of slave devices.

[0047] As an optional embodiment, the integrated circuit communication system can further include an I2C gating expansion device in communication with a plurality of I2C master interfaces, and the I2C gating expansion device is in selective communication with I2C slave interfaces of a plurality of slave devices. Through communication of the I2C master interface with the I2C gating expansion device, one I2C master interface can be in communication with a plurality of I2C slave interfaces of the slave devices. On the one hand, when the addresses of the plurality of slave devices are the same, in order to avoid the problem of address conflict leading to failure of addressing, the plurality of slave devices with the same address can be connected with one I2C master interface through the I2C gating expansion device, so as to ensure that only one of the plurality of slave devices with the same address communicates with the interface buffer device at the same time. On the other hand, through the I2C gating expansion device, the number of slave devices that can be managed by the plurality of I2C master interfaces can be further expanded, and the flexibility and scalability of the interface buffer device can be increased.

[0048] According to an embodiment of the present application, an embodiment of an integrated circuit communication method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described herein can be executed in an order different from that shown herein.

[0049] Figure 3 is a flowchart of an integrated circuit communication method according to an embodiment of the present application, as shown in Figure 3 the method comprises the following steps:

[0050] In step S302, data sent by the master device is received through the uplink interface.

[0051] As an optional embodiment, the execution subject of the method of the present embodiment can be the interface buffer device described above, which can receive, process and forward data sent by the master device and the plurality of slave devices.

[0052] As an optional embodiment, the uplink interface can be an interface with a transmission rate exceeding a predetermined threshold. The number of uplink interfaces can be one or multiple. Through the uplink interface, the interface buffer device can receive data sent by the host device. For example, when the data sent by the host device arrives, the uplink interface can receive the data packet and perform preliminary verification to ensure the integrity and accuracy of the data packet. Once the verification is passed, the uplink interface sends an acknowledgement signal to the host device indicating that the data has been successfully received.

[0053] In step S304, the data sent by the host device is processed to obtain processed data.

[0054] As an optional embodiment, processing the data sent by the host device can include processing the data and verifying the data. By processing the data, the amount of data transmission can be reduced, the communication speed can be accelerated, and the waiting time of the host device and the slave device can be reduced. By verifying the data, the accuracy of the data during processing and transmission can be ensured, and data errors or losses can be prevented. In addition, processing the data sent by the host device can also include advanced processing such as data filtering, error correction, and logical operation, which can enhance the intelligent level and adaptive ability of the interface buffer device and further reduce the burden of the host device.

[0055] In step S306, a target I2C master interface is selected from the plurality of I2C master interfaces.

[0056] As an optional embodiment, the plurality of I2C master interfaces can correspond to the I2C slave interfaces of the plurality of slave devices, respectively. The data sent by the host device can be related to all slave devices or to part of the slave devices. By selecting a target I2C master interface from the plurality of I2C master interfaces, communication can be established with the slave devices that need to receive instructions from the plurality of slave devices, so as not to occupy the operating resources of the slave devices that do not need to receive instructions.

[0057] In step S308, the processed data is sent to the I2C slave interface of the corresponding slave device through the target I2C master interface.

[0058] As an optional embodiment, through the target I2C master interface, communication can be established between the interface buffer device and the I2C slave interface of the corresponding slave device, so as to send the processed data to the I2C slave interface of the corresponding slave device. The processed data can be serialized data and can be transmitted through the SCL and SDA lines, complying with the timing and level requirements of the I2C protocol. Before actual data transmission, the interface buffer device can perform a final format check on the data to ensure that the data meets the requirements of the I2C protocol. During actual data transmission, the processed data can be simultaneously sent to the I2C slave interface of the corresponding slave device through multiple target I2C master interfaces, improving the response speed of the slave device and the throughput of the interface buffer device.

[0059] As an optional embodiment, when sending the processed data to the I2C slave interface of the corresponding slave device through the target I2C master interface, the processed data can be sent to the I2C gating expansion device through the target I2C master interface; based on the corresponding slave device selected by the I2C gating expansion device, the processed data is sent to the I2C slave interface of the corresponding slave device. The I2C gating expansion device can serve as a communication intermediary and be responsible for gating and distributing data among multiple I2C slave devices with the same address. In combination with the interface buffer device, the host device can effectively communicate with multiple slave devices without worrying about underlying address conflicts and communication scheduling issues.

[0060] Step S3010, receiving response data fed back by the corresponding slave device through the target I2C master interface.

[0061] As an optional embodiment, the target I2C master interface can not only send the processed data to the I2C slave interface of the corresponding slave device, but also receive the response data fed back by the corresponding slave device. Before the slave device starts sending the response data, the target I2C master interface can be started to prepare for receiving. After the slave device sends the response data to the target I2C master interface through its I2C slave interface according to the I2C communication protocol, the target I2C master interface can receive the response data, which can include operation results, status information, or request confirmation, etc. The target I2C master interface can also check the received response data to ensure the integrity of the response data in the transmission process.

[0062] Step S3012, processing the response data to obtain processed response data.

[0063] As an optional embodiment, processing the response data can include preliminary analysis and data reorganization of the response data, for example, identifying the type and source of the response data to prepare for subsequent processing. For another example, formatting the original response data according to the needs of the host device can include re-encoding, compressing, or converting the data into a specific data structure, so that the host device can more efficiently parse and use the data. If the host device needs to process the status of multiple slave devices, all status information can be integrated into one report instead of sending the response of each device separately. In addition to this, processing the response data can also include higher-level data processing, such as anomaly detection, threshold monitoring, data filtering, and logical operation. Through these processes, the interface buffer device can autonomously identify anomalies or important information in the data, such as device failure, performance indicator anomaly, etc., and make preliminary decisions or responses according to the pre-set rules when necessary, such as automatically isolating the faulty device or adjusting the system settings. This advanced processing capability relieves the burden of the host device and improves the overall response speed and processing efficiency.

[0064] In step S3014, the processed response data is sent to the host device through the uplink interface.

[0065] As an optional embodiment, the processed response data is sent to the host device through the uplink interface, and a large amount of processed response data can be sent to the host device at one time by using the high transmission rate of the uplink interface, thereby significantly improving the data transmission rate and ensuring that the response data can be quickly transmitted from the interface buffer device to the host device. By sending the processed response data, the data processing burden of the host device can be reduced, so that it can focus on the execution of core tasks.

[0066] Through the above steps, the I2C master interface of the host device and the I2C slave interface of the plurality of slave devices can be connected, thereby achieving the technical effects of expanding the I2C interface and accelerating the communication speed of the host device and the plurality of slave devices, and further solving the technical problem of slow communication speed caused by the limited number of I2C master interfaces of the controller and the selection of communication with the I2C slave interface of the peripheral device in the related art.

[0067] In combination with the above embodiments and optional embodiments, an optional implementation is provided. In the optional implementation, a single Master multi-I2C Slaver system capable of fast response is proposed, and the core is an MCU (or CPU chip, DSP chip, and other chips or circuit units with operation processing capability) to realize an interface buffer circuit (equivalent to the interface buffer device described above). The circuit communicates with the host CPU using a high-speed interface such as SPI, USB, and PCIe, and the other side provides a plurality of I2C master interfaces. The interface buffer circuit can also have a certain capacity of internal memory for storing data. Through the high-speed interface and the plurality of I2C master interfaces provided by the interface buffer circuit, the plurality of I2C master interfaces can access the plurality of I2C slave interfaces at the same time, and the information can be cached in the internal memory. After the information is integrated, the data is sent to the host CPU in a predetermined format through the high-speed interface, thereby realizing the fast access of the host CPU to the plurality of slave devices. Figure 4 is a structural block diagram of a single Master multi-I2C Slaver system capable of fast response according to an optional embodiment of the present application, as shown in Figure 4 The system includes the following modules.

[0068] The host CPU, i.e., the original single Master, is the initiator and the leader of all I2C communications.

[0069] Interface buffer circuit, namely the new circuit module introduced by the system, the core of which is MCU (or CPU, but the general specification is lower than the main CPU, or other chips with data operation ability). As shown in Figure 4 The interface buffer circuit includes the following units, which can be logically divided functional modules in the same chip, or can be separate multiple physical electronic components, and there is interconnection between them, which is not shown in the figure.

[0070] (1) Control unit: responsible for controlling the operation of the entire interface buffer circuit, including the control of each interface, the processing of interface data, and part of the management and response ability of the slave.

[0071] (2) Storage unit: used for caching and CPU communication data, I2C master interface data, and control unit operation data, etc.

[0072] (3) Uplink interface unit: responsible for high-speed interface communication with the CPU, with high speed, such as SPI (20MHz), USB (480MHz), PCIe (2GHz) and other types of interfaces, which can be selected according to actual needs.

[0073] (4) I2C master module: there are multiple I2C master modules, each of which can communicate with one or more I2C slaves, and can also be combined with I2C gating expansion circuit to access multiple I2C slaves with the same address. The I2C master module of the interface buffer circuit can be the I2C interface of the MCU / CPU, or the GPIO interface which is realized as an I2C interface by software control.

[0074] In particular, since the MCU / CPU has multi-task processing capability, the interface buffer circuit can work with multiple I2C masters in parallel without interference, greatly improving the access rate of peripherals. Further, the interface buffer circuit can also determine the next operation based on the data obtained by access, greatly reducing the load of the main CPU.

[0075] For example, the main CPU can only send a "read all I2C peripheral register content" instruction, and the MCU / CPU in the interface buffer circuit will start all I2C masters and read all register information, store it in the storage unit, and perform certain data processing to pass it to the main CPU through the uplink interface unit in a specific format (data compression and data verification can be added).

[0076] For example, the main CPU can send a command of "read all I2C fan devices and feedback the specific rotation speed of the fan device with a rotation speed lower than 5000", and the MCU / CPU in the interface buffer circuit can open the I2C master module for the I2C fan device according to the command and the parameters preset when the interface buffer circuit is initialized, read the actual rotation speed of the corresponding fan device, compare the actual rotation speed with the threshold value of 5000, filter out the value lower than 5000, store the value in the storage unit, and perform certain data processing to deliver the value to the main CPU in a specific format (data compression and data verification can be added) through the uplink interface unit.

[0077] (5) GPIO expansion module: in the communication process between the main CPU and the I2C slave, there is often state control in addition to data transmission. The GPIO expansion module can realize different functions from the I2C master module. The I2C master module can be used for data transmission, and the GPIO expansion module can be used for state control. Through the GPIO expansion module, the data sent by the CPU can be converted into the GPIO format and sent to multiple slave devices to realize the GPIO expansion function.

[0078] Through the system, the CPU can access multiple I2C slaves through a high-speed interface, and has the following advantages: high theoretical bandwidth, for example, the CPU and the interface buffer circuit communicate through the SPI interface, which is equivalent to 200 I2C master interfaces communicating with 200 I2C slave interfaces at the same time (the I2C interface transmission rate is 100 kHz, and the SPI interface transmission rate is 20 MHz), which can realize fast response; high communication reliability, because the interface buffer module itself has a certain computing power, it can realize functions such as data verification, flow control, and repeated information merging, to ensure reliable and efficient communication of the system; fast response speed, because the port buffer circuit has a certain computing function, the trigger condition and processing rules can be set by the host CPU in advance, and the interface buffer circuit can process the I2C slave in real time based on the autonomous response function, such as timed response, abnormal isolation, threshold monitoring trigger information reporting, and interrupt priority grading; strong scalability, the I2C master interface of the interface buffer circuit can be the I2C interface of the MCU / CPU, or it can be realized by software control, so the resource allocation in the buffer interface circuit can be adjusted according to the number of slaves and communication requirements, without modifying the circuit, the actual requirements of each slave can be met; cost advantage, for devices with low complexity, the interface expansion circuit based on complex programmable logic device (CPLD) or field-programmable gate array (FPGA) has high cost and is difficult to bear, while the core device MCU of the interface buffer circuit has a significantly lower cost, so it can be widely applied.

[0079] According to the embodiment of the present application, a kind of integrated circuit communication device is provided, Figure 5 It is the structure diagram of a kind of integrated circuit communication device according to the embodiment of the present application, as Figure 5 Shown, the device includes: first receiving module 502, first processing module 504, selection module 506, first sending module 508, second receiving module 5010, second processing module 5012 and second sending module 5014, the device is described as follows.

[0080] The first receiving module 502 is configured to receive data sent by the host device through an uplink interface; the first processing module 504 is connected to the first receiving module 502 and configured to process the data sent by the host device to obtain processed data; the selection module 506 is connected to the first processing module 504 and configured to select a target I2C master interface from a plurality of I2C master interfaces of integrated circuits; the first sending module 508 is connected to the selection module 506 and configured to send the processed data to an I2C slave interface of a corresponding slave device through the target I2C master interface; the second receiving module 510 is connected to the first sending module 508 and configured to receive response data fed back by the slave device through the target I2C master interface; the second processing module 512 is connected to the second receiving module 510 and configured to process the response data to obtain processed response data; and the second sending module 514 is connected to the second processing module 512 and configured to send the processed response data to the host device through the uplink interface.

[0081] It should be noted that the first receiving module 502, the first processing module 504, the selection module 506, the first sending module 508, the second receiving module 510, the second processing module 512, and the second sending module 514 correspond to steps S302 to S314 in the embodiment, and the plurality of modules have the same instances and application scenarios as the steps, but are not limited to the content disclosed in the above embodiment.

[0082] As an optional embodiment, the first sending module 508 includes a first sending unit and a second sending unit. The first sending unit is configured to send the processed data to an I2C gating expansion device through the target I2C master interface; and the second sending unit is connected to the first sending unit and configured to send the processed data to an I2C slave interface of a corresponding slave device based on the corresponding slave device selected by the I2C gating expansion device.

[0083] According to an embodiment of the present application, a computer readable storage medium is provided, which includes a stored executable program, wherein the computer readable storage medium controls a device where the computer readable storage medium is located to perform the integrated circuit communication method in any of the above embodiments when the executable program is executed.

[0084] According to an embodiment of the present application, an electronic device is provided, which includes a memory storing an executable program and a processor configured to execute the program, wherein the program performs the integrated circuit communication method in any of the above embodiments when executed.

[0085] According to an embodiment of the present application, a computer program product is provided, which includes a computer program, and the computer program is executed by a processor to implement the steps of the method in any of the above embodiments.

[0086] The above-mentioned embodiment numbers of the present application are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0087] In the above-mentioned embodiments of the present application, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0088] In several embodiments provided in the present application, it should be understood that the disclosed technical contents can be implemented by other ways. Among them, the above-mentioned device embodiments are only schematic, for example, the division of the units can be a logical function division, and actual implementation can have another division way, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units or modules shown or discussed can be indirect coupling or communication connection through some interfaces, units or modules, which can be electrical or other forms.

[0089] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place or distributed to multiple units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0090] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be realized in the form of hardware or in the form of software functional unit.

[0091] The integrated unit, if realized in the form of software functional unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application or the whole or part of the technical solutions which essentially contribute to the prior art can be embodied in the form of software product, which is stored in a storage medium and includes a plurality of instructions for making a computer device (which can be a personal computer, a server or a network device, etc.) execute all or part of the steps of the method described in each embodiment of the present application. The above-mentioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and various program code storage media.

[0092] The above merely describes the preferred embodiments of the present application, and it should be pointed out that, for those skilled in the art, several improvements and refinements can be made without departing from the principles of the present application, and these improvements and refinements should also be considered as falling within the protection scope of the present application.

Claims

1. An interface buffer device, characterized in that: include: Uplink interface, communicating with the main device; Multiple integrated circuit I2C master interfaces communicate with corresponding I2C slave interfaces of multiple slave devices respectively; a control unit, configured to control the uplink interface and the plurality of I2C master interfaces, and process data received from the uplink interface and data received from the plurality of I2C master interfaces; The storage unit is used to store data received from the uplink interface, data received from the multiple I2C master interfaces, and processed data obtained after the control unit processes the received data.

2. The interface buffer device according to claim 1, characterized in that: The uplink interface is an interface whose transmission rate exceeds a predetermined threshold.

3. The interface buffer device according to claim 1, characterized in that: The types of the multiple I2C master interfaces include at least one of the following: a hardware I2C master interface of the interface buffer device, and an interface of the interface buffer device that implements an I2C master interface function in a software manner.

4. The interface buffer device according to claim 1, characterized in that: The multiple I2C master interfaces are also used to communicate with an I2C strobe expansion device, and the I2C strobe expansion device selectively communicates with the I2C slave interfaces of multiple slave devices.

5. The interface buffer device according to claim 1, characterized in that: Also includes: Multiple GPIO expansion interfaces communicate with corresponding multiple slave devices.

6. The interface buffer device according to claim 1, characterized in that: The control unit is further configured to process other data received from the upstream interface and data received from the multiple I2C master interfaces based on the rule data received from the upstream interface, and actively control the upstream interface and the multiple I2C master interfaces based on the processed data.

7. An integrated circuit communication system, characterized in that: include: A master device, a plurality of slave devices, and the interface buffer device according to any one of claims 1 to 6.

8. The integrated circuit communication system according to claim 7, wherein: Also includes: An I2C strobe expansion device that communicates with the multiple I2C master interfaces, the I2C strobe expansion device selectively communicating with the I2C slave interfaces of the multiple slave devices.

9. An integrated circuit communication method, characterized in that: include: Receive data sent by the master device through the uplink interface; Processing the data sent by the master device to obtain processed data; Select a target I2C master interface from multiple I2C master interfaces; Sending the processed data to the I2C slave interface of the corresponding slave device through the target I2C master interface; Receive the response data fed back by the corresponding slave device through the target I2C master interface; Processing the response data to obtain processed response data; The processed response data is sent to the master device via the uplink interface.

10. The integrated circuit communication method according to claim 9, wherein: The step of sending the processed data to an I2C slave interface of a corresponding slave device through the target I2C master interface includes: Sending the processed data to the I2C strobe expansion device via the target I2C master interface; Based on the corresponding slave device selected by the I2C strobe expansion device, the processed data is sent to the I2C slave interface of the corresponding slave device.

11. An integrated circuit communication device, characterized in that: include: A first receiving module, configured to receive data sent by the master device through an uplink interface; a first processing module, configured to process the data sent by the master device to obtain processed data; A selection module, configured to select a target I2C master interface from a plurality of integrated circuit I2C master interfaces; A first sending module, configured to send the processed data to an I2C slave interface of a corresponding slave device through the target I2C master interface; A second receiving module, configured to receive the response data fed back by the slave device through the target I2C master interface; A second processing module is used to process the response data to obtain processed response data; The second sending module is configured to send the processed response data to the master device through the uplink interface.

12. A computer-readable storage medium, characterized in that The computer-readable storage medium includes a stored executable program, wherein when the executable program is run, the device where the computer-readable storage medium is located is controlled to execute the integrated circuit communication method according to any one of claims 9 to 10.

13. An electronic device, characterized in that: include: a memory storing an executable program; A processor, configured to run the program, wherein the integrated circuit communication method according to any one of claims 9 to 10 is executed when the program is run.

14. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 9 to 10 are implemented.

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