Data reading and writing method, system and equipment and storage medium

Abstract

The invention relates to the field of data processing, and provides a data read-write method, system and device and a storage medium, and the method comprises the steps: obtaining a read-write type of a data read-write instruction; when the read-write type is a read type, acquiring an arbitration mode for the data read-write instruction; determining a target pointer position of a read pointer based on the arbitration mode; the target pointer position represents a target reading address of a cache region pointed by a reading pointer; and obtaining to-be-read data based on the target pointer position, and performing reading processing on the to-be-read data. According to the method and the device, the data are read in different modes based on different arbitration modes, the target position of the read pointer can be dynamically determined according to a real-time scene, blockage or delay caused by fixed sequence access is avoided, and the flexibility and the efficiency of reading the data in the cache region are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of data processing, and in particular to a data read-write method, system, device and storage medium. BACKGROUND

[0002] The existing chip usually adopts a first-in first-out (FIFO) data buffer structure for data reading, specifically, the data is stored and read according to the order of arrival, that is, the data that enters first is taken out first. However, due to its fixed order characteristics, all data must be processed strictly according to the entering order, resulting in low flexibility in scenarios where certain specific data needs to be processed preferentially. SUMMARY

[0003] The present application provides a data read-write method, system, device and storage medium to at least solve the above technical problems in the prior art.

[0004] According to a first aspect of the present application, a data read-write method is provided, the method comprising: obtaining a read-write type of a data read-write instruction; when the read-write type is a read type, obtaining an arbitration mode for the data read-write instruction; determining a target pointer position of a read pointer based on the arbitration mode; the target pointer position represents a target read address of a cache area pointed to by the read pointer; obtaining to-be-read data based on the target pointer position, and performing read processing on the to-be-read data.

[0005] In an implementable manner, the method further comprises: when the read-write type is a write type, determining a current pointer position of a write pointer; the current pointer position represents a current storage address of a cache area pointed to by the write pointer; obtaining to-be-written data with priority encoding information and weight information; performing write processing on the to-be-written data based on the current pointer position.

[0006] In an implementable manner, the cache area comprises at least two segment cache areas; and the determining of the target pointer position of the read pointer based on the arbitration mode comprises: when the arbitration mode is a first arbitration mode, for any segment cache area, a priority total score for the segment cache area is obtained based on the priority encoding information of the cached data in the segment cache area; the priority total scores of the segment cache areas are sorted in descending order, and each segment cache area corresponding to the sorted priority total score is sequentially taken as a first target cache area, and a head address of the first target cache area is sequentially taken as the target pointer position of the read pointer.

[0007] In an implementation, the obtaining the data to be read based on the target pointer position and performing read processing on the data to be read comprises: obtaining all cache data in the first target cache region based on the target pointer position, and performing read processing on the all cache data as the data to be read.

[0008] In an implementation, the cache region comprises at least two segment cache regions; and the determining the target pointer position of the read pointer based on the arbitration mode comprises: when the arbitration mode is the second arbitration mode, obtaining a weight value for each segment cache region based on weight information of cache data in the segment cache region; in each read cycle, taking the segment cache region with the highest weight value in the segment cache regions as the second target cache region and performing unit decrement on the weight value of the second target cache region, and alternately circulating until the weight values of the segment cache regions are all decremented to zero; and taking the first address of the second target cache region in each read cycle as the target pointer position of the read pointer in sequence.

[0009] In an implementation, the obtaining the data to be read based on the target pointer position and performing read processing on the data to be read comprises: obtaining part of cache data in the second target cache region based on the target pointer position, and performing read processing on the part of cache data as the data to be read.

[0010] In an implementation, the method further comprises: obtaining a write pointer count and a read pointer count based on a number of write processing and a number of read processing; generating water level prompt information based on the write pointer count, the read pointer count and a preset count threshold; the water level prompt information is used to determine whether overflow of the cache region occurs.

[0011] In an implementation, the method further comprises: obtaining a data access instruction for the cache region; the data access instruction comprises a data access address; a real-time level of the data access instruction is higher than a real-time level of the data read-write instruction; determining a to-be-accessed address of the cache region based on the data access address and a preset mapping relationship; the mapping relationship represents a corresponding relationship between the data access address and a cache address of the cache region; performing data access on the cache region based on the to-be-accessed address.

[0012] According to a second aspect of the present application, a data read-write system is provided, and the system comprises: The mode selection module is configured to acquire a read-write type of a data read-write instruction; and acquire an arbitration mode for the data read-write instruction when the read-write type is a read type. The arbitration module is configured to determine a target pointer position of a read pointer based on the arbitration mode; and the target pointer position represents a target read address of a cache area pointed to by the read pointer. The read logic module is configured to acquire to-be-read data based on the target pointer position, and perform read processing on the to-be-read data.

[0013] In an implementation, the system further includes: The write logic module is configured to determine a current pointer position of a write pointer when the read-write type is a write type; the current pointer position represents a current storage address of a cache area pointed to by the write pointer; acquire to-be-written data with priority encoding information and weight information; and perform write processing on the to-be-written data based on the current pointer position.

[0014] In an implementation, the cache area includes at least two segment cache areas. The arbitration module includes a fixed priority module configured to, when the arbitration mode is a first arbitration mode, for any segment cache area, obtain a priority total score for the segment cache area based on priority encoding information of cache data in the segment cache area; sort the priority total scores of the segment cache areas in descending order, sequentially take each segment cache area corresponding to the sorted priority total scores as a first target cache area, and sequentially take a start address of the first target cache area as a target pointer position of a read pointer.

[0015] In an implementation, the read logic module is configured to acquire all cache data in the first target cache area based on the target pointer position, and perform read processing on the all cache data as to-be-read data.

[0016] In an implementation, the cache area includes at least two segment cache areas; and the arbitration module includes a polling arbitration module configured to, when the arbitration mode is a second arbitration mode, for any segment cache area, obtain a weight value for the segment cache area based on weight information of cache data in the segment cache area; in any read cycle, take a segment cache area with a highest weight value in the segment cache areas as a second target cache area and perform unit decrement on the weight value of the second target cache area, and alternately cycle until the weight values of the segment cache areas are all decremented to zero; and sequentially take a start address of the second target cache area in each read cycle as a target pointer position of a read pointer.

[0017] In an implementation, the read logic module is configured to acquire part of cache data in the second target cache area based on the target pointer position, and perform read processing on the part of cache data as to-be-read data.

[0018] In an implementation, the system further comprises: a write pointer counting module configured to obtain a write pointer count based on a number of write processes; a read pointer counting module configured to obtain a read pointer count based on a number of read processes; a data water level detecting module configured to generate a water level prompt based on the write pointer count, the read pointer count, and a preset threshold value; the water level prompt is used to determine whether overflow occurs in the cache area.

[0019] In an implementation, the system further comprises: a fast access module configured to obtain a data access instruction for the cache area; the data access instruction comprises a data access address; a real-time level of the data access instruction is higher than a real-time level of the data read-write instruction; a to-be-accessed address of the cache area is determined based on the data access address and a preset mapping relationship; the mapping relationship represents a correspondence between the data access address and a cache address of the cache area; and data access is performed on the cache area based on the to-be-accessed address.

[0020] According to a third aspect of the present application, an electronic device is provided, comprising: at least one processor; and a memory connected to the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method described in the present application.

[0021] According to a fourth aspect of the present application, a non-transitory computer readable storage medium storing computer instructions is provided, the computer instructions are used to enable the computer to perform the method described in the present application.

[0022] In the present application, the read-write type of the data read-write instruction is obtained; when the read-write type is a read type, the arbitration manner for the data read-write instruction is obtained; the target pointer position of the read pointer is determined based on the arbitration manner; the target pointer position represents a target read address of the cache area pointed to by the read pointer; the to-be-read data is obtained based on the target pointer position, and read processing is performed on the to-be-read data.

[0023] Compared with the related art, the present application has the following beneficial effects: the related art can only strictly process data in a fixed order regardless of the scene requirement, while the present application reads data in different manners based on different arbitration manners, can dynamically determine the target position of the read pointer according to the real-time scene, avoids the blocking or delay problem caused by the fixed order access of the related art, and improves the flexibility and efficiency of the cache area data reading.

[0024] It is to be understood that the description of the technology in this section is not intended to identify key or essential features of the application, and that no feature is essential to the application. Other features, aspects, and advantages of the application will become apparent from the following description, which is given for the purpose of illustration and not limitation. BRIEF DESCRIPTION OF DRAWINGS

[0025] The above and other objects, features and advantages of the present application will become more apparent from the following detailed description read in conjunction with the accompanying drawings, in which: In the drawings:

[0026] Figure 1 An implementation flowchart of a data read-write method according to an embodiment of the application is shown; Figure 2 An application diagram of a data read-write method according to an embodiment of the application is shown; Figure 3 A composition diagram of a data read-write system according to an embodiment of the application is shown; Figure 4 A composition structure diagram of an electronic device according to an embodiment of the application is shown. DETAILED DESCRIPTION

[0027] In order to make the purpose, features and advantages of the application more obvious and easy to understand, the technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only some of the embodiments of the application, but not all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the application.

[0028] The embodiments of the application provide a data read-write method, which combines Figure 1 , Figure 2 The method comprises the following steps: S101: Obtain a read-write type of a data read-write instruction.

[0029] In the application, the data read-write instruction is an instruction issued by a user or other request source, which comprises two read-write types, one being a read type and the other being a write type. The read-write type of the data read-write instruction is obtained by decoding and analyzing the data read-write instruction.

[0030] S102: When the read-write type is the read type, obtain an arbitration mode for the data read-write instruction.

[0031] In this step, the arbitration mode is obtained according to the read-write type of the data read-write instruction. Figure 2As shown, when the read-write type is the read type, the data read-write instruction can include the code or high-low level mark corresponding to the arbitration mode of the user instruction, and the arbitration mode for the data read-write instruction can be determined by analyzing the data read-write instruction.

[0032] S103: Determine the target pointer position of the read pointer based on the arbitration mode; the target pointer position represents the target read address of the cache area pointed to by the read pointer.

[0033] In this embodiment, the arbitration mode includes two types: fixed priority arbitration mode and polling arbitration mode. The read pointer is a pointer used to locate the read starting position when reading data, which points to the storage address of the cache area. The read strategy under different arbitration modes is different, and the read starting position (target pointer position) of the corresponding read pointer is also different. For the specific determination process of the read pointer target pointer position, please refer to the detailed description of the relevant places below, which will not be repeated here.

[0034] S104: Obtain the to-be-read data based on the target pointer position, and perform read processing on the to-be-read data.

[0035] In this step, the cache data is read from the cache area as to-be-read data based on the address pointed to by the read pointer target pointer position and is subjected to read processing. For example, assuming that the read pointer target pointer position points to the cache address 1 of the cache area, the data is read starting from the cache address 1, and the read data can be a piece of data or a data. The specific read quantity will be different depending on the arbitration mode, and the specific read mode will be described in detail below, which will not be repeated here.

[0036] In the scheme shown in steps S101-S104, the read-write type of the data read-write instruction is obtained; when the read-write type is the read type, the arbitration mode for the data read-write instruction is obtained; based on the arbitration mode, the target pointer position of the read pointer is determined; the target pointer position represents the target read address of the cache area pointed to by the read pointer; based on the target pointer position, the to-be-read data is obtained, and the to-be-read data is subjected to read processing. Based on different arbitration modes, the data is read in different ways, the target position of the read pointer can be dynamically determined according to the real-time scene, the blocking or delay caused by the fixed order access is avoided, and the flexibility and efficiency of the cache area data read are improved.

[0037] In some optional schemes, the following steps are further included: When the read-write type is the write type, the current pointer position of the write pointer is determined; the current pointer position represents the current storage address of the cache area pointed to by the write pointer; Obtain the to-be-written data with priority encoding information and weight information; Based on the current pointer position, the to-be-written data is subjected to write processing.

[0038] In the present application, in combination with Figure 2 As shown in the figure, when the read-write type of the data read-write instruction is not the read type, i.e., the read-write type of the data read-write instruction is the write type, the current pointer position of the write pointer is directly read, and the address pointed to by the current pointer position of the write pointer is used as a reference to write the to-be-written data into the cache area. Among the data read-write instruction of the write type, the to-be-written data will be included, and the to-be-written data can be obtained by parsing the data read-write instruction. The to-be-written data is data with priority encoding information and weight information. The priority encoding information is used to represent the priority degree of each (batch) data, and the weight information is used to represent the proportion of each (batch) data in the total data. When the to-be-written data is written, the to-be-written data can be written according to the priority encoding information of the to-be-written data, such as writing the to-be-written data with the highest priority first and writing the to-be-written data with the lowest priority last. The to-be-written data can also be directly written in a random order according to the request sequence. The detailed writing method of the present embodiment is not limited in particular. The present application directly uses the current position of the write pointer as the base address for writing, which can save additional address calculation, simplify the control logic, and reduce the write delay; at the same time, the flexible strategy of sequential or random writing is supported, which can balance the real-time performance and the ease of implementation.

[0039] In some optional schemes, the cache area includes at least two segment cache areas; and the determining of the target pointer position of the read pointer based on the arbitration manner includes: When the arbitration manner is the first arbitration manner, for any segment cache area, a priority total score for the segment cache area is obtained based on the priority encoding information of the cached data in the segment cache area. The priority total scores of the segment cache areas are sorted in descending order, and each segment cache area corresponding to the sorted priority total score is sequentially taken as a first target cache area, and the first address of the first target cache area is sequentially taken as the target pointer position of the read pointer.

[0040] In the present application, in combination with Figure 2 As shown in the figure, the first arbitration manner is a fixed priority arbitration manner. The target pointer position of the read pointer is determined based on the priority encoding information of the cached data in the cache area. Specifically, the cache area is processed by 1 / N segmentation in the present embodiment, where N is the number of data sources. Assuming that there are four data sources when the cache area is written, the cache area is divided into four segments to obtain four segment cache areas. The priority total score of each segment cache area is calculated. Specifically, assuming that the priority encoding information has four kinds, and the priority degree represented by the priority encoding information has the mapping relationship shown in Table 1: Table 1

[0041] The priority coding information is all 2-bit binary data. The cache data in the 4 segment cache areas can be of the same priority or different priorities. The priority total of each segment cache area is the sum of the priority coding information of the cache data in the segment cache area. For example, if the priority coding information of the cache data in the first segment cache area includes 00 and 01, the priority total of the first segment cache area is 00+01=01. The priority coding information of the cache data in the second segment cache area is only 10, so the priority total of the second segment cache area is 10. The priority coding information of the cache data in the third segment cache area includes 01 and 10, so the priority total of the third segment cache area is 01+10=11. The segment cache area with the highest priority total in the segment cache area is taken as the first read area (the first target cache area), and the read starting address (target pointer position) of the read pointer is positioned at the start address of the segment cache area, so as to read the cache data in the segment cache area. After the cache data in the first segment cache area is read, the segment cache area with the highest priority total is taken as the second read area from the remaining segment cache areas, and is updated as the new first target cache area. The read starting address (target pointer position) of the read pointer is positioned at the start address of the segment cache area, so as to read the cache data in the segment cache area. In this way, all the cache data in the segment cache areas is read.

[0042] The arbitration based on the priority total sorting can ensure that the bandwidth is preferentially served to the data segment with the highest value, reduce invalid occupation of the cache and the bus by low-priority data, and improve the cache hit rate and the bandwidth utilization. Meanwhile, through the priority total mechanism of the segment cache area, the cache area is segmented according to the data source, and the overall priority of each segment of data is quantified, so as to realize ordered reading of "high first and low later", and significantly reduce the access delay of high-priority data.

[0043] In some optional solutions, the reading of the data to be read based on the target pointer position includes: Based on the target pointer position, all the cache data in the first target cache area is acquired and read as the data to be read.

[0044] In the application, when the arbitration mode is the first arbitration mode, all the cache data in the first target cache area is read each time, and only after the cache data in the previous first target cache area is completely read, the cache data in the next first target cache area can be read. Through the one-time moving of all the data in each segment, the cross-segment random access and address recalculation overhead can be eliminated, continuous and efficient batch transmission can be realized, and the bus utilization rate is significantly improved.

[0045] In some alternatives, the cache area comprises at least two segment cache areas; and the determining the target pointer position of the read pointer based on the arbitration mode comprises: When the arbitration mode is the second arbitration mode, for any segment cache area, a weight value for the segment cache area is obtained based on the weight information of the cached data in the segment cache area; In any read cycle, the segment cache area with the highest weight value in the segment cache areas is taken as a second target cache area and the weight value thereof is unitarily decremented, and the process is alternately repeated until the weight values of all the segment cache areas are decremented to zero; and the start address of the second target cache area in each read cycle is taken as the target pointer position of the read pointer in turn.

[0046] In the present application, the arbitration mode is combined with the weight information of the cached data in the cache area. Figure 2 As shown in the accompanying drawings, the second arbitration mode is a polling arbitration mode. The polling arbitration mode is based on the weight information of the cached data in the cache area to determine the target pointer position of the read pointer. Specifically, the weight value of each segment cache area is obtained by adding the weight information of the cached data in the segment cache area. In each read cycle, the segment cache area with the highest weight value and a non-zero weight value is selected as a second target cache area, and the weight value of the segment cache area is decremented by one. For example, assuming that the weight value of the first segment cache area is 3, the weight value of the second segment cache area is 5, and the weight value of the third segment cache area is 1. In the first read cycle, the segment cache area with the weight value of 5 is taken as the second target cache area, and the weight value thereof is decremented by one. Then, the weight value of the first segment cache area is 3, the weight value of the second segment cache area is 4, and the weight value of the third segment cache area is 1. In the second read cycle, the segment cache area with the weight value of 4 is taken as the second target cache area, and the weight value thereof is decremented by one. Then, the weight value of the first segment cache area is 3, the weight value of the second segment cache area is 3, and the weight value of the third segment cache area is 1. In the third read cycle, any segment cache area with the weight value of 3 is taken as the second target cache area, and the weight value thereof is decremented by one, and so on, until the weight values of all the segment cache areas are zero. The start address of the second target cache area in each read cycle is the target pointer position of the read pointer.

[0047] In the present application, the read opportunities of the cached data in the segment cache areas are distributed in proportion to the weights, which not only ensures that the segment cache areas with high weights obtain more bandwidth, but also avoids long-term starvation of the segment cache areas with low weights, and realizes the fair and efficient sharing of the bandwidth.

[0048] In some alternatives, the obtaining the to-be-read data based on the target pointer position and performing read processing on the to-be-read data comprises: Based on the target pointer position, part of the cached data in the second target cache area is obtained, and the part of the cached data is taken as the to-be-read data for read processing.

[0049] In the present application, when the arbitration mode is the second arbitration mode, each time the partial cache data in the first target cache area is read, it can be understood that one data weight value is read each time, and the cache data in each segment cache area is read alternately until the weight values of each segment cache area are all 0, that is, the cache data in each segment cache area is read completely. In the present embodiment, each segment cache area is read alternately in units of data units, and the low-weight segment cache area can be serviced without waiting for the entire segment to be emptied, which significantly reduces the waiting delay of reading cache data in the low-weight cache area.

[0050] In some optional solutions, the method further includes: obtaining a write pointer count and a read pointer count based on the number of write processes and the number of read processes; generating water level prompt information based on the write pointer count, the read pointer count, and a preset count threshold; the water level prompt information is used to determine whether overflow occurs in the cache area.

[0051] In the present application, the write pointer and the read pointer move once each time a write process and a read process are performed, and a count is generated once, that is, the write pointer count is the same as the number of write processes, and the read pointer count is the same as the number of read processes. The preset count threshold is a preset baseline threshold, which is usually a value obtained by subtracting 1 from the depth of the cache area. The used space of the cache area = the write pointer count - the read pointer count after synchronization. By synchronizing the write pointer and the read pointer in the clock domain, the metastability problem caused by cross-clock-domain in the asynchronous cache can be avoided, thereby ensuring the accuracy of the used space calculation. By comparing the used space with the baseline threshold, when the difference between the used space and the baseline threshold is less than a fixed value, it indicates that the data amount in the cache is close to full, and the water level prompt information of “about to overflow” is generated to notify the sending end to stop or slow down data writing. When the difference between the used space and the baseline threshold is greater than another fixed value, it indicates that the data amount in the cache is close to empty, and the water level prompt information of “about to underflow” is generated to notify the receiving end to pause data reading. The method can dynamically adapt to scenarios where the data amount is too large or too small, and ensure the efficiency of cache access.

[0052] In some optional solutions, the method further includes: obtaining a data access instruction for the cache area; wherein the data access instruction includes a data access address; the real-time level of the data access instruction is higher than the real-time level of the data read-write instruction; determining a to-be-accessed address of the cache area based on the data access address and a preset mapping relationship; the mapping relationship represents the correspondence between the data access address and the cache address of the cache area; performing data access on the cache area based on the to-be-accessed address.

[0053] In the present application, the data access instruction is a fast access instruction, which is usually applied to a scene with high real-time requirement, and can quickly access or modify the cache data of the cache area. Specifically, in the chip, the cache is usually regarded as a linear black box that can only be sequentially in and out. If the CPU or other debugging tools want to directly read / modify a certain data slot, they must first disassemble the black box into an SRAM with an address. The data access instruction includes a data access address, which is the address on the aforementioned SRAM. According to the correspondence between the SRAM address and the cache area depth (cache address), the to-be-accessed address of the cache area can be located, and the cache data corresponding to the to-be-accessed address is read or modified. Compared with the related art of sequentially reading all data and then picking up the target data, the embodiment of the present application can directly hit the data to be accessed or modified through the mapping relationship, greatly reducing the time complexity and improving the data access efficiency.

[0054] The present application also provides a data read-write system, as shown in Figure 3 The system comprises: A mode selection module is configured to obtain a read-write type of a data read-write instruction, and obtain an arbitration manner for the data read-write instruction when the read-write type is a read type. An arbitration module is configured to determine a target pointer position of a read pointer based on the arbitration manner, and the target pointer position represents a target read address of a cache area pointed to by the read pointer. A read logic module is configured to obtain to-be-read data based on the target pointer position, and perform read processing on the to-be-read data.

[0055] In the read logic module, when a read enable signal is valid and the cache area is not empty, the data of the target read address of the cache area pointed to by the read pointer is read, and then the read pointer is incremented to point to the next readable position.

[0056] In some optional schemes, the system further comprises: A write logic module is configured to determine a current pointer position of a write pointer when the read-write type is a write type, the current pointer position represents a current storage address of a cache area pointed to by the write pointer, obtain to-be-written data with priority encoding information and weight information, and perform write processing on the to-be-written data based on the current pointer position.

[0057] In the write logic module, when a write enable signal is valid and the cache area is not full, the current storage address of the cache area pointed to by the write pointer is written with data, and then the write pointer is incremented to point to the next writable position.

[0058] In some optional schemes, the cache area comprises at least two segment cache areas. The arbitration module comprises a fixed priority module, configured to, when the arbitration mode is the first arbitration mode, obtain, for any segment cache area, a priority total score for the segment cache area based on priority encoding information of cache data in the segment cache area; sort the priority total scores of the segment cache areas in descending order, and sequentially take each segment cache area corresponding to the sorted priority total scores as a first target cache area, and sequentially take a start address of the first target cache area as a target pointer position of the read pointer.

[0059] In the embodiments of the present application, the fixed priority module specifically comprises a priority counter and a segment priority register. The priority counter is configured to calculate the priority total scores of the segment cache areas. The segment priority register is configured to store the priority total scores of the segment cache areas.

[0060] In some optional schemes, the read logic module is configured to obtain all cache data in the first target cache area based on the target pointer position, and perform read processing on the all cache data as to-be-read data.

[0061] In some optional schemes, the cache area comprises at least two segment cache areas; and the arbitration module comprises a polling arbitration module, configured to, when the arbitration mode is the second arbitration mode, obtain, for any segment cache area, a weight value for the segment cache area based on weight information of cache data in the segment cache area; in any read cycle, take a segment cache area with the highest weight value among the segment cache areas as a second target cache area and perform unit decrement on the weight value of the second target cache area, and alternately cycle until the weight values of the segment cache areas are all decremented to zero; and sequentially take a start address of the second target cache area in each read cycle as the target pointer position of the read pointer.

[0062] In the embodiments of the present application, the polling arbitration module specifically comprises a segment weight register, a polling state machine, a weight counter and a weight comparator. The segment weight register is configured to store the weight values of the segment cache areas, the weight counter is configured to decrement the weight of the second target cache area in each read cycle, the weight comparator is configured to compare the weight values of the segment cache areas, and the polling state machine is configured to determine whether the weight values of the segment cache areas are all decremented to zero.

[0063] In some optional schemes, the read logic module is configured to obtain part of cache data in the second target cache area based on the target pointer position, and perform read processing on the part of cache data as to-be-read data.

[0064] In some optional schemes, the system further comprises: a write pointer counting module, configured to obtain a write pointer count based on a number of write processes; a read pointer counting module, configured to obtain a read pointer count based on a number of read processes. a data water level detection module configured to generate a water level prompt based on the write pointer count, the read pointer count, and a preset count threshold, the water level prompt being used to determine whether overflow of the cache area occurs.

[0065] In the embodiments of the present application, the write pointer count module and the read pointer count module are core modules for managing data storage and retrieval, and their functions are to track the write and read positions of data in the cache area and ensure correct transmission of data in sequence. The write pointer points to the next writable data storage position, and the write pointer is incremented when data is written. The read pointer points to the next readable data storage position, and the read pointer is incremented when data is read. In hardware implementation, the read and write pointers are usually implemented by counters, and the bit width of the counter is related to the depth of the cache area. For example, a cache area with a depth of M requires a counter with a bit width of log2(M). In order to distinguish the empty and full states of the cache area, an additional flag bit or comparison logic is usually used. For example, when the read and write pointers are equal, the cache area is empty, and when the write pointer is one more than the read pointer, the cache area is full. In addition, the empty and full states of the cache area can also be determined by the data water level detection module. Specifically, the data water level detection module generates a water level flag signal by detecting the current amount of data stored in the cache in real time, and provides the signal to an external system to adjust the data read and write operation. For example, when the amount of data in the cache is close to full, the water level detection module triggers a "close to full" flag to notify the sending end to stop or slow down data writing; when the amount of data is close to empty, a "close to empty" flag is triggered to prompt the receiving end to pause data reading. In implementation, the water level detection is usually based on the write pointer count module and the read pointer count module to calculate the current amount of data, and the corresponding water level prompt is generated by comparing the amount of data with a preset count threshold.

[0066] In some optional schemes, the system further comprises: a fast access module configured to obtain a data access instruction for the cache area, wherein the data access instruction comprises a data access address, the real-time level of the data access instruction is higher than that of the data read and write instruction, a to-be-accessed address of the cache area is determined based on the data access address and a preset mapping relationship, the mapping relationship represents a corresponding relationship between the data access address and the cache address of the cache area, and data access is performed on the cache area based on the to-be-accessed address.

[0067] In the embodiment, the external data request source accesses or modifies the data in the cache area through an Advanced High-performance Bus (AHB) and an AHB protocol interface. Specifically, the fast access module includes a depth / address converter, a read channel and a write channel. The external read / write request is transmitted to the fast access module through the AHB bus and the AHB protocol interface, the data access address carried by the transmission is converted into a to-be-accessed address (depth) of the cache area according to a preset mapping relationship by the depth / address converter, and the data in the cache area is quickly read based on the to-be-accessed address by the read channel, and the data is quickly written into the cache area by the write channel.

[0068] The main function of the AHB protocol interface is to receive, decode and process the read / write request from the external data request source, and return the corresponding data or response signal. In terms of specific functions, the AHB protocol interface needs to process address decoding, determine whether to respond to this request according to the data access address provided by the external data request source, and analyze the transmission type, transmission size and read / write signal to determine the operation type and data width; during data transmission, the AHB protocol interface returns the read data through the AHB bus, or receives the data on the AHB bus and stores it to the specified address during the write operation; in addition, the AHB protocol interface also needs to generate a response signal, such as OKAY indicating successful operation and ERROR indicating failed operation; in implementation, the AHB protocol interface usually includes address decoder, control logic, data buffer and state machine modules, the address decoder is used to judge the access range, the control logic is used to analyze the bus signal and coordinate the internal operation, the data buffer is used to temporarily store the read / write data, and the state machine is used to manage the timing and state conversion of the interface. Through reasonable design, the AHB protocol interface can efficiently and reliably complete the interaction with the external data request source, and ensure the stable operation of the system bus. In the embodiment, the data read / write system can also directly mount the arbitration module to the AHB bus by designing an interface compatible with the AHB protocol, realizing the sharing of the cache area, saving the area and storage space in the chip, and avoiding resource waste.

[0069] It should be noted that the data read / write system of the embodiment of the application has similar principles to the foregoing data read / write method in solving problems, and therefore the implementation process and implementation principles, advantages of the data read / write system can be seen from the foregoing description of the implementation process and implementation principles, advantages of the method, and the repeated parts will not be described again.

[0070] According to the embodiments of the application, the application further provides an electronic device and a readable storage medium.

[0071] Figure 4A schematic block diagram of an example electronic device 400 that can be used to implement embodiments of the present application is shown. The electronic device is intended to represent various forms of digital computers, such as laptops, desktops, tablets, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown here, their connections and relationships, and their functions, are meant to be examples only, and are not intended to limit the present application described and / or claimed in this document to the embodiments presented herein.

[0072] As shown in Figure 4 The electronic device 400 includes a computing unit 401 that can perform various appropriate actions and processes in accordance with a computer program stored in a read-only memory (ROM) 402 or a computer program loaded into a random access memory (RAM) 403 from a storage unit 408. Various programs and data required for the operation of the electronic device 400 can also be stored in the RAM 403. The computing unit 401, the ROM 402, and the RAM 403 are connected to each other through a bus 404. An input / output (I / O) interface 405 is also connected to the bus 404.

[0073] Various components in the electronic device 400 are connected to the I / O interface 405, including an input unit 406, such as a keyboard, a mouse, etc.; an output unit 407, such as various types of displays, a speaker, etc.; a storage unit 408, such as a magnetic disk, an optical disk, etc.; and a communication unit 409, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 409 allows the electronic device 400 to exchange information / data with other devices through a computer network, such as the Internet, and / or various telecommunication networks.

[0074] The computing unit 401 can be various general and / or special purpose processing components with processing and computing capabilities. Some examples of the computing unit 401 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 401 performs various methods and processes described above, such as the data read-write method. For example, in some embodiments, the data read-write method can be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 408. In some embodiments, part or all of the computer program can be loaded and / or installed onto the electronic device 400 via the ROM 402 and / or the communication unit 409. When the computer program is loaded onto the RAM 403 and executed by the computing unit 401, one or more steps of the data read-write method described above can be performed. Alternatively, in other embodiments, the computing unit 401 can be configured to perform the data read-write method by any other appropriate means, such as by means of firmware.

[0075] Various implementations of the systems and techniques described above can be realized in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), a complex programmable logic device (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0076] Program code for carrying out methods of the present application can be written in any combination of one or more programming languages. The program code can be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the program code, when executed by the processor or controller, produces a means for implementing the functions / acts specified in the flowcharts and / or block diagrams. The program code can be executed entirely on a machine, partially on a machine, partially on a machine as a stand-alone software package, partially on a machine and partially on a remote machine or entirely on a remote machine or server.

[0077] In the context of this application, a machine-readable medium can be a tangible medium that can contain or store program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable storage medium can include but are not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0078] To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0079] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0080] The computer system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server can arise by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0081] It should be understood that the various forms of flow shown above can be used to reorder, add, or delete steps. For example, the steps described in this application can be performed in parallel, in series, or in a different order, as long as the desired results of the technology disclosed in this application can be achieved, and this application does not limit herein.

[0082] In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0083] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A data reading and writing method, characterized in that: The method comprises: Get the read and write type of data read and write instructions; When the read / write type is a read type, obtaining an arbitration method for the data read / write instruction; Determining a target pointer position of a read pointer based on the arbitration method; the target pointer position represents a target read address of the buffer area pointed to by the read pointer; The data to be read is acquired based on the target pointer position, and a read process is performed on the data to be read.

2. The method according to claim 1, characterized in that Also includes: When the read / write type is a write type, determining a current pointer position of a write pointer; The current pointer position represents the current storage address of the buffer area pointed to by the write pointer; Obtaining data to be written with priority coding information and weight information; Based on the current pointer position, write processing is performed on the data to be written.

3. The method according to claim 2, characterized in that The buffer area includes at least two segment buffer areas; and determining the target pointer position of the read pointer based on the arbitration method includes: When the arbitration mode is the first arbitration mode, for any segment buffer area, a total priority score for the segment buffer area is obtained based on priority coding information of the cached data in the segment buffer area; The priority total scores of each segment cache area are sorted in descending order, and each segment cache area corresponding to the sorted priority total score is used as the first target cache area in turn, and the first address of the first target cache area is used as the target pointer position of the read pointer in turn.

4. The method according to claim 3, characterized in that The acquiring the data to be read based on the target pointer position and performing read processing on the data to be read includes: Based on the target pointer position, all cached data in the first target cache area are acquired, and all cached data are read as data to be read.

5. The method according to claim 2, characterized in that The buffer area includes at least two segment buffer areas; and determining the target pointer position of the read pointer based on the arbitration method includes: When the arbitration mode is the second arbitration mode, for any segment cache area, a weight value for the segment cache area is obtained based on weight information of cached data in the segment cache area; In any read cycle, the segment cache with the highest weight value among all segment caches is used as the second target cache and its weight value is decreased by units, and the cycle is repeated until the weight values ​​of all segment caches are decreased to zero; the first address of the second target cache in each read cycle is used as the target pointer position of the read pointer in turn.

6. The method according to claim 5, characterized in that The acquiring the data to be read based on the target pointer position and performing read processing on the data to be read includes: Based on the target pointer position, a portion of cached data in the second target cache area is obtained, and the portion of cached data is read as data to be read.

7. The method according to claim 2, characterized in that The method further comprises: Based on the number of write processes and the number of read processes, a write pointer count and a read pointer count are obtained; Based on the write pointer count, the read pointer count and the preset count threshold, water level prompt information is generated; the water level prompt information is used to determine whether the cache area overflows.

8. The method according to any one of claims 1 to 7, characterized in that The method further comprises: Obtaining a data access instruction for the cache area; wherein the data access instruction includes a data access address; and the real-time level of the data access instruction is higher than the real-time level of the data read and write instruction; Determine the address of the cache area to be accessed based on the data access address and a preset mapping relationship; the mapping relationship represents the correspondence between the data access address and the cache address of the cache area; Based on the address to be accessed, data is accessed to the cache area.

9. A data reading and writing system, characterized in that: The system comprises: A mode selection module, configured to obtain a read / write type of a data read / write instruction; and when the read / write type is a read type, obtain an arbitration method for the data read / write instruction; An arbitration module, configured to determine a target pointer position of a read pointer based on the arbitration method; the target pointer position represents a target read address of a buffer area pointed to by the read pointer; The read logic module is used to obtain the data to be read based on the target pointer position and perform read processing on the data to be read.

10. The system according to claim 9, characterized in that The system further comprises: A write logic module is used to determine the current pointer position of the write pointer when the read-write type is a write type; the current pointer position represents the current storage address of the cache area pointed to by the write pointer; obtain the data to be written with priority coding information and weight information; and based on the current pointer position, perform write processing on the data to be written.

11. The system according to claim 10, wherein: The buffer area includes at least two segment buffer areas; The arbitration module includes a fixed priority module, which is used to, when the arbitration mode is the first arbitration mode, obtain a total priority score for any segment cache area based on the priority coding information of the cached data in the segment cache area; sort the total priority scores of each segment cache area in descending order, and use each segment cache area corresponding to the sorted priority total score as the first target cache area in turn, and use the first address of the first target cache area as the target pointer position of the read pointer in turn.

12. The system according to claim 11, characterized in that The read logic module is used to obtain all cached data in the first target cache area based on the target pointer position, and perform read processing on all cached data as data to be read.

13. The system according to claim 10, wherein: The cache area includes at least two segment cache areas; the arbitration module includes a polling arbitration module for obtaining a weight value for any segment cache area based on weight information of cached data in the segment cache area when the arbitration mode is the second arbitration mode; In any read cycle, the segment cache with the highest weight value among all segment caches is used as the second target cache and its weight value is decreased by units, and the cycle is repeated until the weight values ​​of all segment caches are decreased to zero; the first address of the second target cache in each read cycle is used as the target pointer position of the read pointer in turn.

14. The system according to claim 13, wherein: The read logic module is used to obtain part of the cached data in the second target cache area based on the target pointer position, and perform read processing on the part of the cached data as data to be read.

15. The system according to claim 10, wherein: The system further comprises: A write pointer counting module, configured to obtain a write pointer count based on the number of write transactions; A read pointer counting module, configured to obtain a read pointer count based on the number of read processes; The data water level detection module is used to generate water level prompt information based on the write pointer count, the read pointer count and the preset count threshold; the water level prompt information is used to determine whether the cache area overflows.

16. The system according to any one of claims 9 to 15, characterized in that The system further comprises: A fast access module is used to obtain data access instructions for a cache area; wherein the data access instructions include a data access address; the real-time level of the data access instructions is higher than the real-time level of the data read and write instructions; based on the data access address and a preset mapping relationship, the address to be accessed of the cache area is determined; the mapping relationship represents the correspondence between the data access address and the cache address of the cache area; based on the address to be accessed, data is accessed to the cache area.

17. An electronic device, characterized in that: include: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method according to any one of claims 1 to 8.

18. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to enable a computer to execute the method according to any one of claims 1-8.

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