Satellite-borne image storage system based on row and column combination extended Hamming code error correction

Abstract

The invention discloses a satellite-borne image storage system based on row and column combination extended Hamming code error correction, and the system comprises a power module which is used for providing a stable required voltage for the satellite-borne image storage system; the main control module transmits the data to the storage array module in real time through a DMA controller, and is internally provided with a row-column combined extended Hamming code to perform verification and error correction on the data to be stored so as to realize real-time processing and monitoring of the data; the storage array module is used for storing data; the interface communication module is used for realizing data transmission between the main control module and the central computer; and the temperature monitoring module is used for monitoring the temperature of the circuit board in real time, and regulating and controlling the internal temperature through the main control module and the external thermal insulation structure. The limitation of single-bit error correction and double-bit detection of traditional Hamming codes in satellite-borne storage can be solved, error correction within 4 bits is achieved, and the size of the satellite-borne storage is reduced.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of aerospace electronic equipment, and particularly relates to a spaceborne image storage system based on row-column combination extended Hamming code error correction, which is suitable for high-resolution image data storage and transmission of satellites, deep space probes and other spacecrafts, and is particularly suitable for long-term reliable operation in an extreme temperature environment (-80 DEG C to 50 DEG C). BACKGROUND

[0002] The spaceborne memory undertakes the recording, storage and transmission of scientific data. In a deep space exploration task, the reliability, capacity and environmental adaptability of the spaceborne memory are important guarantees for ensuring the integrity of scientific data. In a planetary exploration task, the spaceborne storage system is long-term in a strong radiation environment, and high-energy particle bombardment can cause single event upset (SEU), single event multi-bit upset and other errors of stored data, so that an error correction coding technology needs to be used to improve the reliability of spaceborne data storage.

[0003] At present, the spaceborne image storage system generally adopts a discrete NAND Flash array and an FPGA control architecture, the size of which is generally above 80 mm in diameter, and the data erasing and writing life is insufficient under the condition of a low temperature working temperature of -80 DEG C. The currently commonly used error correction coding technology is Hamming code. The traditional Hamming code can only correct single bit errors, and the extended Hamming code can detect double bit errors, but the error correction capability is insufficient when facing three bit and above errors, and cannot meet the high reliability storage requirements of spaceborne image data. With the increase of the page capacity of the storage chip, the traditional Hamming code cannot meet the error correction requirements of the current multiple spaceborne storage chips. Therefore, it is urgent to develop a new spaceborne image storage system based on a high reliability error correction algorithm. SUMMARY

[0004] The application aims to provide a spaceborne image storage system based on row-column combination extended Hamming code error correction, so as to solve the limitation of the traditional Hamming code in the spaceborne storage "single bit error correction, double bit detection", realize 4-bit internal error correction, and reduce the volume of the spaceborne memory.

[0005] The technical solution for realizing the application is as follows:

[0006] A spaceborne image storage system based on row-column combination extended Hamming code error correction comprises:

[0007] A power module is used for providing a stable required voltage for the spaceborne image storage system.

[0008] A main control module realizes real-time data transmission to a storage array module through a DMA controller, and is internally provided with row-column combination extended Hamming code, so as to check and correct the data to be stored, and realize real-time processing and monitoring of the data.

[0009] a storage array module for storing data;

[0010] an interface communication module for realizing data transmission between the master module and the central computer;

[0011] a temperature monitoring module for monitoring the temperature of the circuit board in real time, and adjusting the internal temperature through the master module and the external heat preservation structure.

[0012] Compared with the prior art, the present application has the following advantages:

[0013] (1) The present application uses hardware integration and circular ring PCB topology optimization to reduce the volume of the satellite-borne storage system by more than 70%, and the overall PCB is controlled within a diameter of 38mm, and the diameter of the external temperature control structure is less than 50mm, which is significantly reduced compared with the size of the traditional satellite-borne storage, and is suitable for the narrow load cabin of the spacecraft; (2) The satellite-borne storage system provided by the embodiment of the present application realizes a temperature control accuracy of ±1℃ through the cooperation of the temperature monitoring module and the external heat preservation structure, and the number of erasing times of the storage chip is increased to 500,000 times under the condition of-80℃ low temperature; (3) The master module of the present application has a built-in row-column combination expansion hamming code error correction algorithm, which can realize reliable error correction within 4bit, and ensure the integrity and correctness of the data. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a schematic block diagram of the satellite-borne image storage system provided by the embodiment of the present application;

[0015] Figure 2 is a schematic diagram of the front of the PCB of the satellite-borne image storage system provided by the embodiment of the present application;

[0016] Figure 3 is a schematic diagram of the back of the PCB of the satellite-borne image storage system provided by the embodiment of the present application;

[0017] Figure 4 is a circuit diagram of the power module provided by the embodiment of the present application;

[0018] Figure 5 is a circuit diagram of the master module and the temperature monitoring module provided by the embodiment of the present application;

[0019] Figure 6 is a circuit diagram of the interface communication module provided by the embodiment of the present application;

[0020] Figure 7 is a circuit diagram of the high-density storage array module provided by the embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0022] Figure 1 A schematic block diagram of a satellite-borne image storage system provided by an embodiment of the present invention includes a power supply module 1, a main control module 2, a high-density storage array module 3, an interface communication module 4, and a temperature monitoring module 5.

[0023] Specifically, the power module 1 receives an external input 5V voltage and steps it down to a 3.3V system operating voltage through an LDO linear regulator (model: ME6206A33XG) to power each module. The main control module 2 is connected to the interface communication module 4 via the RS-422 protocol, receives the image data stream from the central computer, performs a CRC-32 check, and then writes the data to the high-density storage array module 3 through address mapping. The temperature monitoring module 5 collects the temperature data of the center position of the PCB board in real time through a temperature sensor. When the local temperature is detected to be lower than -2°C, a low-level signal is output through the PA8 pin of the main control module 2, triggering the external temperature control system to start heating. When the temperature rises above 0°C, a high-level signal is output to stop heating.

[0024] Figure 2 A schematic diagram of the front side of the PCB of the satellite-borne image storage system provided by an embodiment of the present invention is shown as follows: Figure 2 As shown, the circular high-density PCB topology has an outer diameter of 38mm, an inner diameter of 13mm, and a maximum thickness of 3mm. A circular hole with a diameter of 13mm is set in the center. The circular hole is filled with hard polyurethane potting material, which forms a buffer layer with a thickness of 1.5mm after curing. The circular hollow design allows the potting material to flow evenly along the circumference during the assembly process, forming a continuous wrapped packaging layer, thereby improving the system's resistance to mechanical shock and vibration and being able to withstand 5000G overload. The PCB adopts a two-layer high-density interconnection process, integrating blind and buried via technology, and the substrate is a polyimide copper-clad board. The power module, main control module, high-density storage array module, interface communication module and temperature monitoring module are symmetrically distributed in a circular layout around the circular hole. The signal routing is designed to minimize the circular path, and the communication speed is guaranteed by equal-length signal routing. The volume is reduced by more than 70% compared with traditional on-board storage.

[0025] The interface communication module is arranged in the sector on the right side of the front of the PCB, and its differential signal lines are connected in parallel to match the transmission line impedance through resistors R8 and R9; the high-density storage array module is arranged in the sector on the left side of the front, and the storage chip U10 is soldered to the left side of the front using a BGA package. The data buses D0-D7 are connected to the main control module through 10kΩ pull-up resistors R12-R21; the power module is placed in the lower area near the periphery of the circular hole.

[0026] Figure 3 A schematic diagram of the back side of the PCB of the satellite-borne image storage system provided by an embodiment of the present invention is shown as follows: Figure 3 As shown, in the upper area of ​​the back side of the circular PCB: the main control module and the temperature sensor U9 are arranged adjacent to each other, and the processor signal routing radially bypasses the central circular hole with a length of ≤10mm to reduce signal delay; the pad of the memory chip U10 is connected to the front circuit through a blind hole, and 4.7μF decoupling capacitors C21, C22, C26 and 0.1μF high-frequency filter capacitors C18-C20, C23-C25 are set at the corresponding positions on the front to reduce power supply noise; the signal line is routed along a circular path with an impedance matching accuracy of 50Ω±3%, and is connected to the inner shielding ground plane through a buried hole to suppress common-mode interference.

[0027] Figure 4 The power module circuit diagram provided by the embodiment of the present invention includes a self-recovery fuse F1, an LDO linear regulator U1, a unidirectional transient suppression tube U2, capacitors C1-C5, a first magnetic bead L1, and a second magnetic bead L2. Figure 2 The input voltage is connected to one end of the fuse F1, and the other end of F1 is connected to the parallel network composed of the unidirectional transient suppression tube U2, capacitors C3, C4, C5, and C1 and the IN pin of the voltage regulator U1. One end of these components is connected to the output end of F1, and the other end is connected to GNDA; the output end of the parallel network is connected to the IN pin of the LDO linear regulator U1, and the GND pin of the LDO linear regulator U1 is connected to GNDA. After the OUT pin of the LDO linear regulator U1 is output, one path is connected to AVCC3.3V through the first ferrite bead L1, and the other path outputs the digital power supply DVCC3.3V and is connected to one end of the second ferrite bead L2 through the capacitor C2. The other end of the second ferrite bead L2 is connected to the analog ground GNDA, one end of the capacitor C2 is connected to the connection point of L1 and L2, and the other end is connected to the digital ground GND. During circuit operation, the input voltage is protected against overcurrent by fuse F1. It is then stabilized by unidirectional transient suppressor diode U2 and filtered by capacitors C3-C5 and C1, providing a stable input for LDO linear regulator U1. LDO linear regulator U1 processes the input voltage and outputs it through the OUT pin. This voltage is then further filtered by a filter circuit consisting of first and second ferrite beads L1 and L2, and capacitor C2, providing stable power to the downstream load. Testing has shown that under conditions of an input voltage of 5V±5%, a load current of 0-150mA, and an ambient temperature of -80°C, the output voltage fluctuation is ≤±1.5%.

[0028] Specifically, the capacitance of the capacitors C2-C5 is 0.1 μF, and the capacitance of the capacitor C1 is 4.7 μF.

[0029] Figure 5 is a circuit diagram of the master control module and the temperature monitoring module provided by the embodiment of the application, Figure 5 comprises the master control module 2 and the temperature monitoring module 5, comprises a master control chip U8, a temperature sensor U9, capacitors C6-C17, a crystal oscillator X1, a resistor R10 and a resistor R11, wherein the temperature sensor U9, the capacitor C12 and the resistor R10 constitute the temperature monitoring module 5, and the rest constitute the master control module 2. The master control module is connected with the high-density storage array module through a DMA controller, so that real-time data transmission is realized. Figure 5, DVCC3.3V directly accesses the D2, F5, K1 pins of the main control chip U8, and the three pins all bear the VDD power function; DVCC3.3V is connected to one end of the capacitors C8-C11 in parallel, and these capacitors are connected in parallel, and the other end of the parallel connection is commonly connected to GNDD, forming a power filter branch. AVCC3.3V directly connects the H1 pin of the main control chip U8, and connects one end of the capacitors C13 and C14 in parallel, and the other end of the parallel connection of the capacitors C13 and C14 is connected to GNDA; at the same time, DVCC3.3V connects the F4 pin of the main control chip U8, and connects one end of the capacitor C15, and the other end of the capacitor C15 is connected to GNDD. C2, E4, E5, E6, J1 pins on the main control chip U8 are used as VSS pins and are connected to GNDD; the G1 pin is used as the VSSA pin and is connected to GNDA. Capacitors C16 and C17 are connected in parallel, one end is commonly connected to the E7 and E8 pins of the main control chip U8, and the other end of the parallel connection of the capacitors C16 and C17 is connected to GNDD. The PA9 and PA10 pins of the main control chip U8 are respectively connected to USART1_A and USART1_B, and are connected to the interface communication module 4 for serial communication; the PA13 and PA14 pins of the main control chip U8 are SWDIO and SWCLK respectively, which are used for program burning; the 3 pin and the 1 pin of the external crystal oscillator X1 are connected through the PH0-OSCIN and PH1-OSCOUT pins of the main control chip U8 respectively, and each is matched with the capacitor C6 and the capacitor C7 to form a Pierce oscillator, the 2 and 4 pins of the crystal oscillator X1 are both connected to GNDD, and the capacitors C6 and C7 are both connected to GNDD; the BOOT0 pin of the main control chip U8 is pulled down to GND through R11; the eMMC of the main control chip U8 is connected to the high-density storage array module 3, the PC8 pin is connected to eMMCD0, the PC9 pin is connected to eMMC_D1, the PC10 pin is connected to eMMC_D2, the PC11 pin is connected to eMMC_D3, the PB8 pin is connected to eMMC_D4, the PB9 pin is connected to eMMC_D5, the PC6 pin is connected to eMMC_D6, and the PC7 pin is connected to eMMC_D7; the PC12 pin is connected to eMMC_CLK, and the PD2 pin is connected to eMMC_CDM;

[0030] Further, the main control module is built-in with an error correction algorithm based on row-column combination extended Hamming code, which can realize 4bit error correction and ensure data integrity and correctness. The working process of the algorithm is divided into two parts of encoding and decoding error correction.

[0031] a. Encoding process. The system divides the 16-bit image data to be stored into a 4x4 matrix data area D, with 4-bit data per row and 4-bit data per column. For each row of matrix data, a (8,4) extended Hamming code is generated to generate a 16-bit row check code H, forming a 4x4 matrix row check code area H. The row check code calculation rule is as follows:

[0032]

[0033] where D represents the original data bit, H represents the row check code bit, and the subscript x is used to distinguish data at different positions, and represents an exclusive or operation.

[0034] The column check code C is generated for each column of data in the matrix using an (8, 4) extended Hamming code, forming a 4x4 matrix column check code area C, and the column check code calculation rule is as follows:

[0035]

[0036] where D represents the original data bit, H represents the row check code bit, C represents the column check code bit, the subscript x is used to distinguish data at different positions, and represents an exclusive or operation.

[0037] The 4x4 matrix data area D, 4x4 matrix row check code H, and 4x4 matrix column check code C are integrated into a 48-bit data block, and the storage format is: column check code C (16 bits) + data area D (16 bits) + row check code H (16 bits), forming a (48, 16) combined extended Hamming code data block.

[0038] b. Decoding error correction process. After reading the (48, 16) combined extended Hamming code data block obtained in the encoding process, first perform extended Hamming code decoding on each row of data and row check code to separate it into C (16bit), D (16bit), and H (16bit); perform (8, 4) extended Hamming code decoding on each row of data to generate a row check vector S H . If S H ≠ [0, 0, 0, 0], it is detected that there is an error in the row. If the row check vector indicates a single bit error, directly locate and correct the bit; if the row check vector indicates a double bit error, record the error position information of the row, and do not correct it temporarily. Then perform (8, 4) extended Hamming code decoding on each column of data and column check code to generate a column check vector S C . Combined with the error position recorded by the row check, through joint analysis of the row and column check vectors, it can be divided into the following four cases:

[0039] (1) For single bit error, S H points to the only error bit, and the row extended check code is used for correction, and the corresponding bit is directly flipped.

[0040] (2) For double bit error, if the double bits are located in the same row, they are located by the row check vector S H , the column check vector S C is calculated, and if a column S C is not zero, the double bit coordinates are determined in combination with the row number, and the two error bits are flipped; if they are located in different rows, the row check vector S H records that there is a single bit error in two rows, and S CRecord two columns of single bit error, the intersection is the error bit, then reverse the two error bits according to the positioning result.

[0041] (3) For three bit errors, if there is one bit error in each row, locate the error through three row check, and correct the error bit by reversing; if there is three bit error in the same row, first locate the error row by using row check, locate the specific error bit by using column check, correct the double bit error among them, and re-calculate the error row check vector according to the above (2), locate the third bit error bit and reverse it; if there is 2bit error in a row + 1bit error in another row, first correct the single bit row by using row check, then locate the double bit error in the same row by using column check, and correct it in the same way as above (2).

[0042] (4) For four bit errors, if the error bits are distributed in 4 rows x 1 column, perform row check code on 4 rows of data respectively to generate row check vector S H , record the row number and column number of the four error rows, and reverse the data row by row to correct the error bit; if it is 1 row x 4 column error, first perform row check to generate row check vector S H , but the row check cannot directly locate, so after getting the row check error identifier, perform column check decoding to calculate column check vector S C , combine the row and column error identifiers to determine the error bit and reverse the data; if it is 2 row x 2 column cross error, locate it by recording the position of row and column double bit error, and use phased error correction, first process the row direction double bit error respectively to ensure that the row check passes, and correct it in the same way as above (2), then verify the column check to ensure that the 4bit error correction is completed.

[0043] After error correction is completed, recalculate the row and column check code, and compare it with the stored check code to verify the accuracy of error correction, until it is verified to be correct, and the stored data is updated.

[0044] This process can realize full coverage correction of single bit to four bit error through the cooperative operation of row and column check. Through random function error injection experiment, repeated 50000 times, the error correction algorithm based on row and column combination extended hamming code proposed in the application can successfully detect and correct.

[0045] Reference Figure 5 The SCL and SDA pins of the temperature sensor U9 in the temperature monitoring module 5 are respectively connected with the I 2 C clock pin PD12 and I 2The C data pin PD13 is connected, and temperature and clock data transmission is realized; the ALERT pin of the temperature sensor U9 is connected with the PC2C pin of the main control chip U8, when the temperature is out of limit, the ALERT pin outputs high level, triggers the interrupt service program of the main control module, and starts the external temperature control system; the GND pin of the temperature sensor U9 is connected with one end of the resistor R10, the other end of the resistor R10 is connected to GNDD, the ADDA0 and EP pins of the temperature sensor U9 are grounded; the V+ pin of the temperature sensor U9 is connected with DVCC 3.3V, and is also connected with the capacitor C12, and the other end of the capacitor C12 is connected with GNDD. The external temperature control structure is composed of a polyimide heater, a PID controller (integrated in the main control module) and a power management unit, and the heater is controlled to start and stop through the PA8 pin of the main control module.

[0046] Specifically, the frequency of the crystal oscillator X1 is 25MHz, the capacitances C6 and C7 have a capacitance value of 20pF, the capacitances C8, C9, C10, C11, C14 and C15 have a capacitance value of 4.7μF, the capacitances C12 and C13 have a capacitance value of 0.1μF, the capacitances C16 and C17 have a capacitance value of 2.2μF, the resistance R10 has a resistance value of 4.7kΩ, and the resistance R11 has a resistance value of 1kΩ.

[0047] Figure 6is a circuit diagram of an interface communication module provided by the embodiment of the present application. The interface communication module 4 is used to realize data transmission between the master control module 2 and the central computer. The interface communication module 4 is a communication interface circuit based on the RS422 transceiver U6, realizing bidirectional conversion of USART and RS422 signals. Specifically, the interface communication module 4 includes the RS422 transceiver U6, resistors R1-R9, the bidirectional transient suppression tube D1, the bidirectional transient suppression tube D2, the unidirectional transient suppression tube U3, the unidirectional transient suppression tube U4, the unidirectional transient suppression tube U5, the unidirectional transient suppression tube U7; the VCC pin of the RS422 transceiver U6 is connected to the digital power supply DVCC 3.3V, and the GND pin of the RS422 transceiver U6 is connected to the digital ground GNDD; USART1_A and USART1_B are used as serial port transceiving signals, and are respectively connected to the DI and RO of the RS422 transceiver U6 through the resistor R6 and the resistor R7, so as to realize signal interaction between the serial port and the chip. The RS422 transceiver U6 internally converts the serial port signal into a differential signal, and outputs from the Y pin and the Z pin; the Y pin is current-limited through the resistor R9, and is connected to RS422_T+, and overvoltage protection is built through the unidirectional transient suppression tube U7 (the other end is connected to DVCC 3.3V), the bidirectional transient suppression tube D2 and the unidirectional transient suppression tube U5 (the other end is connected to GNDD); the A pin is current-limited through the resistor R3, and is connected to RS422_T+, and overvoltage protection is built through the unidirectional transient suppression tube U3 (the other end is connected to DVCC 3.3V), the bidirectional transient suppression tube D1 and the unidirectional transient suppression tube U4 (the other end is connected to GNDD); the Z pin is current-limited through the resistor R8, and is connected to RS422_T-, and protection is realized through the unidirectional transient suppression tube U5, the bidirectional transient suppression tube D2 and the unidirectional transient suppression tube U7, and finally the differential signal is sent from RS422_T+ / -; the B pin is current-limited through the resistor R5, and is connected to RS422_T-, and protection is realized through the unidirectional transient suppression tube U4, the bidirectional transient suppression tube D1 and the unidirectional transient suppression tube U3, and finally the differential signal is sent from RS422_T+ / . After external RS422_R+ / - signals are input, RS422_R+ is overvoltage-protected through the unidirectional transient suppression tube U3 (the other end is connected to DVCC 3.3V), the bidirectional transient suppression tube D1 and the unidirectional transient suppression tube U4 (the other end is connected to GNDD), and then is current-limited through the resistor R1, and is connected to the pin of the RS422 transceiver U6; RS422_R- is protected through the bidirectional transient suppression tube D1 and the unidirectional transient suppression tube U4, is current-limited through the resistor R2 and the resistor R4, and is connected to the B pin of the RS422 transceiver U6; the RS422 transceiver U6 internally converts the differential signal into a serial port signal, and returns to the master control module from the RO pin through USART1_B; and the resistors R3 and R5 provide bias for the receiving end, and guarantee signal identification.

[0048] Specifically, the resistance R1, the resistance R4 resistance 750Ω, the resistance R2 resistance 130Ω, the resistance R3, the resistance R5 resistance 1kΩ, the resistance R6, the resistance R7 resistance 10kΩ, the resistance R8, the resistance R9 resistance 100Ω.

[0049] Figure 7 It is the circuit diagram of high-density storage array module provided by the embodiment of the application, including eMMC storage chip U1, resistors R12-R21, capacitors C18-C27. The storage chip U10 adopts eMMC5.1 protocol, and the number of erasing and writing reaches 500,000 times in the environment of-80 DEG C. DVCC3.3V is used as a power supply, and is first connected to one end of the resistors R12-R21, and the resistors play the roles of current limiting and impedance matching. The other end of R21 is connected to the eMMC_D0 signal end, and eMMC_D0 is directly connected to the A3 pin of the storage chip U10; the other end of R20 is connected to the eMMC_D1, and the A4 pin of the storage chip U10 is connected in correspondence; the other end of R19 is connected to the eMMC_D2, and the A5 pin of the storage chip U10 is connected; the other end of R18 is connected to the eMMC_D3, and the B2 pin of the storage chip U10 is connected; the other end of R17 is connected to the eMMC_D4, and the B3 pin of the storage chip U10 is connected; the other end of R16 is connected to the eMMC_D5, and the B4 pin of the storage chip U10 is connected; the other end of R15 is connected to the eMMC_D6, and the B5 pin of the storage chip U10 is connected; the other end of R14 is connected to the eMMC_D7, and the B6 pin of the storage chip U10 is connected; the other end of R13 is connected to the K5 pin of the storage chip U10, and R13 is also connected to one end of the capacitor C22, and the other end of the capacitor C22 is connected to GNDD; the other end of R12 is connected to the eMMC_CDM, and the M5 pin of the storage chip U10 is connected. The P6, P4, N5, N2, K8, J5, H10, G5, E7, C4 and A6 pins of the storage chip U10 are connected to GNDD, and are used as digital ground. The P5, P3, N4, M4 and C6 pins are all connected to DVCC3.3V. One end of the capacitors C18-C21 is connected to DVCC3.3V, and the other end is connected to GNDD. In addition, the K9, E6, E5, J10 and C2 pins of the storage chip U10 are connected to DVCC3.3V, one end of the capacitors C23-C266 is connected to DVCC3.3V, and the other end is connected to GNDD. One end of the capacitor C27 is connected to the C2 pin of the storage chip U10, and the other end is connected to GNDD.

[0050] Specifically, the storage capacity of the storage chip U10 is 128G, the resistance of the resistors R12-R21 is all 10kΩ, the capacitance of the capacitors C18, C19, C20, C23, C24, C25 is 0.1uF, the capacitance of the capacitors C21, C22 and C26 is 4.7uF, and the capacitance of the capacitor C27 is 1uF. The capacitor with a capacitance of 4.7uF is used for filtering low-frequency noise, and the capacitor with a capacitance of 0.1uF is used for filtering high-frequency noise.

[0051] It should be noted that the PCB of the satellite-borne image storage system is reduced in size by more than 70% compared with a traditional rectangular PCB layout scheme, and can be adapted to the narrow payload cabin space of a space probe. The system is provided with a 5V±5% input voltage by a central computer, the internal working voltage of the system is 3.3V, the power conversion efficiency is greater than or equal to 94%, the rated working current is 150mA(±5%), the standby power consumption is 500μW, and the working power consumption is 500mW, which is greatly reduced compared with the existing satellite-borne storage. The design systemically solves the technical problems of miniaturization and low-power consumption of satellite-borne storage devices.

[0052] It should be noted that the center hole is filled with hard polyurethane foam material, and the thermal conductivity is less than or equal to 0.044W / (m·K), and a 1.5mm thick buffer layer is formed after curing; the filling path of the filling material is evenly diffused along the inner wall of the hole, avoiding uneven filling of the filling material and affecting the impact resistance.

[0053] The above specific embodiments do not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A spaceborne image storage system based on row-column combined extended Hamming code error correction, characterized in that: include: Power supply module, used to provide the required stable voltage for the onboard image storage system; The main control module uses the DMA controller to transfer data to the storage array module in real time. It also has a built-in row and column combination extended Hamming code to verify and correct errors in the stored data, thus achieving real-time data processing and monitoring. Storage array module, used for data storage; Interface communication module, used to realize data transmission between the main control module and the central computer; The temperature monitoring module is used to monitor the temperature of the circuit board in real time and regulate the internal temperature through the main control module and the external insulation structure.

2. The satellite-borne image storage system based on row-column combined extended Hamming code error correction according to claim 1, characterized in that: The main control module verifies and corrects the stored data in two parts: encoding and decoding. a. Encoding process: Divide the 16-bit image data to be stored into a 4×4 matrix data area, with 4 bits of data per row and 4 bits of data per column. Generate a 16-bit row check code using the (8,4) extended Hamming code for each row of the matrix data, forming a 4×4 matrix row check code area. For each column of the matrix data, the (8,4) extended Hamming code is used to generate the column check code to form a 4×4 matrix column check code; The 4×4 matrix data area, 4×4 matrix row check code, and 4×4 matrix column check code are integrated into a 48-bit data block. The storage format is: column check code 16 bits + data area (16 bits) + row check code (16 bits), forming a (48,16) combined extended Hamming code data block. b. Decoding and error correction process: After reading the (48,16) combined extended Hamming code data block obtained in the encoding process, first perform extended Hamming code decoding on each row of data and row check code, separating them into 16-bit column check code, 16-bit + data area, and 16-bit row check code; perform (8,4) extended Hamming code decoding on each row of data to generate a row check vector S H If S H ≠[0,0,0,0], an error is detected in the row; If the row check vector indicates a single-bit error, directly locate and correct the bit; if the row check vector indicates a double-bit error, record the error position information of the row and do not correct it for the time being; then perform (8,4) extended Hamming code decoding on each column data and column check code to generate the column check vector S C .

3. The satellite-borne image storage system based on row-column combined extended Hamming code error correction according to claim 2, characterized in that: The row check code calculation rules are as follows: The column check code calculation rules are as follows: Where D represents the original data bit, H represents the row check code bit, C represents the column check code bit, and the subscript x is used to distinguish data at different positions.

4. The satellite-borne image storage system based on row-column combined extended Hamming code error correction according to claim 2, characterized in that: The decoding error correction process specifically includes the following four situations: (1) For a single bit error, S H Point to the only error bit, use the row extended check code to correct it, and directly flip the corresponding bit; (2) For double-bit errors, if the two bits are located in the same row, the row check vector S H Positioning, calculating column check vector S C , if a column S C Non-zero, combined with the row number to determine the double-bit coordinates, flip the two error bits; if they are located in different rows, the row check vector S H Record two lines with single-bit errors, S C If there is a single-bit error in two columns, the intersection is the error bit, and the two error bits are inverted according to the positioning result; (3) For three-bit errors, if there is a 1-bit error in each row, the error is located by three row checks, and the error bit is flipped and corrected; if there are three-bit errors in the same row, the error row is first located by row check, and the specific error bit is located by column check, and the double-bit error is corrected first, as in the above case (2), and then the row check vector of the error row is recalculated, and the third error bit is located according to the updated row check vector and flipped; if there are 2-bit errors in a row and 1-bit error in another row, the single-bit row is corrected first by row check, and the double-bit error in the same row is located by column check, and the correction method is the same as in the above case (2); (4) For a four-bit error, if the error bits are distributed in 4 rows × 1 column, perform row check code on the 4 rows of data to generate a row check vector S H , record the row and column numbers of the 4 error rows, flip the data row by row, and correct the error bits; if it is a 1 row × 4 column error, first perform row check to generate a row check vector S H However, row checksum cannot be directly located, so after obtaining the row checksum error mark, column checksum decoding is performed to calculate the column checksum vector S C , combined with the error identification of rows and columns, determine the error bit and flip the data; if it is a 2-row × 2-column cross error, cross-locate by recording the double-bit error position of rows and columns, adopt staged error correction, first process the double-bit error in the row direction separately to ensure that the row check passes, and the correction method is the same as the above (2), and then verify the column check to ensure that the 4-bit error correction is completed; After the error correction is completed, the row and column check codes are recalculated and compared with the stored check codes to verify the accuracy of the error correction until the verification passes and the stored data is updated.

5. The satellite-borne image storage system based on row-column combined extended Hamming code error correction according to claim 1, characterized in that: The control module includes a main control chip U8, capacitors C6-C11, capacitors C13-C17, resistor R11 and crystal oscillator X1; The power supply DVCC terminal is connected to one end of the parallel connection of capacitors C8-C11 and then to GNDD. The AVCC terminal is connected to the H1 pin of the main control chip U8 and one end of the parallel connection of capacitors C13 and C14. The other end of the parallel connection of capacitors C13 and C14 is connected to GNDA. The power supply DVCC terminal is connected to the F4 pin of the main control chip U8 and to one end of capacitor C15. The other end of capacitor C15 is connected to GNDD. The C2, E4, E5, E6, J1, and G1 pins on the main control chip U8 are connected to GNDA. Capacitors C16 and C17 are connected in parallel, with one end connected to the E7 and E8 pins of the main control chip U8 and the other end connected to GNDD. ; The PA9 and PA10 pins of the main control chip U8 are connected to the interface communication module; the PA13 and PA14 pins of the main control chip U8 are SWDIO and SWCLK respectively, which are used for program burning; the 3rd and 1st pins of the external crystal oscillator X1 are connected through the PH0-OSCIN and PH1-OSCOUT pins of the main control chip U8, and the respective matching capacitors C6 and C7 form a Pierce oscillator, the 2nd and 4th pins of the crystal oscillator X1 are connected to GNDD, and the capacitors C6 and C7 are connected to GNDD; the BOOT0 pin of the main control chip U8 is pulled down to GND through the resistor R11, and the eMMC is connected to the storage array module.

6. The onboard image storage system based on row-column combined extended Hamming code error correction according to claim 1, characterized in that: The memory array module includes a memory chip U10, resistors R12 to R21, and capacitors C18 to C27; The power supply DVCC end is connected to one end of resistors R12-R21, and the other ends of R12-R21 are respectively connected to the M5, K5, B6, B5, B4, B3, B2, A5, A4, and A3 pins of the memory chip U10; the P6, P4, N5, N2, K8, J5, H10, G5, E7, C4, and A6 pins of the memory chip U10 are connected to GNDD, and the P5, P3, N4, M4, and C6 pins are all connected to the power supply DVCC end; one end of capacitors C18-C21 is connected to the power supply DVCC end, and the other end is connected to GNDD; the K9, E6, E5, J10, and C2 pins of the memory chip U10 are connected to the power supply DVCC end, one end of capacitors C23-C266 is connected to the power supply DVCC end, and the other end is connected to GNDD; one end of capacitor C27 is connected to the C2 pin of the memory chip U10, and the other end is connected to GNDD.

7. The satellite-borne image storage system based on row-column combined extended Hamming code error correction according to claim 1, characterized in that: The power supply module includes a self-recovering fuse F1, an LDO linear regulator U1, a unidirectional transient suppressor U2, capacitors C1-C5, a first magnetic bead L1, and a second magnetic bead L2; the input voltage is connected to one end of the fuse F1, the other end of F1 is connected to a parallel network consisting of a unidirectional transient suppressor U2, capacitors C3, C4, C5, and C1, and the IN pin of the regulator U1, the other end of the parallel network is connected to GNDA, and the output end of the parallel network is connected to the IN pin of the LDO linear regulator U1; the GND pin of the LDO linear regulator U1 is connected to GNDA, and after the OUT pin is output, one path is connected to AVCC3.3V through the first magnetic bead L1, and the other path outputs the digital power supply DVCC end and is connected to one end of the second magnetic bead L2 through the capacitor C2, and the other end of the second magnetic bead L2 is connected to GNDA.

8. The onboard image storage system based on row-column combined extended Hamming code error correction according to claim 1, characterized in that: The temperature monitoring module includes a temperature sensor U9, a capacitor C12 and a resistor R10; the SCL, SDA and ALERT pins of the temperature sensor U9 are respectively connected to the main control module, the ADDA0 and EP pins are grounded, the V+ pin is connected to the power supply DVCC end, and is connected to the capacitor C12 at the same time, and the other end of the capacitor C12 is connected to GNDD; the GND pin of the temperature sensor U9 is connected to one end of the resistor R10, and the other end of the resistor R10 is connected to GNDD; when the temperature exceeds the limit, the ALERT pin outputs a high level, triggering the interrupt service program of the main control module and starting the external temperature control system.

9. The satellite-borne image storage system based on row-column combined extended Hamming code error correction according to claim 1, characterized in that: The main control module is connected to the interface communication module 4 via the RS-422 protocol, receives the image data stream from the central computer, performs a CRC-32 check, and then writes the data into the high-density storage array module through address mapping.

10. The satellite-borne image storage system based on row-column combined extended Hamming code error correction according to claim 1, characterized in that: Integrated on a ring-shaped PCB, a circular hole is set in the center of the PCB, and the hole is filled with hard polyurethane potting material, which forms a buffer layer after curing. The interface communication module is arranged in the sector on the right side of the front of the PCB, and the high-density storage array module is arranged in the sector on the left side of the front. The power module is placed in the area below near the periphery of the circular hole. The main control module and temperature monitoring module are set in the upper area on the back of the PCB.

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