Pixel driving circuit and display panel

Abstract

The invention relates to a pixel driving circuit and a display panel, and relates to the technical field of display driving. The pixel driving circuit comprises a driving transistor, a write-in unit, a storage capacitor, a connecting unit, a reset unit and a light-emitting control unit. A first electrode of the driving transistor is connected with the connecting unit and the light-emitting control unit at a first node, a second electrode is connected with the writing unit and the light-emitting control unit at a second node, and a control electrode is connected with the connecting unit and the storage capacitor at a third node; the reset unit is connected with the storage capacitor and the anode of the light-emitting device; wherein the write-in unit is connected with the first driving unit; the connection unit and the reset unit are respectively connected with the second driving units of different levels; and the light-emitting control unit is connected with the third driving units of different levels. By resetting the second driving units of different levels and the third driving units of different levels, the total number of the required gate driving circuits is reduced, and the narrow frame design of the display panel can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display driving, in particular to a pixel driving circuit and a display panel. BACKGROUND

[0002] In the field of active matrix display panel, each pixel unit is usually integrated with a pixel driving circuit including a thin film transistor (TFT) and a storage capacitor. In order to realize the line-by-line refresh of the picture, a gate driving circuit (Gate Driver on Array, GOA) on the periphery of the panel or integrated on the array substrate generates a gate control signal, sequentially selects the pixel switch TFT of the corresponding row through the scanning line, and then the pixel unit receives the image data voltage signal from the data line and generates an accurate driving current under the control of the image data voltage signal, so as to drive the light emitting device to emit light.

[0003] At present, in order to achieve better display effect, the pixel unit needs to complete the operations of multiple stages such as reset, data writing, threshold voltage compensation and light emission, so that the number of thin film transistors required by the pixel unit gradually increases, thereby requiring more groups of gate driving circuits for outputting multiple gate control signals with different time sequences and phases to realize the cooperative control of each thin film transistor in the pixel unit.

[0004] However, the increase in the number of gate driving circuits will occupy the space of the frame of the display panel, which is not conducive to the realization of the narrow frame design of the display panel. SUMMARY

[0005] The pixel driving circuit provided by the embodiments of the present application saves the occupied space of the frame of the display panel and facilitates the realization of the narrow frame design, so as to at least partially solve the above technical problems.

[0006] In order to achieve the above purpose, according to the first aspect of the present application, a pixel driving circuit is provided, which is connected with a gate control circuit, the gate control circuit includes a plurality of cascaded first driving units, a plurality of cascaded second driving units and a plurality of cascaded third driving units; The pixel driving circuit includes a driving transistor, a storage capacitor, a writing unit, a connecting unit, a reset unit and a light emission control unit; the driving transistor is an oxide transistor; The first electrode of the driving transistor is connected with the connecting unit and the light emission control unit at a first node, the second electrode is connected with the writing unit and the light emission control unit at a second node, and the control electrode is connected with the connecting unit and the storage capacitor at a third node; the reset unit is connected with the storage capacitor and the anode of the light emitting device; The writing unit is connected to the first driving unit; the connecting unit and the resetting unit are respectively connected to the second driving units of different levels; and the light emitting control unit is connected to the third driving units of different levels.

[0007] Optionally, the writing unit includes a first transistor; The first transistor includes a control electrode connected to the first driving unit to receive a write control signal, a first electrode connected to the data signal line, and a second electrode connected to the second node.

[0008] Optionally, the connecting unit includes a second transistor; The second transistor includes a control electrode connected to the n-th stage second driving unit, a first electrode connected to the first node, and a second electrode connected to the storage capacitor; the second transistor is used to control the connection and disconnection between the first node and the storage capacitor according to the n-th stage driving signal output by the n-th stage second driving unit, so as to write the data signal transmitted by the data signal line into the third node; Wherein, n is a positive integer.

[0009] Optionally, in the data writing stage of the pixel driving circuit, the first transistor is controlled to be turned on by the write control signal output by the first driving unit, and the second transistor is controlled to be turned on by the nth level driving signal output by the second driving unit, so as to write the data signal transmitted on the data signal line to the third node.

[0010] Optionally, the reset unit includes a third transistor; The third transistor includes a control electrode connected to the second driving unit of the n+ath level, a first electrode connected to the reset signal line, and a second electrode connected to the anode of the light-emitting device. The third transistor is used to control the connection and disconnection between the reset signal line and the anode of the light-emitting device according to the n+ath level driving signal output by the second driving unit of the n+ath level, thereby realizing reset control of the anode; Wherein, a is a positive integer.

[0011] Optionally, the light emitting control unit includes a fourth transistor and a fifth transistor; The fourth transistor includes a first electrode connected to a voltage source, a second electrode connected to the first node, and a control electrode connected to the third driving unit of the n+bth stage, and is used to control the connection between the voltage source and the first node according to the light-emitting signal of the n+bth stage output by the third driving unit of the n+bth stage; The fifth transistor comprises a first electrode connected with the second node, a second electrode connected with the anode of the light emitting device, and a control electrode connected with the n-th third driving unit, for controlling the on-off between the second node and the light emitting device according to the n-th light emitting signal output by the n-th third driving unit, so as to realize the light emitting control of the light emitting device. wherein b is a positive integer; In the light emitting stage of the pixel driving circuit, the n-th light emitting signal output by the third driving unit controls the fourth transistor to be turned on, and the n+b-th light emitting signal output by the third driving unit controls the fifth transistor to be turned on, so as to make the light emitting device emit light.

[0012] Optionally, in the first reset stage after the data writing stage, the third transistor is turned on according to the n+a-th driving signal, and the fifth transistor is turned on according to the n-th light emitting signal, so as to make the first reset voltage transmitted on the reset signal line reset the anode of the light emitting device, the second node and the first node.

[0013] Optionally, in the second reset stage, the second reset voltage is transmitted on the data signal line, and the first transistor is turned on according to the writing control signal, so as to reset the first node and the second node by the second reset voltage. wherein the second reset stage is after the first reset stage and before the light emitting stage.

[0014] Optionally, in the second reset stage, the fifth transistor is turned on according to the n-th light emitting signal, so as to reset the anode of the light emitting device by the second reset voltage.

[0015] According to the second aspect of the present application, a display panel is provided, comprising the pixel driving circuit described above.

[0016] In summary, in the pixel driving circuit of the embodiments of the present application, the on-off between the data signal line and the driving transistor is controlled by the writing control signal output by the first driving unit; the connection unit and the reset unit reuse the second driving unit, and by using the signals output by different levels of the second driving unit, the independent control of the connection unit and the reset unit can be realized, and no additional gate driving circuit needs to be set; similarly, the light emitting control unit controls the light emitting of the light emitting device by using the light emitting signals output by different levels of the third driving unit, and by reusing the third driving unit, no multiple gate driving circuits need to be set. In this way, the total number of required gate driving circuits is reduced, which is conducive to realizing the narrow frame design of the display panel.

[0017] Other features and advantages of the present application will be described in the following detailed description. BRIEF DESCRIPTION OF DRAWINGS In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some of the embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0018] In order to more completely understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.

[0019] Figure 1 is a circuit diagram of a pixel driving circuit in the related art; Figure 2 is a timing diagram of various driving signals of the pixel driving circuit in the related art; Figure 3 is a circuit diagram of a pixel driving circuit provided in an exemplary embodiment of the present disclosure; Figure 4 is a schematic diagram of a pixel driving circuit and a driving unit provided in an exemplary embodiment of the present disclosure; Figure 5 is a timing diagram of a first reset stage provided in an exemplary embodiment of the present disclosure; Figure 6 is a timing diagram of a second reset stage provided in an exemplary embodiment of the present disclosure; Figure 7 is a schematic diagram of a display panel provided in an exemplary embodiment of the present disclosure.

[0020] Reference signs: 1, writing unit; 2, connection unit; 3, reset unit; 4, light-emitting control unit; 100, pixel driving circuit. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0022] First, based on the content in the foregoing background art, the background of the present application is further described. Referring to Figure 1The pixel driving circuit can include a first thin film transistor Q1, a second thin film transistor Q2, a third thin film transistor Q3, a fourth thin film transistor Q4, a fifth thin film transistor Q5, a sixth thin film transistor Q4, and a capacitor. The first thin film transistor Q1, the second thin film transistor Q2, the third thin film transistor Q3, and the light emitting device are connected in series. The gate of the first thin film transistor Q1 is connected to a first light emitting control signal EM1. The gate of the second thin film transistor Q2 is connected to the fourth thin film transistor Q4. The gate of the third thin film transistor Q3 is connected to a second light emitting control signal EM2. The first electrode of the fourth thin film transistor Q4 is connected to the first thin film transistor Q1 and the second thin film transistor Q2 at a first driving node M. The second electrode of the fourth thin film transistor Q4 is connected to one end of the capacitor and the gate of the second thin film transistor Q2. The gate of the fourth thin film transistor Q4 is connected to a first scan signal SC1. The first electrode of the fifth thin film transistor Q5 is connected to the other end of the capacitor and the anode of the light emitting device. The second electrode of the fifth thin film transistor Q5 is connected to a reset signal. The gate of the fifth thin film transistor Q5 is connected to the second light emitting control signal EM2. The first electrode of the sixth thin film transistor Q4 is connected to an image data signal. The second electrode of the sixth thin film transistor Q4 is connected to a second driving node N connected to the second thin film transistor Q2 and the third thin film transistor Q3. The gate of the sixth thin film transistor Q4 is connected to a second scan signal SC2. The third thin film transistor Q3 and the fifth thin film transistor Q5 are different types.

[0023] Referring to Figure 2 , Figure 2 The timing diagram of the pixel driving circuit in the related art is shown in FIG. 1. When the reset operation is performed, the anode of the light emitting device is reset by turning on the fifth thin film transistor Q5 by the second light emitting control signal EM2 outputting a high level. However, since the third thin film transistor Q3 and the fifth thin film transistor Q5 are driven by the same second light emitting control signal EM2, and the third thin film transistor Q3 and the fifth thin film transistor Q5 are different types, the third thin film transistor Q3 and the fifth thin film transistor Q5 cannot be turned on at the same time, so that the reset signal cannot reset the second driving node N and the first driving node M. In addition, the first light emitting control signal EM1, the second light emitting control signal EM2, the first scan signal SC1, and the second scan signal SC2 are independently controlled signals, and are output by different gate driving circuits, so at least four gate driving circuits are required, and the frame range of the display panel is large.

[0024] Therefore, the technical solution of the present application is proposed. According to the first aspect of the present application, referring to Figure 3The present disclosure provides a pixel driving circuit, which is connected with a gate control circuit. The gate control circuit comprises a plurality of cascaded first driving units, a plurality of cascaded second driving units and a plurality of cascaded third driving units. The pixel driving circuit comprises a driving transistor Tr, a storage capacitor Cst, a writing unit 1, a connecting unit 2, a resetting unit 3 and a light-emitting control unit 4. The driving transistor Tr is an oxide transistor; The first electrode of the driving transistor Tr is connected with the connecting unit 2 and the light-emitting control unit 4 at a first node A, the second electrode is connected with the writing unit 1 and the light-emitting control unit 4 at a second node B, and the control electrode is connected with the connecting unit 2 and the storage capacitor Cst at a third node Q. The resetting unit 3 is connected with the storage capacitor Cst and the anode of the light-emitting device. The writing unit 1 is connected with the first driving unit. The connecting unit 2 and the resetting unit 3 are respectively connected with the second driving units of different levels. The light-emitting control unit 4 is connected with the third driving units of different levels.

[0025] The second driving units of different levels output signals with the same period, the same duty cycle and different phases. The light-emitting signals output by the third driving units of different levels are signals with the same period, the same duty cycle and different phases.

[0026] In the above embodiment, the writing control signal output by the first driving unit controls the on-off between the data signal line and the driving transistor Tr. The connecting unit 2 and the resetting unit 3 multiplex the second driving units. By using the signals output by the second driving units of different levels, the independent control of the connecting unit 2 and the resetting unit 3 can be realized, and no additional gate driving circuit needs to be set. Similarly, the light-emitting control unit 4 controls the light-emitting of the light-emitting device by using the light-emitting signals output by the third driving units of different levels. By multiplexing the third driving units, no multiple gate driving circuits need to be set. In this way, the total number of required gate driving circuits is reduced, which is conducive to realizing the narrow frame design of the display panel.

[0027] In some embodiments, the driving transistor Tr comprises a control electrode connected with the storage capacitor Cst and the connecting unit 2, a first electrode connected with the first node A, and a second electrode connected with the second node B.

[0028] Reference Figure 3 In some embodiments, the writing unit 1 comprises a first transistor T1. The first transistor T1 comprises a control electrode connected with the first driving unit to access the writing control signal, a first electrode connected with the data signal line, and a second electrode connected with the second node B.

[0029] As an example, the first driving unit is configured to drive a corresponding row of pixel circuits, and the nth first driving unit outputs an nth level of write control signal to drive the first transistor T1 in the nth row of pixel driving circuits.

[0030] As an example, the first transistor T1 can be an N-type transistor, and in a data writing operation, the first driving unit outputs a write control signal in a high level state to control the first transistor T1 to be turned on, and at this time, the data signal transmitted on the data signal line can be transmitted to the second node B through the first transistor T1.

[0031] In some embodiments, the connection unit 2 includes a second transistor T2. The second transistor T2 includes a control electrode connected to the nth second driving unit, a first electrode connected to the first node A, and a second electrode connected to the storage capacitor Cst. The second transistor T2 is configured to control the connection between the first node A and the storage capacitor Cst according to the nth level of driving signal output by the nth second driving unit to write the data signal transmitted on the data signal line to the third node Q. Wherein, n is a positive integer.

[0032] Wherein, the nth second driving unit can be the current level, that is, the second transistor T2 in the nth row of pixel driving circuits is connected to the nth second driving unit.

[0033] As an example, the second transistor T2 can be an N-type transistor, and in a data writing operation, in the process of the first driving unit outputting a write control signal in a high level state to transmit the data signal Data to the second node B, the nth second driving unit outputs an nth level of driving signal in a high level state to control the second transistor T2 to be turned on, and the first node A and the storage capacitor Cst are turned on. At this time, the data signal of the second node B is transmitted to the storage capacitor Cst through the driving transistor Tr and the second transistor T2, thereby completing the data writing operation.

[0034] As an example, in the data writing stage of the pixel driving circuit, the write control signal output by the first driving unit controls the first transistor T1 to be turned on, and the nth level of driving signal output by the second driving unit controls the second transistor T2 to be turned on, so as to write the data signal data transmitted on the data signal line to the third node Q.

[0035] Referring to Figure 3 In some embodiments, the reset unit 3 includes a third transistor T3. The third transistor T3 includes a control electrode connected to the nth+a second driving unit, a first electrode connected to the reset signal line, and a second electrode connected to the anode of the light emitting device. The third transistor T3 is configured to control the connection between the reset signal line and the anode of the light emitting device according to the nth+a level of driving signal output by the nth+a second driving unit to achieve reset control of the anode.

[0036] With reference to Figure 4 Wherein, a is a positive integer, a can be 1. For the pixel driving circuit of the Nth row, the connection unit 2 is connected with the n-level second driving unit, and the reset unit 3 is connected with the n+1-level second driving unit. For the next row of the pixel driving circuit of the Nth row, the pixel driving circuit of the N+1th row, the connection unit 2 is connected with the n+1-level second driving unit, and the reset unit 3 is connected with the n+2-level second driving unit, and so on. In this way, the second driving unit of each level is connected with both the connection unit 2 and the reset unit 3, so that the reuse of the second driving unit can be realized.

[0037] As an example, the third transistor T3 can be an N-type transistor. In the first reset stage, the n+a-level second driving unit outputs the n+a-level driving signal in a high level state to control the third transistor T3 to be turned on, so that the reset signal transmitted on the reset signal line is written to the anode of the light emitting device, thereby realizing the reset of the anode of the light emitting device.

[0038] As an example, since the n-level driving signal and the n+a-level driving signal are output by the second driving unit level, the phase of the n+a-level driving signal lags behind the n-level driving signal, and the period of the n-level driving signal and the n+a-level driving signal and the time length of maintaining the high level state and the low level state in a period are consistent, so that the n-level driving signal enters the high level state first, and after the lag phase, the n+a-level driving signal enters the high level state, and then the n+a-level driving signal turns to the low level state first, and after the lag phase, the n+a-level driving signal turns to the low level state. The greater the value of a is, the greater the lag phase is, and the longer the time duration of the n-level driving signal and the n+a-level driving signal in the opposite level state is. The smaller the value of a is, the smaller the lag phase is, and the longer the time duration of the n-level driving signal and the n+a-level driving signal in the same level state is.

[0039] In this way, in the first reset stage, the n+a-level driving signal can be in a high level state and the n-level driving signal can be in a low level state to control the third transistor T3 to be turned on and the second transistor T2 to be turned off.

[0040] With reference to Figure 3In some embodiments, the light emitting control unit 4 comprises a fourth transistor T4 and a fifth transistor T5. The fourth transistor T4 comprises a first electrode connected to a voltage source, a second electrode connected to the first node A, and a control electrode connected to the third driving unit of the n+bth level, for controlling the on-off between the voltage source and the first node A according to the light emitting signal of the n+bth level output by the third driving unit of the n+bth level. The fifth transistor T5 comprises a first electrode connected to the second node B, a second electrode connected to the anode of the light emitting device, and a control electrode connected to the third driving unit of the nth level, for controlling the on-off between the second node B and the light emitting device according to the light emitting signal of the nth level output by the third driving unit of the nth level, to realize the light emitting control of the light emitting device.

[0041] In some embodiments, the third driving unit of the nth level can be the current level, i.e. the fifth transistor T5 of the pixel driving circuit of the nth row is connected to the third driving unit of the nth level, and the fourth transistor T4 of the pixel driving circuit of the nth row is connected to the third driving unit of the n+bth level.

[0042] As an example, in the light emitting stage of the pixel driving circuit, the fourth transistor T4 is controlled to be turned on by the light emitting signal of the nth level output by the third driving unit, and the fifth transistor T5 is controlled to be turned on by the light emitting signal of the n+bth level output by the third driving unit, so that the light emitting device emits light.

[0043] In some embodiments, in the first reset stage after the data writing stage, the third transistor T3 is turned on according to the driving signal of the n+a level, and the fifth transistor T5 is turned on according to the light emitting signal of the nth level, so that the first reset voltage Vi1 transmitted on the reset signal line resets the anode of the light emitting device, the second node B and the first node A.

[0044] In some embodiments, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the driving transistor Tr are of the same type, which can all be N-type transistors.

[0045] In some embodiments, the first reset stage is a reset operation in a writing frame, which can be a reset of the anode of the light emitting device, the second node B and the first node A by a row of pixel driving circuits after completing the data writing operation.

[0046] Reference Figure 5For example, in the first reset stage, the first reset voltage Vi1 transmitted on the reset signal line is transmitted to the anode of the light emitting device through the third transistor T3, at this time, the n+bth light emitting signal of the n+bth third driving unit in high level state is outputted to turn on the fifth transistor T5, so as to reset the second node B by the first reset voltage Vi1 transmitted to the anode of the light emitting device, and at the same time, the data signal is stored in the storage capacitor Cst due to the data write operation completed in the first reset stage, so as to turn on the driving transistor Tr to reset the first node A by the first reset voltage Vi1 transmitted to the second node B, thereby completing the reset of the anode of the light emitting device, the second node B and the first node A.

[0047] It should be noted that the fourth transistor T4 and the fifth transistor T5 can be both N-type transistors, when the n+bth light emitting signal and the nth light emitting signal are both in high level state, the fourth transistor T4 and the fifth transistor T5 are both turned on, at this time, the output voltage of the voltage source flows to the light emitting device through the fourth transistor T4, the driving transistor Tr and the fifth transistor T5, so that the light emitting device starts to emit light. When one of the n+bth light emitting signal and the nth light emitting signal is in low level state, one of the fourth transistor T4 and the fifth transistor T5 is not turned on, so that the light emitting device does not emit light.

[0048] Referring to Figure 4 wherein b is a positive integer, and b can be 3. Since the nth light emitting signal and the n+bth light emitting signal are outputted by different third driving units, the phase of the n+bth light emitting signal lags behind the nth light emitting signal, and the period of the nth light emitting signal and the n+bth light emitting signal and the time length of maintaining high level state and low level state in a period are consistent, so that the nth light emitting signal enters high level state first, and after the lag phase, the n+bth light emitting signal enters high level state, and then the n+bth light emitting signal enters low level state first, and after the lag phase, the n+bth light emitting signal enters low level state. The greater the value of b is, the greater the lag phase is, and the longer the time duration of the opposite level state of the nth light emitting signal and the n+bth light emitting signal is. The smaller the value of b is, the smaller the lag phase is, and the longer the time duration of the same level state of the nth light emitting signal and the n+bth light emitting signal is.

[0049] Thus, in the first reset stage, the nth light emitting signal can be in high level state and the n+bth light emitting signal can be in low level state to control the fourth transistor T4 to be turned off and the fifth transistor T5 to be turned on, so as to perform the reset operation by the first reset voltage Vi1, at this time, the light emitting device does not emit light.

[0050] As an example, after the first reset phase, a second reset node may be entered. The second reset phase is a frame-keeping reset operation, which may be a reset of the second node B, the first node A and the anode of the light-emitting device before controlling the light-emitting device to emit light.

[0051] The refresh duration of a frame includes a write frame and a hold frame. Since data signals are written to the pixel driver circuits row by row, when a row of pixel driver circuits is performing a data write operation, the pixel driver circuits in that row are in the write frame, while the pixel driver circuits in other rows are in the hold frame. During the first reset phase of the write frame, residual charges on the first node A, the second node B, and the anode of the light-emitting device in the pixel driver circuit resulting from the data write operation can be cleared. During the second reset phase of the hold frame, residual charges on the first node A, the second node B, and the anode of the light-emitting device in the pixel driver circuit resulting from the data write operation due to electromagnetic coupling or other factors during the hold phase after the data write operation can be cleared.

[0052] Reference Figure 6 In (a), in some embodiments, in the second reset phase, the second reset voltage Vi2 is transmitted on the data signal line, and the first transistor T1 is turned on according to the write control signal to reset the first node A and the second node B by the second reset voltage Vi2.

[0053] The second reset voltage Vi2 is a preset constant voltage, and its amplitude may be the same as or different from the first reset voltage Vi1.

[0054] As an example, in the second reset phase, the data write operation has been completed, the data signal line stops transmitting the data signal and transmits the second reset voltage Vi2. At this time, the driving signal of the nth stage and the driving signal of the n+ath stage are in a low-level state, so that the second transistor T2 and the third transistor T3 are turned off. The write control signal is in a high-level state to control the first transistor T1 to turn on, and the second node B is reset by the second reset voltage Vi2. Since the data write operation has been completed at this time, the data signal stored in the storage capacitor Cst controls the driving transistor Tr to turn on, so that the second reset voltage Vi2 of the second node B is transmitted to the first node A, thereby resetting the first node A.

[0055] Reference Figure 6 In (b), in some embodiments, in the second reset stage, the fifth transistor T5 is turned on according to the light emitting signal of the nth stage to reset the anode of the light emitting device through the second reset voltage Vi2.

[0056] As an example, in the second reset stage, the light emitting signal of the nth stage is in a high level state to control the fifth transistor T5 to be turned on to reset the anode of the light emitting device by the second reset voltage Vi2 transmitted to the second node B. At this time, the light emitting signal of the nth+b stage is in a low level state, the fourth transistor T4 is turned on, and the light emitting device does not emit light.

[0057] In this way, the reset of the first node A, the second node B and the anode of the light emitting device by the second reset voltage Vi2 transmitted on the data signal line in the holding frame can be realized.

[0058] The second reset stage is after the first reset stage and before the light emitting stage. By resetting the first node A, the second node B and the anode of the light emitting device between the light emitting stages, the residual charge of the last frame or the charge formed during the first reset stage to the light emitting stage due to interference or leakage current can be released. In particular, in the scenario of low frequency display (such as 60Hz), the residual image caused by residual charge is more visually observable, and therefore, by resetting the first node A, the second node B and the anode of the light emitting device through the second reset stage, the low frequency visual effect of the display panel can also be improved.

[0059] Referring to Figure 5 and Figure 6 , the working process of the pixel driving circuit is exemplarily described as follows: In the data writing period t1, the driving signal of the nth stage is in a high level state, the driving signal of the nth+a stage is in a high level state, the writing control signal is in a high level state, the light emitting signal of the nth stage is in a low level state, and the light emitting signal of the nth+b stage is in a low level state to respectively control the first transistor T1 to be turned on, the second transistor T2 to be turned on, the third transistor T3 to be turned on, the fourth transistor T4 to be turned off, and the fifth transistor T5 to be turned off, and the data signal is written into the storage capacitor Cst through the first transistor T1, the driving transistor Tr and the second transistor T2. In the first reset stage t2, the driving signal of the nth stage is in a low level state, the driving signal of the nth+a stage is in a high level state, the writing control signal is in a low level state, the light emitting signal of the nth stage is in a high level state, and the light emitting signal of the nth+b stage is in a low level state to respectively control the first transistor T1 to be turned off, the second transistor T2 to be turned off, the third transistor T3 to be turned on, the fourth transistor T4 to be turned off, and the fifth transistor T5 to be turned on, so that the first reset voltage Vi1 resets the anode of the light emitting device through the third transistor T3, then resets the anode of the light emitting device through the fifth transistor T5, and resets the first node A through the driving transistor Tr.

[0060] In the second reset stage t3, the driving signal of the nth stage is in a low level state, the driving signal of the nth+a stage is in a low level state, the write control signal is in a high level state, the light emitting signal of the nth stage is in a high level state, and the light emitting signal of the nth+b stage is in a low level state, so as to respectively control the first transistor T1 to be turned on, the second transistor T2 to be turned off, the third transistor T3 to be turned off, the fourth transistor T4 to be turned off, and the fifth transistor T5 to be turned on, so that the second reset voltage Vi2 resets the second node B through the first transistor T1, and then resets the anode of the light emitting device through the fifth transistor T5, and resets the first node A through the driving transistor Tr.

[0061] Finally, in the light emitting stage t4, the driving signal of the nth stage is in a low level state, the driving signal of the nth+a stage is in a low level state, the write control signal is in a low level state, the light emitting signal of the nth stage is in a high level state, and the light emitting signal of the nth+b stage is in a high level state, so as to respectively control the first transistor T1 to be turned off, the second transistor T2 to be turned off, the third transistor T3 to be turned off, the fourth transistor T4 to be turned on, and the fifth transistor T5 to be turned on, and the output voltage of the voltage source is transmitted to the light emitting device through the fourth transistor T4, the driving transistor Tr and the fifth transistor T5, so as to drive the light emitting device to emit light.

[0062] According to a second aspect of the present disclosure, a display panel is provided, which comprises the pixel driving circuit described above. The display panel has all the beneficial effects of the pixel driving circuit described above, and the present disclosure will not be repeated here.

[0063] Reference Figure 7 , Figure 7 FIG. 1 is a schematic diagram of a display panel in an embodiment of the present application. The display panel comprises a display area AA and a non-display area NA which is arranged adjacent to the display area AA and surrounds the display area AA. The display area AA is an area in the display panel for displaying, and a plurality of display units for displaying are arranged in the display area AA. The non-display area NA can be a frame area of the display panel, and functional components for assisting the display units in the display area AA to display can be arranged in the non-display area NA.

[0064] The display region AA can be provided with a plurality of light emitting devices D and pixel driving circuits 100 for driving the light emitting devices D in an array. The non-display region NA is provided with a gate driving apparatus. The gate driving apparatus can include a first driving unit 200, a second driving unit 300, and a third driving unit 400, which are cascaded. Each stage of the first driving unit 200 is configured to output a write control signal to the pixel driving circuits 100 of a corresponding row, each stage of the second driving unit 300 is configured to output a driving signal to the pixel driving circuits 100 of different rows, and each stage of the third driving unit 400 is configured to output a light emitting signal to the pixel driving circuits 100 of different rows, so that the pixel driving circuits 100 cooperatively control the light emitting devices to emit light according to the write control signal, the driving signal output from the second driving unit 300 of different stages, and the light emitting signal output from the third driving unit 400 of different stages.

[0065] In addition, according to the size of the display panel, the first driving unit 200, the second driving unit 300, and the third driving unit 400 can be single-side driving or double-side driving. For example, if the size of the display panel is small, the first driving unit 200, the second driving unit 300, and the third driving unit 400 can be arranged on one side of the display panel for single-side driving. If the size of the display panel is large, the load on each transmission line due to voltage drop is heavy, and in this case, the first driving unit 200, the second driving unit 300, and the third driving unit 400 can also be double-side driving.

[0066] In the description of the present application, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0067] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0068] The embodiments, implementation manners and related technical features of the present application can be combined or replaced with each other without conflict.

[0069] The above is only a preferred embodiment of the present application, and does not limit the present application in any form. Any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present application, without departing from the technical solution of the present application, still falls within the scope of the technical solution of the present application.

Claims

1. A pixel driving circuit, characterized in that: The pixel driving circuit is connected to a gate control circuit, and the gate control circuit includes a plurality of cascaded first driving units, a plurality of cascaded second driving units, and a plurality of cascaded third driving units; The pixel driving circuit includes a driving transistor, a storage capacitor, a writing unit, a connecting unit, a reset unit and a light emitting control unit; the driving transistor is an oxide transistor; The first electrode of the driving transistor is connected to the connecting unit and the light emitting control unit at a first node, the second electrode is connected to the writing unit and the light emitting control unit at a second node, and the control electrode is connected to the connecting unit and the storage capacitor at a third node; the reset unit is connected to the storage capacitor and the anode of the light emitting device; The writing unit is connected to the first driving unit; the connecting unit and the resetting unit are respectively connected to the second driving units of different levels; and the light emitting control unit is connected to the third driving units of different levels.

2. The pixel driving circuit according to claim 1, wherein: The writing unit includes a first transistor; The first transistor includes a control electrode connected to the first driving unit to receive a write control signal, a first electrode connected to the data signal line, and a second electrode connected to the second node.

3. The pixel driving circuit according to claim 2, wherein: The connection unit includes a second transistor; The second transistor includes a control electrode connected to the n-th stage second driving unit, a first electrode connected to the first node, and a second electrode connected to the storage capacitor; the second transistor is used to control the connection and disconnection between the first node and the storage capacitor according to the n-th stage driving signal output by the n-th stage second driving unit, so as to write the data signal transmitted by the data signal line into the third node; Wherein, n is a positive integer.

4. The pixel driving circuit according to claim 3, wherein: During the data writing stage of the pixel driving circuit, the first transistor is controlled to be turned on by the write control signal output by the first driving unit, and the second transistor is controlled to be turned on by the n-th level driving signal output by the second driving unit, so as to write the data signal transmitted on the data signal line to the third node.

5. The pixel driving circuit according to claim 4, wherein: The reset unit includes a third transistor; The third transistor includes a control electrode connected to the second driving unit of the n+ath level, a first electrode connected to the reset signal line, and a second electrode connected to the anode of the light-emitting device. The third transistor is used to control the connection and disconnection between the reset signal line and the anode of the light-emitting device according to the n+ath level driving signal output by the second driving unit of the n+ath level, thereby realizing reset control of the anode; Wherein, a is a positive integer.

6. The pixel driving circuit according to claim 5, wherein: The light emitting control unit includes a fourth transistor and a fifth transistor; The fourth transistor includes a first electrode connected to a voltage source, a second electrode connected to the first node, and a control electrode connected to the third driving unit of the n+bth stage, and is used to control the connection between the voltage source and the first node according to the light-emitting signal of the n+bth stage output by the third driving unit of the n+bth stage; The fifth transistor includes a first electrode connected to the second node, a second electrode connected to the anode of the light-emitting device, and a control electrode connected to the n-th level third driving unit, and is used to control the connection between the second node and the light-emitting device according to the n-th level light-emitting signal output by the n-th level third driving unit, thereby realizing light emission control of the light-emitting device; Wherein, b is a positive integer; In the light-emitting stage of the pixel driving circuit, the light-emitting signal of the nth level output by the third driving unit controls the fourth transistor to be turned on, and the light-emitting signal of the n+bth level output by the third driving unit controls the fifth transistor to be turned on, so that the light-emitting device emits light.

7. The pixel driving circuit according to claim 6, wherein: In the first reset stage after the data writing stage, the third transistor is turned on according to the driving signal of the n+a level, and the fifth transistor is turned on according to the light-emitting signal of the n level, so that the first reset voltage transmitted on the reset signal line resets the anode, the second node and the first node of the light-emitting device.

8. The pixel driving circuit according to claim 7, wherein: In a second reset phase, a second reset voltage is transmitted on the data signal line, and the first transistor is turned on according to the write control signal, so as to reset the first node and the second node by the second reset voltage; The second reset phase is after the first reset phase and before the light emitting phase.

9. The pixel driving circuit according to claim 8, wherein: In the second reset stage, the fifth transistor is turned on according to the light emitting signal of the nth stage, so as to reset the anode of the light emitting device by the second reset voltage.

10. A display panel, characterized in that: The pixel driving circuit comprises the pixel driving circuit according to any one of claims 1 to 9.

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