Shift register unit, gate drive circuit and display panel

Abstract

The invention relates to the technical field of display, and provides a shift register unit, a gate drive circuit and a display panel, the shift register unit comprises a first input circuit, a second input circuit, a first output circuit, a second output circuit and a first control circuit, the first input circuit is used for transmitting a signal of a first clock signal end to a first node in response to a signal of a second node; the second input circuit is used for transmitting a signal of a signal input end to a second node in response to a signal of a first clock signal end; the first output circuit is used for responding to the signal of the first node to transmit the signal of the first power supply end to the signal output end; the second output circuit is used for responding to the signal of the second node to transmit the signal of the second clock signal end to the signal output end; the first control circuit is used for responding to a control signal to transmit a signal of the second power supply end to the first node. The shift register unit has a relatively simple structure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a shift register unit, a gate driving circuit and a display panel. BACKGROUND

[0002] The display panel comprises a gate driving circuit, and the gate driving circuit is configured to provide a gate driving signal to a pixel driving circuit. In the related art, the structure of the gate driving circuit is relatively complex, thereby resulting in a relatively large frame width for integrating the gate driving circuit.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0004] According to an aspect of the present disclosure, a shift register unit is provided, wherein the shift register unit comprises:

[0005] a first input circuit connected to a first clock signal terminal, a first node and a second node, the first input circuit being configured to transmit a signal of the first clock signal terminal to the first node in response to a signal of the second node;

[0006] a second input circuit connected to a signal input terminal, the first clock signal terminal and the second node, the second input circuit being configured to transmit a signal of the signal input terminal to the second node in response to a signal of the first clock signal terminal;

[0007] a first output circuit connected to the first node, a signal output terminal and a first power supply terminal, the first output circuit being configured to transmit a signal of the first power supply terminal to the signal output terminal in response to a signal of the first node;

[0008] a second output circuit connected to the second node, the signal output terminal and a second clock signal terminal, the second output circuit being configured to transmit a signal of the second clock signal terminal to the signal output terminal in response to a signal of the second node;

[0009] a first control circuit connected to the first node and a second power supply terminal, the first control circuit being configured to transmit a signal of the second power supply terminal to the first node in response to a control signal.

[0010] In an exemplary embodiment of the present disclosure, the shift register unit further comprises:

[0011] The second control circuit is connected to the second node, the first power supply terminal or the second clock signal terminal, and is configured to transmit a signal of the first power supply terminal or the second clock signal terminal to the second node in response to a control signal.

[0012] In an example embodiment of the present disclosure, the first control circuit is further connected to the first clock signal terminal, and is configured to transmit a signal of the second power supply terminal to the first node in response to a signal of the first clock signal terminal.

[0013] In an example embodiment of the present disclosure, the first control circuit is further connected to a first control signal terminal, and is configured to transmit a signal of the second power supply terminal to the first node in response to a signal of the first control signal terminal.

[0014] The shift register unit is applied to a gate drive circuit, the gate drive circuit comprising a plurality of cascaded shift register units, a signal output terminal of an upper shift register unit being connected to a signal input terminal of a lower shift register unit cascaded therewith, and a signal output terminal of the lower shift register unit being connected to a first control signal terminal of the upper shift register unit cascaded therewith.

[0015] A signal input terminal of a first shift register unit is connected to a first initialization signal terminal, and a first control signal terminal of the first shift register unit is connected to a second initialization signal terminal.

[0016] In an example embodiment of the present disclosure, the shift register unit further comprises:

[0017] A coupling circuit is connected between the first clock signal terminal and a third node, and is configured to couple a voltage change of the first clock signal terminal to the third node.

[0018] The first control circuit is further connected to the third node, and is configured to transmit a signal of the second power supply terminal to the first node in response to a signal of the third node.

[0019] In an example embodiment of the present disclosure, the second control circuit is further connected to a second control signal terminal, and is configured to transmit a signal of the second power supply terminal or the second clock signal terminal to the second node in response to a signal of the second control signal terminal.

[0020] The shift register unit is applied to a gate drive circuit, the gate drive circuit comprising a plurality of cascaded shift register units, a signal output terminal of an upper shift register unit being connected to a signal input terminal of a lower shift register unit cascaded therewith, and a signal output terminal of the lower shift register unit being connected to a second control signal terminal of the upper shift register unit cascaded therewith.

[0021] In one example embodiment of the present disclosure, the first control circuit is further connected to a first control signal terminal, and the first control circuit is configured to transmit a signal of the second power terminal to the first node in response to a signal of the first control signal terminal.

[0022] The second control circuit is further connected to the first control signal terminal, and the second control circuit is configured to transmit a signal of the second power terminal or a second clock signal terminal to the second node in response to a signal of the first control signal terminal.

[0023] The shift register unit is applied to a gate drive circuit, and the gate drive circuit comprises a plurality of cascaded shift register units, a signal output terminal of an upper shift register unit is connected to a signal input terminal of a lower shift register unit cascaded therewith, and a signal output terminal of the lower shift register unit is connected to a first control signal terminal of the upper shift register unit cascaded therewith.

[0024] A signal input terminal of a first shift register unit is connected to a first initialization signal terminal, and a first control signal terminal of the first shift register unit is connected to a second initialization signal terminal.

[0025] In one example embodiment of the present disclosure, the first input circuit comprises:

[0026] A second transistor, a first electrode of which is connected to a first clock signal terminal, a second electrode of which is connected to the first node, and a gate of which is connected to the second node;

[0027] The second input circuit comprises:

[0028] A first transistor, a first electrode of which is connected to a signal input terminal, a second electrode of which is connected to the second node, and a gate of which is connected to the first clock signal terminal;

[0029] The first output circuit comprises:

[0030] A fourth transistor, a first electrode of which is connected to the first power terminal, a second electrode of which is connected to the signal output terminal, and a gate of which is connected to the first node;

[0031] A second capacitor, a first electrode of which is connected to the first node, and a second electrode of which is connected to the first power terminal;

[0032] The second output circuit comprises:

[0033] A fifth transistor, a first electrode of which is connected to the second clock signal terminal, a second electrode of which is connected to the signal output terminal, and a gate of which is connected to the second node;

[0034] A first capacitor, a first electrode of which is connected to the second node, and a second electrode of which is connected to the signal output terminal;

[0035] The first control circuit comprises:

[0036] The third transistor has a first electrode connected to the second power supply end, a second electrode connected to the first node, and a gate electrode connected to the first control signal end or the first clock signal end.

[0037] The second control circuit comprises:

[0038] The sixth transistor has a first electrode connected to the first power supply end or the second clock signal end, a second electrode connected to the second node, and a gate electrode connected to the second control signal end or the first control signal end.

[0039] According to an aspect of the present disclosure, there is provided a gate drive circuit, wherein the gate drive circuit comprises a plurality of the above-mentioned shift register units, and the plurality of shift register units are arranged in cascade.

[0040] According to an aspect of the present disclosure, there is provided a display panel, wherein the display panel comprises the above-mentioned gate drive circuit.

[0041] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0042] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of the present disclosure. It is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0043] Figure 1 Structure diagram of an exemplary embodiment of the shift register unit of the present disclosure;

[0044] Figure 2 Structure diagram of an exemplary embodiment of the gate drive circuit of the present disclosure;

[0045] Figure 3 Structure diagram of Figure 2 Timing diagram of each node in a driving method of the shift register unit in the gate drive circuit shown;

[0046] Figure 4 Structure diagram of another exemplary embodiment of the shift register unit of the present disclosure;

[0047] Figure 5 Structure diagram of another exemplary embodiment of the gate drive circuit of the present disclosure;

[0048] Figure 6 Structure diagram ofFigure 5 Timing chart of each node in a driving method of a shift register unit in the gate driving circuit shown in FIG. 1;

[0049] Figure 7 Structure diagram of another exemplary embodiment of a shift register unit of the present disclosure;

[0050] Figure 8 Structure diagram of another exemplary embodiment of a gate driving circuit of the present disclosure;

[0051] Figure 9 Figure 8 Timing chart of each node in a driving method of a shift register unit in the gate driving circuit shown in FIG. 1;

[0052] Figure 10 Structure diagram of another exemplary embodiment of a shift register unit of the present disclosure. DETAILED DESCRIPTION

[0053] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings; however, these embodiments should not be construed as limiting all example embodiments. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the drawings.

[0054] The terms "one", "a", "said" are used to indicate that there is one or more of the elements / components / etc.; the terms "include" and "has" are used to indicate an open-ended inclusion and that there can be additional elements / components / etc. in addition to those listed.

[0055] The present exemplary embodiments first provide a shift register unit, as Figure 1 ​As shown, it is a structural schematic diagram of an exemplary embodiment of the shift register unit of the present disclosure, which comprises a first input circuit 1, a second input circuit 2, a first output circuit 3, a second output circuit 4, and a first control circuit 5. The first input circuit 1 is connected with a first clock signal end CK, a first node N1 and a second node N2, and is used to transmit the signal of the first clock signal end CK to the first node N1 in response to the signal of the second node N2; the second input circuit 2 is connected with a signal input end IN, the first clock signal end CK and the second node N2, and is used to transmit the signal of the signal input end IN to the second node N2 in response to the signal of the first clock signal end CK; the first output circuit 3 is connected with the first node N1, a signal output end OUT and a first power supply end VGH, and is used to transmit the signal of the first power supply end VGH to the signal output end OUT in response to the signal of the first node N1; the second output circuit 4 is connected with the second node N2, the signal output end OUT and a second clock signal end CB, and is used to transmit the signal of the second clock signal end CB to the signal output end OUT in response to the signal of the second node N2; and the first control circuit 5 is connected with the first node N1 and a second power supply end VGL, and is used to transmit the signal of the second power supply end VGL to the first node N1 in response to a control signal.

[0056] The driving method of the shift register unit provided by the example embodiment can include a first stage, a second stage, a third stage, and a fourth stage. In the first stage, the signal input end IN and the first clock signal end CK output valid levels, the second clock signal end CB outputs an invalid level, the second input circuit 2 transmits the valid level of the signal input end IN to the second node N2, the second output circuit 4 transmits the invalid level of the second clock signal end CB to the signal output end OUT under the action of the second node N2, the first input circuit 1 transmits the valid level of the first clock signal end CK to the first node N1 under the action of the second node N2, and the first output circuit 3 transmits the invalid level of the first power supply end to the signal output end under the action of the valid level of the first node N1. In the second stage, the signal input end IN and the first clock signal end CK output invalid levels, the second clock signal end CB outputs a valid level, the second node N2 maintains a valid level, the second output circuit 4 transmits the valid level of the second clock signal end CB to the signal output end OUT under the action of the second node N2, the first input circuit 1 transmits the invalid level of the first clock signal end to the first node N1 under the action of the second node N2, and the first output circuit 3 is turned off. In the third stage, the signal input end IN and the second clock signal end CB output invalid levels, the first clock signal end CK outputs a valid level, the second input circuit 2 transmits the invalid level of the signal input end IN to the second node N2 under the action of the first clock signal end CK, the second output circuit 4 is turned off, and at the same time, the first control circuit 5 transmits the valid level of the second power supply end VGL to the first node, and the first output circuit 3 transmits the invalid level of the first power supply end VGH to the signal output end OUT under the action of the first node N1. In the fourth stage, the signal input end IN and the first clock signal end CK output invalid levels, the second clock signal end CB outputs a valid level, the first node N1 maintains a valid level, and the first output circuit 3 transmits the invalid level of the first power supply end VGH to the signal output end OUT under the action of the first node N1.

[0057] It should be noted that the valid level is a level that can turn on the target circuit, and the invalid level is a level that can turn off the target circuit. For example, when the target circuit is a P-type transistor, the valid level is a low level, and the invalid level is a high level.

[0058] In the example embodiment, as shown in Figure 1 The shift register unit can further include a second control circuit 6 connected to the second node N2, the first power supply end VGH, or the second clock signal end CB. The second control circuit 6 is configured to transmit the signal of the first power supply end VGH or the second clock signal end CB to the second node N2 in response to a control signal. The second control circuit 6 can input the invalid level to the second node N2 in the third stage to further turn off the second output circuit 4.

[0059] In the example embodiment, as shown in Figure 1 The first control circuit 5 is further connected to a first clock signal terminal CK, and is configured to transmit a signal of the second power supply terminal VGL to the first node N1 in response to a signal of the first clock signal terminal CK.

[0060] In the example embodiment, as shown in Figure 1 The second control circuit 6 is further connected to a second control signal terminal CN2, and is configured to transmit a signal of the second power supply terminal VGL or the second clock signal terminal CB to the second node N2 in response to a signal of the second control signal terminal CN2.

[0061] In the example embodiment, as shown in Figure 1 The first input circuit 1 can include a second transistor T2, a first electrode of the second transistor T2 being connected to the first clock signal terminal CK, a second electrode of the second transistor T2 being connected to the first node N1, and a gate of the second transistor T2 being connected to the second node N2. The second input circuit 2 can include a first transistor T1, a first electrode of the first transistor T1 being connected to the signal input terminal IN, a second electrode of the first transistor T1 being connected to the second node N2, and a gate of the first transistor T1 being connected to the first clock signal terminal CK. The first output circuit 3 can include a fourth transistor T4 and a second capacitor C2, a first electrode of the fourth transistor T4 being connected to the first power supply terminal VGH, a second electrode of the fourth transistor T4 being connected to the signal output terminal OUT, and a gate of the fourth transistor T4 being connected to the first node N1; a first electrode of the second capacitor C2 being connected to the first node N1, and a second electrode of the second capacitor C2 being connected to the first power supply terminal VGH. The second output circuit 4 can include a fifth transistor T5 and a first capacitor C1, a first electrode of the fifth transistor T5 being connected to the second clock signal terminal CB, a second electrode of the fifth transistor T5 being connected to the signal output terminal OUT, and a gate of the fifth transistor T5 being connected to the second node N2; a first electrode of the first capacitor C1 being connected to the second node N2, and a second electrode of the first capacitor C1 being connected to the signal output terminal OUT. The first control circuit 5 can include a third transistor T3, a first electrode of the third transistor T3 being connected to the second power supply terminal VGL, a second electrode of the third transistor T3 being connected to the first node N1, and a gate of the third transistor T3 being connected to the first clock signal terminal CK. The second control circuit 6 can include a sixth transistor T6, a first electrode of the sixth transistor T6 being connected to the first power supply terminal VGH or the second clock signal terminal CB, a second electrode of the sixth transistor T6 being connected to the second node N2, and a gate of the sixth transistor T6 being connected to the second control signal terminal CN2.

[0062] In the example embodiment, as shown in Figure 1 The first transistor T1 to the sixth transistor T6 can be P-type transistors, the first power supply terminal VGH can be a high-level power supply terminal, and the second power supply terminal VGL can be a low-level power supply terminal. It should be understood that in other example embodiments, the first transistor T1 to the sixth transistor T6 can also be N-type transistors, and correspondingly, the first power supply terminal can also be a low-level power supply terminal, and the second power supply terminal can also be a high-level power supply terminal.

[0063] AsFigure 2 Fig. 1 shows a structural schematic diagram of an exemplary embodiment of a gate drive circuit according to the present disclosure, which can include a plurality of cascaded shift register units GOA. The structure of the shift register unit GOA can be as shown in Fig. 2. Figure 1 Fig. 1. In which the signal output end OUT of the upper shift register unit GOA is connected to the signal input end IN of the lower shift register unit GOA cascaded therewith, and the signal output end OUT of the lower shift register unit GOA is connected to the second control signal end CN2 of the upper shift register unit GOA cascaded therewith. The signal input end IN of the first shift register unit GOA is connected to the first initialization signal end STV1.

[0064] Fig. 1. As shown in Fig. 2, the gate drive circuit can further include a first clock signal line LCK and a second clock signal line LCB. The first clock signal line LCK is connected to the first clock signal end CK of the odd-numbered shift register unit and the second clock signal end CB of the even-numbered shift register unit. The second clock signal line LCB is connected to the second clock signal end CB of the odd-numbered shift register unit and the first clock signal end CK of the even-numbered shift register unit. Figure 2 Fig. 1. As shown in Fig. 2, the gate drive circuit can further include a first clock signal line LCK and a second clock signal line LCB. The first clock signal line LCK is connected to the first clock signal end CK of the odd-numbered shift register unit and the second clock signal end CB of the even-numbered shift register unit. The second clock signal line LCB is connected to the second clock signal end CB of the odd-numbered shift register unit and the first clock signal end CK of the even-numbered shift register unit.

[0065] Figure 3 Fig. 1. As shown in Fig. 2, the gate drive circuit can further include a first clock signal line LCK and a second clock signal line LCB. The first clock signal line LCK is connected to the first clock signal end CK of the odd-numbered shift register unit and the second clock signal end CB of the even-numbered shift register unit. The second clock signal line LCB is connected to the second clock signal end CB of the odd-numbered shift register unit and the first clock signal end CK of the even-numbered shift register unit. Figure 2 Fig. 1. As shown in Fig. 2, the gate drive circuit can further include a first clock signal line LCK and a second clock signal line LCB. The first clock signal line LCK is connected to the first clock signal end CK of the odd-numbered shift register unit and the second clock signal end CB of the even-numbered shift register unit. The second clock signal line LCB is connected to the second clock signal end CB of the odd-numbered shift register unit and the first clock signal end CK of the even-numbered shift register unit.

[0066] The exemplary embodiment takes the driving method of the first shift register unit as an example for illustration. The driving method of the shift register unit includes a first stage t1, a second stage t2, a third stage t3, and a fourth stage t4.

[0067] In the first stage t1, the first initialization signal end STV1 and the first clock signal line LCK output low level, and the second clock signal line LCB outputs high level. The first transistor T1 is turned on, the first initialization signal end STV1 inputs low level to the second node N2, the fifth transistor T5 is turned on, the second clock signal line LCB inputs high level to the signal output end OUT, the second transistor T2 is turned on, the first clock signal line LCK inputs low level signal to the first node N1, the fourth transistor T4 is turned on, and the first power supply end VGH inputs high level to the signal output end OUT.

[0068] ​In the second phase t2, the first initialization signal terminal STV1 and the first clock signal line LCK output a high level, and the second clock signal line LCB outputs a low level. The second node N2 maintains a low level signal, the fifth transistor T5 is turned on, the second clock signal line LCB inputs a low level to the signal output terminal OUT, the second transistor T2 is turned on, the first clock signal line LCK inputs a high level to the first node N1, and the fourth transistor T4 is turned off.

[0069] In the third phase t3, the first initialization signal terminal STV1 and the second clock signal line LCB output a high level, and the first clock signal line LCK outputs a low level. The first transistor T1 is turned on, and the first initialization signal terminal STV1 inputs a high level to the second node N2. At the same time, the sixth transistor T6 is turned on, and the first power supply terminal VGH or the second clock signal line LCB inputs a high level to the second node N2. The second transistor T2 and the fifth transistor T5 are turned off, and the third transistor T3 is turned on. The second power supply terminal VGL inputs a low level to the first node N1. The fourth transistor T4 is turned on, and the first power supply terminal VGH inputs a high level to the signal output terminal OUT.

[0070] In the fourth phase t4, the first initialization signal terminal STV1 and the first clock signal line LCK output a high level, the second clock signal line LCB outputs a low level, the second node N2 maintains a high level, the first node N1 maintains a low level, the fourth transistor T4 is turned on, and the first power supply terminal VGH inputs a high level to the signal output terminal OUT.

[0071] like Figure 4 FIG. 1 is a structural diagram of another exemplary embodiment of the shift register unit disclosed in the present invention. Figure 1 The difference between the shift register unit shown is that the first control circuit 5 is connected to the first control signal terminal CN1 , and the first control circuit 5 is configured to respond to the signal of the first control signal terminal CN1 to transmit the signal of the second power terminal VGL to the first node N1 .

[0072] like Figure 5 FIG. 1 is a schematic diagram showing another exemplary embodiment of a gate drive circuit disclosed herein. The gate drive circuit may include multiple Figure 4 The shift register unit GOA shown is configured as a cascade arrangement of multiple shift register units. The signal output terminal OUT of the upper-stage shift register unit GOA is connected to the signal input terminal IN of the lower-stage shift register unit GOA to which it is cascaded, and the signal output terminal OUT of the lower-stage shift register unit GOA is connected to the second control signal terminal CN2 and the first control signal terminal CN1 of the upper-stage shift register unit GOA to which it is cascaded. The signal input terminal IN of the first-stage shift register unit GOA is connected to the first initialization signal terminal STV1, and the first control signal terminal CN1 of the first-stage shift register unit GOA is connected to the second initialization signal terminal STV2.

[0073] As shown in Figure 5 The gate drive circuit can further include a first clock signal line LCK and a second clock signal line LCB. The first clock signal line LCK is connected to the first clock signal end CK of the odd-stage shift register unit and the second clock signal end CB of the even-stage shift register unit. The second clock signal line LCB is connected to the second clock signal end CB of the odd-stage shift register unit and the first clock signal end CK of the even-stage shift register unit.

[0074] As shown in Figure 6 As shown in Figure 5 The timing diagrams of the nodes in the driving method of the shift register unit in the gate drive circuit are shown in FIG. 6. STV1 is the timing diagram of the first initialization signal end, STV2 is the timing diagram of the second initialization signal end, LCK is the timing diagram on the first clock signal line, LCB is the timing diagram on the second clock signal line, N1 is the timing diagram of the first node in the first-stage shift register unit, N2 is the timing diagram of the second node in the first-stage shift register unit, OUT1 is the timing diagram of the signal output end in the first-stage shift register unit, and OUT2 is the timing diagram of the signal output end in the second-stage shift register unit.

[0075] The driving method of the shift register unit includes a first stage t1, a second stage t2, a third stage t3, and a fourth stage t4.

[0076] In the first stage t1, the first initialization signal end STV1 and the first clock signal line LCK output low level, the second initialization signal end STV2 and the second clock signal line LCB output high level. The first transistor T1 is turned on, the first initialization signal end STV1 inputs low level to the second node N2, the fifth transistor T5 is turned on, the second clock signal line LCB inputs high level to the signal output end OUT, the second transistor T2 is turned on, the first clock signal line LCK inputs low level signal to the first node N1, the fourth transistor T4 is turned on, and the first power supply end VGH inputs high level to the signal output end OUT.

[0077] In the second stage t2, the first initialization signal end STV1, the second initialization signal end STV2, and the first clock signal line LCK output high level, and the second clock signal line LCB outputs low level. The second node N2 maintains low level signal, the fifth transistor T5 is turned on, the second clock signal line LCB inputs low level to the signal output end OUT, the second transistor T2 is turned on, the first clock signal line LCK inputs high level to the first node N1, and the fourth transistor T4 is turned off.

[0078] In the third phase t3, the first initialization signal terminal STV1 and the second clock signal line LCB output a high level, while the second initialization signal terminal STV2 and the first clock signal line LCK output a low level. The first transistor T1 is turned on, and the first initialization signal terminal STV1 inputs a high level to the second node N2. Simultaneously, the sixth transistor T6 is turned on, and the first power supply terminal VGH or the second clock signal line LCB inputs a high level to the second node N2. The second transistor T2 and the fifth transistor T5 are turned off, and the third transistor T3 is turned on. The second power supply terminal VGL inputs a low level to the first node N1. The fourth transistor T4 is turned on, and the first power supply terminal VGH inputs a high level to the signal output terminal OUT.

[0079] In the fourth phase t4, the first initialization signal terminal STV1, the second initialization signal terminal STV2, and the first clock signal line LCK output high levels, while the second clock signal line LCB outputs a low level. The second node N2 maintains a high level, the first node N1 maintains a low level, the fourth transistor T4 is turned on, and the first power supply terminal VGH inputs a high level to the signal output terminal OUT.

[0080] like Figure 7 FIG. 1 is a structural diagram of another exemplary embodiment of the shift register unit disclosed in the present invention. Figure 4 The shift register unit shown is different in that the second control circuit 6 is connected to the first control signal terminal CN1 and is used to respond to the signal of the first control signal terminal CN1 to transmit the signal of the first power terminal VGH or the second clock signal terminal CB to the second node N2.

[0081] like Figure 8 FIG. 1 is a schematic diagram showing another exemplary embodiment of a gate drive circuit disclosed herein. The gate drive circuit may include multiple Figure 7 The shift register unit GOA shown is configured as a cascade arrangement of multiple shift register units. The signal output terminal OUT of the upper-stage shift register unit GOA is connected to the signal input terminal IN of the lower-stage shift register unit GOA to which it is cascaded, and the signal output terminal OUT of the lower-stage shift register unit GOA is connected to the first control signal terminal CN1 of the upper-stage shift register unit GOA to which it is cascaded. The signal input terminal IN of the first-stage shift register unit GOA is connected to the first initialization signal terminal STV1, and the first control signal terminal CN1 of the first-stage shift register unit GOA is connected to the second initialization signal terminal STV2.

[0082] like Figure 8As shown, the gate drive circuit can further include a first clock signal line LCK and a second clock signal line LCB, the first clock signal line LCK being connected to the first clock signal end CK of the odd-stage shift register unit and the second clock signal end CB of the even-stage shift register unit, and the second clock signal line LCB being connected to the second clock signal end CB of the odd-stage shift register unit and the first clock signal end CK of the even-stage shift register unit.

[0083] As shown in FIG. 6, the gate drive circuit can further include a first clock signal line LCK and a second clock signal line LCB, the first clock signal line LCK being connected to the first clock signal end CK of the odd-stage shift register unit and the second clock signal end CB of the even-stage shift register unit, and the second clock signal line LCB being connected to the second clock signal end CB of the odd-stage shift register unit and the first clock signal end CK of the even-stage shift register unit. Figure 9 As shown in FIG. 6, the gate drive circuit can further include a first clock signal line LCK and a second clock signal line LCB, the first clock signal line LCK being connected to the first clock signal end CK of the odd-stage shift register unit and the second clock signal end CB of the even-stage shift register unit, and the second clock signal line LCB being connected to the second clock signal end CB of the odd-stage shift register unit and the first clock signal end CK of the even-stage shift register unit. Figure 8 FIG. 7 shows a timing diagram of each node in a driving method of the shift register unit in the gate drive circuit shown in FIG. 6. In the timing diagram, STV1 is a timing diagram of the first initialization signal end, STV2 is a timing diagram of the second initialization signal end, LCK is a timing diagram on the first clock signal line, LCB is a timing diagram on the second clock signal line, N1 is a timing diagram of the first node in the first-stage shift register unit, N2 is a timing diagram of the second node in the first-stage shift register unit, OUT1 is a timing diagram of the signal output end in the first-stage shift register unit, and OUT2 is a timing diagram of the signal output end in the second-stage shift register unit.

[0084] The present exemplary embodiment takes the driving method of the first-stage shift register unit as an example for illustration. The driving method of the shift register unit includes a first stage t1, a second stage t2, a third stage t3, and a fourth stage t4.

[0085] In the first stage t1, the first initialization signal end STV1 and the first clock signal line LCK output low level, and the second initialization signal end STV2 and the second clock signal line LCB output high level. The first transistor T1 is turned on, the first initialization signal end STV1 inputs low level to the second node N2, the fifth transistor T5 is turned on, the second clock signal line LCB inputs high level to the signal output end OUT, the second transistor T2 is turned on, the first clock signal line LCK inputs low level signal to the first node N1, the fourth transistor T4 is turned on, and the first power supply end VGH inputs high level to the signal output end OUT.

[0086] In the second stage t2, the first initialization signal end STV1, the second initialization signal end STV2, and the first clock signal line LCK output high level, and the second clock signal line LCB outputs low level. The second node N2 maintains low level signal, the fifth transistor T5 is turned on, the second clock signal line LCB inputs low level to the signal output end OUT, the second transistor T2 is turned on, the first clock signal line LCK inputs high level to the first node N1, and the fourth transistor T4 is turned off.

[0087] In the third phase t3, the first initialization signal terminal STV1 and the second clock signal line LCB output a high level, while the second initialization signal terminal STV2 and the first clock signal line LCK output a low level. The first transistor T1 is turned on, and the first initialization signal terminal STV1 inputs a high level to the second node N2. Simultaneously, the sixth transistor T6 is turned on, and the first power supply terminal VGH or the second clock signal line LCB inputs a high level to the second node N2. The second transistor T2 and the fifth transistor T5 are turned off, and the third transistor T3 is turned on. The second power supply terminal VGL inputs a low level to the first node N1. The fourth transistor T4 is turned on, and the first power supply terminal VGH inputs a high level to the signal output terminal OUT.

[0088] In the fourth phase t4, the first initialization signal terminal STV1, the second initialization signal terminal STV2, and the first clock signal line LCK output high levels, while the second clock signal line LCB outputs a low level. The second node N2 maintains a high level, the first node N1 maintains a low level, the fourth transistor T4 is turned on, and the first power supply terminal VGH inputs a high level to the signal output terminal OUT.

[0089] like Figure 10 FIG. 1 is a structural diagram of another exemplary embodiment of the shift register unit disclosed in the present invention. Figure 1 The shift register unit shown in FIG. 1 differs in that it may further include a coupling circuit 7 connected between the first clock signal terminal CK and the third node N3. The coupling circuit 7 is configured to couple voltage changes at the first clock signal terminal CK to the third node N3. The first control circuit 5 is also connected to the third node N3. The first control circuit 5 is configured to respond to a signal at the third node N3 to transmit a signal at the second power supply terminal VGL to the first node N1. The coupling circuit 7 may include a third capacitor C3. A first electrode of the third capacitor C3 is connected to the first clock signal terminal CK, and a second electrode is connected to the third node N3.

[0090] Compared to Figure 1 In the shift register unit shown, the first clock signal terminal CK can pull the third node N3 down to a lower potential, thereby fully turning on the third transistor T3. For example, the high level output by the first clock signal terminal CK can be 7V, and the low level output by the first clock signal terminal CK can be -7V. Figure 1 The gate voltage of the third transistor T3 when it is turned on is -7V, and Figure 10 In the shift register unit shown, when the first clock signal terminal CK outputs a high level, the voltage of the third node N3 is 0V. When the first clock signal terminal CK outputs a low level, the voltage of the third node N3 is pulled down to -14V by the coupling circuit 7.

[0091] In this exemplary embodiment, Figure 10The structure of the gate driving circuit formed by the shift register unit shown in Figure 2 may be as shown in Figure 10 The driving method of the shift register unit shown in Figure 1 may be the same as the driving method of the shift register unit shown in

[0092] In other exemplary embodiments, Figure 1 , Figure 4 , Figure 7 , Figure 10 The shift register unit shown in

[0093] It should be noted that the upper shift register unit and the lower shift register unit which are cascaded with each other can be arranged adjacently or not adjacently. For example, as shown in Figure 2 , Figure 4 , Figure 6 , Figure 8 The nth shift register unit and the (n+1)th shift register unit are cascaded, i.e., the upper shift register unit and the lower shift register unit which are cascaded with each other are arranged adjacently, n is a positive integer greater than or equal to 1. It should be understood that in other exemplary embodiments, the nth shift register unit can also be cascaded with the (n+m)th shift register unit, i.e., the upper shift register unit and the lower shift register unit which are cascaded with each other are not arranged adjacently, n and m are positive integers greater than or equal to 1.

[0094] In the present exemplary embodiment, as shown in Figure 2 , Figure 4 , Figure 6 , Figure 8 The gate driving circuit includes two clock signal lines: a first clock signal line LCK and a second clock signal line LCB. It should be understood that in other exemplary embodiments, the gate driving circuit can also include other numbers of clock signal lines, for example, the gate driving circuit can include four clock signal lines, eight clock signal lines, etc.

[0095] Through simulation detection, Figure 1 , Figure 4 , Figure 7 , Figure 10 The threshold voltage of the transistor in the shift register unit shown in Figure 1 , Figure 4 , Figure 7 , Figure 10 The shift register units shown in can normally output shift signals.

[0096] The present exemplary embodiment also provides a display panel, which includes the above-mentioned gate driving circuit. The display panel can be applied to display devices such as mobile phones, tablet computers, televisions, and vehicle-mounted displays.

[0097] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the concepts disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the disclosure being indicated by the following claims.

[0098] It will be understood that the present disclosure is not limited to the precise structures hereinbefore described and illustrated in the drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is indicated by the appended claims, only.

Claims

1. A shift register unit, wherein: The shift register unit includes: a first input circuit connected to a first clock signal terminal, a first node, and a second node, wherein the first input circuit is configured to respond to a signal of the second node to transmit a signal of the first clock signal terminal to the first node; a second input circuit connected to the signal input terminal, the first clock signal terminal, and the second node, the second input circuit being configured to transmit the signal of the signal input terminal to the second node in response to the signal of the first clock signal terminal; a first output circuit connected to the first node, the signal output terminal, and the first power terminal, the first output circuit being configured to respond to a signal from the first node to transmit a signal from the first power terminal to the signal output terminal; a second output circuit connected to the second node, the signal output terminal, and the second clock signal terminal, the second output circuit being configured to respond to a signal of the second node to transmit a signal of the second clock signal terminal to the signal output terminal; The first control circuit is connected to the first node and the second power supply terminal. The first control circuit is used for transmitting the signal of the second power supply terminal to the first node in response to a control signal.

2. The shift register unit according to claim 1, wherein: The shift register unit further includes: The second control circuit is connected to the second node, the first power supply terminal or the second clock signal terminal, and is used to respond to a control signal to transmit the signal of the first power supply terminal or the second clock signal terminal to the second node.

3. The shift register unit according to claim 1 or 2, wherein: The first control circuit is further connected to the first clock signal terminal, and is configured to respond to a signal at the first clock signal terminal to transmit a signal at the second power terminal to the first node.

4. The shift register unit according to claim 1 or 2, wherein: The first control circuit is further connected to a first control signal terminal, and is configured to respond to a signal from the first control signal terminal to transmit a signal from the second power terminal to the first node; The shift register unit is applied to a gate drive circuit, and the gate drive circuit includes a plurality of cascaded shift register units, wherein the signal output end of the upper shift register unit is connected to the signal input end of the lower shift register unit cascaded thereto, and the signal output end of the lower shift register unit is connected to the first control signal end of the upper shift register unit cascaded thereto; The signal input terminal of the first-stage shift register unit is connected to the first initialization signal terminal, and the first control signal terminal of the first-stage shift register unit is connected to the second initialization signal terminal.

5. The shift register unit according to claim 1 or 2, wherein: The shift register unit further includes: a coupling circuit connected between the first clock signal terminal and a third node, the coupling circuit being configured to couple a voltage change of the first clock signal terminal to the third node; The first control circuit is further connected to the third node, and is configured to respond to a signal at the third node to transmit a signal at the second power terminal to the first node.

6. The shift register unit according to claim 2, wherein: The second control circuit is further connected to the second control signal terminal, and the second control circuit is configured to respond to a signal at the second control signal terminal to transmit a signal at the second power supply terminal or the second clock signal terminal to the second node; The shift register unit is applied to a gate drive circuit, which includes a plurality of cascaded shift register units, wherein the signal output end of the upper shift register unit is connected to the signal input end of the lower shift register unit cascaded therewith, and the signal output end of the lower shift register unit is connected to the second control signal end of the upper shift register unit cascaded therewith.

7. The shift register unit according to claim 2, wherein: The first control circuit is further connected to a first control signal terminal, and is configured to respond to a signal from the first control signal terminal to transmit a signal from the second power terminal to the first node; The second control circuit is further connected to the first control signal terminal, and is configured to respond to a signal from the first control signal terminal to transmit a signal from the second power supply terminal or the second clock signal terminal to the second node; The shift register unit is applied to a gate drive circuit, and the gate drive circuit includes a plurality of cascaded shift register units, wherein the signal output end of the upper shift register unit is connected to the signal input end of the lower shift register unit cascaded thereto, and the signal output end of the lower shift register unit is connected to the first control signal end of the upper shift register unit cascaded thereto; The signal input terminal of the first-stage shift register unit is connected to the first initialization signal terminal, and the first control signal terminal of the first-stage shift register unit is connected to the second initialization signal terminal.

8. The shift register unit according to claim 2, wherein: The first input circuit comprises: a second transistor, having a first electrode connected to the first clock signal terminal, a second electrode connected to the first node, and a gate connected to the second node; The second input circuit includes: a first transistor, having a first electrode connected to the signal input terminal, a second electrode connected to the second node, and a gate connected to the first clock signal terminal; The first output circuit includes: a fourth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the signal output terminal, and a gate connected to the first node; a second capacitor, a first electrode of which is connected to the first node, and a second electrode of which is connected to the first power supply terminal; The second output circuit includes: a fifth transistor, having a first electrode connected to the second clock signal terminal, a second electrode connected to the signal output terminal, and a gate connected to the second node; a first capacitor, a first electrode of which is connected to the second node, and a second electrode of which is connected to the signal output terminal; The first control circuit includes: a third transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the first node, and a gate connected to the first control signal terminal or the first clock signal terminal; The second control circuit includes: A sixth transistor has a first electrode connected to the first power supply terminal or the second clock signal terminal, a second electrode connected to the second node, and a gate connected to the second control signal terminal or the first control signal terminal.

9. A gate drive circuit, wherein: The gate driving circuit includes a plurality of shift register units according to any one of claims 1 to 8, and the plurality of shift register units are cascaded.

10. A display panel, wherein: The display panel includes the gate driving circuit according to claim 9.

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