Electronic device

Abstract

An electronic device includes: a processor configured to provide a gradation value; and a display device configured to display an image based on a data voltage, the data voltage being generated based on the gradation value. The display device includes: a data driver for supplying a data voltage to a data output line; a data distributor for coupling the data output lines to the data lines; and a data compensator for compensating the data voltages based on a load difference between the data voltages in adjacent pixel rows.

Description

[0001] This application is a divisional application of patent application entitled "Display device" filed on September 3, 2020, with application number 202010913714.7.

[0002] Cross Reference to Related Applications

[0003] This application claims priority from Korean Patent Application No. 10-2019-0144509 filed on November 12, 2019, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. TECHNICAL FIELD

[0004] The present disclosure relates generally to a display device. BACKGROUND

[0005] As information technology develops, the importance of a display device, which is a medium of connection between a user and information, increases. Accordingly, display devices such as liquid crystal display devices, organic light emitting display devices, and plasma display devices are increasingly used.

[0006] A display device displays an image frame by using a combination of light emitted from a plurality of pixels. A line crosstalk defect in which display quality is deteriorated according to a pattern of an image frame can occur. When the line crosstalk defect occurs, a bright line or a dark line is displayed unexpectedly, and thus, a user can recognize the bright line or the dark line as an error. SUMMARY

[0007] Embodiments provide a display device capable of minimizing a line crosstalk defect when a data distributor is used.

[0008] According to an aspect of the disclosure, there is provided a display apparatus including a data driver configured to provide a first data voltage to a data output line during a first period, provide a second data voltage to the data output line during a second period after the first period, provide a third data voltage to the data output line during a third period after the second period, and provide a fourth data voltage to the data output line during a fourth period after the third period; a data distributor configured to couple the data output line to a first data line during the first period, couple the data output line to a second data line during the second period, couple the data output line to the first data line during the third period, and couple the data output line to the second data line during the fourth period; a first pixel configured to receive a voltage charged in the first data line and the second data line after an initial time of the second period and before an initial time of the third period; a second pixel configured to receive the voltage charged in the first data line and the second data line after the initial time of the fourth period; and a data compensator configured to compensate for the third data voltage and the fourth data voltage based on a first load difference between the first data voltage and the third data voltage and a second load difference between the second data voltage and the fourth data voltage.

[0009] The data compensator can include a first load calculator configured to sequentially output a load value of the first data voltage and a load value of the third data voltage, and a second load calculator configured to sequentially output a load value of the second data voltage and a load value of the fourth data voltage.

[0010] The data compensator can further include a first delay part configured to output the load value of the first data voltage after a predetermined delay time, and a second delay part configured to output the load value of the second data voltage after the predetermined delay time.

[0011] The predetermined delay time can be one horizontal period.

[0012] The data compensator can further include a first load difference calculator configured to output the first load difference based on an output of the first load calculator and an output of the first delay part, and a second load difference calculator configured to output the second load difference based on an output of the second load calculator and an output of the second delay part.

[0013] The data compensator can further include a crosstalk calculator configured to calculate a first crosstalk amount with respect to the third data voltage and a second crosstalk amount with respect to the fourth data voltage based on the first load difference and the second load difference.

[0014] The first crosstalk amount may be a value obtained by adding a first load difference applied with a first weight value and a second load difference applied with a second weight value, and the second crosstalk amount may be a value obtained by adding the first load difference applied with a third weight value and the second load difference applied with a fourth weight value.

[0015] A sign of each of the first weight value, the third weight value, and the fourth weight value may be different from a sign of the second weight value.

[0016] The data compensator may further include a crosstalk compensator configured to compensate the third data voltage based on the first crosstalk amount and to compensate the fourth data voltage based on the second crosstalk amount.

[0017] Each of the first pixel and the second pixel may include a P-type transistor. Each of the first weight value, the third weight value, and the fourth weight value may be a positive number, and the second weight value may be a negative number. The crosstalk compensator may increase the third data voltage as the first crosstalk amount increases, and increase the fourth data voltage as the second crosstalk amount increases.

[0018] The data driver may provide a fifth data voltage to the data output line during a fifth period between the second period and the third period, and provide a sixth data voltage to the data output line during a sixth period after the fourth period. The data distributor may couple the data output line to the third data line during the fifth period, and couple the data output line to the third data line during the sixth period. The first pixel may receive the voltage charged in the first data line, the second data line, and the third data line after the initial moment of the fifth period and before the initial moment of the third period, and the second pixel may receive the voltage charged in the first data line, the second data line, and the third data line after the start of the sixth period.

[0019] The data compensator may compensate for the third data voltage, the fourth data voltage, and the sixth data voltage based on the first load difference, the second load difference, and a third load difference between the fifth data voltage and the sixth data voltage.

[0020] The data compensator may further include a third load calculator configured to sequentially output a load value of the fifth data voltage and a load value of the sixth data voltage.

[0021] The data compensator may further include a third delay part configured to output the load value of the fifth data voltage after a predetermined delay time.

[0022] The data compensator can further include a third load difference calculator configured to output a third load difference based on an output of the third load calculator and an output of the third delay part.

[0023] The data compensator can further include a crosstalk calculator configured to calculate a first crosstalk amount with respect to the third data voltage, a second crosstalk amount with respect to the fourth data voltage, and a third crosstalk amount with respect to the sixth data voltage based on the first load difference, the second load difference, and the third load difference.

[0024] The first crosstalk amount can be a value obtained by adding the first load difference to which a first weight value is applied, the second load difference to which a second weight value is applied, and the third load difference to which a third weight value is applied, the second crosstalk amount can be a value obtained by adding the first load difference to which a fourth weight value is applied, the second load difference to which a fifth weight value is applied, and the third load difference to which a sixth weight value is applied, and the third crosstalk amount can be a value obtained by adding the first load difference to which a seventh weight value is applied, the second load difference to which an eighth weight value is applied, and the third load difference to which a ninth weight value is applied.

[0025] A sign of each of the first weight value, the fourth weight value, the fifth weight value, the seventh weight value, the eighth weight value, and the ninth weight value can be different from a sign of each of the second weight value, the third weight value, and the sixth weight value.

[0026] The data compensator can further include a crosstalk compensator configured to compensate for the third data voltage based on the first crosstalk amount, compensate for the fourth data voltage based on the second crosstalk amount, and compensate for the sixth data voltage based on the third crosstalk amount.

[0027] Each of the first pixel and the second pixel can include a P-type transistor. Each of the first weight value, the fourth weight value, the fifth weight value, the seventh weight value, the eighth weight value, and the ninth weight value can be a positive number, and each of the second weight value, the third weight value, and the sixth weight value can be a negative number. The crosstalk compensator can increase the third data voltage as the first crosstalk amount increases, increase the fourth data voltage as the second crosstalk amount increases, and increase the sixth data voltage as the third crosstalk amount increases. BRIEF DESCRIPTION OF DRAWINGS

[0028] Example embodiments will now be described hereinafter more fully with reference to the accompanying drawings, in which example embodiments can be embodied as various forms, and are not limited to the examples set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0029] In the drawings, the size of some of the elements can be exaggerated and not to scale for illustrative purposes. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between these two elements or one or more intervening elements can also be present. Like reference numerals refer to like elements throughout.

[0030] Figure 1 FIG. 1 is a diagram illustrating a display apparatus according to an embodiment of the present disclosure.

[0031] Figure 2 and Figure 3 FIG. 2 is a diagram illustrating a gray voltage generator according to an embodiment of the present disclosure.

[0032] Figure 4 FIG. 3 is a diagram illustrating a data driver according to an embodiment of the present disclosure.

[0033] Figure 5 and Figure 6 FIG. 4 is a diagram illustrating a data distributor and a pixel according to an embodiment of the present disclosure.

[0034] Figure 7 FIG. 5 is a diagram illustrating a driving method of a display apparatus according to an embodiment of the present disclosure.

[0035] Figure 8 , Figure 9 , Figure 10 and Figure 11 FIG. 6 is a diagram illustrating a line crosstalk defect that can occur when a data distributor is used.

[0036] Figure 12 FIG. 7 is a diagram illustrating a data compensator according to an embodiment of the present disclosure.

[0037] Figure 13 FIG. 8 is a diagram illustrating a data distributor and a pixel according to another embodiment of the present disclosure.

[0038] Figure 14 FIG. 9 is a diagram illustrating a driving method of a display apparatus according to another embodiment of the present disclosure.

[0039] Figure 15 FIG. 10 is a diagram illustrating a data compensator according to another embodiment of the present disclosure.

[0040] Figure 16 FIG. 11 is a diagram illustrating a data distributor and a pixel according to still another embodiment of the present disclosure.

[0041] Figure 17 FIG. 12 is a diagram illustrating a display apparatus according to another embodiment of the present disclosure.

[0042] Figure 18 FIG. 13 is a diagram illustrating a display apparatus according to still another embodiment of the present disclosure.

[0043] Figure 19 is a diagram illustrating a data distributor according to still another embodiment of the disclosure. DETAILED DESCRIPTION

[0044] Hereinafter, exemplary embodiments are described in detail with reference to the accompanying drawings so as to be easily practiced by one of ordinary skill in the art. The disclosure can be implemented in various different forms and is not limited to the exemplary embodiments described herein.

[0045] Portions irrelevant to the description will be omitted for the sake of clarity in describing the disclosure, and throughout the specification, the same or similar constituent elements will be designated by the same reference numerals. Thus, the same reference numerals can be used in different drawings to designate the same or similar elements. The suffix "module" or "part" can be used to designate a component of the disclosure. Use of such a suffix itself is not intended to distinguish a component or a part from another. The suffix "module" or "part" can be used to clearly distinguish a component from another. The suffix "module" or "part" can be used to indicate a minimum unit of an integrated component, or a minimum unit for performing one or more functions. The terms "module" and "part" can be interchangeably used.

[0046] In addition, the size and thickness of each component illustrated in the drawings are arbitrarily shown for the ease of description and the disclosure is not limited thereto. The thickness of several portions and regions is exaggerated for the sake of clarity.

[0047] Figure 1 is a diagram illustrating a display apparatus according to an embodiment of the disclosure.

[0048] Reference Figure 1 The display apparatus 10 according to an embodiment of the disclosure can include a timing controller 11, a data driver 12, a scan driver 13, a pixel 14, a gray voltage generator 15, a data distributor 16, and a data compensator 17.

[0049] The timing controller 11 can receive a gray value and a control signal for each frame from an external processor. The timing controller 11 can convert the gray value into a signal corresponding to the specification of the display apparatus 10. For example, the external processor can provide a red gray value, a green gray value, and a blue gray value with respect to each unit dot. For example, when the pixel 14 has an RGB stripe, the pixel can correspond to the corresponding gray value one-to-one. Accordingly, it can not be necessary to convert the gray value. However, when the pixel 14 has a honeycomb structure, adjacent unit dots share a pixel, and accordingly, the pixel can not correspond to the corresponding gray value one-to-one. Accordingly, it can be necessary to convert the gray value. The converted or unconverted gray value GVs1 can be provided to the data driver 12. In addition, the timing controller 11 can provide a data control signal DCS to the data driver 12. In addition, the timing controller 11 can provide a scan control signal SCS to the scan driver 13.

[0050] The data driver 12 can generate data voltages by using the gray scale values GVs1 and the data control signals DCS and supply the generated data voltages to the data output lines DO1, DO2,.... The data driver 12 can generate the data voltages by performing analog-to-digital conversion on the gray scale values GVs3 compensated by the data compensator 17 using the gray scale voltages DVs provided from the gray scale voltage generator 15.

[0051] For example, the data driver 12 can supply a first data voltage to the data output lines DO1, DO2,... during a first period, supply a second data voltage to the data output lines DO1, DO2,... during a second period after the first period, supply a third data voltage to the data output lines DO1, DO2,... during a third period after the second period, and supply a fourth data voltage to the data output lines DO1, DO2,... during a fourth period after the third period.

[0052] The scan driver 13 can generate scan signals in response to a clock signal, a scan start signal, and the like supplied from the timing controller 11 and supply the generated scan signals to the scan lines SL1, SL2. The scan driver 13 can sequentially supply the scan signals having pulses of an on level to the scan lines SL1, SL2,.... The scan driver 13 can include scan stages configured in the form of a shift register. The scan driver 13 can generate the scan signals in a manner that sequentially transfers the scan start signals in the form of pulses of the on level to a next scan stage under the control of the clock signal. The scan lines SL1, SL2,... can extend in the second direction DR2.

[0053] The pixel 14 can include a plurality of pixels PX disposed in a matrix configuration. Each of the pixels PX can be coupled to a corresponding data line and a corresponding scan line. The pixels PX can include a pixel that emits light of a first color, a pixel that emits light of a second color, and a pixel that emits light of a third color. The first color, the second color, and the third color can be different colors. For example, the first color can be one of red, green, and blue, the second color can be another color that is not the first color among red, green, and blue, and the third color can be another color that is not the first color and the second color among red, green, and blue. In addition, magenta, cyan, and yellow can be used as the first to third colors instead of red, green, and blue. However, for convenience of description, in the present embodiment, a case where red, green, and blue are used as the first, second, and third colors, respectively, is described. Magenta is expressed as a combination of red and blue, cyan is expressed as a combination of green and blue, and yellow is expressed as a combination of red and green.

[0054] The gray scale voltage generator 15 can generate the gray scale voltages DVsbased on the input maximum luminance value DBVI. In the following, a case where a total of 256 gray scales from gray scale 0 (minimum gray scale) to gray scale 255 (maximum gray scale) exist is described as an example for ease of description. However, when a gray scale value has eight or more bits, a larger number of gray scales can exist. The minimum gray scale can be the darkest gray scale, and the maximum gray scale can be the brightest gray scale (e.g., full white).

[0055] The maximum luminance value can be a luminance value of light emitted from a pixel corresponding to the maximum gray scale. For example, the maximum luminance value can be a luminance value of white light generated when a pixel of a first color emits light corresponding to gray scale 255, a pixel of a second color emits light corresponding to gray scale 255, and a pixel of a third color emits light corresponding to gray scale 255. The pixel of the first color, the pixel of the second color, and the pixel of the third color constitute one point. The unit of the luminance value can be nit.

[0056] Accordingly, the pixel PX can display an image frame that is partially (spatially) dark or partially bright, but the maximum luminance of the image frame is limited to the maximum luminance value. The maximum luminance value can be manually set by a user with respect to the operation of the display device 10, or can be automatically set by an algorithm associated with an illuminance sensor, etc. The set maximum luminance value is denoted as the input maximum luminance value DBVI. The gray scale voltage generator 15 can be configured to receive the input maximum luminance value DBVI directly from an external processor, or can be configured to receive the input maximum luminance value DBVI through the timing controller 11.

[0057] The maximum luminance value can vary depending on a product. However, for example, a maximum value of the maximum luminance value can be 1200 nit, and a minimum value of the maximum luminance value can be 4 nit. When the input maximum luminance value DBVI is changed, the gray scale voltage generator 15 can provide different gray scale voltages DVs in response to the same gray scale value, and accordingly, the luminance of emission of the pixel varies.

[0058] The data distributor 16 can selectively couple the data output lines DO1, DO2, …, and the data lines DL1, DL2, DL3, DL4, …, to each other. The number of the data lines DL1, DL2, DL3, DL4, …, can be greater than the number of the data output lines DO1, DO2, …. For example, the number of the data lines DL1, DL2, DL3, DL4, …, can correspond to a multiple of the number of the data output lines DO1, DO2, …. The data distributor 16 can be a kind of de-multiplexer. The data lines DL1, DL2, DL3, DL4, …, can extend in a first direction DR1. The first direction DR1 and the second direction DR2 can be different directions. For example, the first direction DR1 and the second direction DR2 can be orthogonal to each other.

[0059] For example, the ratio of the data output lines DOl, DO2,... to the data lines DLl, DL2, DL3, DL4,... can be 1:2. The data distributor 16 can alternately couple the data output lines DOl, DO2,... to odd-numbered data lines or even-numbered data lines. For example, the data distributor 16 can couple the data output lines DOl, DO2,... to the first data lines DLl, DL3,... during a first time period, couple the data output lines DOl, DO2,... to the second data lines DL2, DL4,... during a second time period, couple the data output lines DOl, DO2,... to the first data lines DLl, DL3,... during a third time period, and couple the data output lines DOl, DO2,... to the second data lines DL2, DL4,... during a fourth time period.

[0060] For example, the ratio of the data output lines DOl, DO2,... to the data lines DLl, DL2, DL3, DL4,... can be 1:3. This will be described later with reference to FIG. 6. Figures 13 to 15 The data compensator 17 can generate the gray value GVs3 by compensating the received gray value GVs2 received from the data driver 12. The gray value GVs2 can be a gray value before the line crosstalk defect is compensated for, and the gray value GVs3 can be a gray value after the line crosstalk defect is compensated for.

[0061] The data compensator 17 can generate the gray value GVs3 by compensating the received gray value GVs2 received from the data driver 12. The gray value GVs2 can be a gray value before the line crosstalk defect is compensated for, and the gray value GVs3 can be a gray value after the line crosstalk defect is compensated for.

[0062] In the present embodiment, when the data compensator 17 compensates the received gray value GVs2 as the compensated gray value GVs3, the input maximum luminance value DBVI can be further used. When the gray value GVs2 and the input maximum luminance value DBVI are provided, the data voltage of the corresponding image frame can be obtained, and thus the data compensator 17 can more accurately compensate for the line crosstalk defect. In another embodiment, the data compensator 17 can refer to another value instead of the input maximum luminance value DBVI so that the data voltage of the corresponding image frame is obtained.

[0063] The data compensator 17 can compensate for the gray value GVs2 of the current pixel row by using a load difference between the load value of the previous pixel row and the load value of the current pixel row. The data driver 12 can perform digital-to-analog conversion on the compensated gray value GVs3 so that the data voltage of the current pixel row is also compensated for. In another embodiment, the data compensator 17 can directly compensate for the data voltage of the current pixel row by using a load difference between the load value of the previous pixel row and the load value of the current pixel row.

[0064] A pixel row can mean pixels coupled to the same scan line. That is, a previous pixel row can mean pixels coupled to a previous scan line to which a scan signal having an on level is supplied at a previous time. A current pixel row can mean pixels coupled to a current scan line to which a scan signal having an on level is supplied at a current time. The previous time and the current time can differ from each other by one horizontal period. One horizontal period can be a minimum interval between rising times of scan signals in adjacent scan lines.

[0065] For example, the data compensator 17 can compensate the third data voltage and the fourth data voltage based on a first load difference between the first data voltage and the third data voltage and a second load difference between the second data voltage and the fourth data voltage, respectively.

[0066] Figure 2 and Figure 3 is a diagram illustrating a gray voltage generator according to an embodiment of the disclosure.

[0067] For example, when an image frame includes three primary colors (red, green, and blue), the gray voltage generator 15 needs to provide a gray voltage with respect to each of the three primary colors. The gray voltage generator 15 can include a first gray voltage generator 15R for a first color, a second gray voltage generator (not shown) for a second color, and a third gray voltage generator (not shown) for a third color. Hereinafter, the first gray voltage generator 15R will be described. The second gray voltage generator and the third gray voltage generator can have substantially the same configuration as the first gray voltage generator 15R, and thus, a repetitive description will be omitted.

[0068] Referring to Figure 2 , the first gray voltage generator 15R can include a selection value provider 1511, a gray voltage output part 1512, resistor strings RS1 to RS11, multiplexers MX1 to MX12, and resistors R1 to R10. The first gray voltage generator 15R can generate first gray voltages RV0, RV1, RV2, RV3, RV4, …, RV253, RV254, and RV255.

[0069] The selection value provider 1511 can provide a selection value to the multiplexers MX1 to MX12 in response to an input maximum luminance value DBVI. The selection value according to the input maximum luminance value DBVI can be pre-stored in a memory device (for example, such as a device such as a register in or connected to the selection value provider 1511).

[0070] The resistor string RS1 can generate an intermediate voltage between a first high voltage applied to the first high voltage terminal VH1 and a second low voltage applied to the first low voltage terminal VL1. The multiplexer MX1 ​​can output a reference voltage VT by selecting one of the intermediate voltages provided from the resistor string RS1 according to a selection value. The multiplexer MX2 can output a 255 grayscale voltage RV255 by selecting one of the intermediate voltages provided from the resistor string RS1 according to a selection value.

[0071] The resistor string RS11 may generate an intermediate voltage between the reference voltage VT and the 255 gray voltage RV255. The multiplexer MX12 may output the 203 gray voltage RV203 by selecting one of the intermediate voltages provided from the resistor string RS11 according to a selection value.

[0072] The resistor string RS10 may generate an intermediate voltage between the reference voltage VT and the gray voltage RV203. The multiplexer MX11 may output a gray voltage RV151 by selecting one of the intermediate voltages provided from the resistor string RS10 according to a selection value.

[0073] The resistor string RS9 may generate an intermediate voltage between the reference voltage VT and the gray voltage RV151. The multiplexer MX10 may output the gray voltage RV87 by selecting one of the intermediate voltages provided from the resistor string RS9 according to a selection value.

[0074] The resistor string RS8 may generate an intermediate voltage between the reference voltage VT and the gray voltage RV87. The multiplexer MX9 may output the gray voltage RV51 by selecting one of the intermediate voltages provided from the resistor string RS8 according to a selection value.

[0075] The resistor string RS7 may generate an intermediate voltage between the reference voltage VT and the gray voltage RV51. The multiplexer MX8 may output the gray voltage RV35 by selecting one of the intermediate voltages provided from the resistor string RS7 according to a selection value.

[0076] The resistor string RS6 may generate an intermediate voltage between the reference voltage VT and the 35 gray voltage RV35. The multiplexer MX7 may output the 23 gray voltage RV23 by selecting one of the intermediate voltages provided from the resistor string RS6 according to a selection value.

[0077] The resistor string RS5 may generate an intermediate voltage between the reference voltage VT and the 23 gray voltage RV23. The multiplexer MX6 may output the 11 gray voltage RV11 by selecting one of the intermediate voltages provided from the resistor string RS5 according to a selection value.

[0078] The resistor string RS4 can generate intermediate voltages between the first high voltage and the 11 gradation voltage RV11. The multiplexer MX5 can output the 7 gradation voltage RV7 by selecting one of the intermediate voltages provided from the resistor string RS4 according to a selection value.

[0079] The resistor string RS3 can generate intermediate voltages between the first high voltage and the 7 gradation voltage RV7. The multiplexer MX4 can output the 1 gradation voltage RV1 by selecting one of the intermediate voltages provided from the resistor string RS3 according to a selection value.

[0080] The resistor string RS2 can generate intermediate voltages between the first high voltage and the 1 gradation voltage RV1. The multiplexer MX3 can output the 0 gradation voltage RV0 by selecting one of the intermediate voltages provided from the resistor string RS2 according to a selection value.

[0081] The above-described gradations 0, 1, 7, 11, 23, 35, 51, 87, 151, 203, and 255 can be referred to as reference gradations. In addition, the gradation voltages RV255, RV0, RV1, RV7, RV11, RV23, RV35, RV51, RV87, RV151, and RV203 generated from the multiplexers MX2 to MX12 can be referred to as reference gradation voltages. The number of reference gradations and the number of gradations corresponding to the reference gradations can be differently set depending on products. Hereinafter, for convenience of description, the gradations 0, 1, 7, 11, 23, 35, 51, 87, 151, 203, and 255 are described as reference gradations.

[0082] The gradation voltage output part 1512 can generate the first gradation voltages RV0 to RV255 by dividing the reference gradation voltages RV0, RV1, RV7, RV11, RV23, RV35, RV51, RV87, RV151, RV203, and RV255. For example, the gradation voltage output part 1512 can generate the first gradation voltages RV2 to RV6 by dividing the reference gradation voltages RV1 and RV7.

[0083] Reference Figure 3 FIG. 1 illustrates white light curves WC1, WC2, …, WC(k-1), and WCk outputting luminance with respect to gradation values. Here, k can be an integer greater than 0.

[0084] Maximum luminance values of the white light curves WC1 to WCk can be different from each other. For example, the maximum luminance value (e.g., 4 nits) of the white light curve WC1 can be the lowest, and the maximum luminance value (e.g., 1200 nits) of the white light curve WCk can be the highest.

[0085] To generate white light, it is assumed that pixels PX of all colors receive data voltages having the same gradation.

[0086] exist Figure 3 The dotted points illustrated on the white light curves WC1 to WCk shown in may correspond to selection values ​​pre-stored in the selection value provider 1511 described above. A more accurate white light curve may be directly represented as the number of selection values ​​increases. However, in order to increase the number of selection values, physical devices such as multiplexers, registers, etc. corresponding to the increased number of selection values ​​are further required, and therefore there are limitations. Therefore, only selection values ​​regarding the above-mentioned reference gray voltages may be pre-stored and used, and other gray voltages may be generated by dividing the reference gray voltages. In addition, for the same reason, selection values ​​regarding some maximum brightness values ​​(e.g., reference maximum brightness values) between 4 nits and 1200 nits may be pre-stored and used, and other maximum brightness values ​​may be generated by interpolating the selection values.

[0087] The pre-stored selection values ​​can be set for each individual product through multiple-time programming (MTP). That is, the selection values ​​can be set and stored through experimental values ​​obtained through repeated measurements to find the conditions under which white light with desired brightness can be emitted relative to the grayscale value.

[0088] Figure 4 is a diagram illustrating a data driver according to an embodiment of the present disclosure.

[0089] refer to Figure 4 , the data driver 12 according to an embodiment of the present disclosure may include a shift register SHR, a sampling latch SLU, a first holding latch HLU1 , a second holding latch HLU2 , a digital-to-analog converter DAU, and a buffer BFU.

[0090] The data control signal DCS received from the timing controller 11 may include a source shift clock SSC, a source start pulse SSP, source output enable signals SOE1 and SOE2 , and the like.

[0091] The shift register SHR may sequentially generate sampling signals while shifting a source start pulse SSP in response to a source shift clock SSC.

[0092] The sampling latches SLU may sequentially receive gray values ​​GVs1 for an image frame from the timing controller 11. The sampling latches SLU may store the gray values ​​GVs1 sequentially provided from the timing controller 11 in corresponding sampling latches in response to sampling signals sequentially supplied from the shift register SHR.

[0093] The first hold latch HLU1 can receive and store the gray value GVs1 stored in the sample latch in response to the first source output enable signal SOE1 being input. The data compensator 17 can receive the gray value GVs2 output from the first hold latch HLU1 and the input maximum luminance value DBVI output from the timing controller 11, and output a compensated gray value GVs3.

[0094] The second hold latch HLU2 can store the compensated gray value GVs3 output from the data compensator 17 in response to the second source output enable signal SOE2 being input.

[0095] The digital-to-analog converter can perform analog-to-digital conversion on the gray value GVs3 compensated by the data compensator 17 by using the gray voltage DVs provided from the gray voltage generator 15.

[0096] Each of the buffers BFU can receive the output of the digital-to-analog converter DAU as a data voltage, and apply the data voltage to the corresponding data output line. For example, each of the buffers BFU can be an operational amplifier. Each of the buffers BFU can be a voltage follower to apply the output of the digital-to-analog converter as a data voltage to the corresponding data output line.

[0097] Figure 5 and Figure 6 is a diagram illustrating a data distributor and a pixel according to an embodiment of the disclosure.

[0098] Referring to Figure 5 , the data distributor 16 can include first transistors M11, M12, … connected to odd-numbered data lines and second transistors M21, M22, … connected to even-numbered data lines. The gate electrodes of the first transistors M11 and M12 can be coupled to a first control line CL1, the first electrodes of the first transistors M11 and M12 can be coupled to data output lines DO1 and DO2, respectively, and the second electrodes of the first transistors M11 and M12 can be coupled to first data lines (odd-numbered data lines: DL1, DL3, …), respectively. The gate electrodes of the second transistors M21 and M22 can be coupled to a second control line CL2, the first electrodes of the second transistors M21 and M22 can be coupled to data output lines DO1 and DO2, respectively, and the second electrodes of the second transistors M21 and M22 can be coupled to second data lines (even-numbered data lines: DL2, DL4, …), respectively. For example, the data distributor 16 can be a demultiplexer having an input-to-output ratio of 1:2.

[0099] The on-periods of the first transistors M11 and M12 and the on-periods of the second transistors M21 and M22 can not overlap with each other. The timing controller 11 can sequentially supply the control signals having the on-levels to the first control line CL1 and the second control line CL2 so that the first transistors M11 and M12 and the second transistors M21 and M22 are sequentially turned on.

[0100] For example, the number of the first transistors M11 and M12 and the number of the second transistors M21 and M22 can be the same. In addition, the number of the first data lines DL1, DL3,... (odd-numbered data lines) and the number of the second data lines DL2, DL4,... (even-numbered data lines) can be the same. The first data lines DL1 and DL3 and the second data lines DL2 and DL4 can be alternately arranged.

[0101] For example, the pixel 14 can include a plurality of pixels PX1, PX2, PX3, PX4, PX5, PX6, PX7, and PX8 arranged in a honeycomb structure. The first pixels PX1, PX2, PX5, and PX6 can be coupled to the first scan line SL1. The first pixels PX1, PX2, PX5, and PX6 can be configured so that red, green, blue, and green are sequentially repeated along the extension direction of the first scan line SL1. The first pixels PX1, PX2, PX5, and PX6 can be coupled to different data lines DL1, DL2, DL3, and DL4.

[0102] In addition, the second pixels PX3, PX4, PX7, and PX8 can be coupled to the second scan line SL2. The second pixels PX3, PX4, PX7, and PX8 can be configured so that blue, green, red, and green are sequentially repeated along the extension direction of the second scan line SL2. The second pixels PX3, PX4, PX7, and PX8 can be coupled to different data lines DL1, DL2, DL3, and DL4.

[0103] The red pixels and the blue pixels can be coupled to the first data line DL1 to be sequentially repeated along the extension direction of the first data line DL1. The green pixels can be coupled to the second data lines DL2 and DL4 along the extension direction of the second data lines DL2 and DL4. The blue pixels and the red pixels can be coupled to the first data line DL3 to be sequentially repeated along the extension direction of the first data line DL3.

[0104] Reference Figure 6 FIG. 13 illustrates an exemplary first pixel PX1. The other pixels PX2 to PX8 can have substantially the same configuration, and thus, a repetitive description will be omitted.

[0105] The gate electrode of the first transistor T1 can be coupled to the second electrode of the storage capacitor Cst, the first electrode of the first transistor T1 can be coupled to the first power supply line ELVDDL, and the second electrode of the first transistor T1 can be coupled to the anode of the light emitting diode LD. The first transistor T1 can be referred to as a driving transistor.

[0106] The gate electrode of the second transistor T2 can be coupled to the first scan line SL1, the first electrode of the second transistor T2 can be coupled to the first data line DL1, and the second electrode of the second transistor T2 can be coupled to the second electrode of the storage capacitor Cst. The second transistor T2 can be referred to as a scan transistor.

[0107] The first electrode of the storage capacitor Cst can be coupled to the first power supply line ELVDDL, and the second electrode of the storage capacitor Cst can be coupled to the gate electrode of the first transistor T1.

[0108] The anode of the light emitting diode LD can be coupled to the second electrode of the first transistor T1, and the cathode of the light emitting diode LD can be coupled to the second power supply line ELVSSL.

[0109] During an emission period of the light emitting diode LD, a first power supply voltage applied to the first power supply line ELVDDL can be higher than a second power supply voltage applied to the second power supply line ELVSSL.

[0110] Although the transistors T1, T2, M11, M12, M21, and M22 are implemented with P-type transistors, a person skilled in the art can replace at least one of the transistors T1, T2, M11, M12, M21, and M22 with an N-type transistor by inverting the phase of a signal.

[0111] Figure 7 FIG. 1 is a diagram illustrating a display apparatus according to an embodiment of the present disclosure.

[0112] First, at time t1a, a first control signal having an on level (low level) can be applied to a first control line CL1. Accordingly, the first transistors M11 and M12 are turned on, the first data output line DO1 and the first data line DL1 are coupled to each other, and the second data output line DO2 and the first data line DL3 are coupled to each other. The data driver 12 can output a first data voltage PXD1 to the first data output line DO1 and output a first data voltage PXD5 to the second data output line DO2. Accordingly, the first data line DL1 can be charged with the first data voltage PXD1, and the first data line DL3 can be charged with the first data voltage PXD5. A period from the time t1a to a time at which a first control signal having an off level is applied can be referred to as a first period.

[0113] Next, at time t2a, the second control signal having the on level can be applied to the second control line CL2. Accordingly, the second transistors M21 and M22 are turned on, the first data output line DO1 and the second data line DL2 are coupled to each other, and the second data output line DO2 and the second data line DL4 are coupled to each other. The second data line DL2 can be charged with the second data voltage PXD2, and the second data line DL4 can be charged with the second data voltage PXD6. A period from the time t2a to the time at which the second control signal having the off level is applied can be referred to as a second period.

[0114] Next, at time t3a, the first scan signal having the on level can be applied to the first scan line SL1. Accordingly, the first pixels PX1, PX2, PX5, and PX6 can receive the data voltages charged in the first data lines DL1 and DL3 and the second data lines DL2 and DL4. In this embodiment, the time t3a can overlap the second period.

[0115] Next, at time t4a, the first control signal having the on level can be applied to the first control line CL1. Accordingly, the first transistors M11 and M12 are turned on, the first data output line DO1 and the first data line DL1 are coupled to each other, and the second data output line DO2 and the first data line DL3 are coupled to each other. The first data line DL1 can be charged with the third data voltage PXD3, and the first data line DL3 can be charged with the third data voltage PXD7. A period from the time t4a to the time at which the first control signal having the off level is applied can be referred to as a third period.

[0116] Next, at time t5a, the second control signal having the on level can be applied to the second control line CL2. Accordingly, the second transistors M21 and M22 are turned on, the first data output line DO1 and the second data line DL2 are coupled to each other, and the second data output line DO2 and the second data line DL4 are coupled to each other. The second data line DL2 can be charged with the fourth data voltage PXD4, and the second data line DL4 can be charged with the fourth data voltage PXD8. A period from the time t5a to the time at which the second control signal having the off level is applied can be referred to as a fourth period.

[0117] Next, at time t6a, the second scan signal having the on level can be applied to the second scan line SL2. Accordingly, the second pixels PX3, PX4, PX7, and PX8 can receive the data voltages charged in the first data lines DL1 and DL3 and the second data lines DL2 and DL4. In this embodiment, the time t6a can overlap the fourth period.

[0118] Figures 8 to 11is a diagram illustrating a line crosstalk defect that can occur when a data compensator is used.

[0119] For example, pixels coupled to the first to (p-1)th scan lines SL(p-1) can receive a data voltage corresponding to 128 gray scale. In the next scan period, some of the pixels coupled to the pth scan line SLp can receive a data voltage corresponding to 128 gray scale, and other pixels can receive a data voltage corresponding to 0 gray scale.

[0120] In an ideal case as shown in Figure 8 , the pixel PXpu coupled to the scan line SLp and the data line DLu can emit light of 128 gray scale. Also, the pixel PXp(u+1) coupled to the scan line SLp and the data line DL(u+1) can emit light of 128 gray scale. For example, the pixel PXpu can be a red pixel or a blue pixel. For example, the pixel PXp(u+1) can be a green pixel. Here, each of p and u is an integer greater than 0.

[0121] However, when data compensation is not performed, the pixel PXp(u+1) emits light of a gray scale higher than 128 gray scale, as shown in Figure 9 , and thus, a bright line of green color can be generated. The gray scale change of the pixel PXpu can be less than the gray scale change of the pixel PXp(u+1). The bright line can be caused by a line crosstalk defect due to a sudden change of the data voltage from 128 gray scale to 0 gray scale of the data lines DLv and DL(v+1). Here, v can be an integer greater than 0.

[0122] For example, pixels coupled to the (q-1)th scan line SL(q-1) can receive a data voltage corresponding to 128 gray scale or a data voltage corresponding to 0 gray scale. In the next scan period, pixels coupled to the qth scan line SLq can all receive a data voltage corresponding to 128 gray scale.

[0123] In an ideal case as shown in Figure 8 , the pixel PXqu coupled to the scan line SLq and the data line DLu can emit light of 128 gray scale. Also, the pixel PXq(u+1) coupled to the scan line SLq and the data line DL(u+1) can emit light of 128 gray scale. Here, q is an integer greater than 0.

[0124] However, when data compensation is not performed, the pixel PXq(u+1) emits light of a gray scale lower than 128 gray scale, as shown in Figure 9The gray scale change of the pixel PXqu can be smaller than that of the pixel PXq(u+1). The dark line can be caused by a line crosstalk defect due to the data voltage of the data lines DLv and DL(v+1) suddenly changing from 0 gray scale to 128 gray scale.

[0125] Referring to Figure 10 and Figure 11 The cause of the line crosstalk defect will be described in detail.

[0126] Referring to Figure 10 The cause of the green bright line generated in the pixel coupled to the p-th scan line SLp after the reception of the data voltage of the pixel coupled to the (p-1)-th scan line SL(p-1) ends will be described.

[0127] First, at time t1b, the first control signal having the on level can be supplied to the first control line CL1. The data voltage applied to the v-th data line DLv can suddenly increase (change from 128 gray scale to 0 gray scale).

[0128] Referring to Figure 11 The parasitic capacitance Cpr can be formed between the first power supply line ELVDDL and the data line DLs. The first power supply line ELVDDL can be commonly coupled to all the pixels PX. Thus, the transient voltage fluctuation of the first power supply line ELVDDL can have an effect on all the data lines DLs.

[0129] When the data voltage of the data line DLv suddenly increases, the first power supply voltage of the first power supply line ELVDDL can transiently increase while the parasitic current flows from the data driver 12 to the first power supply 18. The data voltages of the data lines DLu and DL(u+1) can also transiently increase by the coupling of the parasitic capacitance Cpr.

[0130] The data line DLu can be in a state in which it is coupled to the data output line, and the data line DL(u+1) can be in a floating state in which it is not coupled to the data output line. Thus, the data voltage of the data line DLu can quickly stabilize (decrease) to the voltage V128 corresponding to 128 gray scale. Since the data line DL(u+1) is in the floating state, the wavelength of the data voltage of the data line DL(u+1) can be similar to that of the first power supply voltage.

[0131] The first power supply 18 can be a DC-DC converter that supplies the first power supply voltage to the first power supply line ELVDDL. Since the first power supply 18 includes a feedback circuit, the first power supply 18 can maintain the first power supply voltage to the voltage V1. Thus, the first power supply voltage can stabilize (decrease) to the voltage V1 at time t2b. The sudden change of the first power supply voltage at time t2b can be caused by the first control signal having the off level being supplied.

[0132] At time t2b, the data voltages of the data lines DLu and DL(u+1) can be less than the voltage V128 corresponding to the gray scale 128. This is caused by the increase in the voltage Vcpr charged in the parasitic capacitance Cpr by the parasitic current. The voltage decrease width VD11 of the data line DLu can be greater than the voltage decrease width VD21 of the data line DL(u+1) due to the influence of the data driver 12.

[0133] At time t3b, the second control signal having the on level can be supplied to the second control line CL2. The data voltage applied to the (v+1)th data line DL(v+1) can suddenly increase (change from the 128th gray scale 128 to the 0th gray scale).

[0134] When the data voltage of the data line DL(v+1) rapidly increases, the first power voltage of the first power line ELVDDL can momentarily increase while the parasitic current flows from the data driver 12 to the first power supply 18. The data voltages of the data lines DLu and DL(u+1) can also momentarily increase by the coupling of the parasitic capacitance Cpr.

[0135] The data line DLu can be in a floating state in which it is not coupled to the data output line, and the data line DL(u+1) can be in a state in which it is coupled to the data output line. Accordingly, the data voltage of the data line DL(u+1) can rapidly stabilize (decrease) to the voltage V128 corresponding to the 128th gray scale. Since the data line DLu is in the floating state, the waveform of the data voltage of the data line DLu can be similar to the waveform of the first power voltage.

[0136] Although the second control signal having the off level is supplied, the first power voltage can not rapidly change, unlike at time t2b. This is caused by the supply of the scan signal having the on level to the scan line SLp at time t4b before the second control signal having the off level is supplied. The data lines DLu and DL(u+1) are coupled to the pixels PXpu and PXp(u+1), respectively, by the scan signal having the off level, and thus the first power voltage does not rapidly decrease.

[0137] Accordingly, at time t4b, the data voltage of the data line DLu can be similar to the voltage V128 corresponding to the 128th gray scale. That is, with reference to time t2b, the voltage increase width VD12 at time t4b can be mostly offset by the voltage decrease width VD11.

[0138] On the other hand, with reference to time t2b, the data voltage of the data line DL(u+1) decreases by the voltage decrease width VD22 at time t4b, and thus can become a voltage V4 lower than the voltage V3.

[0139] Accordingly, at time t4b, the pixel PXpu can receive the voltage V128 corresponding to 128 gray scale, and the pixel PXp(u+1) can receive the voltage V4 corresponding to a gray scale higher than 128 gray scale. Accordingly, a green bright line can be generated as the color of the pixel PXp(u+1).

[0140] Figure 12 FIG. 1 is a diagram illustrating a data compensator according to an embodiment of the present disclosure.

[0141] The data compensator 17 according to an embodiment of the present disclosure can include a lookup table 169, a data voltage value extractor 170, a first load calculator 171, a second load calculator 172, a first delay part 173, a second delay part 174, a first load difference calculator 175, a second load difference calculator 176, a crosstalk calculator 177, and a crosstalk compensator 178.

[0142] The data compensator 17 can compensate for the third data voltages PXD3 and PXD7 and the fourth data voltages PXD4 and PXD8 based on a first load difference LDD1 between the first data voltages PXD1 and PXD5 and the third data voltages PXD3 and PXD7 and a second load difference LDD2 between the second data voltages PXD2 and PXD6 and the fourth data voltages PXD4 and PXD8.

[0143] The lookup table 169 can pre-store data voltage values corresponding to an input maximum luminance value and a gray scale value. The lookup table 169 can be a separate memory device, or exist as a part of another memory device.

[0144] The data voltage value extractor 170 can receive the input maximum luminance value DBVI from the timing controller 11 and the gray scale value GVs2 from the data driver 12, and extract the data voltage value VVs2 corresponding to the input maximum luminance value DBVI and the gray scale value GVs2 from the lookup table 169. As described above, the gray scale voltage generator 15 can output various gray scale voltages DVs with respect to each gray scale, for example, the first gray scale voltages RV0, RV1, RV2, RV3, RV4, …, RV253, RV254, and RV255, according to the input maximum luminance value DBVI. Accordingly, in this embodiment, crosstalk is compensated for based on the data voltage value VVs2, so that compensation for crosstalk is performed more accurately than a case in which crosstalk is compensated for based on the gray scale value GVs2.

[0145] The first load calculator 171 can calculate a load value by using some of the data voltage values VVs2. For example, the first load calculator 171 can calculate a load value by adding data voltage values corresponding to data voltages supplied to the first data lines DL1 and DL3 among the data voltage values VVs2.

[0146] Since the data voltage values VVs2 are sequentially supplied in units of pixels, the first load calculator 171 can sequentially calculate and output the load values. Referring to Figure 7 , the first load calculator 171 can first calculate and output the load values of the first data voltages PXD1 and PXD5. Next, the first load calculator 171 can calculate and output the load values of the third data voltages PXD3 and PXD7. That is, the first load calculator 171 can sequentially output the load values of the first data voltages PXD1 and PXD5 and the load values of the third data voltages PXD3 and PXD7.

[0147] The second load calculator 172 can calculate the load values by using some of the data voltage values VVs2. For example, the second load calculator 172 can calculate the load values by adding the data voltage values corresponding to the data voltages supplied to the second data lines DL2 and DL4 among the data voltage values VVs2.

[0148] Since the data voltage values VVs2 are sequentially supplied in units of pixels, the second load calculator 172 can sequentially calculate and output the load values. Referring to Figure 7 , the second load calculator 172 can first calculate and output the load values of the second data voltages PXD2 and PXD6. Next, the second load calculator 172 can calculate and output the load values of the fourth data voltages PXD4 and PXD8. That is, the second load calculator 172 can sequentially output the load values of the second data voltages PXD2 and PXD6 and the load values of the fourth data voltages PXD4 and PXD8.

[0149] In an embodiment, each of the load values output from the first load calculator 171 and the second load calculator 172 can be a most significant bit (MSB) of a value obtained by adding the data voltage values. That is, only some bits corresponding to the MSB containing the largest amount of information are transmitted, so that the capacity (number of bits) of the registers required for the first delay part 173 and the second delay part 174 can be minimized.

[0150] The first delay part 173 can output the load values of the first data voltages PXD1 and PXD5 after a predetermined delay time. For example, the first delay part 173 can be configured as a delay register. The capacity of the register can correspond to the number of bits of the load values. The predetermined delay time can be one horizontal period.

[0151] The second delay part 174 can output load values of the second data voltages PXD2 and PXD6 after a predetermined delay time. For example, the second delay part 174 can be configured as a delay register. The capacity of the register can correspond to the number of bits of the load values. The predetermined delay time can be one horizontal period.

[0152] The first load difference calculator 175 can output a first load difference LDD1 based on the output LD1n of the first load calculator 171 and the output LD1(n-1) of the first delay part 173. For example, the output LD1n of the first load calculator 171 can be load values of the third data voltages PXD3 and PXD7. The output LD1(n-1) of the first delay part 173 can be load values of the first data voltages PXD1 and PXD5. Accordingly, the first load difference calculator 175 can calculate the first load difference LDD1 between the first data voltages PXD1 and PXD5 and the third data voltages PXD3 and PXD7.

[0153] The second load difference calculator 176 can output a second load difference LDD2 based on the output LD2n of the second load calculator 172 and the output LD2(n-1) of the second delay part 174. For example, the output LD2n of the second load calculator 172 can be load values of the fourth data voltages PXD4 and PXD8. The output LD2(n-1) of the second delay part 174 can be load values of the second data voltages PXD2 and PXD6. Accordingly, the second load difference calculator 176 can calculate the second load difference LDD2 between the second data voltages PXD2 and PXD6 and the fourth data voltages PXD4 and PXD8.

[0154] The crosstalk calculator 177 can calculate a first crosstalk amount XT1 with respect to the third data voltages PXD3 and PXD7 and a second crosstalk amount XT2 with respect to the fourth data voltages PXD4 and PXD8 based on the first load difference LDD1 and the second load difference LDD2. For example, the first crosstalk amount XT1 and the second crosstalk amount XT2 can be calculated as shown in Equation 1 below.

[0155] Equation 1

[0156]

[0157] C11 can be a first weight value, C12 can be a second weight value, C21 can be a third weight value, and C22 can be a fourth weight value.

[0158] For example, the first crosstalk amount XT1 may be a value obtained by adding the first load difference LDD1 to which the first weight value C11 is applied and the second load difference LDD2 to which the second weight value C12 is applied. In addition, the second crosstalk amount XT2 may be a value obtained by adding the first load difference LDD1 to which the third weight value C21 is applied and the second load difference LDD2 to which the fourth weight value C22 is applied.

[0159] The sign of each of the first weight value C11, the third weight value C21, and the fourth weight value C22 may be different from the sign of the second weight value C12. For example, each of the first weight value C11, the third weight value C21, and the fourth weight value C22 may be a positive number, and the second weight value C12 may be a negative number. For example, Figure 10 The magnitude and sign of the first weight value C11 are predetermined based on the voltage reduction width VD11 shown in FIG. Figure 10 The voltage increase width VD12 shown in FIG is used to predetermine the size and sign of the second weight value C12, which can be based on Figure 10 The magnitude and sign of the third weight value C21 are predetermined by the voltage reduction width VD21 shown in FIG. Figure 10 The voltage reduction width VD22 shown in FIG2 is used to predetermine the size and sign of the fourth weight value C22.

[0160] The crosstalk compensator 178 may compensate the third data voltages PXD3 and PXD7 based on the first crosstalk amount XT1 and compensate the fourth data voltages PXD4 and PXD8 based on the second crosstalk amount XT2. The grayscale value GVs3 output from the crosstalk compensator 178 may include the compensated third data voltages PXD3 and PXD7 and the compensated fourth data voltages PXD4 and PXD8.

[0161] For example, the crosstalk compensator 178 may increase the third data voltages PXD3 and PXD7 as the first crosstalk amount XT1 increases, and may increase the fourth data voltages PXD4 and PXD8 as the second crosstalk amount increases.

[0162] For example, in Figure 10 In the case shown in , the first crosstalk amount XT1 may be relatively small, and the second crosstalk amount XT2 may be relatively large. Therefore, the crosstalk compensator 178 may suppress the green component of the bright line by increasing the fourth data voltages PXD4 and PXD8.

[0163] Therefore, the display device 10 according to the present disclosure may minimize a line crosstalk defect that may occur when the data distributor 16 is used.

[0164] Figure 13 is a diagram illustrating a data distributor and pixels according to another embodiment of the present disclosure.

[0165] Referring to Figure 13 The data distributor 16' can include first transistors M11' and M12', second transistors M21' and M22', and third transistors M31' and M32'. The gate electrodes of the first transistors M11' and M12' can be coupled to the first control line CL1, the first electrodes of the first transistors M11' and M12' can be coupled to the data output lines DO1 and DO2, and the second electrodes of the first transistors M11' and M12' can be coupled to the first data lines DL1 and DL4. The gate electrodes of the second transistors M21' and M22' can be coupled to the second control line CL2, the first electrodes of the second transistors M21' and M22' can be coupled to the data output lines DO1 and DO2, and the second electrodes of the second transistors M21' and M22' can be coupled to the second data lines DL2 and DL5. The gate electrodes of the third transistors M31' and M32' can be coupled to the third control line CL3, the first electrodes of the third transistors M31' and M32' can be coupled to the data output lines DO1 and DO2, and the second electrodes of the third transistors M31' and M32' can be coupled to the third data lines DL3 and DL6. For example, the data distributor 16' can be a demultiplexer having an input-to-output ratio of 1:3.

[0166] The on-periods of the first transistors M11' and M12', the on-periods of the second transistors M21' and M22', and the on-periods of the third transistors M31' and M32' can not overlap with each other. The timing controller 11 can supply control signals having on-levels to the first control line CL1, the second control line CL2, and the third control line CL3 so that the first transistors M11' and M12', the second transistors M21' and M22', and the third transistors M31' and M32' are sequentially turned on.

[0167] For example, the number of the first transistors M11' and M12', the number of the second transistors M21' and M22', and the number of the third transistors M31' and M32' can be the same. Also, the number of the first data lines DL1 and DL4, the number of the second data lines DL2 and DL5, and the number of the third data lines DL3 and DL6 can be the same. The first data lines DL1 and DL4, the second data lines DL2 and DL5, and the third data lines DL3 and DL6 can be sequentially arranged.

[0168] For example, the pixels 14' can include pixels PX1', PX2', PX3', PX4', PX5', PX6', PX7', PX8', PX9', PX10', PX11', and PX12' arranged in an RGB stripe structure. The first pixels PX1', PX2', PX5', PX7', PX8', and PX11' can be coupled to the first scan line SL1. The first pixels PX1', PX2', PX5', PX7', PX8', and PX11' can be configured such that red, green, and blue are sequentially repeated in an extension direction of the first scan line SL1. The first pixels PX1', PX2', PX5', PX7', PX8', and PX11' can be respectively coupled to different data lines DL1, DL2, DL3, DL4, DL5, and DL6.

[0169] In addition, the second pixels PX3', PX4', PX6', PX9', PX10', and PX12' can be coupled to the second scan line SL2. The second pixels PX3', PX4', PX6', PX9', PX10', and PX12' can be configured such that red, green, and blue are sequentially repeated in an extension direction of the second scan line SL2. The second pixels PX3', PX4', PX6', PX9', PX10', and PX12' can be respectively coupled to different data lines DL1 to DL6.

[0170] The red pixels can be coupled to the first data lines DL1 and DL4 to sequentially repeat in an extension direction of the first data lines DL1 and DL4. The green pixels can be coupled to the second data lines DL2 and DL5 to sequentially repeat in an extension direction of the second data lines DL2 and DL5. The blue pixels can be coupled to the third data lines DL3 and DL6 to sequentially repeat in an extension direction of the third data lines DL3 and DL6.

[0171] The configuration of each of the pixels PX1' to PX12' can be the same as the configuration shown in FIG. 1, and thus, a repeated description will be omitted. Figure 6

[0172] Figure 14 FIG. 1 is a diagram illustrating a driving method of a display apparatus according to an embodiment of the disclosure.

[0173] ​First, at time tc1, the first control signal having an on level (low level) can be applied to the first control line CL1. Accordingly, the first transistors M11' and M12' are turned on, the first data output line DO1 and the first data line DL1 are coupled to each other, and the second data output line DO2 and the first data line DL4 are coupled to each other. The data driver 12' can output the first data voltage PXD1' to the first data output line DO1 and output the first data voltage PXD7' to the second data output line DO2. Accordingly, the first data line DL1 can be charged with the first data voltage PXD1', and the first data line DL4 can be charged with the first data voltage PXD7'. A period from the time tc1 to a time at which the first control signal having an off level is applied can be referred to as a first period.

[0174] Next, at time t2c, the second control signal having an on level can be applied to the second control line CL2. Accordingly, the second transistors M21' and M22' are turned on, the first data output line DO1 and the second data line DL2 are coupled to each other, and the second data output line DO2 and the second data line DL5 are coupled to each other. The second data line DL2 can be charged with the second data voltage PXD2', and the second data line DL5 can be charged with the second data voltage PXD8'. A period from the time t2c to a time at which the second control signal having an off level is applied can be referred to as a second period.

[0175] Next, at time t3c, the third control signal having an on level can be applied to the third control line CL3. Accordingly, the third transistors M31' and M32' are turned on, the first data output line DO1 and the third data line DL3 are coupled to each other, and the second data output line DO2 and the third data line DL6 are coupled to each other. The third data line DL3 can be charged with the fifth data voltage PXD5', and the third data line DL6 can be charged with the fifth data voltage PXD11'. A period from the time t3c to a time at which the third control signal having an off level is applied can be referred to as a fifth period.

[0176] Next, at time t4c, the first scan signal having an on level can be applied to the first scan line SL1. Accordingly, the first pixels PX1', PX2', PX5', PX7', PX8', and PX11' can receive the data voltages charged in the first data lines DL1 and DL4, the second data lines DL2 and DL5, and the third data lines DL3 and DL6, respectively. In this embodiment, the time tc4 can overlap with the fifth period.

[0177] Next, at time t5c, the first control signal having an on level can be applied to the first control line CL1. Accordingly, the first transistors M11' and M12' are turned on, the first data output line DO1 and the first data line DL1 are coupled to each other, and the second data output line DO2 and the first data line DL4 are coupled to each other. The first data line DL1 can be charged with the third data voltage PXD3', and the first data line DL4 can be charged with the third data voltage PXD9'. A period from the time t5c to a time at which the first control signal having an off level is applied can be referred to as a third period.

[0178] Next, at time t6c, the second control signal having an on level can be applied to the second control line CL2. Accordingly, the second transistors M21' and M22' are turned on, the first data output line DO1 and the second data line DL2 are coupled to each other, and the second data output line DO2 and the second data line DL5 are coupled to each other. The second data line DL2 can be charged with the fourth data voltage PXD4', and the second data line DL5 can be charged with the fourth data voltage PXD10'. A period from the time t6c to a time at which the second control signal having an off level is applied can be referred to as a fourth period.

[0179] Next, at time t7c, the third control signal having an on level can be applied to the third control line CL3. Accordingly, the third transistors M31' and M32' are turned on, the first data output line DO1 and the third data line DL3 are coupled to each other, and the second data output line DO2 and the third data line DL6 are coupled to each other. The third data line DL3 can be charged with the sixth data voltage PXD6', and the third data line DL6 can be charged with the sixth data voltage PXD12'. A period from the time t7c to a time at which the third control signal having an off level is applied can be referred to as a sixth period.

[0180] Next, at time t8c, the second scan signal having an on level can be applied to the second scan line SL2. Accordingly, the second pixels PX3', PX4', PX6', PX9', PX10', and PX12' can receive the data voltages charged in the first data lines DL1 and DL4, the second data lines DL2 and DL5, and the third data lines DL3 and DL6. In this embodiment, the time t8c can overlap with the sixth period.

[0181] Figure 15 FIG. 1 is a diagram illustrating a data compensator according to an embodiment of the disclosure.

[0182] The data compensator 17' according to another embodiment of the disclosure can include a look-up table 169, a data voltage value extractor 170, a first load calculator 171, a second load calculator 172, a third load calculator 179, a first delay part 173, a second delay part 174, a third delay part 180, a first load difference calculator 175, a second load difference calculator 176, a third load difference calculator 181, a crosstalk calculator 177', and a crosstalk compensator 178'. Hereinafter, only the parts different from the data compensator 17 shown in FIG. 26 will be mainly described. Figure 12

[0183] The data compensator 17' can compensate for the third data voltages PXD3' and PXD9', the fourth data voltages PXD4' and PXD10', and the sixth data voltages PXD6' and PXD12' based on the first load difference LDD1, the second load difference LDD2, and the third load difference LDD3 between the fifth data voltages PXD5' and PXD11' and the sixth data voltages PXD6' and PXD12'.

[0184] The third load calculator 179 can calculate the load values by using some of the data voltage values VVs2. For example, the third load calculator 179 can calculate the load values by adding the data voltage values corresponding to the data voltages supplied to the third data lines DL3 and DL6 among the data voltage values VVs2.

[0185] Since the data voltage values VVs2 are sequentially supplied in units of pixels, the third load calculator 179 can sequentially calculate and output the load values. Referring to Figure 14 , the third load calculator 179 can calculate and output the load values of the fifth data voltages PXD5' and PXD11'. Next, the third load calculator 179 can calculate and output the load values of the sixth data voltages PXD6' and PXD12'. That is, the third load calculator 179 can sequentially output the load values of the fifth data voltages PXD5' and PXD11' and the load values of the sixth data voltages PXD6' and PXD12'.

[0186] In an embodiment, each of the load values output from the third load calculator 179 can be an MSB of a value obtained by adding the data voltage values. That is, only a bit corresponding to the MSB containing the largest amount of information is transmitted, so that the capacity (number of bits) of the register required for the third delay part 180 can be minimized.

[0187] ​The third delay part 180 can output load values of the fifth data voltages PXD5' and PXD11' after a predetermined delay time. For example, the third delay part 180 can be configured as a delay register. The capacity of the register can correspond to the number of bits of the load values. The predetermined delay time can be one horizontal period.

[0188] The third load difference calculator 181 can output a third load difference LDD3 based on the output LD3n of the third load calculator 179 and the output LD3(n-1) of the third delay part 180. For example, the output LD3n of the third load calculator 179 can be load values of the sixth data voltages PXD6' and PXD12'. The output LD3(n-1) of the third delay part 180 can be load values of the fifth data voltages PXD5' and PXD11'. Accordingly, the third load difference calculator 181 can calculate the third load difference LDD3 between the fifth data voltages PXD5' and PXD11' and the sixth data voltages PXD6' and PXD12'.

[0189] The crosstalk calculator 177' can calculate a first crosstalk amount XT1' with respect to the third data voltages PXD3' and PXD9', a second crosstalk amount XT2' with respect to the fourth data voltages PXD4' and PXD10', and a third crosstalk amount XT3' with respect to the sixth data voltages PXD6' and PXD12' based on the first load difference LDD1, the second load difference LDD2, and the third load difference LDD3. For example, the first crosstalk amount XT1', the second crosstalk amount XT2', and the third crosstalk amount XT3' can be calculated as shown in Equation 2 below.

[0190] Equation 2

[0191]

[0192] D11 can be a first weight value, D12 can be a second weight value, D13 can be a third weight value, D21 can be a fourth weight value, D22 can be a fifth weight value, D23 can be a sixth weight value, D31 can be a seventh weight value, D32 can be an eighth weight value, and D33 can be a ninth weight value.

[0193] For example, the first crosstalk amount XT1' can be a value obtained by adding the first load difference LDD1 to which the first weight value D11 is applied, the second load difference LDD2 to which the second weight value D12 is applied, and the third load difference LDD3 to which the third weight value D13 is applied. The second crosstalk amount XT2' can be a value obtained by adding the first load difference LDD1 to which the fourth weight value D21 is applied, the second load difference LDD2 to which the fifth weight value D22 is applied, and the third load difference LDD3 to which the sixth weight value D23 is applied. The third crosstalk amount XT3' can be a value obtained by adding the first load difference LDD1 to which the seventh weight value D31 is applied, the second load difference LDD2 to which the eighth weight value D32 is applied, and the third load difference LDD3 to which the ninth weight value D33 is applied.

[0194] Here, the sign of each of the first weight value D11, the fourth weight value D21, the fifth weight value D22, the seventh weight value D31, the eighth weight value D32, and the ninth weight value D33 can be different from the sign of each of the second weight value D12, the third weight value D13, and the sixth weight value D23. For example, each of the first weight value D11, the fourth weight value D21, the fifth weight value D22, the seventh weight value D31, the eighth weight value D32, and the ninth weight value D33 can be a positive number. Each of the second weight value D12, the third weight value D13, and the sixth weight value D23 can be a negative number. As described with reference to FIG. 6, the size and the sign of each of the weight values can be determined in advance by considering the voltage decrease width and the voltage increase width. Figure 10

[0195] The crosstalk compensator 178' can compensate for the third data voltages PXD3' and PXD9' based on the first crosstalk amount XT1', compensate for the fourth data voltages PXD4' and PXD10' based on the second crosstalk amount XT2', and compensate for the sixth data voltages PXD6' and PXD12' based on the third crosstalk amount XT3'.

[0196] The gray value GVs3' output from the crosstalk compensator 178' can include the compensated third data voltages PXD3' and PXD9', the compensated fourth data voltages PXD4' and PXD10', and the compensated sixth data voltages PXD6' and PXD12'.

[0197] For example, the crosstalk compensator 178' can increase the third data voltages PXD3' and PXD9' as the first crosstalk amount XT1' increases, increase the fourth data voltages PXD4' and PXD10' as the second crosstalk amount XT2' increases, and increase the sixth data voltages PXD6' and PXD12' as the third crosstalk amount XT3' increases.

[0198] ​Accordingly, the display apparatus 10 according to the disclosure can minimize a line crosstalk defect that can occur when the data distributor 16' is used.

[0199] Figure 16 FIG. 10 is a diagram illustrating a data distributor and a pixel according to yet another embodiment of the disclosure.

[0200] Referring to Figure 16 FIG. 11 illustrates a data driver 12'', a data distributor 16'', and a pixel 14' according to yet another embodiment of the disclosure. The structure of the pixel 14' can be an RGB stripe structure, and Figure 13 as the pixel 14' shown in FIG. 9.

[0201] The data distributor 16'' can include first transistors M11'', M12'', and M13'' and second transistors M21'', M22'', and M23''. The gate electrodes of the first transistors M11'', M12'', and M13'' can be coupled to a first control line CL1, the first electrodes of the first transistors M11'', M12'', and M13'' can be coupled to a data output line DO1, and the second electrodes of the first transistors M11'', M12'', and M13'' can be coupled to first data lines DL1, DL2, and DL3, respectively. The gate electrodes of the second transistors M21'', M22'', and M23'' can be coupled to a second control line CL2, the first electrodes of the second transistors M21'', M22'', and M23'' can be coupled to a data output line DO2, and the second electrodes of the second transistors M21'', M22'', and M23'' can be coupled to second data lines DL4, DL5, and DL6, respectively. For example, the data distributor 16'' can be a demultiplexer having an input-to-output ratio of 1:3.

[0202] The on-periods of the first transistors M11'', M12'', and M13'' and the on-periods of the second transistors M21'', M22'', and M23'' can not overlap with each other. The timing controller 11 can sequentially provide the control signals having the on level to the first control line CL1 and the second control line CL2 so that the first transistors M11'', M12'', and M13'' and the second transistors M21'', M22'', and M23'' are sequentially turned on.

[0203] For example, the number of the first transistors M11'', M12'', and M13'' and the number of the second transistors M21'', M22'', and M23'' can be the same. In addition, the number of the first data lines DL1, DL2, and DL3 and the number of the second data lines DL4, DL5, and DL6 can be the same.

[0204] The first data lines DL1, DL2, and DL3 corresponding to the first transistors M11", M12", and M13" can be arranged continuously, and next, the second data lines DL4, DL5, and DL6 corresponding to the second transistors M21", M22", and M23" can be arranged continuously.

[0205] Figure 16 The data distributor 16" and the pixel 14' shown in FIG. 10A can be driven using the same method as the method shown in FIG. 9A. Figure 10 The data compensator disclosed in FIG. 10A can be applied to the data distributor 16" and the pixel 14' shown in FIG. 10A. Figure 12 Figure 16

[0206] Figure 17 is a diagram illustrating a display apparatus according to another embodiment of the disclosure.

[0207] Figure 17 The display apparatus 10a shown in FIG. 11A can include a modified timing controller 11a, a data compensator 17a, and a data driver 12a.

[0208] First, the timing controller 11a can provide the gray value GVs2 to the data compensator 17a. Next, and Figure 12 or Figure 15 The data compensator 17a can provide the data driver 12a with the gray value GVs3 in which the line crosstalk defect is compensated for, as with the embodiment shown in FIG. 10A.

[0209] According to this embodiment, unlike the embodiment shown in FIG. 11A, the data driver 12a can include a single hold latch. Accordingly, the configuration of the data driver 12a can be simplified, and the cost of the data driver 12a can be reduced. Figure 4

[0210] Figure 18 is a diagram illustrating a display apparatus according to still another embodiment of the disclosure. Figure 19 is a diagram illustrating a data distributor according to still another embodiment of the disclosure.

[0211] Figure 18 The display apparatus 10b shown in FIG. 12A can include a modified timing controller 11b, a data compensator 17b, and a data driver 12b.

[0212] ​​​First, the timing controller 11b can supply the gray value GVs2 to the data compensator 17b. The data compensator 17b can not include any data voltage value extractor and any look-up table. That is, the first load calculator 171b and the second load calculator 172b can directly use the gray value GVs2. The data compensator 17b can generate a gray value GVs3 whose line crosstalk defect is compensated for by using the gray value GVs2 instead of the data voltage value. Next, the timing controller 11b can supply the gray value GVs1 corresponding to the compensated gray value GVs3 to the data driver 12b.

[0213] According to this embodiment, unlike the embodiment shown in Figure 4 The data driver 12b can include a single holding latch. Therefore, the configuration of the data driver 12b can be simplified, and the cost of the data driver 12b can be reduced.

[0214] Further, according to this embodiment, the data compensator 17b does not include any data voltage value extractor and any look-up table. Therefore, the configuration of the data compensator 17b can be simplified, and the cost of the data compensator 17b can be reduced.

[0215] In the display apparatus according to the present disclosure, when the data distributor is used, the line crosstalk defect can be minimized.

[0216] Example embodiments have been disclosed herein and, although a particular terminology is employed, it is understood that the terms are used in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, characteristics, and / or elements described in connection with a particular embodiment can be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless expressly stated otherwise, as would be apparent to one of ordinary skill in the art at the time of the filing of this application. Accordingly, one skilled in the art will recognize that the disclosure is not limited to the embodiments disclosed, but is intended to cover any changes readily apparent to one of ordinary skill in the art following the principles set forth herein.

Claims

1. An electronic device comprising: a processor configured to provide grayscale values; as well as a display device configured to display an image based on a data voltage generated based on the grayscale value, Wherein, the display device includes: a data driver configured to supply a first data voltage to a data output line during a first period, supply a second data voltage to the data output line during a second period following the first period, supply a third data voltage to the data output line during a third period following the second period, and supply a fourth data voltage to the data output line during a fourth period following the third period; a data distributor configured to couple the data output line to a first data line during the first period, to couple the data output line to a second data line during the second period, to couple the data output line to the first data line during the third period, and to couple the data output line to the second data line during the fourth period; and a data compensator configured to compensate the third data voltage and the fourth data voltage based on a first load difference between the first data voltage and the third data voltage and a second load difference between the second data voltage and the fourth data voltage, and Wherein, the data compensator includes: a first load calculator configured to sequentially output a load value of the first data voltage and a load value of the third data voltage; and A second load calculator is configured to sequentially output a load value of the second data voltage and a load value of the fourth data voltage.

2. The electronic device according to claim 1, in, The display device further comprises: a first pixel configured to receive the voltage charged in the first data line and the second data line after an initial time of the second period and before an initial time of the third period; and The second pixel is configured to receive the voltage charged in the first data line and the second data line after an initial time of the fourth period.

3. The electronic device according to claim 1, wherein The data compensator further comprises: a first delay part configured to output the load value of the first data voltage after a predetermined delay time; and A second delay part is configured to output the load value of the second data voltage after the predetermined delay time.

4. The electronic device according to claim 3, wherein The predetermined delay time is one horizontal period.

5. The electronic device according to claim 3, wherein The data compensator further comprises: a first load difference calculator configured to output the first load difference based on an output of the first load calculator and an output of the first delay section; and A second load difference calculator is configured to output the second load difference based on an output of the second load calculator and an output of the second delay section. The electronic device according to claim 5 , wherein: The data compensator further includes a crosstalk calculator configured to calculate a first crosstalk amount with respect to the third data voltage and a second crosstalk amount with respect to the fourth data voltage based on the first load difference and the second load difference.

7. The electronic device according to claim 6, wherein: The first crosstalk amount is a value obtained by adding the first load difference to which a first weight value is applied and the second load difference to which a second weight value is applied, and The second crosstalk amount is a value obtained by adding the first load difference to which a third weight value is applied and the second load difference to which a fourth weight value is applied.

8. The electronic device according to claim 7, wherein: A sign of each of the first weight value, the third weight value, and the fourth weight value is different from a sign of the second weight value.

9. The electronic device according to claim 8, wherein: The data compensator further includes a crosstalk compensator configured to compensate the third data voltage based on the first crosstalk amount and to compensate the fourth data voltage based on the second crosstalk amount.

10. The electronic device according to claim 9, in, The display device further comprises: a first pixel configured to receive the voltage charged in the first data line and the second data line after an initial time of the second period and before an initial time of the third period; and a second pixel configured to receive a voltage charged in the first data line and the second data line after an initial moment of the fourth period, wherein each of the first pixel and the second pixel includes a P-type transistor, wherein each of the first weight value, the third weight value, and the fourth weight value is a positive number, and the second weight value is a negative number, and The crosstalk compensator increases the third data voltage as the first crosstalk amount increases, and increases the fourth data voltage as the second crosstalk amount increases.

11. The electronic device according to claim 5, in, The display device further comprises: a first pixel configured to receive the voltage charged in the first data line and the second data line after an initial time of the second period and before an initial time of the third period; and a second pixel configured to receive the voltage charged in the first data line and the second data line after an initial moment of the fourth period, wherein the data driver provides a fifth data voltage to the data output line during a fifth period between the second period and the third period, and provides a sixth data voltage to the data output line during a sixth period after the fourth period, wherein the data distributor couples the data output line to a third data line during the fifth period, and couples the data output line to the third data line during the sixth period, The first pixel receives the voltage charged in the first data line, the second data line and the third data line after the initial moment of the fifth period and before the initial moment of the third period, and The second pixel receives the voltage charged in the first data line, the second data line, and the third data line after an initial moment of the sixth period.

12. The electronic device according to claim 11, wherein The data compensator compensates the third data voltage, the fourth data voltage, and the sixth data voltage based on the first load difference, the second load difference, and a third load difference between the fifth data voltage and the sixth data voltage.

13. The electronic device according to claim 12, wherein: The data compensator further includes a third load calculator configured to sequentially output a load value of the fifth data voltage and a load value of the sixth data voltage.

14. The electronic device according to claim 13, wherein: The data compensator further includes a third delay part configured to output the load value of the fifth data voltage after the predetermined delay time.

15. The electronic device according to claim 14, wherein The data compensator further includes a third load difference calculator configured to output the third load difference based on an output of the third load calculator and an output of the third delay section.

16. The electronic device according to claim 15, wherein The data compensator further includes a crosstalk calculator configured to calculate a first crosstalk amount with respect to the third data voltage, a second crosstalk amount with respect to the fourth data voltage, and a third crosstalk amount with respect to the sixth data voltage based on the first load difference, the second load difference, and the third load difference.

17. The electronic device according to claim 16, wherein: the first crosstalk amount being a value obtained by adding the first load difference to which a first weight value is applied, the second load difference to which a second weight value is applied, and the third load difference to which a third weight value is applied, The second crosstalk amount is a value obtained by adding the first load difference to which a fourth weight value is applied, the second load difference to which a fifth weight value is applied, and the third load difference to which a sixth weight value is applied, and The third crosstalk amount is a value obtained by adding the first load difference to which a seventh weight value is applied, the second load difference to which an eighth weight value is applied, and the third load difference to which a ninth weight value is applied.

18. The electronic device according to claim 17, wherein: The sign of each of the first weight value, the fourth weight value, the fifth weight value, the seventh weight value, the eighth weight value, and the ninth weight value is different from the sign of each of the second weight value, the third weight value, and the sixth weight value.

19. The electronic device according to claim 18, wherein The data compensator further includes a crosstalk compensator configured to compensate the third data voltage based on the first crosstalk amount, compensate the fourth data voltage based on the second crosstalk amount, and compensate the sixth data voltage based on the third crosstalk amount.

20. The electronic device according to claim 19, wherein Each of the first pixel and the second pixel includes a P-type transistor, wherein each of the first weight value, the fourth weight value, the fifth weight value, the seventh weight value, the eighth weight value, and the ninth weight value is a positive number, and each of the second weight value, the third weight value, and the sixth weight value is a negative number, and The crosstalk compensator increases the third data voltage as the first crosstalk amount increases, increases the fourth data voltage as the second crosstalk amount increases, and increases the sixth data voltage as the third crosstalk amount increases.

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