Display panel and driving method thereof

Abstract

The invention provides a display panel and a driving method thereof. The display panel comprises a plurality of pixel circuits, the pixel circuit comprises a plurality of light-emitting elements and a driving module which is used for controlling the mode of reference current flowing through the light-emitting elements (the times of flowing through the light-emitting elements in unit duration and the duration of each time) according to received data signals so as to control the light-emitting brightness of the light-emitting elements. And the selection module is electrically connected to the driving module and the corresponding light-emitting elements, and is used for controlling the driving module to form a current path with the light-emitting elements in a time-sharing manner, so that the reference current flows into the light-emitting elements in the time-sharing manner, the increase of the number of pixel circuits is effectively avoided, and the power consumption of a product is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a driving method thereof. BACKGROUND

[0002] Micro LED (Micro Light Emitting Diode) display technology refers to assembling LED pixels of micron level to a driving panel to form a high-density LED display array.

[0003] At present, the driving mode of Micro LED is digital driving, that is, a constant current source is provided for LED pixels, and the light-emitting time length in a frame is controlled to make the LED pixels present corresponding gray-scale brightness, so in full-color display, current sources need to be provided for LED pixels of multiple colors, and when the resolution of the product is improved, the number of pixel circuits required also increases, resulting in an increase in the power consumption of the product. SUMMARY

[0004] Embodiments of the present application provide a display panel and a driving method thereof to improve the problem that the number of pixel circuits increases and the power consumption of the product increases due to the realization of full-color display of the existing Micro LED product.

[0005] Embodiments of the present application provide a display panel, which comprises a plurality of pixel circuits, and each pixel circuit comprises:

[0006] a plurality of light-emitting elements;

[0007] a driving module electrically connected to the plurality of light-emitting elements, configured to control the number of times of the reference current flowing through the light-emitting elements in a unit time length and the time length of each time of the reference current flowing through the light-emitting elements according to a received data signal, so as to control the light-emitting brightness of the light-emitting elements;

[0008] a selection module electrically connected to the driving module and the corresponding plurality of light-emitting elements, configured to control the driving module to form a current path between the driving module and the plurality of light-emitting elements in time, so that the reference current flows into the plurality of light-emitting elements in time.

[0009] Embodiments of the present application also provide a driving method of a display panel, wherein the display panel comprises a plurality of pixel circuits, and each pixel circuit comprises a plurality of light-emitting elements, a driving module, and a selection module electrically connected to the driving module and the corresponding plurality of light-emitting elements.

[0010] The driving method of the display panel comprises:

[0011] The driving module controls the frequency of the reference current flowing through the light emitting element according to the received data signal, so as to control the light emitting brightness of the light emitting element.

[0012] The selection module controls the driving module to form a current path between the driving module and the light emitting elements in time, so as to make the reference current flow into the light emitting elements in time.

[0013] The present application provides a display panel and a driving method thereof. The pixel circuit in the display panel comprises a plurality of light emitting elements and a driving module, and the driving module is used for controlling the frequency of the reference current flowing through the light emitting element according to the received data signal, so as to control the light emitting brightness of the light emitting element. The pixel circuit further comprises a selection module electrically connected to the driving module and the corresponding plurality of light emitting elements, and the selection module is used for controlling the driving module to form a current path between the driving module and the light emitting elements in time, so as to make the reference current flow into the light emitting elements in time. Thus, the plurality of light emitting elements are driven by a single pixel circuit, and the number of pixel circuits is effectively avoided from increasing, which is beneficial to reduce the power consumption of the product. BRIEF DESCRIPTION OF DRAWINGS

[0014] The present application will be further described below with reference to the drawings. It should be noted that the drawings in the following description are only used to explain some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of the drawings.

[0015] Figure 1 The architecture diagram of the display panel provided for the embodiments of the present application.

[0016] Figure 2 And Figure 3 The circuit diagram of the sub-pixel provided for the embodiments of the present application.

[0017] Figure 4 And Figure 5 The timing diagram of part of nodes in the sub-pixel provided for the embodiments of the present application.

[0018] Figure 6 The division schematic diagram of each sub-frame provided for the embodiments of the present application.

[0019] Figure 7 The flow chart of the driving method of the display panel provided for the embodiments of the present application. DETAILED DESCRIPTION

[0020] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments of the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0021] The terms "first", "second" in the present application are used to distinguish different objects, rather than to describe a specific sequence. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or modules is not limited to the listed steps or modules, but can optionally include steps or modules not listed, or can optionally include other steps or modules inherent to the process, method, product or device.

[0022] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearance of the phrase in various places in the specification does not necessarily all refer to the same embodiment, nor does it necessarily refer to a separate or alternative embodiment. It is expressly understood that the embodiments described herein can be combined with each other.

[0023] Embodiments of the present application provide a display panel, including but not limited to the following embodiments and combinations between the following embodiments.

[0024] In some embodiments, in combination with Figures 1 to 3 As shown, the display panel 100 includes a plurality of pixels Pi, which at least includes a pixel circuit 20, the pixel circuit 20 includes: a plurality of light emitting elements EL; a driving module 201 electrically connected to a plurality of the light emitting elements EL, for controlling the number of times of the reference current Ir flowing through the light emitting elements EL within a unit time and the time length of each time flowing through the light emitting elements according to the received data signal DP, to control the light emitting brightness of the light emitting elements EL; a selection module 202 electrically connected to the driving module 201 and a plurality of corresponding light emitting elements EL, for controlling the driving module 201 to form a current path between a plurality of the light emitting elements EL in time, so that the reference current Ir flows into a plurality of the light emitting elements EL in time.

[0025] The display panel 100 can be a self-luminous display panel, i.e., the plurality of light emitting elements EL include at least one of a micro light emitting diode or an organic light emitting semiconductor, and the display panel 100 displays a picture by self-luminous of the light emitting element EL in the sub-pixel Pi. The specific type of the light emitting element EL is not limited in the embodiment. Further, when the light emitting element EL is a micro light emitting diode, a high-density LED display array can be formed by assembling the micro light emitting diode in a micron level to the driving panel.

[0026] However, each light emitting element EL can only emit monochromatic light. In full-color display, if pixel circuits corresponding to the LED pixels of multiple colors are provided respectively to drive the LED pixels, the number of pixel circuits will increase, which is not conducive to reducing the power consumption of the product.

[0027] Each pixel Pi can be understood as a part of a film layer corresponding to the light emitting element EL in the pixel circuit 20, in addition to the pixel circuit 20.

[0028] Specifically, as shown in Figure 1 The display panel 100 can further include a gate driving circuit 101 including a plurality of cascaded gate driving units, a timing controller 102, each gate driving unit being electrically connected between the timing controller 102 and a plurality of corresponding pixels Pi, for outputting a gate signal Gate transmitted to the plurality of corresponding pixels Pi, and at least one source driver 103, each source driver 103 being electrically connected between the timing controller 102 and a plurality of corresponding pixels Pi, for outputting the above-mentioned data signal DP transmitted to a plurality of corresponding pixel circuits 20. The display panel 100 can include a panel body 10 and a driving chip electrically connected, the panel body 10 has the above-mentioned gate driving circuit 101 and a plurality of sub-pixels Pi disposed on a substrate thereof, and the driving chip can include the timing controller 102 and the source driver 103.

[0029] As shown in Figure 1 The gate driving unit can output a corresponding gate signal Gate according to a first control signal provided by the timing controller 102, and a plurality of gate pulses in the plurality of gate signals Gate for opening a plurality of rows of sub-pixels Pi can be arranged in time sequence on a time axis to sequentially open the plurality of rows of sub-pixels Pi.

[0030] The source driver 103 can generate a plurality of data signals DP output to the plurality of columns of sub-pixels Pi through the plurality of data lines according to the second control signal provided by the timing controller 102, each data signal DP can include a plurality of unit data signals corresponding to the plurality of sub-pixels Pi in the same column, and when each row of sub-pixels Pi is turned on, the plurality of data lines respectively receive a plurality of unit data signals of the plurality of sub-pixels Pi in the same row, so that the plurality of unit data signals act on the plurality of sub-pixels Pi in the same row, to realize the light emission of a light emitting element EL in each of the plurality of sub-pixels Pi in the same row. In this way, the light emitting elements EL of all rows can be controlled to emit light in turn to present a complete picture.

[0031] As can be understood, as shown in Figure 2 and Figure 3 each pixel Pi in the embodiment includes a pixel circuit 20 and a plurality of light emitting elements EL, so that the plurality of light emitting elements EL share the same pixel circuit 20, rather than setting a separate pixel circuit 20 for each light emitting element EL. In the case where the number of light emitting elements EL is the same, the number of pixel circuits 20 is effectively reduced, which is beneficial to reduce the power consumption of the product.

[0032] Specifically, the driving module 201 in the embodiment can control the number of times the reference current Ir flows through the light emitting element EL within a unit time and the time length of each flow through the light emitting element EL (the time length of different flows through the light emitting element EL can be the same or different) according to the received data signal DP, that is, control the specific way in which the light emitting element EL is acted on by the reference current Ir, thereby controlling the light emission time length of the light emitting element EL, and further controlling the light emission brightness of the light emitting element EL; wherein, a selection module 202 electrically connected to the driving module 201 and the corresponding plurality of light emitting elements EL is further provided, and the selection module 202 can control the driving module 201 to form a current path between the driving module 201 and the plurality of light emitting elements EL in time, that is, the driving module 201 can form a current path between the driving module 201 and one of the plurality of light emitting elements EL in different time periods, so that the above-mentioned reference current Ir acts on the light emitting element EL according to the corresponding specific way (related to the corresponding data signal DP) to realize the light emission control of the light emitting element EL, thereby realizing the driving of the plurality of light emitting elements EL by a single pixel circuit 20.

[0033] In some embodiments, in combination with Figures 2 to 5As shown, one frame F includes a plurality of subframes (then corresponding to include first subframe F1, second subframe F2 and third subframe F3) corresponding to a plurality of the light emitting elements EL (for example, including first light emitting element EL1, second light emitting element EL2 and third light emitting element EL3, of course, the number of light emitting elements EL can also be less than 3 or more than 3) in the same pixel circuit 20, to respectively control the light emission of a plurality of the light emitting elements EL, the data signal DP includes a plurality of sub-data signals (then corresponding to include first sub-data signal DP1, second sub-data signal DP2 and third sub-data signal DP3) corresponding to a plurality of the light emitting elements EL.

[0034] Among them, in each of the subframes (each of the first subframe F1, the second subframe F2 and the third subframe F3), the selection module 202 is used to control the driving module 201 to be in electrical communication with a corresponding one of the light emitting elements EL (a corresponding one of the first light emitting element EL1, the second light emitting element EL2 and the third light emitting element EL3), so that the driving module 201 is used to control the number of times the reference current Ir flows through the corresponding light emitting element EL within a unit time and the time length of each time the reference current Ir flows through the light emitting element EL according to the corresponding sub-data signal (a corresponding one of the first sub-data signal DP1, the second sub-data signal DP2 and the third sub-data signal DP3).

[0035] As can be known from the above discussion, in the first subframe F1 of one frame F, the driving module 201 controls the number of times the reference current Ir flows through the corresponding light emitting element EL within a unit time and the time length of each time the reference current Ir flows through the light emitting element EL according to the first sub-data signal DP1 in the data signal DP, that is, the frequency is determined by the first sub-data signal DP1, thereby controlling the light emitting time of the light emitting element EL (also determined by the first sub-data signal DP1), and further controlling the light emitting brightness of the light emitting element EL (determined by the first sub-data signal DP1); At the same time, the selection module 202 controls the driving module 201 to be in electrical communication with the first light emitting element EL1, so that the reference current Ir acts on the light emitting element EL according to the corresponding specific manner (related to the corresponding sub-data signal), to realize the light emission control of the first light emitting element EL1.

[0036] Similarly, it can be known that in the second subframe F2 of one frame F, the pixel circuit 20 realizes the light emission control of the second light emitting element EL2, and in the third subframe F3 of one frame F, the pixel circuit 20 realizes the light emission control of the third light emitting element EL3.

[0037] In summary, a single pixel circuit 20 can realize the light emission control of a plurality of corresponding light emitting elements EL within one frame F by forming a current path between the pixel circuit 20 and the corresponding light emitting elements EL in different subframes of one frame F.

[0038] In some embodiments, combined Figures 2 to 6 As shown, each of the subframes (each of the first subframe F1, the second subframe F2, and the third subframe F3) includes multiple subfields (for example, including the first subfield S1, the second subfield S2, to the eighth subfield S8), and the subdata signal (a corresponding one of the first subdata signal DP1, the second subdata signal DP2, and the third subdata signal DP3) includes multiple bit data corresponding to the multiple subfields (the corresponding first bit data B1, the second bit data B2, to the eighth bit data B8); within the multiple subfields of each of the subframes (each of the first subfield S1, the second subfield S2, to the eighth subfield S8), the selection module 202 is used to control the driving module 201 to be electrically connected to the corresponding one of the light-emitting elements EL, so that the driving module 201 is used to determine the effective period of time during which the reference current Ir flows through the corresponding light-emitting element EL according to the corresponding multiple bit data.

[0039] Furthermore, the weights of the plurality of bit data in the sub-data signal DP are different, and the driving module 201 is further configured to determine the duration of the effective period during which the reference current Ir flows through the light emitting element EL according to the weight of each bit data.

[0040] Specifically, such as Figure 6 As shown, for example, each sub-data signal includes 8 bits of data arranged in sequence (i.e., the first bit of data B1, the second bit of data B2, to the eighth bit of data B8), the value of each bit of data can be the first value (e.g., 1) or the second value (e.g., 0), and the weight of each bit of data is different; wherein, the value of the bit data is used to control the light-emitting element EL to emit light or be extinguished (i.e., whether the above-mentioned reference current Ir flows through the light-emitting element EL in the sub-field), and the weight of the bit data is used to control the duration of the light-emitting element EL to emit light or the duration of the extinguishing (i.e., the duration of the above-mentioned reference current Ir flowing through or not flowing through the light-emitting element EL in the sub-field), so each sub-data signal can be used to determine the number of times the reference current Ir flows through the corresponding light-emitting element EL in a unit time length and the duration of each flow through the light-emitting element EL.

[0041] It can be considered that the subfield corresponding to the bit data having the first value (eg, 1) includes a corresponding “valid period”, and the weight of the bit data corresponds to the duration of the “valid period”.

[0042] Specifically, if Figure 6As shown, each of the sub-fields (each of the first sub-field S1, the second sub-field S2, and the eighth sub-field S8) in each of the sub-frames can include a sub- blanking period t1 and a sub-light emitting period t2 arranged in sequence. The length of the sub-light emitting period t2 is proportional to the weight of the corresponding bit data. The greater the weight, the longer the length of the sub-light emitting period t2, and vice versa.

[0043] For example, if the selection module 202 has controlled the driving module 201 to be in electrical communication with a corresponding light emitting element EL in a sub-frame, then for each of the sub-fields in the sub-frame, the following analysis is made:

[0044] When the value of the corresponding bit data is the first value (i.e., “1”), the reference current Ir flows through the light emitting element EL to cause it to emit light. The greater the weight of the bit data, the longer the length of time that the light emitting element EL emits light in the sub-field. The smaller the weight of the bit data, the shorter the length of time that the light emitting element EL emits light in the sub-field.

[0045] When the value of the corresponding bit data is the second value (i.e., “0”), the reference current Ir does not flow through the light emitting element EL to cause it to be extinguished. The greater the weight of the bit data, the longer the length of time that the light emitting element EL is extinguished in the sub-field. The smaller the weight of the bit data, the shorter the length of time that the light emitting element EL is extinguished in the sub-field.

[0046] In some embodiments, as shown in Figure 2 and Figure 3 The driving module 201 includes a constant current source unit 2011 for transmitting the reference current Ir, and a driving switch unit 2012 electrically connected between the plurality of light emitting elements EL and the constant current source unit 2011 for controlling the on-off of the current path between the constant current source unit 2011 and the corresponding plurality of light emitting elements EL according to the data signal DP.

[0047] The constant current source unit 2011 can copy the reference current Ir generated by the current mirror and transmit it to the driving switch unit 2012. Meanwhile, the driving switch unit 2012 can control the on-off of the current path between the constant current source unit 2011 and the corresponding light emitting element EL according to the corresponding sub-data signal in the data signal DP to control the effective period and its length of the reference current Ir flowing through the corresponding light emitting element EL in the corresponding sub-frame.

[0048] In some embodiments, as shown in Figure 2 and Figure 3As shown, the driving switch unit 2012 includes: a switch sub-unit 20121 electrically connected between the constant current source unit 2011 and the plurality of light emitting elements EL, for connecting or disconnecting the current path between the constant current source unit 2011 and the plurality of light emitting elements EL; and a storage sub-unit 20122 electrically connected to the switch sub-unit 20121, for controlling the on period of the switch sub-unit 20121 according to the data signal DP, to control the period in which the reference current Ir flows through the plurality of light emitting elements EL.

[0049] That is, in this embodiment, the storage sub-unit 20122 controls the on period of the switch sub-unit 20121 in the corresponding sub-frame according to the data signal DP (or the corresponding sub-data signal), for example, when the switch sub-unit 20121 is on, the current path between the constant current source unit 2011 and the corresponding light emitting element EL is connected, and when the switch sub-unit 20121 is off, the current path between the constant current source unit 2011 and the corresponding light emitting element EL is disconnected, thereby controlling the period (i.e., the period when the switch sub-unit 20121 is on) in which the reference current Ir flows through the corresponding light emitting element EL in the sub-frame.

[0050] In some embodiments, as shown in Figure 2 and Figure 3 The storage sub-unit 20122 includes: a first storage sub-unit 001 for controlling the signal of a second node A2 according to the data signal DP and the signal of a first node A1; and a second storage sub-unit 002 for controlling the signal of the first node A1 according to the inverted data signal DN and the signal of the second node A2, the phase of the inverted data signal DN being opposite to the phase of the data signal DP; wherein at least one of the signal of the first node A1 and the signal of the second node A2 is used to control the on period of the switch sub-unit 20121.

[0051] That is, in this embodiment, by setting the storage sub-unit 20122 to include the first storage sub-unit 001 controlled by the data signal DP and the signal of the first node A1, and the second storage sub-unit 002 controlled by the inverted data signal DN and the signal of the second node A2, the control of the signal of the second node A2 and the signal of the first node A1 can be respectively realized, thereby controlling the on period of the switch sub-unit 20121.

[0052] Specifically, as shown in Figure 2 and Figure 3As shown, the first storage subunit 001 and the second storage subunit 002 each include a data write transistor (data write transistor M11 for the first storage subunit 001 or data write transistor M12 for the second storage subunit 002), a first data storage transistor (first data storage transistor M7 for the first storage subunit 001 or first data storage transistor M8 for the second storage subunit 002), and a second data storage transistor (second data storage transistor M9 for the first storage subunit 001 or second data storage transistor M10 for the second storage subunit 002).

[0053] For the data write transistor M11 of the first storage subunit 001, the gate thereof is electrically connected to a write line for transmitting a write signal WL, the first source / drain thereof is electrically connected to a data line for transmitting the data signal DP, and the second source / drain thereof is electrically connected to the first node A1.

[0054] For the first data storage transistor M7 and the second data storage transistor M9 of the first storage subunit 001, the gates thereof are both electrically connected to the first node A1, the first source / drain of the former is electrically connected to a first voltage line for transmitting a first voltage signal VGH (a constant voltage signal), the first source / drain of the latter is electrically connected to a second voltage line for transmitting a second voltage signal VGL (a constant voltage signal), and the second source / drains thereof are both electrically connected to the second node A2.

[0055] For the data write transistor M12 of the second storage subunit 002, the gate thereof is electrically connected to the write line, the first source / drain thereof is electrically connected to a second data line for transmitting the inverted data signal DN, and the second source / drain thereof is electrically connected to the second node A2.

[0056] For the first data storage transistor M8 and the second data storage transistor M10 of the second storage subunit 002, the gates thereof are both electrically connected to the second node A2, the first source / drain of the former is electrically connected to the first voltage line, the first source / drain of the latter is electrically connected to the second voltage line, and the second source / drains thereof are both electrically connected to the first node A1.

[0057] As can be known from the above discussion, the signal of the first node A1 is controlled by the data write transistor M11 of the first storage subunit 001, the first data storage transistor M8 and the second data storage transistor M10 of the second storage subunit 002, and the signal of the second node A2 is controlled by the data write transistor M12 of the second storage subunit 002, the first data storage transistor M7 and the second data storage transistor M9 of the first storage subunit 001.

[0058] In order to realize that the signal of the first node A1 and the signal of the second node A2 are affected by the first voltage signal VGH and the second voltage signal VGL in time, the first data storage transistor M7 and the second data storage transistor M9 of the first storage subunit 001 can be different from each other in the P-type transistor and the N-type transistor, and the first data storage transistor M8 and the second data storage transistor M10 of the second storage subunit 002 can be different from each other in the N-type transistor and the P-type transistor.

[0059] For the convenience of description, it is assumed that the data write transistor M11 and the second data storage transistor M9 of the first storage subunit 001, the data write transistor M12 and the second data storage transistor M10 of the second storage subunit 002 are all N-type transistors, and the first data storage transistor M7 of the first storage subunit 001 and the first data storage transistor M8 of the second storage subunit 002 are all P-type transistors. The level of the first voltage signal VGH can be greater than the level of the second voltage signal VGL.

[0060] In combination with FIG. 2, Figures 2 to 5 As shown in FIG. 2, the write signal WL is at a corresponding high level in the initial period of each subfield (each of the first subfield S1, the second subfield S2, and the eighth subfield S8) of each subframe F, so that the data write transistor M11 of the first storage subunit 001 is turned on to transmit the corresponding bit data (one of the first value and the second value, for example, 1) in the data signal DP to the first node A1, and the data write transistor M12 of the second storage subunit 002 is turned on to transmit the corresponding bit data (the other of the first value and the second value, for example, 0) in the inverted data signal DN to the second node A2. Then, the first data storage transistor M7 of the first storage subunit 001 is turned off and the second data storage transistor M9 is turned on to transmit the second voltage signal VGL to the second node A2, and the first data storage transistor M8 of the second storage subunit 002 is turned on and the second data storage transistor M10 is turned off to transmit the first voltage signal VGH to the first node A1. Further, the potential of the first node A1 is further increased under the action of the first voltage signal VGH, which increases the on degree of the second data storage transistor M9 of the first storage subunit 001, and the potential of the second node A2 is further decreased under the action of the second voltage signal VGL, which increases the on degree of the first data storage transistor M8 of the second storage subunit 002, thereby improving the stability of the potential of the first node A1 and the potential of the second node A2.

[0061] In some embodiments, as shown in FIG. 3, Figure 2 and Figure 3As shown, the constant current source unit 2011 includes a constant current source transistor M1, a gate of the constant current source transistor M1 is electrically connected to a current control line for transmitting a current control signal VBIAS, a first source-drain end of the constant current source transistor M1 is electrically connected to a third voltage line for transmitting a third voltage signal VDD, and a second source-drain end of the constant current source transistor M1 is electrically connected to the driving switch unit 2012; wherein the current control signal VBIAS is used to control the amplitude of the reference current Ir.

[0062] As can be known from the above, the constant current source unit 2011 can copy the reference current Ir generated by the current mirror and transmit it to the driving switch unit 2012. On the basis of the above, the constant current source unit 2011 in the embodiment can control the amplitude of the reference current Ir according to the current control signal VBIAS, so as to realize the regulation of the amplitude of the reference current Ir.

[0063] Specifically, the current control signal VBIAS can be a voltage signal, and by controlling the potential of the gate of the constant current source transistor M1, the control of the conduction degree of the constant current source transistor M1 can be realized, and then the control of the amplitude of the reference current Ir output by the second source-drain end of the constant current source transistor M1 can be realized.

[0064] In some embodiments, as shown in Figure 2 and Figure 3 As shown, the driving switch unit 2012 includes a first driving switch transistor M2, a gate of the first driving switch transistor M2 is electrically connected to the first node A1 or the second node A2, a first source-drain end of the first driving switch transistor M2 is electrically connected to the constant current source unit 2011, and a second source-drain end of the first driving switch transistor M2 is electrically connected to a corresponding plurality of the light emitting elements EL.

[0065] As can be known from the above discussion about the first storage subunit 001 and the second storage subunit 002, the two can respectively realize the control of the potential of the second node A2 and the potential of the first node A1. In the embodiment, the gate of the first driving switch transistor M2 in the driving switch unit 2012 is electrically connected to the first node A1 or the second node A2, so the signal of the first node A1 or the signal of the second node A2 can control the conduction of the first driving switch transistor M2, so as to control whether a current path is formed between the constant current source transistor M1 and the corresponding plurality of light emitting elements EL.

[0066] For ease of description, the first driving switch transistor M2 is taken as a P-type transistor with its gate electrically connected to the first node A1. As can be seen from the above analysis, in a sub-field, if the value of the corresponding bit data in the data signal DP and the value of the corresponding bit data in the inverted data signal DN are 1 and 0 respectively, the potential of the first node A1 and the potential of the second node A2 are the corresponding high potential and low potential respectively, so the first driving switch transistor M2 in this embodiment is off at this time; on the contrary, if the value of the corresponding bit data in the data signal DP and the value of the corresponding bit data in the inverted data signal DN are 0 and 1 respectively, the first driving switch transistor M2 in this embodiment is on at this time.

[0067] In some embodiments, as shown in Figure 2 and Figure 3 The driving switch unit 2012 further includes a second driving switch transistor M3, the gate of the second driving switch transistor M3 is electrically connected to a switch line for transmitting a switch signal PWM, the first source-drain end of the second driving switch transistor M3 is electrically connected to the constant current source unit 2011, and the second source-drain end of the second driving switch transistor M3 is electrically connected to the corresponding plurality of light emitting elements EL; wherein the gates of the second driving switch transistors M3 in different pixel circuits 20 are all electrically connected to the same switch line, and the switch signal PWM and the corresponding data signal DP are used to control the effective period of the corresponding driving current.

[0068] That is, the second driving switch transistor M3 can be arranged in series with the first driving switch transistor M2, and both are controlled by the switch signal PWM and the data signal DP respectively, thereby jointly controlling whether a current path is formed between the constant current source transistor M1 and the corresponding plurality of light emitting elements EL.

[0069] Specifically, as shown in Figures 2 to 5 The switch signal PWM is at the corresponding high level in the initial period of each sub-frame (each of the first sub-frame F1, the second sub-frame F2 and the third sub-frame F3) of each frame F (located before the corresponding first sub-field S1), so that the second driving switch transistor M3 which is a P-type transistor is off, so that any light emitting element EL which emits light in the previous sub-frame is extinguished; and is at the corresponding low potential after the initial period of the sub-frame, so that the second driving switch transistor M3 is on, and then the first driving switch transistor M2 is controlled by the corresponding sub-data signal in the data signal DP to be on in the corresponding effective period according to the plurality of bit data (including the first bit data B1, the second bit data B2 to the eighth bit data B8) in the plurality of sub-fields (including the first sub-field S1, the second sub-field S2 to the eighth sub-field S8), thereby controlling the light emitting element EL to emit light in the corresponding effective period.

[0070] Of course, in other embodiments, the switch signal PWM can also be switched from a corresponding high level to a corresponding low level within each subfield of each subframe, so that the second drive switch transistor M3 is sequentially turned on multiple times within multiple subfields.

[0071] In some embodiments, in combination with Figures 2 to 5 As shown, the reference current Ir includes multiple sub-reference currents corresponding to multiple light emitting elements EL in the same pixel circuit 20, and the amplitudes of different sub-reference currents are different; in different subframes (for example, the first subframe F1, the second subframe F2 or the third subframe F3), the drive module 201 is configured to control the sub-reference currents with different amplitudes to flow through the corresponding light emitting elements EL according to the corresponding sub-data signals DP.

[0072] That is, the amplitudes of the sub-reference currents of different light emitting elements EL in the same pixel circuit 20 can be set differently according to the characteristic differences or characteristic requirements of the different light emitting elements EL.

[0073] Specifically, in the corresponding subframe, the light emitting efficiency of the light emitting element EL under the driving of the corresponding sub-reference current is greater than the light emitting efficiency under the driving of another sub-reference current; or, in the corresponding subframe, the light emitting brightness of the light emitting element EL under the driving of the corresponding sub-reference current is greater than the light emitting brightness under the driving of another sub-reference current.

[0074] That is, by differentiating the amplitudes of the different sub-reference currents corresponding to different light emitting elements EL, each light emitting element EL can achieve its own higher light emitting efficiency under the driving of the corresponding sub-reference current compared with other sub-reference currents, which is beneficial to realize high-efficiency light emitting of each light emitting element EL.

[0075] Or, by differentiating the amplitudes of the different sub-reference currents corresponding to different light emitting elements EL, each light emitting element EL can achieve higher light emitting brightness under the driving of the corresponding sub-reference current compared with other sub-reference currents, which is beneficial to realize high-brightness light emitting of each light emitting element EL.

[0076] Of course, in other embodiments, the amplitudes of the different sub-reference currents corresponding to different light emitting elements EL can also be differentiated for other purposes, for example, by differentiating the amplitudes of the different sub-reference currents corresponding to different light emitting elements EL to make the chromaticity and brightness of multiple light emitting elements EL meet the required white balance.

[0077] In some embodiments, in combination with Figures 2 to 5As shown, the selection module 202 includes a plurality of selection units 2021, each of which is electrically connected to a corresponding light emitting element EL and configured to control the period of electrical connection between the corresponding light emitting element EL and the driving module 201 according to a corresponding selection signal (e.g., one of the first selection signal G1, the second selection signal G2, and the third selection signal G3).

[0078] That is, each selection signal acts on a corresponding selection unit 2021 to control the period of electrical connection between the corresponding light emitting element EL and the driving module 201, thereby controlling the period of light emission of the light emitting element EL.

[0079] Specifically, as shown in Figure 2 In the same pixel circuit 20, a plurality of light emitting elements EL are connected in series, and the selection unit 2021 is connected in parallel with the corresponding light emitting element EL. That is, each selection unit 2021 can control whether the above-mentioned sub-reference current flows through the light emitting element EL by controlling whether the light emitting element EL is short-circuited.

[0080] Further, as shown in Figure 2 The selection unit 2021 includes a selection transistor (e.g., one of the first selection transistor M4, the second selection transistor M5, and the third selection transistor M6), the gate electrode of which is electrically connected to a selection line for transmitting the selection signal (i.e., a corresponding one of the first selection signal G1, the second selection signal G2, and the third selection signal G3), the first source / drain terminal of which is connected to the anode of the corresponding light emitting element EL, and the second source / drain terminal of which is connected to the cathode of the corresponding light emitting element EL.

[0081] Specifically, when the selection signal (e.g., the first selection signal G1) controls the corresponding selection transistor (i.e., the corresponding first selection transistor M4) to be turned on, that is, the selection transistor short-circuits the corresponding light emitting element EL, a current circuit is formed between the corresponding light emitting element EL (i.e., the corresponding first light emitting element EL1) and the driving module 201; and when the selection signal (e.g., the first selection signal G1) controls the corresponding selection transistor (i.e., the corresponding first selection transistor M4) to be turned off, that is, the selection transistor does not short-circuit the corresponding light emitting element EL, a current path is formed between the corresponding light emitting element EL (i.e., the corresponding first light emitting element EL1) and the driving module 201.

[0082] As can be seen from the above discussion, in the pixel circuit 20, Figure 2In the scheme, by connecting the selection transistor in parallel with the corresponding light emitting element EL, whether the corresponding light emitting element EL is short-circuited and whether the corresponding sub reference current acts on the light emitting element EL can be controlled by controlling whether each selection transistor is turned on.

[0083] As shown in Figure 4 As shown in Figure 2 The timing diagram corresponding to the circuit shown in FIG. 6 is shown in FIG. 7, where the first selection transistor M4, the second selection transistor M5 and the third selection transistor M6 are all N-type transistors.

[0084] In the first sub-frame F1, only the second selection signal G2 and the third selection signal G3 are at the corresponding high potential, the second selection transistor M5 and the third selection transistor M6 are both turned on to short-circuit the second light emitting element EL2 and the third light emitting element EL3 respectively, and the current control signal VBIAS is at the corresponding first level V1, so that the constant current source unit 2011 outputs the sub reference current corresponding to the first light emitting element EL1, and the sub reference current only flows through the first light emitting element EL1;

[0085] In the second sub-frame F2, only the first selection signal G1 and the third selection signal G3 are at the corresponding high potential, the first selection transistor M4 and the third selection transistor M6 are both turned on to short-circuit the first light emitting element EL1 and the third light emitting element EL3 respectively, and the current control signal VBIAS is at the corresponding second level V2, so that the constant current source unit 2011 outputs the sub reference current corresponding to the second light emitting element EL2, and the sub reference current only flows through the second light emitting element EL2;

[0086] In the third sub-frame F3, only the first selection signal G1 and the second selection signal G2 are at the corresponding high potential, the first selection transistor M4 and the second selection transistor M5 are both turned on to short-circuit the first light emitting element EL1 and the second light emitting element EL2 respectively, and the current control signal VBIAS is at the corresponding third level V3, so that the constant current source unit 2011 outputs the sub reference current corresponding to the third light emitting element EL3, and the sub reference current only flows through the third light emitting element EL3.

[0087] Specifically, as shown in Figure 3 In the same pixel circuit 20, each selection unit 2021 is connected in series with the corresponding light emitting element EL to form a corresponding series branch, and a plurality of series branches are connected in parallel. That is, each selection unit 2021 can control whether the above-mentioned sub reference current flows through the light emitting element EL by controlling whether the series branch in which the light emitting element EL is located is open-circuited.

[0088] Further, as shown in Figure 2As shown, the selection unit 2021 includes a selection transistor (for example, one of the first selection transistor M4, the second selection transistor M5, and the third selection transistor M6), a gate electrode of the selection transistor is electrically connected to a selection line for transmitting a selection signal (that is, a corresponding one of the first selection signal G1, the second selection signal G2, and the third selection signal G3), one of a first source / drain terminal and a second source / drain terminal of the selection transistor is electrically connected to the driving module 201, and the other is connected to the corresponding light emitting element EL.

[0089] Specifically, when the selection signal (for example, the first selection signal G1) controls the corresponding selection transistor (that is, the corresponding first selection transistor M4) to be turned on, that is, the selection transistor electrically connects the branch in which the corresponding light emitting element EL is located, so that the corresponding light emitting element EL (that is, the corresponding first light emitting element EL1) and the driving module 201 form a current path; and when the selection signal (for example, the first selection signal G1) controls the corresponding selection transistor (that is, the corresponding first selection transistor M4) to be turned off, that is, the selection transistor disconnects the branch in which the corresponding light emitting element EL is located, so that the corresponding light emitting element EL (that is, the corresponding first light emitting element EL1) and the driving module 201 form a current circuit.

[0090] In combination with the above analysis of Figure 2 and Figure 4 , if it is still taken as an example that the first selection transistor M4, the second selection transistor M5, and the third selection transistor M6 are all N-type transistors, as shown in Figure 5 , as shown in Figure 3 , the difference between the corresponding timing diagram of the circuit and Figure 4 is as follows:

[0091] In the first subframe F1, only the first selection signal G1 is a corresponding high potential, the first selection transistor M4 is turned on to electrically connect the series branch in which the first light emitting element EL1 is located, the current control signal VBIAS is a corresponding first level V1, so that the sub-reference current corresponding to the first light emitting element EL1 output by the constant current source unit 2011 only flows through the first light emitting element EL1;

[0092] In the second subframe F2, only the second selection signal G2 is a corresponding high potential, the second selection transistor M5 is turned on to electrically connect the series branch in which the second light emitting element EL2 is located, the current control signal VBIAS is a corresponding second level V2, so that the sub-reference current corresponding to the second light emitting element EL2 output by the constant current source unit 2011 only flows through the second light emitting element EL2;

[0093] In the third sub-frame F3, only the third selection signal G3 is a corresponding high level, the third selection transistor M6 is turned on to electrically connect the series branch in which the third light emitting element EL3 is located, the current control signal VBIAS is a corresponding third level V3, so that the sub-reference current corresponding to the third light emitting element EL3 output by the constant current source unit 2011 only flows through the third light emitting element EL3.

[0094] Embodiments of the present application also provide a driving method of a display panel, wherein the display panel 100 can include a plurality of pixels Pi as described above, each of the pixels Pi includes a pixel circuit 20 and a plurality of light emitting elements EL, the pixel circuit 20 includes a driving module 201 and a selection module 202 electrically connected to the driving module 201 and the plurality of light emitting elements EL corresponding to the driving module 201, and the details can be referred to the related description above.

[0095] As shown in the following figure, Figure 7 the driving method of the display panel includes but is not limited to the following steps:

[0096] S1, controlling, by the driving module, the number of times of the reference current flowing through the light emitting element in a unit time and the time length of each time of the reference current flowing through the light emitting element according to the received data signal, to control the light emitting brightness of the light emitting element;

[0097] As can be known from the above description, the driving module 201 can control the number of times of the reference current Ir flowing through the corresponding light emitting element EL in a unit time and the time length of each time of the reference current Ir flowing through the light emitting element EL according to the received data signal DP, that is, control the specific way of the light emitting element EL being acted on by the reference current Ir, thereby controlling the light emitting time length of the light emitting element EL, and further controlling the light emitting brightness of the light emitting element EL;

[0098] S2, controlling, by the selection module, the driving module to form a current path between the driving module and the plurality of light emitting elements in time, so that the reference current flows into the plurality of light emitting elements in time;

[0099] As can be known from the above description, the selection module 202 can control the driving module 201 to be electrically connected to the plurality of light emitting elements EL in time, so that the driving module 201 can form a current path between the driving module 201 and one of the plurality of light emitting elements EL in different time periods, so that the reference current Ir acts on the light emitting element EL according to the corresponding frequency, to realize the light emitting control of the light emitting element EL, thereby realizing the driving of the plurality of light emitting elements EL by the single pixel circuit 20.

[0100] The display panel and the driving method thereof are described in detail above, and the principles and implementation manners of the present application are described by using specific examples. The above description of the embodiments is only used to help understand the technical solutions of the present application and the core ideas thereof. It should be understood by those skilled in the art that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced equivalently. The modifications or replacements do not change the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: The device comprises a plurality of pixel circuits, wherein the pixel circuits include: a plurality of light-emitting elements; a driving module, electrically connected to the plurality of light-emitting elements, for controlling the number of times a reference current flows through the light-emitting elements and the duration of each flow through the light-emitting elements within a unit time according to a received data signal, so as to control the brightness of the light-emitting elements; The selection module is electrically connected to the driving module and the corresponding plurality of light-emitting elements, and is used to control the driving module to form a current path with the plurality of light-emitting elements in a time-sharing manner, so that the reference current flows into the plurality of light-emitting elements in a time-sharing manner.

2. The display panel according to claim 1, wherein: The driving module includes: a constant current source unit, configured to transmit the reference current; and The driving switch unit is electrically connected between the plurality of light-emitting elements and the constant current source unit, and is used to control the on / off of the current path between the constant current source unit and the corresponding plurality of light-emitting elements according to the data signal.

3. The display panel according to claim 2, wherein: The driving switch unit includes: a switch subunit, electrically connected between the constant current source unit and the plurality of light-emitting elements, for connecting or disconnecting a current path between the constant current source unit and the plurality of light-emitting elements; The storage subunit is electrically connected to the switch subunit and is used to control the conduction period of the switch subunit according to the data signal, so as to control the period during which the reference current flows through the plurality of light-emitting elements.

4. The display panel according to claim 3, wherein: The storage sub-unit includes a first storage sub-unit and a second storage sub-unit, and the first storage sub-unit and the second storage sub-unit each include a data writing transistor, a first data storage transistor and a second data storage transistor; In the first storage subunit: The gate of the data writing transistor is electrically connected to a writing line for transmitting a writing signal, the first source and drain terminals of the data writing transistor are electrically connected to a first data line for transmitting the data signal, and the second source and drain terminals of the data writing transistor are electrically connected to a first node; The gate of the first data storage transistor and the gate of the second data storage transistor are both electrically connected to the first node, the first source and drain terminals of the first data storage transistor are electrically connected to a first voltage line for transmitting a first voltage signal, the first source and drain terminals of the second data storage transistor are electrically connected to a second voltage line for transmitting a second voltage signal, and the second source and drain terminals of the first data storage transistor and the second source and drain terminals of the second data storage transistor are both electrically connected to a second node; In the second storage subunit: The gate of the data writing transistor is electrically connected to the writing line, the first source and drain terminals of the data writing transistor are electrically connected to the second data line for transmitting an inverted data signal, and the second source and drain terminals of the data writing transistor are electrically connected to the second node; The gate of the first data storage transistor and the gate of the second data storage transistor are both electrically connected to the second node, the first source and drain terminals of the first data storage transistor are electrically connected to the first voltage line, the first source and drain terminals of the second data storage transistor are electrically connected to the second voltage line, and the second source and drain terminals of the first data storage transistor and the second source and drain terminals of the second data storage transistor are both electrically connected to the first node; The phase of the inverted data signal is opposite to the phase of the data signal.

5. The display panel according to claim 4, wherein: The constant current source unit includes: a constant current source transistor, wherein the gate of the constant current source transistor is electrically connected to a current control line for transmitting a current control signal, a first source-drain terminal of the constant current source transistor is electrically connected to a third voltage line for transmitting a third voltage signal, and a second source-drain terminal of the constant current source transistor is electrically connected to the drive switch unit; The current control signal is used to control the amplitude of the reference current.

6. The display panel according to claim 4, wherein: The driving switch unit includes: A first driving switch transistor, wherein the gate of the first driving switch transistor is electrically connected to the first node or the second node, the first source and drain terminals of the first driving switch transistor are electrically connected to the constant current source unit, and the second source and drain terminals of the first driving switch transistor are electrically connected to the corresponding plurality of light-emitting elements.

7. The display panel according to claim 6, wherein: The driving switch unit further includes: a second driving switch transistor, wherein a gate of the second driving switch transistor is electrically connected to a switch line for transmitting a switching signal, a first source and drain end of the second driving switch transistor is electrically connected to the constant current source unit, and a second source and drain end of the second driving switch transistor is electrically connected to the corresponding plurality of light-emitting elements; The gates of the second driving switch transistors in different pixel circuits are electrically connected to the same switching line, and the switching signal and the corresponding data signal are used to control the effective period of the corresponding driving current.

8. The display panel according to any one of claims 1 to 7, characterized in that: One frame includes a plurality of sub-frames corresponding to a plurality of the light-emitting elements in the same pixel circuit, and the data signal includes a plurality of sub-data signals corresponding to the plurality of the light-emitting elements; In each of the sub-frames, the selection module is used to control the driving module to be electrically connected to a corresponding light-emitting element, so that the driving module is used to control the frequency of the reference current flowing through the corresponding light-emitting element according to the corresponding sub-data signal.

9. The display panel according to claim 8, wherein: The reference current includes a plurality of sub-reference currents corresponding to a plurality of the light-emitting elements in the same pixel circuit, and the amplitudes of different sub-reference currents are different; In different sub-frames, the driving module is configured to control the sub-reference currents with different amplitudes to flow through the corresponding light-emitting elements according to the corresponding sub-data signals.

10. The display panel according to claim 9, wherein: In the corresponding sub-frame, the luminous efficiency of the light-emitting element when driven by the corresponding sub-reference current is greater than the luminous efficiency when driven by another sub-reference current; Alternatively, in the corresponding sub-frame, the luminance of the light-emitting element when driven by the corresponding sub-reference current is greater than the luminance of the light-emitting element when driven by another sub-reference current.

11. The display panel according to claim 8, wherein Each of the subframes includes a plurality of subfields, and the sub-data signal includes a plurality of bit data corresponding to the plurality of subfields; In the multiple subfields of each subframe, the selection module is used to control the driving module to be electrically connected to the corresponding light-emitting element, so that the driving module is used to determine the effective period of the reference current flowing through the corresponding light-emitting element according to the corresponding multiple bit data.

12. The display panel according to claim 11, wherein: The weights of the plurality of bit data in the sub-data signal are different, and the driving module is further configured to determine the duration of the effective period during which the reference current flows through the corresponding light-emitting element according to the weight of each bit data.

13. The display panel according to any one of claims 1 to 7, characterized in that: The selection module includes: A plurality of selection units, each of which is electrically connected to a corresponding light emitting element, is configured to control a period of electrical connection between the corresponding light emitting element and the driving module according to a corresponding selection signal.

14. The display panel according to claim 13, wherein: The plurality of light emitting elements in the same pixel circuit are connected in series, and the selection unit is connected in parallel to the corresponding light emitting element.

15. The display panel according to claim 14, wherein: The selection unit includes: Select transistors; When the selection signal controls the corresponding selection transistor to be turned on, a current circuit is formed between the corresponding light-emitting element and the driving module; When the selection signal controls the corresponding selection transistor to be turned off, a current path is formed between the corresponding light-emitting element and the driving module.

16. The display panel according to claim 13, wherein: Each selection unit in the same pixel circuit is connected in series with the corresponding light-emitting element to form a corresponding series branch, and a plurality of the series branches are connected in parallel.

17. The display panel according to claim 16, wherein: The selection unit includes: Select transistors; When the selection signal controls the corresponding selection transistor to be turned on, a current path is formed between the corresponding light-emitting element and the driving module; When the selection signal controls the corresponding selection transistor to be turned off, a current circuit is formed between the corresponding light-emitting element and the driving module.

18. The display panel according to any one of claims 1 to 7, characterized in that: The plurality of light-emitting elements include at least one of micro light-emitting diodes and organic light-emitting semiconductors.

19. A method for driving a display panel, characterized in that: The display panel includes a plurality of pixel circuits, each of which includes a plurality of light-emitting elements, a driving module, and a selection module electrically connected to the driving module and the corresponding plurality of light-emitting elements; The driving method of the display panel includes: Controlling, by the driving module, the number of times the reference current flows through the light-emitting element within a unit time and the duration of each flow through the light-emitting element according to the received data signal, so as to control the brightness of the light-emitting element; The selection module controls the driving module to form a current path with the plurality of light-emitting elements in a time-sharing manner, so that the reference current flows into the plurality of light-emitting elements in a time-sharing manner.

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