Display panel and display device

Abstract

The invention provides a display panel and a display device. The gate drive circuit of the display panel comprises a first control module, a first output module, a second output module, a second control module and a compensation module which are electrically connected, the first control module and the second control module are arranged in the first direction, and in the second direction, the distance between the boundary of the side, away from a display area, of the compensation module and the display area is smaller than that of the first control module. The distance between the boundary of one side, far away from the display area, of the first control module or / and the second control module and the display area is smaller; the compensation module for compensating the potential of the first node is arranged between the first control module and the second control module, and the boundary of the side, away from the display area, of the compensation module shrinks inwards relative to the boundary of the first control module or / and the second control module. That is, the newly added compensation module does not increase the size of the gate drive circuit in the second direction, so that the narrow bezel design is realized under the condition that the stability of the control signal output by the gate drive circuit is ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] In the related art, an OLED (Organic Light-Emitting Diode) display panel includes a pixel driving circuit and a gate driving circuit outputting a control signal to the pixel driving circuit. The gate driving circuit is usually composed of a large number of transistors, which occupies a large space in the frame, which is contrary to the narrow frame design of the current display panel.

[0003] The current gate driving circuit reduces the number of transistors to achieve the reduction of the frame, and the reduction of the number of transistors causes the gate potential of the output transistor to fail to reach the preset value, thereby causing the output of the control signal to be abnormal, so that the narrow frame design of the display panel and the stability of the control signal cannot be considered. SUMMARY

[0004] The embodiments of the present application provide a display panel and a display device to solve the technical problem that the narrow frame design of the existing display panel and the stability of the control signal output by the gate driving circuit cannot be considered.

[0005] The embodiments of the present application provide a display panel, which includes a display area and a non-display area arranged on at least one side of the display area, and a gate driving circuit arranged in the non-display area, the gate driving circuit including:

[0006] a first control module;

[0007] a first output module, which is electrically connected to a first node with the first control module;

[0008] a second output module, which is electrically connected to an output end of the first output module;

[0009] a second control module, which is electrically connected to a second node with the second output module, and is electrically connected to the first node with the first output module and the first control module; and

[0010] a compensation module, an output end of which is electrically connected to the first node;

[0011] The first control module and the second control module are arranged along a first direction, and the compensation module is arranged between the first control module and the second control module, and in a second direction, a distance between the compensation module and a side boundary of the display area is smaller than a distance between the first control module or / and the second control module and the side boundary of the display area, and the first direction and the second direction intersect.

[0012] The display device provided by the embodiment of the present application comprises the display panel as described above.

[0013] Other features and advantages of the present application will be described in detail in the following detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0015] In order to more completely understand the present application and its advantages, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.

[0016] FIG. 1 It is a first structure diagram of the display panel of the present application.

[0017] FIG. 2 It is a structure diagram of the pixel driving circuit in the display panel of the present application.

[0018] FIG. 3 It is a second structure diagram of the display panel of the present application.

[0019] FIG. 4 It is a first structure diagram of the gate driving circuit in the display panel of the present application.

[0020] FIG. 5 It is a film layer structure diagram in the display panel of the present application.

[0021] FIG. 6 It is a film layer structure diagram of the first embodiment in the third gate circuit of the present application.

[0022] FIG. 7A It is a film layer structure diagram of the first gate layer in the third gate circuit of the present application. FIG. 6

[0023] It is a film layer structure diagram of the light shielding layer in the third gate circuit of the present application. FIG. 7B FIG. 6 It is a film layer structure diagram of the light shielding layer in the third gate circuit of the present application.​

[0024] FIG. 7C For FIG. 6 The film layer diagram of the first active layer in the embodiment.

[0025] FIG. 7D For FIG. 6 The film layer stack diagram of the first active layer and the first gate layer in the embodiment.

[0026] FIG. 7E For FIG. 6 The film layer stack diagram of the third gate layer in the embodiment.

[0027] FIG. 7F For FIG. 6 The film layer diagram of the second active layer in the embodiment.

[0028] FIG. 7G For FIG. 6 The film layer stack diagram of the fourth gate layer in the embodiment.

[0029] FIG. 7H For FIG. 6 The film layer stack diagram of the first active layer, the second active layer, the first gate layer, the third gate layer and the fourth gate layer in the embodiment.

[0030] FIG. 7I For FIG. 6 The film layer stack diagram of the light shielding layer, the first active layer, the second active layer, the first gate layer, the third gate layer and the fourth gate layer in the embodiment.

[0031] FIG. 7J For FIG. 6 The film layer diagram of the first source-drain layer in the embodiment.

[0032] FIG. 7K For FIG. 6 The film layer stack diagram of the first active layer, the second active layer, the first gate layer, the third gate layer, the fourth gate layer and the first source-drain layer in the embodiment.

[0033] FIG. 7L For FIG. 6 The film layer diagram of the second source-drain layer in the embodiment.

[0034] FIG. 8 The second structure diagram of the gate driving circuit in the display panel of the present application.

[0035] FIG. 9 The film layer structure diagram of the second embodiment in the third gate circuit of the present application.

[0036] FIGS. 10A-10F In turn FIG. 9 The single film layer diagram of the first active layer, the first gate layer, the second active layer, the third gate layer, the first source-drain layer and the second source-drain layer in the embodiment.

[0037] FIG. 11The third embodiment of the third gate circuit in the application is shown in the following film layer structure diagram.

[0038] FIGS. 12A-12F The first active layer, the first gate layer, the second active layer, the third gate layer, the first source-drain layer and the second source-drain layer are shown in the following single layer film layer diagram. FIG. 11

[0039] FIG. 13 The first embodiment of the second gate circuit in the application is shown in the following film layer structure diagram.

[0040] FIGS. 14A-14H The first active layer, the first gate layer, the second active layer, the third gate layer, the first source-drain layer and the second source-drain layer are shown in the following single layer film layer diagram. FIG. 13

[0041] The second embodiment of the second gate circuit in the application is shown in the following film layer structure diagram. FIG. 15

[0042] The first active layer, the first gate layer, the second active layer, the third gate layer, the first source-drain layer and the second source-drain layer are shown in the following single layer film layer diagram. FIGS. 16A-16F FIG. 15 The third embodiment of the second gate circuit in the application is shown in the following film layer structure diagram.

[0043] FIG. 17 The first active layer, the first gate layer, the second active layer, the third gate layer, the first source-drain layer and the second source-drain layer are shown in the following single layer film layer diagram.

[0044] DETAILED DESCRIPTION FIGS. 18A-18F FIG. 17 The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by a person skilled in the art without creative labor fall within the protection scope of the application. Please refer to

[0045] The application provides a display panel 100, which includes a display area AA and a non-display area NA arranged on at least one side of the display area AA. The non-display area NA is provided with a gate drive circuit 300. The gate drive circuit 300 includes a first control module 311, a first output module 312, a second output module 313, a second control module 314 and a compensation module 315 which are electrically connected.

[0046] The application provides a display panel 100, which includes a display area AA and a non-display area NA arranged on at least one side of the display area AA. The non-display area NA is provided with a gate drive circuit 300. The gate drive circuit 300 includes a first control module 311, a first output module 312, a second output module 313, a second control module 314 and a compensation module 315 which are electrically connected. FIGS. 1-18F

[0047] ​​​In the embodiment, the first output module 312 and the first control module 311 are electrically connected to the first node M; the second output module 313 is electrically connected to the output end of the first output module 312; the second control module 314 and the second output module 313 are electrically connected to the second node P, and the second control module 314 and the first output module 312 are electrically connected to the first node M; and the output end of the compensation module 315 is electrically connected to the first node M.

[0048] In the embodiment, the first control module 311 and the second control module 314 are arranged along the first direction X, and the compensation module 315 is arranged between the first control module 311 and the second control module 314. In the second direction Y, the distance between the compensation module 315 and the side boundary of the display area AA away from the display area AA is smaller than the distance between the first control module 311 or / and the second control module 314 and the side boundary of the display area AA away from the display area AA, and the first direction X and the second direction Y intersect.

[0049] In the embodiment, the compensation module 315 for compensating the potential of the first node M is arranged between the first control module 311 and the second control module 314, and the side boundary of the compensation module 315 away from the display area AA is relatively inwardly recessed from the side boundary of the first control module 311 or / and the second control module 314, that is, the newly added compensation module 315 does not increase the size of the gate drive circuit 300 in the second direction Y. In the case of ensuring the stability of the control signal output by the gate drive circuit 300, the narrow frame design is realized.

[0050] Please refer to FIG. 4 , the gate drive circuit 300 further comprises a third control module 316, the control end of the third control module 316 is electrically connected to the first node M, and the output end of the third control module 316 is electrically connected to the second node P.

[0051] Please refer to FIG. 4 , the gate drive circuit 300 further comprises a voltage stabilizing module 317, the input end of the voltage stabilizing module 317 is electrically connected to the first node M, the output end of the voltage stabilizing module 317 and the control end of the first output module 312 are electrically connected to the third node Q, and the voltage stabilizing module 317 is configured to electrically connect the first node M and the third node Q.

[0052] The technical solutions of the present application will be described in combination with specific embodiments.

[0053] Please refer to FIG. 1The display panel 100 includes a display area AA and a non-display area NA arranged adjacent to the display area AA, and a plurality of sub-pixels PL are arranged in the display area AA. Optionally, the non-display area NA surrounds the display area AA, and the display area AA is surrounded by the non-display area NA. The display area AA is an area in the display panel 100 for displaying, and a plurality of display units for displaying are arranged in the display area AA. The non-display area NA can be a frame area of the display panel 100, and functional components for assisting the display units in the display area AA to display can be arranged in the non-display area NA.

[0054] Referring to FIG. 1 A binding terminal 400 is arranged at the lower side of the display area AA, and the binding terminal 400 can be connected with an external circuit. The binding terminal 400 transmits signals input by the external circuit to data lines, so as to drive the display panel 100 to display a picture. For example, the binding terminal 400 can be connected with a chip or a chip on film, and is used to provide power supply and driving signals for the display panel 100.

[0055] In the embodiment, a plurality of light emitting devices LED and pixel driving circuits PC for driving the light emitting devices LED can be arranged in the display area AA in an array. The pixel driving circuit PC can be aTbC, a is greater than or equal to 2, and b is greater than or equal to 1, for example, 6T1C, 7T1C, 8T2C, and the like. Hereinafter, the pixel driving circuit PC of 6T1C is taken as an example for description.

[0056] Referring to FIG. 2 The pixel driving circuit PC can include a switching transistor T2A, a driving transistor T1A, a compensation transistor T3A, a reset transistor T4A, a first light emitting transistor T5A, a second light emitting transistor T6A, and a storage capacitor Cst.

[0057] Referring to FIG. 2The first electrode of the switch transistor T2A is connected to the data signal line Data, the second electrode of the switch transistor T2A is connected to the control node Ba, and the gate of the switch transistor T2A receives the switch control signal Nscan1; the first electrode of the drive transistor T1A is connected to the control node Aa, the second electrode of the drive transistor T1A is connected to the control node Ba, and the gate of the drive transistor T1A is connected to the control node Qa; the first electrode of the compensation transistor T3A is connected to the control node Aa, the second electrode of the compensation transistor T3A is connected to the control node Qa, and the gate of the compensation transistor T3A receives the compensation control signal Nscan2; the first electrode of the reset transistor T4A receives the reset signal Vi, the second electrode of the reset transistor T4A is connected to the control node Ca, and the gate of the reset transistor T4A receives the second light-emitting control signal EM2; the first electrode of the first light-emitting transistor T5A is connected to the high-level source VDD, the second electrode of the first light-emitting transistor T5A is connected to the control node Aa, and the gate of the first light-emitting transistor T5A receives the first light-emitting control signal EM1; the first electrode of the second light-emitting transistor T6A is connected to the control node Ba, the second electrode of the second light-emitting transistor T6A is connected to the control node Ca, and the gate of the second light-emitting transistor T6A receives the second light-emitting control signal EM2; one end of the storage capacitor Cst is connected to the control node Qa, and the other end of the storage capacitor Cst is connected to the control node Ca; the anode of the light-emitting device LED is connected to the control node Ca, and the cathode of the light-emitting device LED is connected to the low-level source VSS.

[0058] In the embodiment, the high-level source VDD is used to provide a constant voltage high level to the pixel driving circuit PC, and the low-level source VSS is used to provide a constant voltage low level to the pixel driving circuit PC.

[0059] In the embodiment, the switch transistor T2A, the drive transistor T1A, the compensation transistor T3A, and the reset transistor T4A can be one of a P-type transistor or an N-type transistor, and the first light-emitting transistor T5A and the second light-emitting transistor T6A can be the other one of a P-type transistor or an N-type transistor; for example, the switch transistor T2A, the drive transistor T1A, the compensation transistor T3A, and the reset transistor T4A of the present application are N-type transistors, and the first light-emitting transistor T5A and the second light-emitting transistor T6A are P-type transistors, that is, the effective level of the switch transistor T2A, the drive transistor T1A, the compensation transistor T3A, and the reset transistor T4A is a high level, and the effective level of the first light-emitting transistor T5A and the second light-emitting transistor T6A is a low level.

[0060] In the embodiment, the first electrode can be one of a source or a drain, and the second electrode can be the other one of a source or a drain.

[0061] In this embodiment, the first light-emitting transistor T5A and the second light-emitting transistor T6A can be composed of at least two series-connected transistors to reduce the leakage current of the first light-emitting transistor T5A and the second light-emitting transistor T6A.

[0062] In this embodiment, the second direction Y is parallel to the scan lines of the display panel 100, and the included angle between the first direction X and the second direction Y is greater than 0° and less than or equal to 90°.

[0063] Referring to FIG. 3 , the gate drive circuit 300 is arranged in the non-display area NA, and the gate drive circuit 300 can be arranged on both sides of the display area AA; the gate drive circuit 300 can include N gate drive units 300a connected in cascade, and the plurality of gate drive units 300a can be arranged along the first direction X. The structure of the gate drive unit 300a can be various, for example, in the structure of FIG. 3 , the gate drive unit 300a can include a plurality of first gate circuits 310 arranged along the first direction X and connected in cascade, a plurality of second gate circuits 320 arranged along the first direction X and connected in cascade, and a plurality of third gate circuits 330 arranged along the first direction X and connected in cascade.

[0064] Referring to FIG. 3 , the first gate circuit 310 is arranged on one side of the display area AA, and a first gate circuit 310 is used to output a switching control signal Nscan1 to a row of sub-pixels PL, that is, a row of pixel drive circuits PC needs a first gate circuit 310.

[0065] Referring to FIG. 3 , the second gate circuit 320 is arranged on the side of the first gate circuit 310 away from the display area AA, and the second gate circuit 320 is used to output a compensation control signal Nscan2 to two rows of sub-pixels PL, that is, two rows of pixel drive circuits PC need a second gate circuit 320.

[0066] Referring to FIG. 3 , the third gate circuit 330 is arranged on the side of the second gate circuit 320 away from the display area AA, and the third gate circuit 330 is used to output a first light-emitting control signal EM1 or a second light-emitting control signal EM2 to two rows of sub-pixels PL, that is, two rows of pixel drive circuits PC need a third gate circuit 330; for example, the third gate circuit 330 located on one side of the display area AA is used to output the first light-emitting control signal EM1, and the third gate circuit 330 located on the other side of the display area AA is used to output the second light-emitting control signal EM2.

[0067] It should be noted that the reset signal Vi is a constant voltage, which does not need to be controlled by the corresponding gate drive circuit 300, and can be directly connected to the corresponding constant voltage source.

[0068] It should be noted that the positions of the first gate circuit 310, the second gate circuit 320 and the third gate circuit 330 of the present application can be exchanged, for example, the second gate circuit 320, the third gate circuit 330 and the first gate circuit 310 can be arranged along the second direction Y, the third gate circuit 330, the second gate circuit 320 and the first gate circuit 310 can be arranged along the second direction Y, and the third gate circuit 330, the first gate circuit 310 and the second gate circuit 320 can be arranged along the second direction Y.

[0069] In the present embodiment, the first gate circuit 310, the second gate circuit 320 and the third gate circuit 330 of the present application can be mTnC gate circuits. In the following embodiment, the third gate circuit 330 is taken as an example of a 7T1C to describe the structure of the gate drive unit 300a of the present application.

[0070] Referring to FIG. 4 , the first control module 311 includes a first transistor T1, the drain of the first transistor T1 is connected to an initial signal line or the output end OUT of the previous stage first gate circuit 310, the source of the first transistor T1 is connected to a first node M, and the first transistor T1 can be a single-gate or double-gate structure, for example FIG. 4 , the gate of the first transistor T1 in FIG. 4 is a double-gate structure, and the double gate of the first transistor T1 is connected to a clock control line CK.

[0071] Referring to FIG. 4 , the first output module 312 includes a fifth transistor T5 and a first capacitor C1, the drain of the fifth transistor T5 is connected to a low potential line VGL, the source of the fifth transistor T5 is connected to the output end OUT of the first gate circuit 310, and the fifth transistor T5 can be a single-gate or double-gate structure, for example FIG. 4 , the gate of the fifth transistor T5 in FIG. 4 is a double-gate structure, and the double gate of the fifth transistor T5 is connected to a second node Q; the first plate C1a of the first capacitor C1 is connected to the second node Q, and the second plate C1b of the first capacitor C1 is connected to the output end OUT of the first gate circuit 310.

[0072] Referring to FIG. 4 , the second control module 314 includes a second transistor T2, the double gate of the second transistor T2 is connected to the first node M, the drain of the second transistor T2 is connected to a high potential line VGH, and the source of the second transistor T2 is connected to a second node P.

[0073] Referring to FIG. 4 , the third control module 316 includes a third transistor T3, the drain of the third transistor T3 is connected to a low level source VGL, the source of the third transistor T3 is connected to the second node P, and the third transistor T3 can be a single-gate or double-gate structure, for example FIG. 4The gate of the third transistor T3 in the first gate circuit 310 includes a first gate of the third transistor T3 and a second gate of the third transistor T3, the first gate of the third transistor T3 is connected to the first node M, and the second gate of the third transistor T3 is connected to the low-level source VGL.

[0074] Referring to FIG. 4 The compensation module 315 includes a seventh transistor T7, a drain of the seventh transistor T7 is connected to the low-level source VGL, and a source of the seventh transistor T7 is connected to the first node M. The seventh transistor T7 can be a single-gate structure or a double-gate structure, for example FIG. 4 The gate of the seventh transistor T7 in the first gate circuit 310 includes a first gate of the seventh transistor T7 and a second gate of the seventh transistor T7, the first gate of the seventh transistor T7 is connected to the second node P, and the second gate of the seventh transistor T7 is connected to the low-level source VGL.

[0075] Referring to FIG. 4 The second output module 313 further includes a sixth transistor T6, a drain of the sixth transistor T6 is connected to the high-level source VGH, and a source of the sixth transistor T6 is connected to the output end OUT of the first gate circuit 310. The sixth transistor T6 can be a single-gate structure or a double-gate structure, for example FIG. 4 The gate of the sixth transistor T6 in the first gate circuit 310 is a double-gate structure, and the double gate of the sixth transistor T6 is connected to the second node P.

[0076] Referring to FIG. 6 The voltage stabilizing module 317 further includes a fourth transistor T4, a drain of the fourth transistor T4 is connected to the first node M, and a source of the fourth transistor T4 is connected to the second node Q. The double gate of the fourth transistor T4 is connected to the low-level source VGL.

[0077] Specifically, the transistor types of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be one of a silicon semiconductor transistor and an oxide semiconductor transistor. For example, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be silicon semiconductor transistors, and the third transistor T3 and the seventh transistor T7 can be oxide semiconductor transistors.

[0078] Specifically, the oxide semiconductor transistor can be a metal oxide transistor, and the silicon semiconductor transistor can be a low-temperature polysilicon transistor.

[0079] It should be noted that the transistors of the present application are all double-gate designs, and the transistors can also be single-gate design transistors, for example, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can all be single-gate structures of silicon semiconductor transistors, that is, the light-shielding layer is not used as a bottom gate structure, and the gate is the only gate; at the same time, for the transistors of the double-gate design, the gate refers to the bottom gate and the top gate, for example, the third transistor T3 is a double-gate design, and the gate of the third transistor T3 refers to the first gate and the second gate of the third transistor T3. Similarly, the gate of the other transistors can be understood with reference to the above description of the transistors, and will not be described again in the following embodiments.

[0080] Referring to FIG. 6 , the third control module 316 can be arranged between the compensation module 315 and the first control module 311, and in the second direction Y, the distance between the third control module 316 and the display area AA on the side away from the display area AA is less than the distance between the first control module 311 or / and the second control module 314 and the display area AA on the side away from the display area AA.

[0081] Referring to FIG. 6 , the voltage stabilizing module 317 can be arranged between the third control module 316 and the first control module 311, and in the second direction Y, the distance between the voltage stabilizing module 317 and the display area AA on the side away from the display area AA is less than or equal to the distance between the first control module 311 and the display area AA on the side away from the display area AA.

[0082] That is, in the structure of FIG. 4 , the first transistor T1, the fourth transistor T4, the third transistor T3, the seventh transistor T7, and the second transistor T2 of the present application are sequentially and spaced apart in the first direction X, and the distance between the first transistor T1 and the display area AA on the side away from the display area AA is greater than or equal to the distance between the fourth transistor T4 and the display area AA on the side away from the display area AA, and the distance between the fourth transistor T4 and the display area AA on the side away from the display area AA is greater than or equal to the distance between the third transistor T3 and the display area AA on the side away from the display area AA, and the distance between the third transistor T3 and the display area AA on the side away from the display area AA is greater than or equal to the distance between the seventh transistor T7 and the display area AA on the side away from the display area AA.

[0083] That is, the seventh transistor T7 of the present application can be arranged in the region between the second transistor T2 and the third transistor T3, and the distance between the seventh transistor T7 and the display area AA on the side away from the display area AA does not exceed the distance between the first transistor T1 and the display area AA on the side away from the display area AA, that is, the newly added compensation module 315 does not increase the size of the gate drive circuit 300 in the second direction Y, and in the case of ensuring the stability of the control signal output by the gate drive circuit 300, the narrow frame design is realized.

[0084] The film layers of the display panel 100 of the present application are described below with respect to the structure of FIG. 5

[0085] Referring to FIG. 5 The display area AA and the non-display area NA of the display panel 100 can be provided with a substrate 110 and an array driving layer 120 disposed on the substrate 110. In the display area AA, the display panel 100 can further be provided with a pixel definition layer disposed on the array driving layer 120, a light emitting device layer disposed in the same layer as the pixel definition layer, and an encapsulation layer disposed on the pixel definition layer. The film layer structure in the non-display area NA is mainly described below.

[0086] In the present embodiment, the substrate 110 supports various layers disposed on the substrate 110. When the display panel 100 is a bottom emission light emitting display device or a double-sided emission light emitting display device, a transparent substrate 110 is used. When the display panel 100 is a top emission light emitting display device, a semi-transparent or non-transparent substrate 110 as well as a transparent substrate 110 can be used.

[0087] In the present embodiment, the substrate 110 is used to support various film layers disposed on the substrate 110, and the substrate 110 can be made of an insulating material such as glass, quartz, or a polymer resin. The substrate 110 can be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. Examples of flexible materials for the flexible substrate include polyimide (PI), but are not limited to polyimide (PI).

[0088] In the present embodiment, the substrate 110 can include a first flexible base 111, a first barrier layer 112, a second flexible base 113, and a second barrier layer 114 disposed in layers, the first flexible base 111 and the second flexible base 113 can be formed of the same material such as polyimide, and the first barrier layer 112 and the second barrier layer 114 can be formed of an inorganic material including at least one of SiOx and SiNx, for example.

[0089] In the present embodiment, the first flexible base 111 is formed by coating a polymeric material on a support base (not shown) and then curing the polymeric material, the second flexible base 113 is formed by coating the same material as the material of the first flexible base 111 and curing the material, and the second flexible base 113 is formed by the same method as the method of forming the first flexible base 111. Each of the first flexible base 111 and the second flexible base 113 can be formed to have a thickness of about 8 μm to about 12 μm. Furthermore, when the substrate 110 is formed of the first flexible base 111 and the second flexible base 113, small holes, cracks, etc. formed during the manufacture of the first flexible base 111 are covered by the second flexible base 113, so that the above-described defects can be removed. ​

[0090] Referring to FIG. 5 , the array driving layer 120 can include a plurality of thin film transistors, which can be etch stop type, back channel etch type, or divided into bottom gate thin film transistor, top gate thin film transistor, etc. according to the position of the gate and the active layer, or divided into N-type thin film transistor, P-type thin film transistor according to the performance of the thin film transistor; wherein, FIG. 2 The thin film transistor in FIG. 5 is not a structural diagram of any transistor in , but only a schematic diagram of each film layer of the display panel 100 of the present application.

[0091] Referring to FIG. 5 , the array driving layer 120 can include a light shielding layer 121 disposed on the substrate 110, a buffer layer 122 disposed on the light shielding layer 121, a first active layer 123 disposed on the buffer layer 122, a first gate insulating layer 124 disposed on the first active layer 123, a first gate layer 125 disposed on the first gate insulating layer 124, a second gate insulating layer 126 disposed on the first gate layer 125, a second gate layer 127 disposed on the second gate insulating layer 126, a first interlayer insulating layer 128 disposed on the second gate layer 127, a second active layer 129 disposed on the first interlayer insulating layer 128, a third gate insulating layer 130 disposed on the second active layer 129, a third gate layer 131 disposed on the third gate insulating layer 130, a fourth gate insulating layer 132 disposed on the third gate layer 131, a fourth gate layer 133 disposed on the fourth gate insulating layer 132, a second interlayer insulating layer 134 disposed on the fourth gate layer 133, a first source-drain layer 135 disposed on the second interlayer insulating layer 134, a first planar layer 136 disposed on the first source-drain layer 135, a second source-drain layer 137 disposed on the first planar layer 136, and a second planar layer 138 disposed on the second source-drain layer 137.

[0092] Referring to FIG. 5 , the light shielding layer 121 is disposed on or in the second barrier layer 114, and the light shielding layer 121 is used to shield external light from entering the thin film transistor from the bottom. The material of the light shielding layer 121 can be composed of black light shielding material, such as black light shielding metal or black organic material, etc.

[0093] Referring to FIG. 5 , the buffer layer 122 is disposed on the light shielding layer 121, and the material of the buffer layer 122 can include a compound composed of nitrogen element, silicon element and oxygen element, such as a single layer of silicon oxide film, or a stacked structure of silicon oxide-silicon nitride.

[0094] Referring to FIG. 5The first active layer 123 is disposed on the buffer layer 122, and the second active layer 129 can be disposed on the first interlayer insulating layer 128. The material of the first active layer 123 and the second active layer 129 can be one of a silicon semiconductor transistor or an oxide semiconductor transistor, such as a metal oxide semiconductor, amorphous silicon, or low-temperature polysilicon. In this application, the material of the first active layer 123 can be low-temperature polysilicon, and the material of the second active layer 129 can be indium gallium zinc oxide semiconductor.

[0095] Referring to FIG. 5 The first gate insulating layer 124, the second gate insulating layer 126, the third gate insulating layer 130, the fourth gate insulating layer 132, the first interlayer insulating layer 128, and the second interlayer insulating layer 134 are respectively disposed on the corresponding metal layer or semiconductor layer to separate the metal layers or semiconductor layers of different layers. The materials of the first gate insulating layer 124, the second gate insulating layer 126, the first interlayer insulating layer 128, the third gate insulating layer 130, the fourth gate insulating layer 132, and the second interlayer insulating layer 134 can be inorganic materials combined with silicon oxide and nitrogen, or organic materials with flatness, or stacked structures of silicon oxide, silicon nitride, aluminum oxide, etc.

[0096] Referring to FIG. 5 The first gate layer 125, the second gate layer 127, the third gate layer 131, and the fourth gate layer 133 are respectively disposed on the corresponding insulating layer. The materials of the first gate layer 125, the second gate layer 127, the third gate layer 131, and the fourth gate layer 133 can include Cr, W, Ti, Ta, Mo, Al, Cu, or a single-layer or multi-layer metal structure composed of at least two of the above-mentioned metals, such as Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0097] Referring to FIG. 5 The materials of the first source-drain layer 135 and the second source-drain layer 137 can include Cr, W, Ti, Ta, Mo, Al, Cu, or a single-layer or multi-layer metal structure composed of at least two of the above-mentioned metals, such as Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0098] Referring to FIG. 5The first planar layer 136 and the second planar layer 138 can be laid in the whole layer or only in the display area AA and part of the non-display area NA to ensure the film layer flatness of the array driving layer 120. The materials of the first planar layer 136, the second planar layer 138 and the third planar layer 140 can be inorganic materials combined with nitrogen and oxygen or flexible materials such as polytetrafluoroethylene.

[0099] It should be noted that FIG. 5 The structures of two oxide transistors and one silicon semiconductor transistor are listed in Table 1, FIG. 4 The three transistors in Table 1 are only schematic diagrams of film layers of different types of transistors in the non-display area NA, which do not represent the specific structures of the transistors in the non-display area NA.

[0100] It should be noted that the material of the second gate layer 127 is usually prepared by using titanium to shield the influence of the bottom charge in the display area AA. The spacing between the second gate layer 127 and the second active layer 129 is small. In order to improve the bias temperature stress (BTS) characteristics of the oxide transistor, the first gate layer 125 is used as the bottom gate of the oxide transistor in the present application, so the structure in Table 1 does not show the second gate layer 127. FIG. 4 The structure in Table 1 does not show the second gate layer 127.

[0101] Please refer to FIG. 7A The third gate circuit 330 includes a first capacitor C1 with a first plate C1a and a second plate C1b. Since the present application is suitable for setting the plate conductive layer to have the first active layer 123, the first gate layer 125, the second gate layer 127, the second active layer 129, the third gate layer 131 and the fourth gate layer 133.

[0102] In the present embodiment, the first plate C1a is located in the film layer where the first gate layer 125 is located, and the second plate C1b is located in the film layer where the third gate layer 131 is located, that is, the first plate C1a is prepared by using the material of the first gate layer 125, and the second plate C1b is prepared by using the material of the third gate layer 131.

[0103] Alternatively, the first plate C1a is located in the film layer where the first gate layer 125 is located, and the second plate C1b is located in the film layer where the second active layer 129 is located, that is, the first plate C1a is prepared by using the material of the first gate layer 125, and the second plate C1b is prepared by using the material of the second active layer 129.

[0104] Alternatively, the first plate C1a is located in the film layer where the third gate layer 131 is located, and the second plate C1b is located in the film layer where the fourth gate layer 133 is located, that is, the first plate C1a is prepared by using the material of the third gate layer 131, and the second plate C1b is prepared by using the material of the fourth gate layer 133.

[0105] The technical solutions of the present application are described below in detail with reference to the specific structure of the circuit structure in FIG. 7A

[0106] Please refer to FIG. 7A The first gate layer 125 includes the gate T1G of the first transistor T1, the gate T2G of the second transistor T2, the gate T4G of the fourth transistor T4, the gate T5G of the fifth transistor T5, and the gate T6G of the sixth transistor T6.

[0107] Please refer to FIG. 7A The first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all silicon semiconductor transistors. Therefore, in order to improve the mobility of the above-mentioned transistors, the present application sets the above-mentioned transistors as double-gate transistors, and the first gate layer 125 includes the top gate of the above-mentioned transistors. For example, the first gate layer 125 includes the second gate T1Gb of the first transistor T1, the second gate T2Gb of the second transistor T2, the second gate T4Gb of the fourth transistor T4, the second gate T5Gb of the fifth transistor T5, and the second gate T6Gb of the sixth transistor T6.

[0108] Please refer to FIG. 7A The first gate layer 125 further includes the first gate T3Ga of the third transistor T3 and the first gate T7Ga of the seventh transistor T7 connected thereto. The first gate T3Ga of the third transistor T3 and the first gate T7Ga of the seventh transistor T7 are the bottom gates of the corresponding transistors, and the first gate T3Ga of the third transistor T3 and the first gate T7Ga of the seventh transistor T7 are connected through an electrically connected segment extending in an L shape or longitudinally.

[0109] Please refer to FIG. 7A ​The second gate T2Gb of the second transistor T2, the first gate T7Ga of the seventh transistor T7, the first gate T3Ga of the third transistor T3, the second gate T4Gb of the fourth transistor T4, and the second gate T1Gb of the first transistor T1 are arranged along the first direction X, the second gate T6Gb of the sixth transistor T6 and the second gate T5Gb of the fifth transistor T5 are arranged along the first direction X, the second gate T2Gb of the second transistor T2 and the second gate T6Gb of the sixth transistor T6 are arranged adjacent along the second direction Y, the first gate T7Ga of the seventh transistor T7 and the second gate T6Gb of the sixth transistor T6 are arranged adjacent along the second direction Y, and the first gate T3Ga of the third transistor T3, the second gate T4Gb of the fourth transistor T4, and the second gate T1Gb of the first transistor T1 are arranged adjacent along the second direction Y and the second gate T5Gb of the fifth transistor T5.

[0110] Referring to FIG. 7A The second gate T6Gb of the sixth transistor T6 and the second gate T5Gb of the fifth transistor T5 each include a branch gate extending along the second direction Y; for example, the second gate T6Gb of the sixth transistor T6 includes three branch gates, and the second gate T5Gb of the fifth transistor T5 includes a trunk gate and seven branch gates connected to the trunk gate and arranged along the first direction X and spaced apart.

[0111] Referring to FIG. 7A The interval between the second gate T6Gb of the sixth transistor T6 and the second gate T5Gb of the fifth transistor T5 can be equal to or different from the interval between two adjacent branch gates in the second gate T5Gb of the fifth transistor T5.

[0112] Referring to FIG. 7A The first gate layer 125 further includes a first transfer segment ET1, a second transfer segment ET2, a third transfer segment ET3, a fourth transfer segment ET4, and a fifth transfer segment ET5, the first transfer segment ET1 extending along the second direction Y, and the second transfer segment ET2 extending along the first direction X.

[0113] Referring to FIG. 7BThe main trunk gate of the second gate T5Gb of the fifth transistor T5 is connected with the first transmission section ET1 and extends to the end away from the fifth transistor T5, the first transmission section ET1 is arranged between the first gate T3Ga of the third transistor T3 and the second gate T4Gb of the fourth transistor T4, the second transmission section ET2 is connected with the first gate T3Ga of the third transistor T3 and the second gate T4Gb of the fourth transistor T4 away from the one end of the first transmission section ET1, the third transmission section ET3 is arranged at the second gate T2Gb of the second transistor T2 close to the sixth transistor T6, and the fifth transmission section ET5 is arranged at the main trunk gate of the second gate T6Gb of the sixth transistor T6 and extends to the end away from the sixth transistor T6.

[0114] Please refer to FIG. 7B Since the fifth transistor T5 is used for outputting the control signal to the pixel driving circuit PC, the load of the fifth transistor T5 is greater than that of other non-output transistors, and in order to ensure the output load of the fifth transistor T5, the area of the fifth transistor T5 can be greater than that of other non-output transistors. At the same time, since the sixth transistor T6 is used for pulling down the potential of the output point of the fifth transistor T5, the area of the sixth transistor T6 can be smaller than that of the fifth transistor T5, but the area of the sixth transistor T6 needs to be greater than that of other non-output transistors.

[0115] In the embodiment, the area of the second gate T5Gb of the fifth transistor T5 is greater than that of the second gate T6Gb of the sixth transistor T6, and the area of the second gate T6Gb of the sixth transistor T6 is greater than that of the gate of other non-output transistors.

[0116] In the embodiment, the first gate T3Ga of the third transistor T3, the second gate T4Gb of the fourth transistor T4 and the first gate T7Ga of the seventh transistor T7 can be connected in sequence through the second transmission section ET2 and the electrical connection section ET0.

[0117] In this embodiment, the width of the first gate T3Ga of the third transistor T3 and the first gate T7Ga of the seventh transistor T7 is greater than the width of the second gate T1Gb of the first transistor T1, the second gate T2Gb of the second transistor T2, the second gate T4Gb of the fourth transistor T4, the second gate T3Gb of the third transistor T3 and the second gate T7Gb of the seventh transistor T7; that is, since the first gate T3Ga of the third transistor T3 and the first gate T7Ga of the seventh transistor T7 are both the bottom gate of the corresponding transistor, the second gate T1Gb of the first transistor T1, the second gate T2Gb of the second transistor T2, the second gate T4Gb of the fourth transistor T4, the second gate T3Gb of the third transistor T3 and the second gate T7Gb of the seventh transistor T7 are all the top gate of the corresponding transistor, and the bottom gate usually has the effect of light shielding, therefore the width of the bottom gate is usually greater than the width of the top gate.

[0118] Please refer to FIG. 7I The light shielding layer 121 includes the first gate T1Ga of the first transistor T1, the first gate T2Ga of the second transistor T2, the first gate T4Ga of the fourth transistor T4, the first gate T5Ga of the fifth transistor T5 and the first gate T6Ga of the sixth transistor T6.

[0119] Please refer to FIG. 7C The first gate T2Ga of the second transistor T2, the first gate T4Ga of the fourth transistor T4 and the first gate T1Ga of the first transistor T1 extend along the second direction Y, the first gate T2Ga of the second transistor T2, the first gate T4Ga of the fourth transistor T4 and the first gate T1Ga of the first transistor T1 are arranged along the first direction X, the first gate T6Ga of the sixth transistor T6 and the first gate T5Ga of the fifth transistor T5 are arranged along the first direction X, the first gate T2Ga of the second transistor T2 and the first gate T6Ga of the sixth transistor T6 are arranged adjacent along the second direction Y, and the first gate T4Ga of the fourth transistor T4 and the first gate T1Ga of the first transistor T1 are arranged adjacent along the second direction Y with the first gate T5Ga of the fifth transistor T5.

[0120] It should be noted that the gate structure in the light shielding layer 121 is the bottom gate of the corresponding transistor.

[0121] Please refer to FIG. 7CThe first gate T1Ga and the second gate T1Gb of the first transistor T1 are arranged in overlap in the thickness direction of the display panel 100, and the area of the first gate T1Ga is greater than or equal to the area of the second gate T1Gb; the first gate T2Ga and the second gate T2Gb of the second transistor T2 are arranged in overlap in the thickness direction of the display panel 100, and the area of the first gate T2Ga is greater than or equal to the area of the second gate T2Gb; the first gate T4Ga and the second gate T4Gb of the fourth transistor T4 are arranged in overlap in the thickness direction of the display panel 100, and the area of the first gate T4Ga is greater than or equal to the area of the second gate T4Gb; the first gate T5Ga and the second gate T5Gb of the fifth transistor T5 are arranged in overlap in the thickness direction of the display panel 100, and the area of the first gate T5Ga is greater than or equal to the area of the second gate T5Gb; and the first gate T6Ga and the second gate T6Gb of the sixth transistor T6 are arranged in overlap in the thickness direction of the display panel 100, and the area of the first gate T6Ga is greater than or equal to the area of the second gate T6Gb.

[0122] In the embodiment, the transistors described above are all double-gate structures, and the structure of the bottom gate can be the same as the pattern of the top gate, but the area of the bottom gate is greater than the area of the top gate, that is, the bottom gate can be reused as the light shielding part and the driving gate of the corresponding transistor.

[0123] In the embodiment, the second gate of the transistor described above is directly connected with the first gate through the via hole.

[0124] Referring to FIG. 7D The first active layer 123 includes the active pattern T1A of the first transistor T1, the active pattern T2A of the second transistor T2, and the active pattern T4A of the fourth transistor T4, the active pattern T5A of the fifth transistor T5, and the active pattern T6A of the sixth transistor T6. The active pattern T1A of the first transistor T1, the active pattern T2A of the second transistor T2, and the active pattern T4A of the fourth transistor T4 all extend along the first direction X, and the active pattern T1A of the first transistor T1 and the active pattern T4A of the fourth transistor T4 are connected along the first direction X.

[0125] Referring to FIG. 7I The active pattern T6A of the sixth transistor T6 and the active pattern T5A of the fifth transistor T5 are connected, and the active pattern T6A of the sixth transistor T6 and the active pattern T5A of the fifth transistor T5 both include at least two active sub-parts arranged at intervals along the second direction Y, and the active sub-parts of the sixth transistor T6 and the fifth transistor T5 are connected along the first direction X.

[0126] Referring to FIG. 7DThe active pattern T2A of the second transistor T2 and the second gate T2Gb of the second transistor T2 have an overlapping portion, and the overlapping portion is a channel of the second transistor T2; the active pattern T4A of the fourth transistor T4 and the second gate T4Gb of the fourth transistor T4 have an overlapping portion, and the overlapping portion is a channel of the fourth transistor T4; the active pattern T1A of the first transistor T1 and the second gate T1Gb of the first transistor T1 have an overlapping portion, and the overlapping portion is a channel of the first transistor T1; the active pattern T6A of the sixth transistor T6 and the second gate T6Gb of the sixth transistor T6 have an overlapping portion, and the overlapping portion is a channel of the sixth transistor T6; and the active pattern T5A of the fifth transistor T5 and the second gate T5Gb of the fifth transistor T5 have an overlapping portion, and the overlapping portion is a channel of the fifth transistor T5.

[0127] Please refer to FIG. 7C In the top view direction of the display panel 100, the channel of the above-mentioned transistor completely falls into the first gate of the corresponding transistor.

[0128] Please refer to FIG. 7D The length of the gate T6G of the sixth transistor T6 and the gate T5G of the fifth transistor T5 in the second direction Y is relatively long, and since the sixth transistor T6 and the fifth transistor T5 are oxide transistors, they have the advantage of low leakage current but the characteristic of small mobility. In order to improve the mobility of the sixth transistor T6 and the fifth transistor T5, the channel width in the transistor can be increased. Therefore, in order to further increase the channel width of the transistor, the size of the active pattern T6A of the sixth transistor T6 and the active pattern T5A of the fifth transistor T5 in the second direction Y can be increased as much as possible. However, when the size of the semiconductor structure in the second direction Y is too large, the active part will have a problem of static electricity concentration, which will cause the active part to be damaged by static electricity. Therefore, the structure of the active pattern T6A of the sixth transistor T6 and the active pattern T5A of the fifth transistor T5 can be arranged as multiple sub-active parts in a spaced arrangement.

[0129] In this embodiment, the width of the active pattern T6A of the sixth transistor T6 and the active pattern T5A of the fifth transistor T5 can be the same.

[0130] Please refer to FIG. 7E and FIG. 7F The channel width of the active pattern T1A of the first transistor T1 can be greater than or equal to the channel width of the transistors other than the sixth transistor T6 and the fifth transistor T5. Since the first transistor T1 is used to control the potential of the second node Q, in order to ensure the accuracy of the potential of the second node Q, the width of the active pattern T1A of the first transistor T1 in the second direction Y is increased to improve the mobility of the first transistor T1.

[0131] Meanwhile, since the fourth transistor T4 is also used to control the potential of the second node Q, the width of the active pattern T1A of the first transistor T1 in the second direction Y can be equal to the width of the active pattern T4A of the fourth transistor T4 in the second direction Y.

[0132] Referring to FIG. 7H , the third gate layer 131 includes the second gate T3Gb of the third transistor T3 and the second gate T7Gb of the seventh transistor T7, and the second gate T3Gb of the third transistor T3 and the second gate T7Gb of the seventh transistor T7 are arranged in the first direction X and extend in the second direction Y. The above-mentioned gates can serve as top gates of the corresponding transistors.

[0133] Referring to FIG. 7H , the second active layer 129 includes the active pattern T3A of the third transistor T3 and the active pattern T7A of the seventh transistor T7, and the active pattern T3A of the third transistor T3 and the active pattern T7A of the seventh transistor T7 both extend in the first direction X, and the active pattern T3A of the third transistor T3 and the active pattern T7A of the seventh transistor T7 are arranged in the second direction Y.

[0134] Referring to FIG. 7I , the active pattern T3A of the third transistor T3 and the second gate T3Gb of the third transistor T3 have an overlapping portion, and the overlapping portion is the channel of the third transistor T3; the active pattern T7A of the seventh transistor T7 and the second gate T7Gb of the seventh transistor T7 have an overlapping portion, and the overlapping portion is the channel of the seventh transistor T7.

[0135] Referring to FIG. 7E , the first gate T3Ga and the second gate T3Gb of the third transistor T3 are arranged in the thickness direction of the display panel 100, and the area of the first gate T3Ga is greater than the area of the second gate T3Gb; the first gate T7Ga and the second gate T7Gb of the seventh transistor T7 are arranged in the thickness direction of the display panel 100, and the area of the first gate T7Ga is greater than the area of the second gate T7Gb.

[0136] Referring to FIG. 7E , in the plan view direction of the display panel 100, the channel of the third transistor T3 and the channel of the seventh transistor T7 both fall within the first gate of the corresponding transistor.

[0137] Referring to FIG. 7GThe third gate layer 131 further includes a first plate C1a of the first capacitor C1, a sixth transfer segment ET6, a seventh transfer segment ET7, and an eighth transfer segment ET8. The first plate C1a includes a first main body part C1aa and a first extension part C1ab connected to the first main body part C1aa. The area of the first main body part C1aa is greater than the area of the first extension part C1ab. The first extension part C1ab and the partial main trunk gate and the partial branch gate of two gates of the fifth transistor T5 are arranged in an overlapping manner.

[0138] Referring to FIG. 7G The third gate layer 131 further includes a sixth transfer segment ET6, a seventh transfer segment ET7, and an eighth transfer segment ET8. The sixth transfer segment ET6 is connected to the first extension part C1ab, and the sixth transfer segment ET6 is arranged on the side of the first extension part C1ab away from the fifth transistor T5. The seventh transfer segment ET7 extends along the first direction X, and the eighth transfer segment ET8 extends along the second direction Y. The seventh transfer segment ET7 is arranged on the side of the first main body part C1aa away from the fifth transistor T5, and the eighth transfer segment ET8 is arranged on the side of the sixth transistor T6 away from the fifth transistor T5.

[0139] Referring to FIG. 7J The fourth gate layer 133 includes a second plate C1b of the first capacitor C1. The second plate C1b is arranged opposite to the first plate C1a, and the area of the second plate C1b is less than the area of the first plate C1a. That is, the orthographic projection of the second plate C1b on the substrate 110 is located within the orthographic projection of the first plate C1a on the substrate 110.

[0140] In the embodiment, the second plate C1b includes a second main body part C1ba and a second extension part C1bb. The second main body part C1ba corresponds to the first main body part C1aa, and the second extension part C1bb corresponds to the first extension part C1ab.

[0141] Referring to FIG. 7K The fourth gate layer 133 includes a ninth transfer segment ET9, and the ninth transfer segment ET9 is connected to the side of the second main body part C1ba close to the fifth transistor T5.

[0142] Referring to FIG. 7J and FIG. 7K The first source-drain layer 135 includes a source T6S of the sixth transistor T6, a drain T6D of the sixth transistor T6, a source T5S of the fifth transistor T5, and a drain T5D of the fifth transistor T5.

[0143] Referring to FIG. 7J and FIG. 7KThe source T6S of the sixth transistor T6, the drain T6D of the sixth transistor T6, the source T5S of the fifth transistor T5, and the drain T5D of the fifth transistor T5 each include branch electrodes extending along the second direction Y and arranged at intervals along the first direction X, for example, the source T5S of the fifth transistor T5 and the drain T5D of the fifth transistor T5 each include five branch electrodes extending along the second direction Y and arranged along the first direction X, and the branch electrodes of the source T5S of the fifth transistor T5 and the drain T5D of the fifth transistor T5 are arranged alternately along the first direction X.

[0144] Referring to FIG. 7J and FIG. 7K , the branch electrodes of the source T6S of the sixth transistor T6 close to the drain T5D of the fifth transistor T5 are shared by the source T6S of the sixth transistor T6 and the source T5S of the fifth transistor T5, and the shared branch electrodes close to one end of the display area AA are the output end OUT of the first gate circuit 310.

[0145] Referring to FIG. 7J and FIG. 7K , the branch electrodes of the two gates of the sixth transistor T6 can be arranged between the branch electrodes of the source T6S of the sixth transistor T6 and the branch electrodes of the drain T6D of the sixth transistor T6 arranged at intervals, and the branch electrodes of the two gates of the fifth transistor T5 are arranged between the branch electrodes of the source T5S of the fifth transistor T5 and the branch electrodes of the drain T5D of the fifth transistor T5 arranged at intervals.

[0146] Referring to FIG. 7J and FIG. 7K , the first source-drain layer 135 includes a first connection section CT1, and the first connection section CT1 is used for connecting the second clock control line CK2 in the second source-drain layer 137 and the second gate T1Gb of the first transistor T1.

[0147] Referring to FIG. 7J and FIG. 7K , the first source-drain layer 135 includes a second connection section CT2, one end of the second connection section CT2 is connected to one end of the seventh transfer section ET7 close to the first transistor T1, and the other end of the second connection section CT2 is connected to one end of the active pattern T1A of the first transistor T1 through a via hole.

[0148] Referring to FIG. 7J and FIG. 7KThe first source-drain layer 135 includes a third connection segment CT3, the third connection segment CT3 includes two lateral segments and a middle segment connecting the two lateral segments, an end of the first lateral segment is connected to the other end of the active pattern T1A of the first transistor T1, a middle position of the middle segment is connected to the second gate T3Gb of the third transistor T3 close to one end of the fifth transistor T5, a connection point of the middle segment and the second lateral segment is connected to the third transfer segment ET3, and an end of the second lateral segment away from the middle segment is connected to one end of the active pattern T7A of the seventh transistor T7.

[0149] Referring to FIG. 7J and FIG. 7K , the first source-drain layer 135 includes a fourth connection segment CT4, the fourth connection segment CT4 is in L shape, one end of the fourth connection segment CT4 is connected to the active pattern T4A of the fourth transistor T4 away from one end of the first transistor T1, the other end of the fourth connection segment CT4 is connected to the first transfer segment ET1, and a middle connection point of the fourth connection segment CT4 is connected to the sixth transfer segment ET6.

[0150] Referring to FIG. 7J and FIG. 7K , the first source-drain layer 135 includes a fifth connection segment CT5, the fifth connection segment CT5 includes a lateral segment and a longitudinal segment, one end of the lateral segment away from the longitudinal segment is connected to the first low potential line VGL1 of the second source-drain layer 137, and the other end of the longitudinal segment away from the lateral segment is connected to the other end of the active pattern T7A of the seventh transistor T7, and the lateral segment also passes through the via and is connected to one end of the active pattern T3A of the third transistor T3 and the second transfer segment ET2.

[0151] Referring to FIG. 7L and FIG. 6 , the first source-drain layer 135 includes a sixth connection segment CT6, the sixth connection segment CT6 includes a lateral segment and a longitudinal segment connected to each other, one end of the longitudinal segment away from the lateral segment is connected to the other end of the active pattern T3A of the third transistor T3, a middle position of the longitudinal segment is connected to the second gate T7Gb of the seventh transistor T7 away from one end of the sixth transistor T6, a connection point of the lateral segment and the middle segment is connected to one end of the active pattern T2A of the second transistor T2, and one end of the lateral segment away from the longitudinal segment is connected to the fifth transfer segment ET5.

[0152] Referring to FIG. 7L and FIG. 6 , the first source-drain layer 135 includes a seventh connection segment CT7, the seventh connection segment CT7 is connected to the other end of the active pattern T2A of the second transistor T2 away from one end of the sixth transistor T6.

[0153] Referring to FIG. 6 and FIG. 8 , the first source-drain layer 135 includes a seventh connection segment CT7, the seventh connection segment CT7 is connected to the other end of the active pattern T2A of the second transistor T2 away from one end of the sixth transistor T6.The first source-drain layer 135 includes an eighth connection segment CT8 extending along the first direction X, and the drain T5D of the fifth transistor T5 and the seventh connection segment CT7 are connected with the eighth connection segment CT8. The eighth connection segment CT8 is arranged in the first capacitor C1, and the eighth connection segment CT8 and the high potential line VGH in the second source-drain layer 137 are connected.

[0154] Please refer to FIG. 8 and FIG. 8 The first source-drain layer 135 includes a ninth connection segment CT9 extending along the first direction X and arranged in parallel with the eighth connection segment CT8. The eighth connection segment CT8 and the ninth connection segment CT9 are provided with the source T6S of the sixth transistor T6, the drain T6D of the sixth transistor T6, the source T5S of the fifth transistor T5, and the drain T5D of the fifth transistor T5. One end of the ninth connection segment CT9 is connected with the ninth transmission segment ET9 away from one end of the first capacitor C1, and the other end of the ninth connection segment CT9 is connected with the fourth transmission segment ET4 to transmit the control signal of the current stage to the display area AA through the fourth transmission segment ET4. The ninth connection segment CT9 is also connected with the eighth transmission segment ET8, and one end of the eighth transmission segment ET8 away from the ninth connection segment CT9 is connected with the seventh transmission segment ET7 of the next stage to transmit the control signal of the current stage to the first transistor T1 of the next stage.

[0155] It should be noted that the ninth connection segment CT9 of the present application is multiplexed as the main source of the source T6S of the sixth transistor T6 and the main source of the source T5S of the fifth transistor T5.

[0156] It should be noted that the "connection" of the present application can mean direct connection or indirect connection, but both are electrical connection.

[0157] Please refer to FIG. 4 and FIG. 8 The second source-drain layer 137 includes the first low potential line VGL1, the first control clock line CK1, the second control clock line CK2, the high potential line VGH, and the second low potential line VGL2, which all extend along the first direction X and are arranged at intervals along the second direction Y.

[0158] In the present embodiment, the first low potential line VGH1 is connected through the via and the fifth connection segment CT5, the high potential line VGH is connected through the via and the eighth connection segment CT8, and the second low potential line VGL2 is connected through the via and the drain T5D of the fifth transistor T5.

[0159] In the embodiment, the high potential line VGH and the sixth transistor T6 overlap and are connected, the second low potential line VGL2 and the fifth transistor T5 overlap and are connected, the first low potential line VGL1 and the third transistor T3, the fourth transistor T4 and the seventh transistor T7 are connected, the third transistor T3, the fourth transistor T4 and the seventh transistor T7 are used for switch control of signals, and the fifth transistor T5 and the sixth transistor T6 are connected with the output end OUT of the gate circuit, so that the high potential line VGH and the second low potential line VGL2 need a larger output load capacity.

[0160] Please refer to FIG. 4 and FIG. 8 , the width of the high potential line VGH and the second low potential line VGL2 is greater than the width of the first low potential line VGL1, so as to improve the output load capacity of the high potential line VGH and the second low potential line VGL2.

[0161] The first control clock line CK1 passes through the via and the fifth connection segment CT5 of the third gate circuit 330 of the odd stage to be connected, so as to transmit the clock signal in the first control clock line CK1 to the third transistor T3, the fourth transistor T4 and the seventh transistor T7 of the odd stage. The second control clock line CK2 passes through the via and the fifth connection segment CT5 of the third gate circuit 330 of the even stage to be connected, so as to transmit the clock signal in the second control clock line CK2 to the third transistor T3, the fourth transistor T4 and the seventh transistor T7 of the even stage. For example, the third gate circuit 330 shown in the accompanying drawings of the present application is the gate circuit of the even stage. FIG. 9 The third gate circuit 330 shown in the accompanying drawings of the present application is the gate circuit of the even stage.

[0162] In the embodiment of the present application, in order to ensure that the output signals of different output clock lines are the same, the present application can make the line width of the two output clock lines equal.

[0163] Please refer to FIG. 9 , FIGS. 10A-10F , which is a second structure diagram of the gate driving circuit in the display panel of the present application.

[0164] In the embodiment, FIG. 9 The gate driving circuit 300 in the accompanying drawings of the present application includes the first control module 311, the first output module 312, the second output module 313, the second control module 314, the compensation module 315, the third control module 316 and the voltage stabilizing module 317 which are electrically connected, and the structure of the gate driving circuit 300 is the same as that of the gate driving circuit 300 in the accompanying drawings of the present application. FIG. 9 The structure of the gate driving circuit 300 in the accompanying drawings of the present application is the same as that of the gate driving circuit 300 in the accompanying drawings of the present application.

[0165] FIG. 8 and FIG. 9 The difference between the gate driving circuit 300 in the accompanying drawings of the present application and the gate driving circuit 300 in the accompanying drawings of the present application is that FIG. 6The first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may all be single-gate structures of silicon semiconductor transistors, and the third transistor T3 and the seventh transistor T7 may be double-gate structures of oxide semiconductor transistors.

[0166] See also FIG. 9 , FIG. 9 This is a film layer structure diagram of the second embodiment of the third gate circuit of this application. FIG. 11 In order FIG. 11 Single-layer film diagram of the first active layer, the first gate layer, the second active layer, the third gate layer, the first source and drain layer, and the second source and drain layer.

[0167] FIGS. 12A-12F The structure in FIG. 11 In the embodiment structure diagram, FIG. 11 The structure and FIG. 8 The structures in are the same or similar, except that FIG. 11 No light shielding layer is provided, so that the first transistor T1 , the second transistor T2 , the fourth transistor T4 , the fifth transistor T5 , and the sixth transistor T6 can all be single-gate structures of silicon semiconductor transistors.

[0168] at the same time, FIG. 6 The first electrode C1a is located in the film layer where the first gate layer 125 is located, and the second electrode C1b is located in the film layer where the third gate layer 131 is located, that is, the first electrode C1a is made of the material of the first gate layer 125, and the second electrode C1b is made of the material of the third gate layer 131.

[0169] Meanwhile, the fourth gate layer is not provided in this embodiment, and only two gate layers are required in the non-display area.

[0170] See also FIG. 11 , FIG. 11 This is a film layer structure diagram of the third embodiment of the third gate circuit of this application. FIG. 13 In order FIG. 13 Single-layer film diagram of the first active layer, the first gate layer, the second active layer, the third gate layer, the first source and drain layer, and the second source and drain layer.

[0171] FIGS. 14A-14H The structure in FIG. 13 In the embodiment structure diagram, FIG. 13 The structure and FIG. 4 The structures in are the same or similar, except that FIG. 13 No light shielding layer is provided, so that the first transistor T1 , the second transistor T2 , the fourth transistor T4 , the fifth transistor T5 , and the sixth transistor T6 can all be single-gate structures of silicon semiconductor transistors.

[0172] at the same time, FIG. 6 The first electrode C1a is located in the film layer where the first gate layer 125 is located, and the second electrode C1b is located in the film layer where the second active layer 129 is located, that is, the first electrode C1a is made of the material of the first gate layer 125, and the second electrode C1b is made of the material of the second active layer 129.

[0173] Meanwhile, the fourth gate layer is not provided in this embodiment, and only two gate layers are required in the non-display area.

[0174] See also FIG. 13 , FIG. 6 This is a film layer structure diagram of the first embodiment of the second gate circuit of this application. FIG. 15 In order FIGS. 16A-16F Single-layer film diagram of the middle light-shielding layer, the first active layer, the first gate layer, the second active layer, the third gate layer, the fourth gate layer, the first source-drain layer, and the second source-drain layer.

[0175] FIG. 15 For this application FIG. 15 The embodiment structure diagram in the embodiment structure diagram, that is, the circuit structure diagram of the second gate circuit and the third gate circuit of the present application can be the same. At the same time, FIG. 13 The structure and FIG. 15 The structures in are the same or similar, except that FIG. 13 The size of the transistor and FIG. 15 The transistors in the are different.

[0176] See also FIG. 17 , FIG. 17 This is a film layer structure diagram of the second embodiment of the second gate circuit of this application. FIGS. 18A-18F In order FIG. 17 Single-layer film diagram of the first active layer, the first gate layer, the second active layer, the third gate layer, the first source and drain layer, and the second source and drain layer.

[0177] FIG. 17 The structure in FIG. 13 In the embodiment structure diagram, FIG. 17 The structure and FIG. 13 The structures in are the same or similar, except that FIG. 17 No light shielding layer is provided, so that the first transistor T1 , the second transistor T2 , the fourth transistor T4 , the fifth transistor T5 , and the sixth transistor T6 can all be single-gate structures of silicon semiconductor transistors.

[0178] at the same time, ​ The first electrode C1a is located in the film layer where the first gate layer 125 is located, and the second electrode C1b is located in the film layer where the third gate layer 131 is located, that is, the first electrode C1a is made of the material of the first gate layer 125, and the second electrode C1b is made of the material of the third gate layer 131.

[0179] Meanwhile, the fourth gate layer is not arranged in the embodiment, and only two gate layers are needed in the non-display area.

[0180] Please refer to ​ , ​ The third embodiment of the second gate circuit of the application is shown in the film layer structure diagram. ​ In sequence ​ The single film layer diagram of the first active layer, the first gate layer, the second active layer, the third gate layer, the first source-drain layer and the second source-drain layer in the embodiment.

[0181] ​ The structure in the embodiment is ​ The structure diagram of the embodiment in the embodiment is ​ The structure in the embodiment is the same as or similar to the structure in the embodiment, and the difference is that ​ The light shielding layer is not arranged in the embodiment, so that the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 can all be single-gate structure of silicon semiconductor transistor. ​ Meanwhile,

[0182] The first electrode plate C1a is located in the film layer where the first gate layer 125 is located, and the second electrode plate C1b is located in the film layer where the second active layer 129 is located, that is, the first electrode plate C1a is prepared by using the material of the first gate layer 125, and the second electrode plate C1b is prepared by using the material of the second active layer 129. ​ Meanwhile, the fourth gate layer is not arranged in the embodiment, and only two gate layers are needed in the non-display area.

[0183] It should be noted that the application also proposes a display device, which comprises the display panel described above, and the display device of the application can be any product or component with display function, such as mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator and the like.

[0184] In the description of the application, the terms “first” and “second” are only used for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with “first” and “second” can explicitly or implicitly include one or more features. In the description of the application, the meaning of “multiple” is two or more, unless otherwise specifically limited.

[0185] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0186]

[0187] ​The embodiments, implementation manners and related technical features of the present application can be combined with each other without conflict.

[0188] The above is only a preferred embodiment of the present application, and does not limit the present application in any form. Any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present application without departing from the technical solution content of the present application still falls within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: The device comprises a display area and a non-display area provided on at least one side of the display area, wherein a gate drive circuit is provided in the non-display area, and the gate drive circuit comprises: a first control module; a first output module, electrically connected to the first control module at a first node; a second output module, electrically connected to an output end of the first output module; a second control module electrically connected to the second output module at a second node, and electrically connected to the first output module and the first control module at the first node; and a compensation module, wherein an output end of the compensation module is electrically connected to the first node; The first control module and the second control module are arranged along a first direction, and the compensation module is arranged between the first control module and the second control module. In the second direction, the distance between the boundary of the compensation module away from the display area and the display area is smaller than the distance between the boundary of the first control module and / or the second control module away from the display area and the display area, and the first direction and the second direction intersect.

2. The display panel according to claim 1, wherein The gate drive circuit further includes a third control module, wherein a control terminal of the third control module is electrically connected to the first node, and an output terminal of the third control module is electrically connected to the second node; In which, the third control module is arranged between the compensation module and the first control module, and in the second direction, the distance between the boundary of the third control module away from the display area and the display area is smaller than the distance between the boundary of the first control module and / or the second control module away from the display area and the display area.

3. The display panel according to claim 2, wherein: The gate drive circuit further includes a voltage stabilizing module, wherein an input terminal of the voltage stabilizing module is electrically connected to the first node, an output terminal of the voltage stabilizing module and a control terminal of the first output module are electrically connected to a third node, and the voltage stabilizing module is configured to electrically conduct the first node and the third node; In which, the voltage stabilizing module is arranged between the third control module and the first control module, and in the second direction, the distance between the boundary of the voltage stabilizing module away from the display area and the display area is less than or equal to the distance between the boundary of the first control module away from the display area and the display area.

4. The display panel according to claim 3, wherein: The first control module includes a first transistor; The second control module includes a second transistor, wherein a gate of the second transistor and an output terminal of the first transistor are connected to a first node; The third control module includes a third transistor, and the third transistor includes a first gate and a second gate, the second gate of the third transistor is connected to the input terminal of the third transistor, and the second gate of the third transistor is connected to the first node; The voltage stabilizing module includes a fourth transistor, and an input end of the fourth transistor is connected to the first node; The first output module includes a fifth transistor, wherein the gate of the fifth transistor and the output end of the fourth transistor are connected to the second node; The second output module includes a sixth transistor, the gate of the sixth transistor and the output end of the second transistor and the output end of the third transistor are connected to a third node, and the output end of the sixth transistor and the output end of the fifth transistor are connected to the output ends of corresponding gate circuits; The compensation module includes a seventh transistor, and the seventh transistor includes a first gate and a second gate, the first gate of the seventh transistor is electrically connected to the input end of the seventh transistor, the second gate of the seventh transistor is electrically connected to the second node, and the output end of the seventh transistor is electrically connected to the first node.

5. The display panel according to claim 4, wherein: The display panel includes: substrate; a first gate layer, disposed on one side of the first gate layer, the first gate layer including a gate of the first transistor, a gate of the second transistor, a first gate of the third transistor, a gate of the fourth transistor, and a first gate of the seventh transistor, wherein the first gate of the third transistor, the gate of the fourth transistor, and the first gate of the seventh transistor are connected; a second gate layer, disposed on a side of the first gate layer away from the base substrate; a third gate layer, provided on a side of the third gate layer away from the base substrate, the third gate layer including the second gate of the third transistor and the second gate of the seventh transistor; Among them, the gate of the first transistor, the gate of the fourth transistor, the first gate of the third transistor, the first gate of the seventh transistor, and the gate of the second transistor all extend along the second direction and are arranged along the first direction, and the second gate of the third transistor and the second gate of the seventh transistor all extend along the second direction and are arranged at intervals along the first direction, the first gate and the second gate of the third transistor overlap, and the first gate and the second gate of the seventh transistor overlap.

6. The display panel according to claim 5, wherein: The widths of the first gate of the third transistor and the first gate of the seventh transistor are both greater than the widths of the gate of the first transistor, the gate of the second transistor, the gate of the fourth transistor, the second gate of the third transistor, and the second gate of the seventh transistor.

7. The display panel according to claim 4, wherein: The display panel includes a first active layer, wherein the first active layer includes an active pattern of a first transistor, an active pattern of a second transistor, and an active pattern of a fourth transistor extending along the first direction; The active pattern of the first transistor is connected to the active pattern of the fourth transistor, and the active pattern of the fourth transistor is spaced apart from the active pattern of the second transistor. 8 . The display panel according to claim 7 , wherein a width of the active pattern of the first transistor is equal to a width of the active pattern of the fourth transistor, and a width of the active pattern of the fourth transistor is greater than a width of the active pattern of the second transistor.

9. The display panel according to any one of claims 1 to 8, wherein: The gate drive circuit further includes a first capacitor, the first capacitor including a first plate and a second plate, the first plate being electrically connected to the first node, and the second plate being electrically connected to the output end of the first output module; The display panel includes a base substrate, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, and a fourth gate layer provided on the base substrate, the first electrode is located in the film layer where the first gate layer is located, and the second electrode is located in the film layer where the third gate layer or the second active layer is located; Alternatively, the first electrode plate is located in the film layer where the third gate layer is located, and the second electrode plate is located in the film layer where the fourth gate layer is located.

10. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 9.

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