Array substrate, display panel and display device

Abstract

The invention discloses an array substrate, a display panel and a display device, and the array substrate comprises a plurality of grid signal lines which are at least partially located in a display area, extend in a first direction and are arranged at intervals in a second direction; the shifting register group is located in the non-display area and comprises a plurality of shifting register units cascaded in the second direction, and each unit comprises an interface end and signal outgoing lines electrically connected with the interface end in a one-to-one mode; signal leading-out sections of the plurality of functional signal lines extend along a second direction and are connected to the terminal area, at least one functional signal line is configured as a test signal line, a signal leading-out section of the test signal line is provided with a first reserved welding point, and a signal leading-out line extends to the first reserved welding point; and the test signal line can be welded with the signal lead-out line at the target row position so as to lead out the interface end signal to the terminal area. According to the scheme, by arranging the signal outgoing line and the welding point, the internal signal of the gate drive circuit can be directly led out to the test point without disassembling the screen, and the fault analysis efficiency and precision are improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] Display panels are typically equipped with a gate drive circuit, typically composed of multiple cascaded shift registers. The gate drive circuit can be used to provide electrical signals to scan lines to control the conduction or cutoff of thin-film transistors in sub-pixels electrically connected to the scan lines.

[0003] When reliability risk issues occur, it is often necessary to test the gate drive circuit. The current mainstream testing method is to disassemble the screen and test the relevant waveforms for analysis. How to shorten the analysis time and improve the analysis accuracy is a technical problem faced by technical personnel in this field. Summary of the Invention

[0004] The embodiments of the present application provide an array substrate, a display panel, and a display device, which can test the signal waveform of internal circuits without disassembling the screen, thereby shortening the analysis time and improving the analysis accuracy.

[0005] In a first aspect, an embodiment of the present application provides an array substrate having a display area and a non-display area at least partially surrounding the display area, the non-display area including a terminal area, the array substrate including: a substrate; a plurality of gate signal lines, at least partially located in the display area, the plurality of gate signal lines extending along a first direction and arranged at intervals along a second direction, the first direction intersecting the second direction; a shift register group, located in the non-display area, the shift register group including a plurality of shift register units cascaded along the second direction, each shift register unit including a plurality of interface terminals, the interface terminals including an output terminal, the output terminal being electrically connected to the corresponding gate signal line The shift register unit further includes at least one signal lead-out line, which is electrically connected to the interface end in a one-to-one correspondence; a plurality of functional signal lines, wherein the signal lead-out section in the functional signal line extends at least partially along the second direction, and the signal lead-out section is connected to the terminal area, at least one functional signal line is configured as a test signal line, and the test signal line further includes a plurality of first reserved fusion points located in the signal lead-out section, the signal lead-out line extends to the position of the first reserved fusion point, and the test signal line can be fused and electrically connected to the signal lead-out line at the target row position, so that the signal of the corresponding interface end is led out to the terminal area by the test signal line.

[0006] The array substrate provided by the first aspect embodiment of the present application improves the efficiency and reliability of abnormal detection of the gate test circuit, the signal lead-out line is arranged in the shift register unit of the non-display area, and is extended to the first reserved fusion point of the functional signal line, the signal lead-out section of the test signal line further leads out the signal of the interface end to the terminal area, direct external access to the signal of the interface end in the gate drive circuit is realized, the target row signal is led out to the terminal area test point through the fusion technology without disassembling the screen, and the sample damage risk and time loss caused by traditional disassembly detection are avoided.

[0007] Secondly, the design of multiplexing the functional signal line as the test signal line fully utilizes the redundant line resource of the panel frame area, through the cooperative layout of the signal lead-out section extending along the second direction and the first reserved fusion point, the additional wiring is avoided to occupy the space of the display area, and the independence and anti-interference of the test signal path are ensured, which is especially suitable for the high integration requirement of the thinned and narrow frame panel.

[0008] In addition, the cascaded structure of the shift register unit and the test signal line supports accurate positioning row by row, in combination with the dynamic conduction mechanism of the first reserved fusion point, a directional detection channel can be quickly established for the shift register unit of the abnormal row, the problems of serious signal attenuation and low positioning accuracy of the traditional edge sampling technology are solved, and the fault analysis accuracy and efficiency are significantly improved.

[0009] Secondly, the design of multiplexing the functional signal line as the test signal line fully utilizes the redundant line resource of the panel frame area, through the cooperative layout of the signal lead-out section extending along the second direction and the first reserved fusion point, the additional wiring is avoided to occupy the space of the display area, and the independence and anti-interference of the test signal path are ensured, which is especially suitable for the high integration requirement of the thinned and narrow frame panel.

[0010] Thirdly, the display device provided by the third aspect embodiment of the present application also includes the display panel provided by any one of the second aspect embodiments of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0011] The features, advantages, and technical effects of the exemplary embodiments of the present application will be described below with reference to the accompanying drawings.

[0012] Figure 1 is a plane structure schematic diagram of an array substrate provided by the first aspect embodiment of the present application;

[0013] Figure 2 is a plane structure schematic diagram of another array substrate provided by the first aspect embodiment of the present application;

[0014] Figure 3 is a plane structure schematic diagram of another array substrate provided by the first aspect embodiment of the present application;

[0015] Figure 4 is Figure 3 a layout at a virtual pixel circuit in

[0016] Figure 5 is Figure 4 a cross-sectional structure schematic view of the layout shown in FIG. 1 along the direction of A-A;

[0017] Figure 6 is Figure 1 an equivalent circuit diagram at the shift register unit in FIG. 2;

[0018] Figure 7 is Figure 1 another equivalent circuit diagram at the shift register unit in FIG. 3;

[0019] Figure 8 is Figure 1 still another equivalent circuit diagram at the shift register unit in FIG. 4;

[0020] Figure 9 is a cross-sectional structure schematic view of a test signal line of an array substrate provided by an embodiment of the first aspect of the present application;

[0021] Figure 10 is a plane structure schematic view of a display panel provided by an embodiment of the second aspect of the present application;

[0022] Figure 11 is a structure schematic view of a display device provided by an embodiment of the third aspect of the present application.

[0023] wherein:

[0024] 100-array substrate; 101-wiring layer; 102-insulating layer; AA-display area; NA-non-display area; BA-terminal area; SS-substrate;

[0025] 10-gate signal line;

[0026] 20-shift register group; VSR-shift register unit; 21-output module; 22-noise reduction module; Gout-output terminal; PU-first signal terminal; PD-second signal terminal; 24-signal lead-out line;

[0027] 30-functional signal line; 301-signal lead-out segment; 301a-straight-out sub-segment; 301b-fan-out sub-segment; 302-signal driving segment; 31-control signal line; 311-first control signal sub-line; 312-second control signal sub-line; 32-data signal line; 321-virtual signal line;

[0028] Test-test signal line; S1-first reserved fusion point; S2-second reserved fusion point;

[0029] 40-virtual pixel circuit; 41-fusion block;

[0030] 50-signal terminal;

[0031] 200-display panel;

[0032] 300-display device;

[0033] X-first direction; Y-second direction.

[0034] In the drawings, like parts are given like reference numerals, but the drawings are not necessarily drawn to scale. DETAILED DESCRIPTION

[0035] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0036] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0037] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0038] It should be noted that the transistor in the embodiments of the present application can be an N-type transistor or a P-type transistor. For the N-type transistor, the on level is high level and the off level is low level. That is, when the gate of the N-type transistor is high level, the first electrode and the second electrode of the N-type transistor are turned on, and when the gate of the N-type transistor is low level, the first electrode and the second electrode of the N-type transistor are turned off. For the P-type transistor, the on level is low level and the off level is high level. That is, when the control electrode of the P-type transistor is low level, the first electrode and the second electrode of the P-type transistor are turned on, and when the control electrode of the P-type transistor is high level, the first electrode and the second electrode of the P-type transistor are turned off. In the specific implementation, the gate of each transistor is used as the control electrode thereof, and according to the signal of the gate of each transistor and the type of the transistor, the first electrode can be used as the source electrode and the second electrode can be used as the drain electrode, or the first electrode can be used as the drain electrode and the second electrode can be used as the source electrode, which is not distinguished herein. In addition, the on level and the off level in the embodiments of the present application are generic, the on level refers to any level that can turn on the transistor, and the off level refers to any level that can turn off / turn off the transistor.

[0039] In the embodiments of the present application, the term "electrically connected" can refer to that two components are directly electrically connected, or that two components are electrically connected via one or more other components.

[0040] In the embodiments of the present application, the first node, the second node and the third node are only defined for the convenience of describing the circuit structure, and the first node, the second node and the third node are not an actual circuit unit.

[0041] Various modifications and changes can be made to the present application in light of the foregoing without departing from the spirit or scope of the present application, which is defined in the appended claims. Accordingly, the present application is intended to embrace all such modifications and changes that fall within the scope of the corresponding claims (claimed technical solutions) and their equivalents. It should be noted that the embodiments provided by the present application can be combined with each other without contradiction.

[0042] Before the technical solutions provided by the embodiments of the present application are described, in order to facilitate the understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0043] In the related art, with the rapid development of display technology, the Gate on Array (GOA) technology can directly integrate the driving circuit in the display panel, significantly reducing the dependence on external driving chips, and gradually becoming the core technology of high-resolution and narrow-frame display products.

[0044] The conventional GOA circuit outputs the gate driving signal row by row through cascaded shift register units to achieve accurate control of a thin film transistor (TFT) array.

[0045] However, in the actual application of the display panel, the GOA circuit is prone to signal abnormalities due to process deviation, material aging or external interference, such as timing offset, voltage fluctuation or node failure of the output signal (Gout) of the GOA circuit. Such faults directly manifest as screen display abnormalities, such as horizontal lines, flickering or local brightness unevenness, which seriously affect product reliability and user experience.

[0046] For fault detection of the GOA circuit, the related art has long relied on physical detection methods of disassembling the screen.

[0047] Specifically, when the display panel has abnormalities in the reliability test (RA) or actual use, the color filter (CF) layer or other light improvement layers need to be peeled off by mechanical or laser means to expose the underlying TFT array, and then the wave form data is collected by contacting specific signal lines such as the Gout node, the pull up (PU) node and the pull down (PD) node through a probe.

[0048] However, as the display panel evolves towards thinness and flexibility, the thickness of the glass substrate or flexible substrate has been greatly reduced, and the physical disassembly process is prone to cause substrate breakage or line damage, resulting in a significant increase in sample scrap rate.

[0049] In addition, the disassembly operation takes a long time, and each detection takes several hours, which seriously slows down the fault analysis efficiency.

[0050] More importantly, secondary damage may be introduced due to environmental disturbance after disassembly, which causes deviation between the detection results and the real fault mode, further reducing the accuracy of problem positioning.

[0051] The key signal nodes of the GOA circuit, such as the PU node, the PD node and the Gout node, are usually located at the bottom layer of the TFT array and are completely covered by the CF layer or other light improvement layers and packaging structures of the upper layer.

[0052] On the one hand, if the real-time waveforms of these nodes are to be directly obtained, the upper layer structure must be destructively removed, which not only has high technical difficulty, but also makes it difficult to completely restore the signal path due to the complexity of the panel structure.

[0053] On the other hand, existing non-destructive detection techniques, such as edge signal sampling, are limited by signal attenuation and noise interference, and can only indirectly infer the internal node state, and cannot accurately locate the abnormal row or failed device.

[0054] For example, some solutions attempt to indirectly collect signals through reserved test points (Test Pad) on the edge of the panel. However, such test points are usually only connected to the control signal lines used to control the global potential signals, and cannot directly access the internal nodes of each level of shift register, such as the PU / PD voltage signals. This results in rough detection accuracy and makes it difficult to meet the needs of high-precision fault diagnosis.

[0055] In addition, redundant circuits widely used in display panel design, such as dummy data signal lines (Dummy Data) and switch signal lines (Switch, SW), can be used to assist in detection, but there is a contradiction between their regular functions and test requirements.

[0056] For example, dummy data is floating during normal display to avoid interfering with image data, but its potential testing value remains untapped. Furthermore, some control signal lines, such as SW signals, while capable of dynamic switching, lack direct connections to internal nodes. This inefficient resource utilization further exacerbates the limitations of detection solutions.

[0057] At the same time, the parasitic capacitance effect and signal crosstalk caused by multi-layer metal routing make the external test signal easily distorted during transmission, resulting in reduced credibility of the test results.

[0058] In summary, the core contradiction in the existing technology of GOA circuit detection lies in the insufficient accuracy of non-destructive detection methods and the low engineering feasibility of destructive detection.

[0059] This key issue is particularly prominent in thin, narrow-frame, and flexible panels, becoming a key obstacle to improving display product yields and rapidly analyzing faults. Therefore, there is an urgent need for an array substrate that includes test circuitry that can directly access the internal nodes of the GOA circuit and achieve high-precision signal acquisition without disassembling the display.

[0060] In order to solve the above-mentioned technical problems and meet technical needs, the embodiments of the present application provide an array substrate, a display panel and a display device.

[0061] The following will be combined Figures 1 to 11 The array substrate, display panel and display device provided in the embodiments of the present application are described in detail.

[0062] Figure 1 The planar structure of an array substrate provided by the embodiment of the first aspect of the present application is shown. Figure 2 FIG2 shows a planar structure of another array substrate provided by an embodiment of the first aspect of the present application. Figure 3The planar structure of another array substrate provided by the first aspect of the application is shown.

[0063] Please refer to Figures 1 to 3 In the first aspect, the array substrate 100 provided by the embodiments of the application has a display area AA and a non-display area NA surrounding the display area AA at least partially, and the non-display area NA includes a terminal area BA. The array substrate 100 includes a substrate SS, a plurality of gate signal lines 10, a shift register group 20, and a plurality of functional signal lines 30.

[0064] The substrate SS serves as a basic support structure in the array substrate 100 and provides a support carrier for other array circuits.

[0065] The plurality of gate signal lines 10 are located at least partially in the display area AA, extend along a first direction X, and are arranged at intervals along a second direction Y. The first direction X intersects the second direction Y.

[0066] The shift register group 20 is located in the non-display area NA. The shift register group 20 includes a plurality of shift register units VSR cascaded along the second direction Y. Each shift register unit VSR includes a plurality of interface ends, and the interface ends include an output end Gout. The output end Gout is electrically connected to a corresponding gate signal line 10. The shift register unit VSR further includes at least one signal lead-out line 24, which is electrically connected to the interface ends one by one.

[0067] The plurality of functional signal lines 30, and a signal lead-out segment 301 in the functional signal line 30 extends at least partially along the second direction Y and is connected to the terminal area BA. At least one functional signal line 30 is configured as a test signal line Test. The test signal line Test further includes a plurality of first reserved fusion points S1 located at the signal lead-out segment 301. The signal lead-out line 24 extends to the position of the first reserved fusion point S1. The test signal line Test can be electrically connected to the signal lead-out line 24 at a target row position to lead the signal of the corresponding interface end to the terminal area BA.

[0068] The array substrate 100 provided by the first aspect of the application improves the efficiency and reliability of the abnormal detection of the gate test circuit. By setting the signal lead-out line 24 in the shift register unit VSR in the non-display area NA and extending it to the first reserved fusion point S1 of the test signal line Test, the signal lead-out segment 301 of the test signal line Test further leads the signal of the interface end to the terminal area BA, which realizes the direct external access to the signal of the interface end in the gate driving circuit. The target row signal can be led out to the terminal area BA for testing through the fusion technology without disassembling the screen, which avoids the sample damage risk and time loss caused by the traditional disassembly detection.

[0069] Secondly, the design of multiplexing part of the functional signal lines 30 as the test signal lines Test makes full use of the redundant line resources of the panel frame area, and through the cooperative layout of the signal lead-out segments 301 extending along the second direction Y and the first reserved fusion points S1, the additional wiring is avoided to occupy the space of the display area AA, and the independence and anti-interference of the test signal path are ensured, which is especially suitable for the high integration requirement of thinning and narrow frame panel.

[0070] In addition, the cascaded structure of the shift register units VSR and the test signal lines Test supports precise positioning row by row, and in combination with the dynamic conduction mechanism of the first reserved fusion points S1, a directional detection channel can be quickly established for the shift register units VSR of the abnormal row, solving the problems of serious signal attenuation and low positioning accuracy of the traditional edge sampling technology, and significantly improving the fault analysis accuracy and efficiency.

[0071] The array substrate 100 includes a plurality of gate signal lines 10 extending along the first direction X and spaced apart along the second direction Y, which are at least partially distributed in the display area AA, for driving the pixel units row by row.

[0072] The shift register group 20 is arranged in the non-display area NA and is composed of a plurality of shift register units VSR cascaded along the second direction Y. Each shift register unit VSR includes a plurality of interface terminals, such as an output terminal Gout, a clock signal terminal, and a reset terminal. The interface terminal is defined as a signal input or output node of the internal circuit of the shift register unit VSR, and is not an independent circuit unit, but a functional concept for describing the connection relationship of the circuit.

[0073] The output terminal Gout is directly electrically connected with the corresponding gate signal line 10, ensuring the row-by-row transmission of the gate drive signal.

[0074] Each shift register unit VSR also integrates at least one signal lead-out line 24, which is connected with the interface terminals one by one to form a signal path from the internal circuit node to the outside.

[0075] The functional signal lines 30 are distributed in the non-display area NA, and the signal lead-out segments 301 thereof extend along the second direction Y and are connected to the terminal area BA. The terminal area BA is usually located on both sides of the display area AA along the second direction Y, but the layout can be adjusted according to actual design requirements.

[0076] At least one functional signal line 30 is configured as a test signal line Test, a signal leading-out segment 301 of which is provided with a plurality of first reserved fusion points S1, and the signal leading-out line 24 extends to the position of the fusion point. When the shift register unit VSR of the target row is abnormal, the test signal line Test is connected with the signal leading-out line 24 of the row by fusion technology, so that the signal at the interface end is led out to the test point of the terminal area BA through the test signal line Test, and non-destructive detection is realized.

[0077] Specifically, the interface end is a signal interaction node of the shift register unit VSR, and is directly associated with the functional modules inside the shift register unit VSR. The signal leading-out line 24 is physically connected with the interface end through metal wiring, forming a directional path from the circuit core to the outside.

[0078] The test signal line Test in the functional signal line 30 multiplexes the redundant line resources of the panel frame area, such as the idle control signal line or the virtual data line. The layout design of the signal leading-out segment 301 extending along the second direction Y is adapted to the setting position of the terminal area BA, facilitating the signal leading-out to the terminal area BA, avoiding the occupation of the display area AA space, and ensuring the independence and anti-interference ability of the signal transmission path, especially adapting to the high-density wiring demand of the thinned and narrow-frame panel.

[0079] Exemplarily, the first reserved fusion point S1 is located at the signal leading-out segment 301 of the test signal line Test, and the connection with the signal leading-out line 24 of the target row is realized through laser welding or local heating fusion technology.

[0080] Exemplarily, the fusion operation is performed from the side of the array substrate 100 away from the light-emitting side of the entire display panel. The heating position is accurate and the welding point is small, and the influence on the surrounding circuit is negligible, meeting the conventional test process requirements.

[0081] The cascade structure of the shift register unit VSR combined with the dynamic connection mechanism of the fusion point supports the accurate positioning of the abnormal signal source row by row, and effectively solves the problems of signal attenuation and positioning ambiguity caused by the long path in the traditional edge signal sampling technology, significantly improving the detection accuracy and efficiency.

[0082] Exemplarily, the first direction X and the second direction Y are perpendicular to each other. In fact, the relative position relationship between the first direction X and the second direction Y is not specifically limited in the embodiments of the present application, as long as the first direction X and the second direction Y intersect.

[0083] The specific embodiments of the functional signal line 30 arranged at different positions will be further described in subsequent other embodiments of the first aspect of the present application.

[0084] Please refer to Figure 1 and Figure 2In some embodiments, the functional signal lines 30 include control signal lines 31, which are located in the non-display area NA and on the side of the shift register group 20 away from the display area AA. The elements in the shift register unit VSR are electrically connected to the corresponding control signal lines 31. At least one control signal line 31 is configured as a test signal line Test.

[0085] In these embodiments, the functional signal lines 30 include control signal lines 31, which are located in the non-display area NA and distributed on the side of the shift register group 20 away from the display area AA. The control signal lines 31 are used as special lines in the frame area of the display panel 200 to conduct various test signals, such as clock signals, reset signals, or voltage monitoring signals. The control signal lines 31 are not independent functional modules, but are integrated into the signal transmission channel in the non-display area NA.

[0086] The elements in the shift register unit VSR are electrically connected to the control signal lines 31, which are configured as the test signal lines Test. When the shift register unit VSR in the target row needs to be detected, the control signal lines 31 form a signal path from the internal circuit to the frame area and the terminal area BA.

[0087] The preset electrical connection means that at least one control signal line 31 is configured as a test signal line Test. The signal lead-out segment 301 of the test signal line Test extends to the terminal area BA along the second direction Y and a plurality of first reserved fusion points S1 are provided in this segment.

[0088] When the shift register unit VSR in the target row is abnormal, the test signal line Test is connected to the signal lead-out line 24 in this row through laser or heating fusion technology, so that the signals at the interface end are accurately led out to the test points in the terminal area BA through the test signal line Test.

[0089] By multiplexing the existing control signal lines 31 in the frame area, the additional wiring for the display area AA is avoided, and the physical isolation layout of the shift register group 20 and the test signal line Test is used to reduce signal crosstalk and ensure the independence of the detection path.

[0090] The fusion operation is performed from the side of the array substrate 100 on the non-light-emitting side of the display panel 200 product. The solder points are small and accurately positioned, and have negligible impact on the surrounding circuit, which is suitable for the testing needs of high-integration panels.

[0091] Alternatively, the idle lines in the control signal lines 31 are further enabled, and the idle lines in the control signal lines 31 are configured as the test signal lines Test in the special test lines for the shift register unit VSR.

[0092] The configuration of the test signal line Test in the control signal line 31 will be further described in the subsequent other embodiments in the first aspect of the application.

[0093] Please refer to Figure 1 In some embodiments, the control signal line 31 includes a first control signal sub-line 311 configured as the test signal line Test, which is electrically connected to the signal lead-out line 24 of the target row position by fusion in the abnormality detection working condition, and the signal of the corresponding interface end is led out to the terminal area BA by the first control signal sub-line 311.

[0094] In these embodiments, the control signal line 31 includes a first control signal sub-line 311 configured as the test signal line Test, which is located in the non-display area NA and extends to the terminal area BA along the second direction Y.

[0095] The first control signal sub-line 311 is the original idle line of the frame area, which does not participate in the transmission of functional signals in normal display, and is only temporarily activated by fusion technology in the abnormality detection working condition.

[0096] The signal lead-out line 24 of the shift register unit VSR extends from the interface end through the signal lead-out line 24 to the first reserved fusion point S1 of the first control signal sub-line 311, forming a potential signal path.

[0097] When the target row is abnormal, the fusion point is precisely welded from the non-light-emitting side of the array substrate 100 by laser or local heating, so that the first control signal sub-line 311 is conductive with the signal lead-out line 24 of the shift register unit VSR of the row, thereby directly leading out the interface end signal to the test point of the terminal area BA.

[0098] The first control signal sub-line 311 uses the idle wiring resources in the non-display area NA, avoiding the additional occupation of the display area AA space. The layout of the first control signal sub-line 311 away from the display area AA further reduces the crosstalk in the signal transmission process, ensuring the independence and signal integrity of the detection path.

[0099] The fusion operation is only for the specific fusion point of the target row, the welding point size is small and the positioning is accurate, which has no significant influence on the surrounding circuit, and is suitable for the process requirements of high-precision panels.

[0100] Please refer to Figure 2In some embodiments, the control signal line 31 further comprises a second control signal sub-line 312 originally configured as a display detection signal line. In the abnormality detection mode, at least one second control signal sub-line 312 is multiplexed as a test signal line Test. The second control signal sub-line 312 is fused with the signal lead-out line 24 at the target row position to realize electrical connection, and the signal of the corresponding interface end is led out to the terminal area BA by the second control signal sub-line 312.

[0101] In these embodiments, the control signal line 31 further comprises a second control signal sub-line 312 originally configured as a display detection signal line, such as a VT (Voltage Test) for a liquid crystal display panel 200 (LCD) or a CT (Current Test) for an organic light emitting diode display panel 200 (OLED). The line of the second control signal sub-line 312 extends from the non-display area NA around the display area AA to the terminal area BA and keeps the complete detection loop intact.

[0102] In the abnormality detection mode, at least one second control signal sub-line 312 is multiplexed as a test signal line Test. The second control signal sub-line 312 is fused with the signal lead-out line 24 at the target row position to realize electrical connection, and the signal of the corresponding interface end is led out to the terminal area BA by the second control signal sub-line 312.

[0103] Specifically, the second control signal sub-line 312 extends along the second direction Y in the non-display area NA. The signal lead-out segment 301 of the second control signal sub-line 312 is provided with a first reserved fusion point S1. The signal lead-out line 24 extends from the interface end of the shift register unit VSR to the first reserved fusion point S1, forming a potential connection path.

[0104] The fusion operation is implemented from the side of the array substrate 100 on the non-light-emitting side of the display panel 200 product. The fusion point of the target row is accurately positioned, and directional conduction is established through a small solder joint to avoid interference with the surrounding circuit.

[0105] The multiplexing design of the second control signal sub-line 312 fully utilizes the physical resources of the original detection line. Without the need for additional wiring, the test function can be realized, which is particularly suitable for the narrow frame demand of high-integration panels.

[0106] At the same time, the complete reserved line path of the second control signal sub-line 312 ensures the independence and low attenuation characteristics of signal transmission, solving the noise interference problem caused by temporary flying wires in traditional detection.

[0107] Please refer to Figure 3In some embodiments, the functional signal line 30 further comprises a data signal line 32, the data signal line 32 being located in the display area AA, and at least one data signal line 32 is configured as a test signal line Test.

[0108] When in the abnormality detection mode, the data signal line 32 is fused with the gate signal line 10 at the target row position to achieve electrical connection, and the signal at the output end Gout is led out to the terminal area BA via the gate signal line 10 and the data signal line 32.

[0109] In these embodiments, through the function switching of the gate signal line 10 and the data signal line 32, a high-precision and low-cost internal signal detection path of the gate circuit is provided while maintaining the display performance.

[0110] Exemplarily, part of the data signal lines 32 are distributed as redundant resources at the edge of the display area AA, and are in a floating state to avoid interfering with image data transmission during normal display, and part of them extending along the second direction Y as signal leading-out segments 301 extend to the edge of the display area AA and are provided with first reserved fusion points S1.

[0111] The signal leading-out line 24 is directly connected to the output end Gout of the shift register unit VSR by using the existing gate signal line 10 at the target row position due to the limited layout space of the array line in the display area AA, so the signal at the output end can be directly detected.

[0112] The signal leading-out line 24 of the shift register unit VSR extends from the interface end to the position of the first reserved fusion point S1. When an abnormality occurs in the target row, the first reserved fusion point S1 is accurately welded from the array substrate 100 on the same side as the non-light-emitting side in the display panel 200 product by laser or precise heating operation, so that the data signal line 32 is conducted with the signal leading-out line 24 of the row, thereby leading the interface end signal out to the terminal area BA test port through the data signal line 32.

[0113] The data signal line 32 multiplexes part of the redundant data signal line 32 resources at the edge of the display area AA, which not only avoids the compression of the pixel aperture ratio caused by the addition of test wiring, but also reduces signal attenuation by using the inherent low-impedance characteristics of the data signal line 32.

[0114] The first reserved fusion point S1 is arranged at the edge of the display area AA, and does not need to penetrate the display functional layer during operation, ensuring that the detection process has no effect on the picture.

[0115] Please continue to refer to Figure 3In some embodiments, the data signal line 32 includes a virtual signal line 321, at least one virtual signal line 321 is configured as a test signal line Test, when in an abnormality detection working condition, the virtual signal line 321 is fused with the gate signal line 10 at the target row position to achieve electrical connection, and the signal of the output terminal Gout is led out to the terminal area BA by the gate signal line 10 and the virtual signal line 321.

[0116] In these embodiments, by using the gate signal line 10 and the redundant virtual signal line 321, a high-precision, low-cost internal signal detection path of the gate circuit is provided while maintaining display performance.

[0117] Further, the virtual signal line 321 in the data signal line 32 is distributed at the edge of the display area AA as a redundant resource, and is in a floating state during normal display to avoid interfering with image data transmission, and the part extending along the second direction Y as a signal leading segment 301 extends to the edge of the display area AA and is provided with a first reserved fusion point S1 at the position overlapping with the gate signal line.

[0118] The signal of the shift register unit VSR is transmitted to the first reserved fusion point S1 position through the gate signal line 10.

[0119] When an abnormality occurs in the target row, the first reserved fusion point S1 is accurately welded from the same side of the array substrate 100 as the non-light-emitting side of the display panel 200 product by laser or precise heating operation, so that the virtual signal line 321 is conductive with the gate signal line 10 of the row, thereby leading the interface terminal signal to the terminal area BA test port through the virtual signal line 321.

[0120] The data signal line 32 multiplexes the part of the redundant virtual signal line 321 resource at the edge of the display area AA, which not only avoids the compression of the pixel aperture ratio caused by the addition of test wiring, but also reduces signal attenuation by using the inherent low impedance characteristics of the virtual signal line 321.

[0121] The first reserved fusion point S1 is provided at the edge of the display area AA, and does not need to penetrate the display functional layer during operation, ensuring that the detection process has no effect on the picture.

[0122] Please refer to Figures 1 to 3In some embodiments, the functional signal line 30 includes a control signal line 31 located in the non-display area NA, and a signal driving segment 302 in the control signal line 31 extends along the first direction X and is arranged at intervals along the second direction Y in the non-display area NA. The control signal line 31 includes a second control signal sub-line 312 configured to drive a switch circuit, and the second control signal sub-line 312 further includes a second reserved fusion point S2 located at the signal driving segment 302. A virtual signal line 321 configured as a test signal line Test also extends to the position of the second reserved fusion point S2. In an abnormality detection working condition, the virtual signal line 321 is fused with the second reserved fusion point S2 to achieve electrical connection. The second control signal sub-line 312 inputs an on-level signal, and the signal of the data signal line 32 is led out by the virtual signal line 321.

[0123] In these embodiments, the second control signal sub-line 312 serves as a driving switch circuit for inputting an on-level signal, and the signal driving segment 302 is provided with a second reserved fusion point S2. The virtual signal line 321 configured as a test signal line Test extends from the edge of the display area AA to the non-display area NA and is aligned with the position of the second reserved fusion point S2. In an abnormality detection working condition, the virtual signal line 321 is fused with the second reserved fusion point S2 by laser or local heating to conduct, while the second control signal sub-line 312 inputs an on-level signal to activate the driving switch function, so that the signal of the target data signal line 32 is led out to the terminal area BA test port through the virtual signal line 321.

[0124] The virtual signal line 321 serves as a redundant line on the periphery of the display area AA and is in a floating state in normal operation. The signal leading-out segment 301 extends along the second direction Y to the terminal area BA in the non-display area NA and forms a potential connection path with the data signal line 32 through the second reserved fusion point S2.

[0125] The second control signal sub-line 312 serves as an original function driving switch, and controls the on-off state of the corresponding data signal line 32 by inputting an on-level signal, thereby bypassing the intermediate line level that cannot be directly accessed in traditional testing.

[0126] By multiplexing the cooperative layout of the control signal line 31 and the virtual signal line 321, the detection range is expanded to part of the deep-level data signal path without adding new lines, solving the problem of signal unreachability caused by wiring limitations.

[0127] The fusion operation precisely acts on the fusion point at the edge of the display area AA, and the small welding point is located at the edge of the display area AA, avoiding interference with picture display, while retaining the driving switch control ability of the original second control sub-line for the data signal line 32.

[0128] Figure 4 It is shown thatFigure 3 The layout of the virtual pixel circuit 40 in FIG. Figure 5 Shown Figure 4 The cross-sectional structure of the layout along the AA direction is shown.

[0129] See also Figure 4 and Figure 5 In some embodiments, the array substrate 100 further includes a plurality of virtual pixel circuits 40 located in the display area AA and arranged along the second direction Y. The virtual signal line 321 passes through the virtual pixel circuit 40. The first reserved welding point S1 is located at the position of the virtual pixel circuit 40. A welding block 41 is provided in the virtual pixel circuit 40. Under abnormal detection conditions, the virtual signal line 321 is welded to the signal lead line 24 at the target row position through the welding block 41 to achieve electrical connection.

[0130] In these embodiments, the array substrate 100 is provided with a plurality of dummy pixel circuits 40 arranged along the second direction Y at the edge of the display area AA. The dummy pixel circuits 40 have a structure similar to that of actual pixel circuits but have no display function and are mainly used for process uniformity compensation.

[0131] The dummy signal line 321 passes through the inside of the dummy pixel circuit 40 , and its first reserved welding point S1 is located at a position where it overlaps with the gate signal line 10 in the dummy pixel circuit 40 , and a welding block 41 is integrated at this position.

[0132] The welding block 41 is made of a highly conductive metal, has a size greater than the width of the data signal line 32 , and covers a specific area of ​​the dummy pixel circuit 40 .

[0133] Under abnormal detection conditions, the welding block 41 of the target row is precisely welded from the side of the array substrate 100 that is on the same layer as the non-light-emitting side by laser or local heating, so that the virtual signal line 321 is connected to the gate signal line 10, thereby leading the output terminal Gout signal of the shift register unit VSR to the terminal area BA through the gate signal line 10 and the virtual signal line 321.

[0134] In this design, the welding block 41 solves the welding reliability problem caused by the thin line width of the data signal line 32 by expanding the contact area and enhancing the structural stability, thereby avoiding signal distortion caused by solder point offset or poor contact.

[0135] The layout of the dummy pixel circuit 40 not only retains the original process balance function, but also provides a physical support platform for the welding operation, ensuring the precise alignment of the first reserved welding point S1 and the gate signal line 10 .

[0136] Please continue reading Figure 4 and Figure 5In some embodiments, the fusing block 41 is arranged in the same layer as the virtual signal line 321 and is connected to each other, and the orthogonal projection of the fusing block 41 on the substrate SS at least partially overlaps with the orthogonal projection of the gate signal line 10 on the substrate SS.

[0137] In these embodiments, the fusing block 41 is arranged as an extension of the virtual signal line 321 in the same layer, and the position relationship of the overlapping of the orthogonal projection of the fusing block 41 and the gate signal line 10 further reduces the difficulty of the fusing operation.

[0138] The fusing block 41 is arranged in the same layer as the virtual signal line 321, the fusing block 41 is composed of a highly conductive metal, and the orthogonal projection covers part of the area of the gate signal line 10 and extends to one side of the virtual signal line 321 and is connected to the virtual signal line 321.

[0139] In the abnormal detection working condition, the laser or heating fusing operation precisely acts on the fusing block 41 from the same side of the array substrate 100 and the non-light-emitting side, and through local high temperature, the corresponding metal layer of the fusing block 41 and the gate signal line 10 are fused and combined to form a stable conduction path, so that the signal of the output terminal Gout is transmitted to the terminal area BA through the virtual signal line 321.

[0140] In the virtual pixel circuit 40, the active layer is removed, but the insulating layer on both sides of the active layer is retained, providing a flat substrate support for the fusing block 41.

[0141] The material and structure of the fusing block 41 compatible with the normal pixel process ensure that the fusing block 41 can be prepared and formed synchronously with the virtual signal line 321 in the display panel process without additional process steps.

[0142] Exemplarily, the gate signal line 10 is located on the side of the active layer away from the substrate SS, and the virtual pixel circuit 40 adopts a top gate structure.

[0143] Alternatively, the gate signal line 10 can also be located on the side of the active layer close to the substrate SS, and the virtual pixel circuit 40 adopts a bottom gate structure.

[0144] Figure 6 An equivalent circuit diagram of a shift register unit VSR in Figure 1 is shown.

[0145] Please refer to Figures 1 to 3 and Figure 6 In some embodiments, the shift register unit VSR further includes an output module 21, the output module 21 includes an output terminal Gout, and the signal lead-out line 24 is electrically connected to the output terminal Gout, and in the abnormal detection working condition, the signal of the output terminal Gout corresponding to the target row position is led out to the terminal area BA by the test signal line Test.

[0146] In these embodiments, the output terminal Gout signal can be led out through the signal lead-out line 24 to the terminal area BA via the test signal line Test.

[0147] Figure 7 Another equivalent circuit diagram at the shift register unit VSR in Figure 1 is shown, Figure 8 Another equivalent circuit diagram at the shift register unit VSR in Figure 1 is shown.

[0148] Referring to Figures 1 to 3 and Figures 7 to 8 In some embodiments, the shift register unit VSR further comprises a noise reduction module 22, the noise reduction module 22 comprising a first signal terminal PU and a second signal terminal PD, the noise reduction module 22 controlling the voltage of the second signal terminal PD based on the signal of the first signal terminal PU and controlling the voltage of the first signal terminal PU based on the signal of the second signal terminal PD, the signal lead-out line 24 being electrically connected with the first signal terminal PU or the second signal terminal PD, and in the abnormal detection working condition, the signal of the first signal terminal PU or the second signal terminal PD corresponding to the target row position being led out to the terminal area BA via the test signal line Test.

[0149] In these embodiments, the interlocking characteristics of the first signal terminal PU and the second signal terminal PD, and the signal of the first signal terminal PU and the second signal terminal PD being led out to the terminal area BA through the signal lead-out line 24 can quickly locate the fault source, and improve the diagnosis efficiency and maintenance accuracy of complex circuit faults.

[0150] Exemplarily, the first signal terminal PU is a PU pull-up node, the second signal terminal PD is a PD pull-down node, and the noise reduction module 22 of the shift register unit VSR comprises the first signal terminal PU and the second signal terminal PD, wherein the first signal terminal PU controls the driving of the output terminal Gout through the current or voltage of the pull-up transistor, and the second signal terminal PD pulls down the voltage of the first signal terminal PU and the output terminal Gout to the off level through the current or voltage of the pull-down transistor to realize reset.

[0151] The signal lead-out line 24 is directly electrically connected with the first signal terminal PU or the first signal terminal PU, forming a signal path from the internal node to the terminal area BA of the non-display area NA.

[0152] In the abnormal detection working condition, the test signal line Test is connected with the target row signal lead-out line 24 through the fusion technology, so that the real-time voltage signal of the first signal terminal PU or the first signal terminal PU is transmitted to the terminal area BA test port via the test signal line Test.

[0153] The noise reduction module 22 is controlled by the interlocking mechanism of the first signal end PU and the second signal end PD. The level of the first signal end PU controls the switching state of the transistor, and the level of the second signal end PD inversely affects the reset of the first signal end PU, thereby ensuring the stability of the gate signal.

[0154] When the first signal end PU has abnormal voltage due to transistor threshold drift or capacitor leakage, the signal lead-out line 24 directly captures the dynamic change thereof. If the second signal end PD cannot be effectively reset due to aging of the pull-down transistor, the signal waveform thereof can be accurately collected through the test signal line Test.

[0155] By directly accessing the key signals of the PU / PD nodes, the limitation of traditional detection that can only observe the waveform of the output end Gout is broken, and deep analysis of internal failure modes of the shift register unit VSR, such as insufficient pull-up capability and pull-down delay, is realized.

[0156] The fusion operation is performed on the target row-specific node, avoiding global signal interference.

[0157] It should be noted that, Figure 6 , Figure 7 and Figure 8 The shift register unit VSR is taken as an example for illustration.

[0158] Alternatively, in other embodiments, the shift register unit VSR can also be other types of GOA circuits, such as but not limited to 4T1C GOA circuit, 6T1C GOA circuit, 8T1C GOA circuit, 10T2C GOA circuit, 12T1C GOA circuit, etc.

[0159] Figure 9 A cross-sectional structure schematic diagram of the test signal line Test of the array substrate 100 provided by the first aspect embodiment of the present application is shown.

[0160] Referring to Figure 9 In some embodiments, the array substrate 100 is a multi-layer wiring structure, including wiring layers 101 and insulating layers 102 stacked along the thickness direction, the insulating layers 102 being located between the wiring layers 101, a plurality of functional signal lines 30 and signal lead-out lines 24 being distributed in the wiring layers 101, and the insulating layer 102 between the signal lead-out line 24 and the functional signal line 30 close to itself being configured as an organic film layer.

[0161] In these embodiments, the insulating layer 102 between the signal lead-out line 24 and the functional signal line 30 close to itself is configured as an organic film layer, and the organic film layer has a relatively thick thickness, which can further better shield the mutual interference between different signals and avoid mutual coupling between different signals.

[0162] Referring to Figures 1 to 3In some embodiments, the signal leading-out section 301 further comprises a straight-out sub-section 301a and a fan-out sub-section 301b, the terminal area BA is provided with a plurality of signal terminals 50, the straight-out sub-section 301a extends along the second direction Y and is arranged at intervals along the first direction X, and the straight-out sub-section 301a is electrically connected to the signal terminals 50 in the terminal area BA through the fan-out sub-section 301b.

[0163] In these embodiments, the signal leading-out section 301 needs to be adjusted in direction to form the fan-out sub-section 301b near the terminal area BA, and is gathered to the terminal area BA and electrically connected to the signal terminals 50 in the terminal area BA.

[0164] Figure 10 A planar structure of a display panel 200 provided by the second aspect of the present application is shown.

[0165] Referring to Figure 10 In the second aspect, the embodiments of the present application further provide a display panel 200, comprising the array substrate 100 provided in any of the embodiments of the first aspect of the present application.

[0166] The display panel 200 provided by the second aspect of the present application has the beneficial effects of the array substrate 100 provided by any of the embodiments of the first aspect of the present application, and thus the details are not repeated here.

[0167] The display panel 200 provided by the embodiments of the present application can be an organic light-emitting diode (OLED) display panel 200.

[0168] Those skilled in the art should understand that in other implementations of the present application, the display panel 200 can also be a liquid crystal display (LCD) display panel 200 or any other display panel 200 using the shift register group 20 as the gate drive circuit in the display panel 200.

[0169] Figure 11 A planar structure of a display device 300 provided by the third aspect of the present application is shown.

[0170] Referring to Figure 11 In the third aspect, the embodiments of the present application further provide a display device 300, comprising the display panel 200 provided in any of the embodiments of the second aspect of the present application.

[0171] In a second aspect, the embodiments of the present application further provide a display device 300 comprising the display panel 200 of any of the above embodiments. Since the display device 300 provided by the embodiments of the present application comprises the display panel 200 of any of the above embodiments, the display device 300 provided by the third aspect of the embodiments of the present application has the beneficial effects of the display panel 200 of any of the above embodiments of the second aspect, which will not be described herein again.

[0172] Figure 11 The embodiments only take the mobile phone as an example to describe the display device 300. It can be understood that the display device 300 provided by the embodiments of the present application can be a wearable product, a computer, a television, a vehicle-mounted display device 300, and other display devices 300 having a display function. The present application does not make specific limitations thereto.

[0173] The display device 300 provided by the embodiments of the present application has the beneficial effects of the display panel 200 provided by the embodiments of the present application. For specific descriptions of the display panel 200, reference can be made to the specific descriptions of the display panel 200 in the above embodiments, which will not be described herein again.

[0174] The display device 300 in the embodiments of the present application includes, but is not limited to, a mobile phone, a personal digital assistant (PDA), a tablet computer, an electronic book, a television, an access control, a smart fixed telephone, a console, and other devices having a display function.

[0175] Although the present application has been described with reference to the preferred embodiments, various modifications can be made to the present application without departing from the scope thereof, and equivalent components can be substituted therefor. In particular, the technical features mentioned in each embodiment can be combined in any manner as long as there is no structural conflict. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. An array substrate, characterized in that: The array substrate comprises a display area and a non-display area at least partially surrounding the display area, wherein the non-display area includes a terminal area, and the array substrate comprises: substrate; a plurality of gate signal lines, at least partially located in the display area, the plurality of gate signal lines extending along a first direction and spaced apart along a second direction, the first direction intersecting the second direction; a shift register group located in the non-display area, the shift register group comprising a plurality of shift register units cascaded along the second direction, each of the shift register units comprising a plurality of interface terminals, the interface terminals comprising an output terminal electrically connected to the corresponding gate signal line, the shift register unit further comprising at least one signal lead line electrically connected to the interface terminals in a one-to-one correspondence; A plurality of functional signal lines, wherein the signal lead-out sections in the functional signal lines extend at least partially along the second direction, and the signal lead-out sections are connected to the terminal area, at least one of the functional signal lines is configured as a test signal line, and the test signal line further comprises a plurality of first reserved fusion points located in the signal lead-out sections, the signal lead-out lines extend to the positions of the first reserved fusion points, and the test signal lines can be fused and electrically connected with the signal lead-out lines at the target row positions so that the signals at the corresponding interface ends are led out from the test signal lines to the terminal area.

2. The array substrate according to claim 1, wherein: The functional signal lines include control signal lines, which are located in the non-display area and on the side of the shift register group away from the display area. The elements in the shift register unit are electrically connected to the corresponding control signal lines, and at least one of the control signal lines is configured as the test signal line.

3. The array substrate according to claim 2, wherein: The control signal line includes a first control signal sub-line, and the first control signal sub-line is configured as the test signal line; Under abnormal detection conditions, the first control signal sub-line is fused with the signal lead-out line at the target row position to achieve electrical connection, and the corresponding signal at the interface end is led out to the terminal area by the first control signal sub-line.

4. The array substrate according to claim 2, wherein: The control signal line further includes a second control signal sub-line, which is originally configured as a display detection signal line; Under abnormal detection conditions, at least one of the second control signal sub-lines is multiplexed and configured as the test signal line, the second control signal sub-line is fused with the signal lead-out line at the target row position to achieve electrical connection, and the corresponding signal at the interface end is led out to the terminal area by the second control signal sub-line.

5. The array substrate according to claim 1, wherein: The functional signal lines further include data signal lines, the data signal lines are located in the display area, and at least one of the data signal lines is configured as the test signal line; When in an abnormal detection condition, the data signal line is fused with the gate signal line at the target row position to achieve electrical connection, and the signal at the output end is led out to the terminal area via the gate signal line and the data signal line.

6. The array substrate according to claim 5, wherein: The data signal lines include virtual signal lines, at least one of the virtual signal lines is configured as the test signal line; When in the abnormal detection working condition, the virtual signal line is fused with the gate signal line at the target row position to achieve electrical connection, and the signal at the output end is led out to the terminal area by the virtual signal line.

7. The array substrate according to claim 6, wherein: The functional signal line includes a control signal line, the control signal line is located in a non-display area, and the signal driving segments in the control signal line extend along the first direction in the non-display area and are arranged at intervals along the second direction. The control signal line includes a second control signal sub-line, the second control signal sub-line is configured to drive a switch circuit, and the second control signal sub-line also includes a second reserved welding point located in the signal driving segment. The virtual signal line configured as the test signal line also extends to the position of the second reserved welding point. Under the abnormality detection working condition, the virtual signal line is welded to the second reserved welding point to achieve electrical connection, the second control signal sub-line inputs a conduction level signal, and the signal of the data signal line is led out by the virtual signal line.

8. The array substrate according to claim 7, wherein: The array substrate further includes a plurality of dummy pixel circuits located in the display area and arranged along the second direction, the dummy signal lines passing through the dummy pixel circuits, the first reserved welding points being located at the positions of the dummy pixel circuits, and the dummy pixel circuits being provided with welding blocks; Under the abnormality detection working condition, the virtual signal line is electrically connected to the gate signal line at the target row position by fusing the fusing block.

9. The array substrate according to claim 8, wherein: The fusing block and the dummy signal line are arranged in the same layer and are connected to each other. The orthographic projection of the fusing block on the substrate at least partially overlaps with the orthographic projection of the gate signal line on the substrate.

10. The array substrate according to claim 1, wherein: The shift register unit further includes an output module, the output module includes the output end, and the signal lead is electrically connected to the output end; Under the abnormality detection working condition, the signal of the output end corresponding to the target row position is led out to the terminal area by the test signal line.

11. The array substrate according to claim 1, wherein: The shift register unit further includes a noise reduction module, the noise reduction module including a first signal terminal and a second signal terminal, the noise reduction module controls the voltage of the second signal terminal based on the signal of the first signal terminal, and controls the voltage of the first signal terminal based on the signal of the second signal terminal, and the signal lead wire is electrically connected to the first signal terminal or the second signal terminal; Under the abnormality detection working condition, the signal of the first signal end or the second signal end corresponding to the target row position is led out to the terminal area by the test signal line.

12. The array substrate according to claim 1, wherein: The array substrate is a multi-layer routing structure, including routing layers and insulating layers stacked along the thickness direction, the insulating layers are located between the routing layers, and the plurality of functional signal lines and the signal lead lines are distributed on the routing layers, and the insulating layer between the signal lead lines and the functional signal lines close to the signal lead lines is configured as an organic film layer.

13. The array substrate according to claim 1, wherein: The signal lead-out section also includes a straight-out sub-segment and a fan-out sub-segment. The terminal area is provided with a plurality of signal terminals. The straight-out sub-segment extends along the second direction and is arranged at intervals along the first direction. The straight-out sub-segment is electrically connected to the signal terminals located in the terminal area through the fan-out sub-segment.

14. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 13.

15. A display device, characterized in that: The display panel comprises the display panel according to claim 14.

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