Driving circuit of display panel and method thereof, display panel, and display device

Abstract

The application discloses a driving circuit and a method thereof of a display panel, the display panel and a display device, and relates to the technical field of display. The circuit comprises a picture detection module, the picture detection module is arranged to detect a picture scene type of an input picture, and determine a picture detection signal according to the picture scene type; a compensation trigger module, a signal trigger end of the compensation trigger module is electrically connected with a first signal interface of the picture detection module, the compensation trigger module is arranged to receive the picture detection signal sent by the picture detection module, and trigger a level signal of a heavy load picture according to the picture detection signal, and generate a clock signal; and a charging compensation module, a signal input end of the charging compensation module is electrically connected with a signal output end of the compensation trigger module, the charging compensation module is arranged to perform charging compensation according to the clock signal sent by the compensation trigger module. The application aims to improve the surface uniformity of a super-large size screen picture display.

Description

Driving circuit and method for display panel, display panel and display device Technical Field

[0001] This application relates to the field of display technology, and in particular to a driving circuit and method for a display panel, a display panel, and a display device. Background Technology

[0002] As display panels rapidly develop towards ultra-large sizes, factors such as excessively long horizontal data transmission distances and high line impedance result in significant RC (resistance-capacitance) loads during transmission, which become more pronounced towards the center of the screen.

[0003] Existing technology reduces the RC load by lowering the line resistance of the clock signal (CK), thereby alleviating the gate delay problem caused by excessive impedance. However, this method still cannot eliminate color shift when the line resistance is reduced to the limit of the panel line's own impedance. Especially under heavy H-Line (one line bright, one line black) display, the RC load in the middle of the screen causes the rise / fall edge delay of the CK waveform, resulting in a deviation between the actual charging time and the ideal time. This causes the problem of black levels becoming brighter and white levels becoming darker, which seriously affects the uniformity of the display of ultra-large screens.

[0004] Therefore, improving the uniformity of image display on ultra-large screens is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] The main objective of this application is to provide a driving circuit and method for a display panel, as well as a display panel and a display device, which aims to improve the surface uniformity of ultra-large screen display.

[0006] To achieve the above objectives, this application provides a driving circuit for a display panel, the driving circuit comprising:

[0007] The image detection module is configured to detect the image scene type of the input image and determine the image detection signal based on the image scene type.

[0008] The compensation trigger module is electrically connected to the first signal interface of the screen detection module. The compensation trigger module is configured to receive the screen detection signal sent by the screen detection module and generate a clock signal based on the level trigger signal of the screen detection signal being a reloaded screen.

[0009] A charging compensation module is provided, wherein the signal input terminal of the charging compensation module is electrically connected to the signal output terminal of the compensation trigger module, and the charging compensation module is configured to perform charging compensation based on the clock signal sent by the compensation trigger module.

[0010] In one embodiment, the charging compensation module includes a boost compensation unit;

[0011] The non-inverting input terminal of the boost compensation unit constitutes the signal input terminal of the charging compensation module and is electrically connected to the signal output terminal of the compensation trigger module.

[0012] The out-of-phase input terminal of the boost compensation unit is connected to the signal output terminal of the boost compensation unit.

[0013] In one embodiment, the driving circuit includes a level conversion integrated chip, the charging compensation module includes a gate voltage detection unit and a voltage compensation unit, and the compensation trigger module and the voltage compensation unit are integrated within the level conversion integrated chip;

[0014] The clock signal terminal of the gate voltage detection unit constitutes the signal input terminal of the charging compensation module and is electrically connected to the signal output terminal of the compensation trigger module.

[0015] The right voltage sampling terminal of the gate voltage detection unit is electrically connected to the right terminal of each gate trace, the left voltage sampling terminal of the gate voltage detection unit is electrically connected to the left terminal of each gate trace, and the detection output terminal of the gate voltage detection unit is electrically connected to the signal acquisition terminal of the image detection module.

[0016] The second signal terminal of the image detection module is electrically connected to the voltage compensation unit.

[0017] In one embodiment, the gate voltage detection unit is configured to, in response to a clock signal sent by the compensation trigger module, perform voltage acquisition line by line for a preset number of gate traces, acquire the left-side trace voltage, middle trace voltage, and right-side trace voltage of each gate trace, determine the average voltage detection value based on the right-side trace voltage, middle trace voltage, and left-side trace voltage of each gate trace, and transmit the clock signal carrying the average voltage detection value to the voltage compensation unit via the screen detection module.

[0018] The voltage compensation unit is configured to charge and compensate the clock signal based on the average voltage detection value after receiving the clock signal carrying the average voltage detection value.

[0019] In one embodiment, the compensation triggering module includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a sixth switch.

[0020] The gate terminal of the first switch, the gate terminal of the third switch, and the first path terminal of the fifth switch are respectively connected to the power supply terminal, and the first path terminal of the first switch is electrically connected to the first path terminal of the third switch.

[0021] The connection point where the first path terminal of the first switch is electrically connected to the first path terminal of the third switch forms the signal output terminal of the compensation trigger module, and is electrically connected to the signal input terminal of the charging compensation module.

[0022] The second path terminal of the first switch is electrically connected to the first path terminal of the second switch, and the second path terminal of the second switch is grounded.

[0023] The gate terminal of the second switch forms the signal trigger terminal of the compensation trigger module, which is electrically connected to the first signal interface of the image detection module, the gate terminal of the fifth switch, and the gate terminal of the sixth switch. The second path terminal of the fifth switch is electrically connected to the first path terminal of the sixth switch, and the second path terminal of the sixth switch is grounded.

[0024] The gate terminal of the fourth switch is connected to the connection point of the second path terminal of the fifth switch and the first path terminal of the sixth switch. The first path terminal of the fourth switch is electrically connected to the second path terminal of the third switch. The second path terminal of the fourth switch is grounded.

[0025] Furthermore, to achieve the above objectives, this application also provides a panel compensation method, which is applied to the driving circuit described in any of the above claims, and the panel compensation method includes:

[0026] After determining the scene type of the input screen, the control screen detection module determines the screen detection signal based on the scene type;

[0027] When the image detection signal is a level trigger signal for a reloaded image, the compensation trigger module is controlled to generate a clock signal based on the level trigger signal;

[0028] The charging compensation module is controlled to perform charging compensation based on a clock signal.

[0029] In one embodiment, the charging compensation module includes a boost compensation unit, and the step of controlling the charging compensation module to perform charging compensation according to a clock signal includes:

[0030] Determine the voltage gain factor of the boost compensation unit, and control the charging compensation module to boost the clock voltage threshold of the clock signal according to the voltage gain factor;

[0031] The display panel is charged and compensated for under heavy load based on the clock voltage threshold after boosting.

[0032] In one embodiment, the charging compensation module includes a gate voltage detection unit and a voltage compensation unit, and the step of controlling the charging compensation module to perform charging compensation according to a clock signal includes:

[0033] The gate voltage detection unit is controlled to collect the right-side trace voltage, middle trace voltage, and left-side trace voltage of each gate trace line by line when a clock signal is acquired, and to determine the average voltage detection value based on the right-side trace voltage, middle trace voltage, and left-side trace voltage of each gate trace.

[0034] A clock signal carrying the average voltage detection value is generated based on the clock signal and the average voltage detection value, and the voltage compensation unit is controlled to charge and compensate the clock signal based on the average voltage detection value.

[0035] In addition, to achieve the above objectives, this application also provides a display panel, the display panel including the driving circuit described in any of the above claims, the driving circuit including a screen detection module, a compensation trigger module and a charging compensation module;

[0036] The display panel includes a display area and a non-display area surrounding the display area. The display panel is fixedly provided with multiple parallel gate traces. The non-display area is provided with a gate voltage detection unit in the charging compensation module on the side near the circuit board. The screen detection module and the level conversion integrated chip are fixedly arranged on the circuit board. The compensation trigger module and the voltage compensation unit in the charging compensation module are integrated into the level conversion integrated chip.

[0037] In addition, to achieve the above objectives, this application also provides a display device, which includes the display panel described above;

[0038] Alternatively, a memory, a processor, and a panel compensation program stored in the memory and executable on the processor, wherein the processor, when executing the panel compensation program, implements the steps of the panel compensation method as described in any of the preceding embodiments.

[0039] This application applies a driving circuit for a display panel that integrates a screen detection module, a compensation trigger module, and a charging compensation module to an ultra-large display panel. This can fundamentally solve the problem of uneven display caused by excessive line impedance and significantly improve the uniformity of the display on ultra-large screens. Specifically, the screen detection module can accurately identify the screen scene type caused by abnormal RC load due to heavy screen by detecting the input screen in real time. Next, the screen detection signal generated based on the screen scene type is transmitted to the signal trigger terminal of the compensation trigger module through the first signal interface of the screen detection module. At this time, the compensation trigger module generates a pre-corrected clock signal based on the level trigger signal of the screen detection signal as a heavy screen and sends it to the charging compensation module. This allows the charging compensation module to reconstruct the timing characteristics of the clock signal (such as the rising / falling edge slope) to compensate for the signal delay caused by excessive line impedance. This ensures that the central area of ​​the ultra-large screen can still obtain the same charging time as the edge area of ​​the screen under heavy screen (i.e., H-Line heavy screen), thereby eliminating the color shift phenomenon of black level brightness increase and white level brightness decrease caused by RC load difference, and thus significantly improving the uniformity of the ultra-large screen display. Attached Figure Description

[0040] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0041] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 is a structural block diagram of the simulated panel with gradually increasing RC load according to this application;

[0043] Figure 2 is a schematic diagram of the CK delay simulation waveform of the simulated panel RC load gradually increasing in this application;

[0044] Figure 3 is a structural block diagram of the first embodiment of the driving circuit of the display panel of this application;

[0045] Figure 4 is a schematic diagram of clock signal waveform compensation involved in the embodiment of this application;

[0046] Figure 5 is a schematic diagram of the boost compensation unit circuit involved in the embodiment of this application;

[0047] Figure 6 is a schematic diagram of the driving circuit of the display panel involved in the embodiment of this application;

[0048] Figure 7 is a schematic diagram of the compensation trigger module circuit involved in the embodiment of this application;

[0049] Figure 8 is a schematic diagram of the structure for detecting a gate trace according to an embodiment of this application;

[0050] Figure 9 is a schematic diagram of the structure for detecting two gate traces in an embodiment of this application;

[0051] Figure 10 is a schematic diagram of the structure for detecting N gate lines in an embodiment of this application;

[0052] Figure 11 is a schematic diagram of the structure of the display device involved in the embodiment of this application.

[0053] Explanation of icon numbers:

[0054] 10. Image detection module; 20. Compensation trigger module; 30. Charging compensation module; OP1. Operational amplifier; R1. First resistor; R2. Second resistor; 31. Gate voltage detection unit; 32. Voltage compensation unit; 40. Level conversion integrated chip; Q1. First switch; Q2. Second switch; Q3. Third switch; Q4. Fourth switch; Q5. Fifth switch; Q6. Sixth switch.

[0055] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0056] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0057] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0058] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0059] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0060] With the continuous development of display technology, the size of LCD (Liquid Crystal Display) screens is getting larger and larger. For example, 94-inch and 100-inch screens are already in mass production. However, with the increase in size, the requirements for the charging time of ultra-large screen panels are more stringent. One important point is that due to the large panel size, the data transmission distance is too long, and the line impedance is too high, resulting in a large RC load during the transmission process. This is more obvious towards the center of the screen. Especially under heavy loads of H-Line (one line bright and one line black), the center of the screen will experience misalignment due to gate delay, resulting in a color shift phenomenon where black levels become brighter and white levels become darker.

[0061] Figure 1 shows the simulated panel where the RC load gradually increases with the size, and Figure 2 shows the simulated waveform of the gate delay as the RC load gradually increases. Existing technology reduces the RC load by lowering the resistance value of CK, thus reducing the bus line resistance and consequently the gate delay (the timing delay of the scan signal caused by the RC load during transmission). However, this approach fails to eliminate the color shift phenomenon once the CK resistance value is reduced to the point where the impedance of the panel lines alone is insufficient to reduce the RC load.

[0062] To eliminate color shift in ultra-large screen displays and improve the uniformity of ultra-large screen displays, this application provides a driving circuit and method for a display panel, a display panel, and a display device.

[0063] This application provides a driving circuit for a display panel. Referring to FIG3, FIG3 is a structural block diagram of a first embodiment of the driving circuit for the display panel of this application. The driving circuit for the display panel includes:

[0064] The image detection module 10 is configured to detect the image scene type of the input image and determine the image detection signal based on the image scene type.

[0065] In this embodiment, the image detection module 10 intelligently identifies and classifies the input image, enabling accurate judgment based on the differences between overloaded and normal image scenes. Differential image detection signals are output via high and low level signals. For example, the image detection module 10 automatically detects the input image from the video source. If the image scene type is an overloaded image, a high level is provided as the image detection signal to activate the compensation trigger module 20, enabling the charging compensation module 30 to perform charging compensation for the overloaded image. If the image scene type is a normal image, a low level is provided as the image detection signal to the compensation trigger module 20 to disable the charging compensation function, avoiding excessive intervention in normal image scenes. This ensures display uniformity while reducing panel power consumption and the risk of signal distortion.

[0066] It should be noted that the image detection module 10 can be understood as a TCONIC (Timing Controller Integrated Circuit). A normal image can be understood as any video image except for heavy-load scenes. The video source can be understood as a video input device such as a camera, player, or computer. A heavy-load scene can be understood as a horizontally alternating bright and black image (H-Line, one line bright, one line black).

[0067] In a specific embodiment, after receiving the input image from the video source, the image detection module 10 scans the pixel brightness values ​​of the input image line by line and detects whether the absolute difference in brightness between the pixel brightness value of each line and the pixel brightness value of the adjacent line is higher than a preset bright-black alternation standard threshold. If the absolute difference in brightness of multiple consecutive lines (e.g., 6 lines) is higher than the bright-black alternation standard threshold, the input image is determined to be a reloaded image. If at least one of the absolute differences in brightness of multiple consecutive lines does not exceed the bright-black alternation standard threshold, the input image is determined to be a normal image.

[0068] The compensation trigger module 20 is electrically connected to the first signal interface of the screen detection module 10. The compensation trigger module 20 is configured to receive the screen detection signal sent by the screen detection module 10 and generate a clock signal based on the level trigger signal of the screen detection signal being a reloaded screen.

[0069] In this embodiment, through the electrical connection between the signal trigger terminal of the compensation trigger module 20 and the first signal interface of the screen detection module 10, after the compensation trigger module 20 receives the screen detection signal sent by the screen detection module 10, the compensation trigger module 20 automatically generates a pre-corrected clock signal based on the screen detection signal as a high-level trigger signal. This allows the charging compensation module 30, which is electrically connected to the compensation trigger module 20, to increase the rising / falling edge slope of the clock signal by boosting the voltage, thereby offsetting the charging time deviation caused by the panel RC load and eliminating the color shift phenomenon in the center of the screen.

[0070] A charging compensation module 30 is provided, wherein the signal input terminal of the charging compensation module 30 is electrically connected to the signal output terminal of the compensation trigger module 20, and the charging compensation module 30 is configured to perform charging compensation based on the clock signal sent by the compensation trigger module 20.

[0071] In this embodiment, through the electrical connection between the signal input terminal of the charging compensation module 30 and the signal output terminal of the compensation trigger module 20, the charging compensation module 30 performs voltage boosting processing on the clock signal to increase the rising / falling edge slope of the clock signal, thereby realizing waveform compensation of the clock signal waveform and forming the compensated waveform B20 shown in Figure 4, so that the compensated charging time ti is consistent with the ideal charging time t0, so as to eliminate the color shift phenomenon caused by the timing delay of the actual waveform B10 shown in Figure 4.

[0072] Furthermore, in some feasible embodiments, the charging compensation module 30 includes a boost compensation unit; the non-inverting input terminal of the boost compensation unit constitutes the signal input terminal of the charging compensation module 30 and is electrically connected to the signal output terminal of the compensation trigger module 20; the out-of-inverting input terminal of the boost compensation unit is connected to the signal output terminal of the boost compensation unit.

[0073] In this embodiment, the boost compensation unit provided in this application may include an operational amplifier OP1, a first resistor R1, and a second resistor R2. Its circuit structure is shown in Figure 5. When the non-inverting input terminal of the operational amplifier is connected to the clock signal sent by the signal input terminal of the charging compensation module 30, the clock voltage threshold V_CK of the clock signal is boosted according to the preset feedback boosting algorithm. Thus, the charging time (and the compensated charging time) under the horizontal alternating bright and black drawing can be made consistent with the ideal charging time through the boosted clock voltage threshold Vout, so as to eliminate the timing delay caused by the RC load. It can effectively suppress the color shift phenomenon of black level brightness rise and white level brightness decay caused by the difference of RC load, thereby significantly improving the uniformity of the ultra-large screen display.

[0074] It should be noted that the preset feedback boosting algorithm expression is Vout=[1+(R1 / R2)]*V_CK, where R1 represents the resistance value of the first resistor R1 and R2 represents the resistance value of the second resistor R2. In other words, the ratio of the resistance values ​​of the first resistor R1 and the second resistor R2 determines the voltage gain factor [1+(R1 / R2)]. This resistance ratio can be customized according to application requirements.

[0075] Furthermore, in some other feasible embodiments, the driving circuit includes a level conversion integrated chip 40, the charging compensation module 30 includes a gate voltage detection unit 31 and a voltage compensation unit 32, the compensation trigger module 20 and the voltage compensation unit 32 are integrated within the level conversion integrated chip 40; the clock signal terminal of the gate voltage detection unit 31 constitutes the signal input terminal of the charging compensation module 30 and is electrically connected to the signal output terminal of the compensation trigger module 20; the right voltage sampling terminal of the gate voltage detection unit 31 is electrically connected to the right trace terminal of each gate trace, the left voltage sampling terminal of the gate voltage detection unit 31 is electrically connected to the left trace terminal of each gate trace, the detection output terminal of the gate voltage detection unit 31 is electrically connected to the signal acquisition terminal of the image detection module 10; the second signal terminal of the image detection module 10 is electrically connected to the voltage compensation unit 32.

[0076] In this embodiment, the gate voltage detection unit 31 in the charging compensation module 30 is encapsulated in the non-display area of ​​the display panel as shown by the shaded area in FIG6, and the compensation trigger module 20 and the voltage compensation unit 32 in the charging compensation module 30 are integrated in the level conversion integrated chip 40, so as to replace the design of the compensation trigger module 20 and the charging compensation module 30 as peripheral circuits as shown in FIG3. This not only effectively reduces the cost of peripheral circuits, but also increases the versatility of the level conversion integrated chip 40.

[0077] It should be noted that the level shifting integrated chip 40 can generate a clock signal output to the display panel. The level shifting integrated chip 40 and the screen detection module 10 (i.e., TCONIC) are assembled on the PCBA (Printed Circuit Board Assembly) shown in Figure 6, and the blank rectangle in Figure 6 represents the effective display area.

[0078] Furthermore, in some feasible embodiments, the gate voltage detection unit 31 is configured to, in response to the clock signal sent by the compensation trigger module 20, perform voltage acquisition line by line for a preset number of gate traces, acquire the left-side trace voltage, middle trace voltage, and right-side trace voltage of each gate trace, determine the average voltage detection value based on the right-side trace voltage, middle trace voltage, and left-side trace voltage of each gate trace, and transmit the clock signal carrying the average voltage detection value to the voltage compensation unit 32 via the screen detection module 10; the voltage compensation unit 32 is configured to, upon receiving the clock signal carrying the average voltage detection value, perform charging compensation on the clock signal based on the average voltage detection value.

[0079] In this embodiment, referring to FIG6, through the electrical connection between the gate voltage detection unit 31 and the compensation trigger module 20, the compensation trigger module 20 responds to the level trigger signal during heavy screen and outputs a clock signal to the voltage detection unit 31. The voltage detection unit 31 responds to the rising edge or falling edge of the clock signal to start a voltage detection cycle.

[0080] During the voltage detection cycle, the gate voltage detection unit 31 performs line-by-line scanning and voltage acquisition operations on a preset number of gate traces (for example, N gate traces evenly distributed on the display panel can be selected, or key traces with representative RC load characteristics can be selected based on historical data). Specifically, for each selected gate trace, the voltage values ​​at three specific locations on the gate trace are simultaneously acquired by the multiplexer and analog-to-digital converter circuit built into the voltage detection unit 31. The first is the voltage at the starting point of the left end of the gate trace, defined as the left-side trace voltage (i.e., VL1, VL2, VL3, VL4, ... and VLn shown in Figure 6); the second is the voltage near the geometric midpoint of the gate trace, defined as the middle trace voltage (i.e., V_m1, V_m2, V_m3, V_m4, ... and V_mn shown in Figure 6); and the third is the voltage at the starting point of the right end of the gate trace, defined as the right-side trace voltage (i.e., Vr1, Vr2, Vr3, Vr4, ... and Vrn shown in Figure 6).

[0081] After the voltage acquisition of the preset number of gate traces is completed, the voltage data of each gate trace is processed by the data processing chip of the gate voltage detection unit 31. Specifically, for a single gate trace i (i = 1, 2, 3, ..., n), firstly, the voltage difference between the left and right trace voltages and the middle trace voltage of this single gate trace i is calculated, that is, the voltage difference between the left trace voltage VLi and the middle trace voltage V_mi (VLi-V_mi), and the voltage difference between the right trace voltage Vri and the middle trace voltage V_mi (Vri-V_mi). Next, the arithmetic mean of the calculated voltage difference (VLi-V_mi) and the voltage difference (Vri-V_mi) is taken as the average trace voltage difference of gate trace i. Subsequently, the gate voltage detection unit 31 sends the data packet carrying the average trace voltage difference of each trace to the screen detection module 10 through a serial or parallel communication interface, and the screen detection module 10 performs average processing on the average trace voltage difference of all gate traces (i.e., the preset number of gate traces to be detected). This allows for the accurate acquisition of a voltage detection average value that excludes gate trace process deviations. Subsequently, the clock signal carrying the voltage detection average value is sent to the voltage compensation unit 32 through the second signal terminal of the screen detection module 10. The voltage compensation unit 32 then performs voltage boosting processing on the voltage detection average value according to a preset feedback boosting algorithm. This allows for targeted compensation of charging time deviations caused by trace impedance differences through the boosted voltage detection average value. As a result, the charging time (and the compensated charging time) under alternating bright and black horizontal images is consistent with the ideal charging time. This not only effectively eliminates the local errors that may be introduced by traditional single-point detection, but also adapts to the RC load differences in different areas (especially the middle and edges of large-size panels), significantly improving the uniformity of charging across the entire screen. Ultimately, this solves display quality problems such as color shift and brightness unevenness from the signal source, and is especially suitable for surface uniformity optimization of ultra-large-size display panels under heavy load images.

[0082] It should be noted that the voltage compensation unit 32 is the same as the boost compensation unit, that is, the circuit structure of the voltage compensation unit 32 can be referred to Figure 5.

[0083] In a specific embodiment, the starting voltage on the left side of the first gate line (i.e., the left-side line voltage) is defined as VL1, the middle voltage (i.e., the middle line voltage) as V_m1, and the starting voltage on the right side (i.e., the right-side line voltage) as Vr1. Similarly, the starting voltage on the left side of the second gate line is defined as VL2, the middle voltage as V_m2, and the starting voltage on the right side as Vr2. Because the lines on large-size panels are very long, taking the first gate line as an example, the starting voltage VL1 on the left side is basically the same as the starting voltage Vr1 on the right side. As the line length increases towards the middle, the voltage gradually decreases, eventually reaching the middle voltage V_m1. This creates a voltage difference between the two sides and the center, which is the cause of color shift. Eliminating this voltage difference will eliminate the color shift. Therefore, by detecting three voltage data points from a single gate line and calculating them, the average line voltage difference can be obtained. The expression for this average line voltage difference is as follows:

[0084]

[0085] Calculating the average of the voltage difference between the two ends can accurately obtain the average voltage difference of the trace, which significantly improves the accuracy of the overall voltage difference value of each gate trace. The voltage difference between the two ends refers to the voltage difference on the left side (VL1-V_m1) and the voltage difference on the right side (Vr1-V_m1).

[0086] Since the manufacturing process of each gate trace may vary, the number of gate traces detected can be increased. For example, increasing the number of gate traces detected to two can improve data accuracy. This can be calculated using the following algorithm:

[0087]

[0088] By calculating the average voltage difference between the two sides and the middle of a single gate trace, and then adding the average voltage difference of the two traces together and taking the average value, a data that eliminates the influence of gate trace process deviation is obtained.

[0089] To further improve data accuracy, as shown in Figure 6, the number of gate traces can be increased, and the average voltage difference across all traces can be averaged to obtain the average voltage detection value. The specific algorithm is as follows:

[0090]

[0091] Where n represents the preset number of gate traces to detect; the more preset traces, the more accurate the average voltage detection value. Specifically, the average voltage difference of all gate traces detected by the gate voltage detection unit 31 is transmitted to the image detection module 10. The image detection module 10 averages the average voltage difference of all gate traces to obtain a clock signal carrying the average voltage detection value. This clock signal is then output to the internal voltage compensation unit 32 to boost the voltage (i.e., the resistance ratio). The boosted clock signal waveform (i.e., the clock signal waveform carrying the boosted average voltage detection value) is then given to the level conversion integrated chip 40 for real-time adjustment. Finally, the boosted clock signal waveform is output (i.e., the clock signal waveform carrying the boosted average voltage detection value). This achieves the effect of the same charging time for panels with different process effects, eliminates the influence of inter-chip differences, and achieves color shift consistency.

[0092] Further, in some other feasible embodiments, the compensation trigger module 20 includes a first switch Q1, a second switch Q2, a third switch Q3, a fourth switch Q4, a fifth switch Q5, and a sixth switch Q6; the gate terminals of the first switch Q1, the third switch Q3, and the first path terminals of the fifth switch Q5 are respectively connected to a power supply terminal; the first path terminal of the first switch Q1 is electrically connected to the first path terminal of the third switch Q3; the connection point between the first path terminal of the first switch Q1 and the first path terminal of the third switch Q3 constitutes the signal output terminal of the compensation trigger module 20, which is electrically connected to the signal input terminal of the charging compensation module 30; the second path terminal of the first switch Q1 is connected to the second switch Q6. The first path terminal of Q2 is electrically connected, and the second path terminal of the second switch Q2 is grounded; the gate terminal of the second switch Q2 constitutes the signal trigger terminal of the compensation trigger module 20, which is electrically connected to the first signal interface of the image detection module 10, the gate terminal of the fifth switch Q5, and the gate terminal of the sixth switch Q6, respectively. The second path terminal of the fifth switch Q5 is electrically connected to the first path terminal of the sixth switch Q6, and the second path terminal of the sixth switch Q6 is grounded; the gate terminal of the fourth switch Q4 intersects at the connection node where the second path terminal of the fifth switch Q5 is electrically connected to the first path terminal of the sixth switch Q6, and the first path terminal of the fourth switch Q4 is electrically connected to the second path terminal of the third switch, and the second path terminal of the fourth switch Q4 is grounded.

[0093] In this embodiment, the first switch Q1, second switch Q2, third switch Q3, fourth switch Q4, and sixth switch Q6 in the compensation trigger module 20 are N-type MOSFETs, and the fifth switch Q5 is a P-type MOSFET. Based on the characteristics of N-type MOSFETs being turned on at a high level and P-type MOSFETs being turned on at a low level, a constant high level is input to the gate terminals of the first switch Q1 and the third switch Q3. The gate terminal of the second switch Q2 is connected to the first signal interface (GPIO1 in Figure 7) of the image detection module 10. The source terminal of the second switch Q2 is connected to a clock signal, and the source terminal of the fourth switch Q4 is connected to a constant low level. Since the image detection module 10 automatically detects the scene type of the input video source, it determines the corresponding image detection signal. That is, when the image detection module 10 detects an H-Line image, it sends a high-level signal to the first signal interface connected to the gate terminal of the second switch Q2; when it detects a normal image, it sends a low-level signal to the same first signal interface.

[0094] Specifically, when the gate of the second switch Q2 receives a high-level signal, the second switch Q2 circuit and the sixth switch Q6 in the compensation trigger module 20 will be turned on after receiving the high-level signal, while the fifth switch Q5 will be turned off when receiving the high-level signal. At this time, the drain terminal connected to the fifth switch Q5 and the sixth switch Q6 will generate a low-level signal. The fourth switch Q4 will be turned off due to the low level, ultimately causing the signal output terminal of the compensation trigger module 20 (i.e., the OUT terminal shown in Figure 7) to output the clock signal CK shown in Figure 7. Conversely, when the gate of the second switch Q2 receives a low-level signal, the second switch Q2 circuit and the sixth switch Q6 in the compensation trigger module 20 will be turned off due to the low level, while the fifth switch Q5 will be turned on. At this time, the drain terminal connected to the fifth switch Q5 and the sixth switch Q6 will generate a high-level signal. The fourth switch Q4 will be turned on due to the high level, pulling the signal CK low to the ground terminal, ultimately causing the signal output terminal of the compensation trigger module 20 to not output the signal CK. This results in a compensation trigger module 20 that outputs a clock signal CK when an H-line screen is detected and does not output a clock signal CK when a normal screen is detected. This not only compensates for the clock signal waveform of the overloaded screen, but also avoids excessive intervention in the normal screen scene. This ensures display uniformity and reduces the risk of panel power consumption and signal distortion.

[0095] In summary, this application applies the driving circuit of the display panel, which integrates the screen detection module 10, the compensation trigger module 20 and the charging compensation module 30, to an ultra-large size display panel. This can fundamentally solve the problem of uneven display caused by excessive line impedance and significantly improve the uniformity of the display of ultra-large size screen images. Specifically, the screen detection module 10 can accurately identify the screen scene type caused by abnormal RC load due to heavy screen by real-time detection of the input screen. Next, the screen detection signal generated based on the screen scene type is transmitted to the signal trigger terminal of the compensation trigger module 20 through the first signal interface of the screen detection module 10. At this time, the compensation trigger module 20 generates a pre-corrected clock signal based on the level trigger signal of the screen detection signal being a heavy screen and sends it to the charging compensation module 30 so that the charging compensation module 30 can reconstruct the timing characteristics of the clock signal (such as the rising / falling edge slope) to compensate for the signal delay caused by excessive line impedance. This ensures that the central area of ​​the ultra-large screen can still obtain the same charging time as the edge area of ​​the screen under heavy screen (i.e., H-Line heavy screen), thereby eliminating the color shift phenomenon of black level brightness increase and white level brightness decrease caused by RC load difference, and thus significantly improving the uniformity of the ultra-large screen display.

[0096] Furthermore, based on the first embodiment of the driving circuit of the display panel of this application, a second embodiment of the panel compensation method of this application is proposed.

[0097] The panel compensation method of this application is applied to the driving circuit of the display panel of any of the above claims. The panel compensation method of this application is executed by the display device applied to the driving circuit of the display panel. The panel compensation method of this application includes the following implementation steps S10 to S30.

[0098] Step S10: After determining the scene type of the input screen, the control screen detection module 10 determines the screen detection signal according to the scene type.

[0099] In this embodiment, the image detection module 10 intelligently identifies and classifies the input image, enabling accurate judgment based on the differences between overloaded and normal image scenes. Differential image detection signals are output via high and low level signals. For example, the image detection module 10 automatically detects the input image from the video source. If the image scene type is an overloaded image, a high level is provided as the image detection signal to activate the compensation trigger module 20, enabling the charging compensation module 30 to perform charging compensation for the overloaded image. If the image scene type is a normal image, a low level is provided as the image detection signal to the compensation trigger module 20 to disable the charging compensation function, avoiding excessive intervention in normal image scenes. This ensures display uniformity while reducing panel power consumption and the risk of signal distortion.

[0100] Step S20: When the screen detection signal is a level trigger signal for a reloaded screen, control the compensation trigger module 20 to generate a clock signal based on the level trigger signal.

[0101] In this embodiment, through the electrical connection between the signal trigger terminal of the compensation trigger module 20 and the first signal interface of the screen detection module 10, after the compensation trigger module 20 receives the screen detection signal sent by the screen detection module 10, the compensation trigger module 20 automatically generates a pre-corrected clock signal based on the screen detection signal as a high-level trigger signal. This allows the charging compensation module 30, which is electrically connected to the compensation trigger module 20, to increase the rising / falling edge slope of the clock signal by boosting the voltage, thereby offsetting the charging time deviation caused by the panel RC load and eliminating the color shift phenomenon in the center of the screen.

[0102] Step S30: Control the charging compensation module 30 to perform charging compensation according to the clock signal.

[0103] In this embodiment, through the electrical connection between the signal input terminal of the charging compensation module 30 and the signal output terminal of the compensation trigger module 20, the charging compensation module 30 performs voltage boosting processing on the clock signal to increase the rising / falling edge slope of the clock signal, thereby realizing waveform compensation of the clock signal waveform and forming the compensated waveform B20 shown in Figure 4, so that the compensated charging time ti is consistent with the ideal charging time t0, so as to eliminate the color shift phenomenon caused by the timing delay of the actual waveform B10 shown in Figure 4.

[0104] Furthermore, in some other feasible embodiments, the charging compensation module 30 includes a boost compensation unit, and the above step S20: controlling the charging compensation module 30 to perform charging compensation according to the clock signal may also include implementing steps S201 to S202.

[0105] Step S201: Determine the voltage gain factor of the boost compensation unit, and control the charging compensation module 30 to boost the clock voltage threshold of the clock signal according to the voltage gain factor.

[0106] In this embodiment, the charging compensation module 30 provided in this application includes a boost compensation unit, which may include an operational amplifier OP1, a first resistor R1, and a second resistor R2. Since the voltage gain factor is [1+(R1 / R2)], the voltage gain factor of the boost compensation unit can be accurately obtained by calculating the resistance ratio of the first resistor R1 and the second resistor R2. Next, based on the product of the voltage gain factor and the clock voltage threshold, the boosted clock voltage threshold can be accurately obtained.

[0107] Step S202: Perform charging compensation on the display panel during the heavy load screen according to the clock voltage threshold after boosting.

[0108] In this embodiment, the charging time (and the compensated charging time) under the horizontal alternating bright and black drawing is made consistent with the ideal charging time by the boosted clock voltage threshold Vout, so as to eliminate the timing delay caused by the RC load. This can effectively suppress the color shift phenomenon caused by the increase of black level brightness and the decrease of white level brightness due to the difference of RC load, thereby significantly improving the uniformity of the ultra-large screen display.

[0109] Furthermore, in some feasible embodiments, the charging compensation module 30 includes a gate voltage detection unit 31 and a voltage compensation unit 32. The above step S20, which controls the charging compensation module 30 to perform charging compensation according to the clock signal, may also include implementing steps A10 to A20.

[0110] Step A10: Control the gate voltage detection unit 31 to collect the right-side trace voltage, middle trace voltage and left-side trace voltage of each gate trace line by line when the clock signal is collected, and determine the average voltage detection value based on the right-side trace voltage, middle trace voltage and left-side trace voltage of each gate trace.

[0111] In this embodiment, through the electrical connection between the gate voltage detection unit 31 and the compensation trigger module 20, the compensation trigger module 20 responds to the level trigger signal during heavy screen loads and outputs a clock signal to the voltage detection unit 31. The voltage detection unit 31 responds to the rising or falling edge of the clock signal to start a voltage detection cycle. During the voltage detection cycle, the gate voltage detection unit 31 performs line-by-line scanning and voltage acquisition operations on a corresponding number of gate traces according to the preset detection quantity set by the user. The preset detection quantity is the number of gate traces that the user flexibly sets according to the actual application scenario (such as panel size, process fluctuation range, or real-time requirements). Specifically, it can be configured to detect 1, 2, or N (N≥3) gate traces, so that the gate voltage detection unit 31 can achieve the best balance between detection accuracy and processing efficiency to meet the optimization needs of different application scenarios.

[0112] Specifically, for each selected gate trace, the voltage values ​​at three specific locations on the gate trace are synchronously acquired by the voltage detection unit 31 using a built-in multiplexer and analog-to-digital converter circuit. The first is the voltage at the left starting point of the gate trace, defined as the left-side trace voltage (i.e., VL1, VL2, VL3, VL4, ..., and VLn as shown in Figure 6); the second is the voltage near the geometric midpoint of the gate trace, defined as the middle trace voltage (i.e., V_m1, V_m2, V_m3, V_m4, ..., and V_mn as shown in Figure 6); and the third is the voltage at the right starting point of the gate trace, defined as the right-side trace voltage (i.e., Vr1, Vr2, Vr3, Vr4, ..., and Vrn as shown in Figure 6).

[0113] After the voltage acquisition of the preset number of gate traces is completed, the voltage data of each gate trace is processed by the data processing chip of the gate voltage detection unit 31. Specifically, for a single gate trace i (i = 1, 2, 3, ..., n), firstly, the voltage difference between the left and right trace voltages and the middle trace voltage of this single gate trace i is calculated, that is, the voltage difference between the left trace voltage VLi and the middle trace voltage V_mi (VLi-V_mi), and the voltage difference between the right trace voltage Vri and the middle trace voltage V_mi (Vri-V_mi). Next, the arithmetic mean of the calculated voltage difference (VLi-V_mi) and the voltage difference (Vri-V_mi) is taken as the average trace voltage difference of gate trace i. Subsequently, the gate voltage detection unit 31 sends the data packet carrying the average trace voltage difference of each trace to the screen detection module 10 through a serial or parallel communication interface, and the screen detection module 10 performs average processing on the average trace voltage difference of all gate traces (i.e., the preset number of gate traces to be detected). This allows for the accurate acquisition of a voltage detection average value that excludes gate trace process deviations. Subsequently, the clock signal carrying the voltage detection average value is sent to the voltage compensation unit 32 through the second signal terminal of the screen detection module 10. The voltage compensation unit 32 then performs voltage boosting processing on the voltage detection average value according to a preset feedback boosting algorithm. This allows for targeted compensation of charging time deviations caused by trace impedance differences through the boosted voltage detection average value. As a result, the charging time (and the compensated charging time) under alternating bright and black horizontal images is consistent with the ideal charging time. This not only effectively eliminates the local errors that may be introduced by traditional single-point detection, but also adapts to the RC load differences in different areas (especially the middle and edges of large-size panels), significantly improving the uniformity of charging across the entire screen. Ultimately, this solves display quality problems such as color shift and brightness unevenness from the signal source, and is especially suitable for surface uniformity optimization of ultra-large-size display panels under heavy load images.

[0114] It should be noted that, if further improvement in data accuracy is required, the intermediate line voltage V_mi of gate line i (i = 1, 2, 3, ..., n) can be divided into voltage V_mri and voltage V_mLi. Voltage V_mLi refers to the voltage value from the left end of gate line i to its geometric midpoint, and voltage V_mri refers to the voltage value from the right end of gate line i to its geometric midpoint.

[0115] In a specific embodiment, when the preset detection quantity is 1 line, the gate voltage detection unit 31 performs the above voltage acquisition and line averaging process only on a single representative gate trace i (i = A) (such as the gate trace in the central area of ​​the panel as shown in Figure 8, the key gate trace determined based on historical data, or the gate trace at the farthest end of the driver chip represented by the black rectangle list in Figure 8). The gate voltage detection unit 31 has the fastest detection speed and the lowest system resource consumption when the preset detection quantity is 1 line. It is suitable for scenarios with extremely high real-time requirements and good panel uniformity (i.e., small-size display panel scenarios, such as smartphones, smartwatches, and portable device screens). For example, referring to Figure 8, when the gate voltage detection unit 31 locates the gate trace i (i=A) according to the preset row scanning sequence, it synchronously acquires four key voltage values ​​on the gate trace i (i=A), namely, the voltage VLA at the starting point of the left end of the trace, the voltage V_mLA at the midpoint of the left half of the trace, the voltage V_mrA at the midpoint of the right half of the trace, and the voltage VrA at the starting point of the right end of the trace; next, it calculates the voltage difference (VLA-V_mLA) and the voltage difference (VrA-V_mrA) respectively; then it performs an arithmetic average of the two voltage difference values ​​to output a more accurate average trace voltage difference value of the gate trace i (i=A) [(VLA-V_mLA)+(VrA-V_mrA)] / 2; and uses this average trace voltage difference value [(VLA-V_mLA)+(VrA-V_mrA)] / 2 as the voltage detection average value of the gate trace i (i=A).

[0116] To improve detection accuracy, the amount of data detected can be increased, which can increase the number of gate lines detected, such as increasing the number of gate lines detected to N, where N is greater than or equal to 2 and is a natural number.

[0117] In a preferred embodiment, when the preset number of gate lines to be detected is 2, referring to FIG9, since the gate traces on the side away from the driver chip (the black rectangular column shown in FIG9) usually have the longest transmission path and the largest RC load, their voltage attenuation and signal delay phenomena are the most significant. The gate voltage detection unit 31 performs voltage detection on the gate traces i (i=1,2) on the side away from the driver chip. That is to say, the voltage detection of the gate voltage detection unit 31 when the preset number of detection is 2 is suitable for medium-sized display panel scenarios (such as tablet computers, laptops, and automotive displays). For example, the gate voltage detection unit 31 acquires four key voltage values ​​(i.e., voltage VL1, voltage V_mL1, voltage V_mr1, and voltage Vr1) on gate line i (i=1) and four key voltage values ​​(i.e., voltage VL2, voltage V_mL2, voltage V_mr2, and voltage Vr2) on gate line i (i=2) line by line according to a preset row scan; then, the average voltage detection value of gate line i (i=1,2) is calculated based on the four key voltage values ​​on gate line i (i=1) and the four key voltage values ​​on gate line i (i=2).

[0118] Additionally, it should be noted that the expression for the average voltage detection value of gate trace i (i = 1, 2) is as follows:

[0119]

[0120] In a preferred embodiment, to further improve detection accuracy, the number of gate lines detected is further increased by setting the number of detections to N, where N is greater than 2. When the preset number of detections is N (N=n), referring to Figure 10, since the gate traces on the side furthest from the driver chip (the black rectangular column shown in Figure 10) usually have the longest transmission path and the largest RC load, their voltage attenuation and signal delay phenomena are the most significant. That is, the N (N=n) gate traces at the farthest end of the driver chip are selected as the preset number of gate traces to be detected. In other words, the gate voltage detection unit 31 will perform voltage detection on the gate traces i (i=1,2,3...n) on the side furthest from the driver chip. In other words, the voltage detection of the gate voltage detection unit 31 when the preset number of detections is N is suitable for display scenarios where there are certain fluctuations in the manufacturing process or significant differences in the RC load of different areas of the panel (i.e., ultra-large size, high resolution display panels, such as high-end TVs, commercial large screens, and gaming monitors). For large and medium-sized, ultra-large, and high-resolution display panels, voltage attenuation and signal delay are generally more significant at the mid-to-far ends, causing severe color shift. Therefore, multiple gate lines can be detected at the mid-to-far ends of the panel to collect data. Similarly, for color shift issues caused by uneven RC load, voltage drop, or signal attenuation due to panel manufacturing processes, multiple gate lines can also be detected. Since color shift may not occur at the mid-to-far ends but can occur anywhere on the panel, the positions of the multiple detection gate lines can be set across the entire display panel, or they can be set based on the locations where color shift is more likely to occur. This application does not impose any limitations on this.

[0121] Specifically, for a single gate trace i (i = 1, 2, 3, ..., n), firstly, the voltage difference between the left and right trace voltages and the middle trace voltage of this single gate trace i is calculated, that is, the voltage difference between the left trace voltage VLi and the middle trace voltage V_mi (VLi-V_mi), and the voltage difference between the right trace voltage Vri and the middle trace voltage V_mi (Vri-V_mi). Next, the arithmetic mean of the calculated voltage difference (VLi-V_mi) and the voltage difference (Vri-V_mi) is taken as the average trace voltage difference of gate trace i. Subsequently, the gate voltage detection unit 31 sends the data packet carrying the average trace voltage difference of each trace to the screen detection module 10 through a serial or parallel communication interface, and the screen detection module 10 performs average processing on the average trace voltage difference of N gate traces to accurately obtain a voltage detection average value that excludes gate trace process deviations. Based on the above principles and processes, the display panel completes voltage detection of multiple gate traces through the driving module and the control module.

[0122] Additionally, it should be noted that the expression for the average voltage detection value of gate trace i (i = 1, 2, 3... n) is:

[0123]

[0124] Where n represents the preset detection quantity; the more preset detection quantities, the more accurate the average voltage detection value. Specifically, the average voltage difference of the n gate traces detected by the gate voltage detection unit 31 is transmitted to the image detection module 10. The image detection module 10 averages the average voltage difference of the n gate traces to obtain a clock signal carrying the average voltage detection value. This clock signal is then output to the internal voltage compensation unit 32 to boost the voltage (i.e., the resistance ratio). The boosted clock signal waveform (i.e., the clock signal waveform carrying the boosted average voltage detection value) is then given to the level conversion integrated chip 40 for real-time adjustment. Finally, the boosted clock signal waveform is output (i.e., the clock signal waveform carrying the boosted average voltage detection value). This achieves the effect of the same charging time for panels with different process effects, eliminates the influence of inter-chip differences, and achieves color shift consistency.

[0125] Step A20: Generate a clock signal carrying the average voltage detection value based on the clock signal and the average voltage detection value, and control the voltage compensation unit 32 to perform charging compensation on the clock signal based on the average voltage detection value.

[0126] In this embodiment, the voltage compensation unit 32 integrated in the level conversion integrated chip 40 performs voltage boosting processing on the average voltage detection value according to a preset feedback boosting algorithm. This allows the boosted average voltage detection value to specifically compensate for the charging time deviation caused by the difference in trace impedance, making the charging time (and the compensated charging time) under alternating bright and black horizontal images consistent with the ideal charging time. This not only effectively eliminates the local errors that may be introduced by traditional single-point detection, but also adapts to the RC load differences in different areas (especially the middle and edges of large-size panels), significantly improving the uniformity of charging across the entire screen. Ultimately, this solves display quality problems such as color shift and brightness unevenness from the signal source, and is especially suitable for optimizing the surface uniformity of ultra-large-size display panels under heavy load images.

[0127] In summary, the electrical connection between the compensation trigger module 20 and the image detection module 10 in this application can effectively eliminate the color shift problem of ultra-large H-Line images. It can detect H-Line images and perform waveform compensation on the clock signal output by the compensation trigger module 20 based on the H-Line image through the boost compensation unit shown in Figure 3, which is electrically connected to the compensation trigger module 20. It exits compensation when there is a non-H-line image (i.e., normal image) to prevent overcompensation for normal images. It can also achieve the same charging time by using the level conversion integrated chip 40 that integrates the compensation trigger module 20 and the voltage compensation unit 32 to connect to panels with different process effects, thereby eliminating the influence of inter-chip differences and achieving the consistency of eliminating color shift.

[0128] In addition, this application also provides a display panel, the display panel including the driving circuit described in any of the above claims, the driving circuit including a screen detection module, a compensation trigger module and a charging compensation module;

[0129] The display panel includes a display area and a non-display area surrounding the display area. The display panel is fixedly provided with multiple parallel gate traces. The non-display area is provided with a gate voltage detection unit in the charging compensation module on the side near the circuit board. The screen detection module and the level conversion integrated chip are fixedly arranged on the circuit board. The compensation trigger module and the voltage compensation unit in the charging compensation module are integrated into the level conversion integrated chip.

[0130] Furthermore, this application also provides a display device. Please refer to Figure 11, which is a schematic diagram of the structure of the display device involved in the embodiment of this application. Specifically, the display device in this embodiment may be a device for locally running a panel compensation method.

[0131] As shown in Figure 11, the display device in this embodiment may include: a display panel or processor 1001, such as a CPU, a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen and an input unit such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).

[0132] The memory 1005 is disposed on the main body of the display device. The memory 1005 stores a program that performs corresponding operations when executed by the processor 1001. The memory 1005 is also used to store parameters used by the display device. The memory 1005 can be a high-speed RAM or a stable, non-volatile memory, such as a disk storage device. Optionally, the memory 1005 can also be a storage device independent of the aforementioned processor 1001.

[0133] Those skilled in the art will understand that the display device structure shown in FIG11 does not constitute a limitation on the display device, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0134] As shown in Figure 11, the memory 1005, which serves as a storage medium, may include an operating system, a network communication module, a user interface module, and a panel compensation program.

[0135] In the display device shown in FIG11, the processor 1001 can be used to call the panel compensation program stored in the memory 1005 and execute the steps of the panel compensation method as described above.

[0136] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0137] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0138] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a display device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0139] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A driving circuit for a display panel, characterized in that, The driving circuit includes: a screen detection module, configured to detect the screen scene type of the input screen and determine a screen detection signal based on the screen scene type; a compensation trigger module, the signal trigger terminal of which is electrically connected to the first signal interface of the screen detection module, configured to receive the screen detection signal sent by the screen detection module and generate a clock signal based on the level trigger signal of the screen detection signal being a reloaded screen; and a charging compensation module, the signal input terminal of which is electrically connected to the signal output terminal of the compensation trigger module, configured to perform charging compensation based on the clock signal sent by the compensation trigger module; the compensation trigger module includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a sixth switch; the gate terminals of the first and third switches and the first path terminal of the fifth switch are respectively connected to a power supply terminal, and the first path terminal of the first switch... The first terminal of the first switch is electrically connected to the first path terminal of the third switch; the connection point of the first path terminal of the first switch electrically connected to the first path terminal of the third switch forms the signal output terminal of the compensation trigger module, which is electrically connected to the signal input terminal of the charging compensation module; the second path terminal of the first switch is electrically connected to the first path terminal of the second switch, and the second path terminal of the second switch is grounded; the gate terminal of the second switch forms the signal trigger terminal of the compensation trigger module, which is electrically connected to the first signal interface of the image detection module, the gate terminal of the fifth switch, and the gate terminal of the sixth switch respectively; the second path terminal of the fifth switch is electrically connected to the first path terminal of the sixth switch, and the second path terminal of the sixth switch is grounded; the gate terminal of the fourth switch intersects at the connection point of the second path terminal of the fifth switch electrically connected to the first path terminal of the sixth switch; the first path terminal of the fourth switch is electrically connected to the second path terminal of the third switch, and the second path terminal of the fourth switch is grounded.

2. The driving circuit as described in claim 1, characterized in that, The charging compensation module includes a boost compensation unit; the non-inverting input terminal of the boost compensation unit constitutes the signal input terminal of the charging compensation module and is electrically connected to the signal output terminal of the compensation trigger module; the out-of-inverting input terminal of the boost compensation unit is connected to the signal output terminal of the boost compensation unit.

3. The driving circuit as described in claim 1, characterized in that, The driving circuit includes a level conversion integrated chip, the charging compensation module includes a gate voltage detection unit and a voltage compensation unit, and the compensation trigger module and the voltage compensation unit are integrated within the level conversion integrated chip; the clock signal terminal of the gate voltage detection unit constitutes the signal input terminal of the charging compensation module and is electrically connected to the signal output terminal of the compensation trigger module; the right voltage sampling terminal of the gate voltage detection unit is electrically connected to the right trace terminal of each gate trace, the left voltage sampling terminal of the gate voltage detection unit is electrically connected to the left trace terminal of each gate trace, the detection output terminal of the gate voltage detection unit is electrically connected to the signal acquisition terminal of the image detection module; the second signal terminal of the image detection module is electrically connected to the voltage compensation unit.

4. The driving circuit as described in claim 3, characterized in that, The gate voltage detection unit is configured to, in response to a clock signal sent by the compensation trigger module, perform voltage acquisition line by line for a preset number of gate traces, acquire the left-side trace voltage, middle trace voltage, and right-side trace voltage of each gate trace, determine the average voltage detection value based on the right-side trace voltage, middle trace voltage, and left-side trace voltage of each gate trace, and transmit a clock signal carrying the average voltage detection value to the voltage compensation unit via the screen detection module; the voltage compensation unit is configured to, upon receiving the clock signal carrying the average voltage detection value, perform charging compensation on the clock signal based on the average voltage detection value.

5. A panel compensation method, characterized in that, The panel compensation method is applied to the driving circuit according to any one of claims 1 to 4. The panel compensation method includes: after determining the scene type of the input screen, controlling the screen detection module to determine the screen detection signal according to the scene type; when the screen detection signal is a level trigger signal of a reloaded screen, controlling the compensation trigger module to generate a clock signal according to the level trigger signal; and controlling the charging compensation module to perform charging compensation according to the clock signal.

6. The panel compensation method as described in claim 5, characterized in that, The charging compensation module includes a boost compensation unit. The step of controlling the charging compensation module to perform charging compensation based on a clock signal includes: determining the voltage gain factor of the boost compensation unit, and controlling the charging compensation module to boost the clock voltage threshold of the clock signal based on the voltage gain factor; and performing charging compensation on the display panel during the heavy load screen based on the boosted clock voltage threshold.

7. The panel compensation method as described in claim 5, characterized in that, The charging compensation module includes a gate voltage detection unit and a voltage compensation unit. The step of controlling the charging compensation module to perform charging compensation based on a clock signal includes: controlling the gate voltage detection unit to collect the right-side trace voltage, middle trace voltage, and left-side trace voltage of each gate trace line by line when the clock signal is acquired, and determining the average voltage detection value based on the right-side trace voltage, middle trace voltage, and left-side trace voltage of each gate trace; generating a clock signal carrying the average voltage detection value based on the clock signal and the average voltage detection value, and controlling the voltage compensation unit to perform charging compensation on the clock signal based on the average voltage detection value.

8. A display panel, characterized in that, The display panel includes the driving circuit according to any one of claims 1 to 4, the driving circuit including a screen detection module, a compensation trigger module and a charging compensation module; the display panel includes a display area and a non-display area surrounding the display area, the display panel is fixedly provided with a plurality of parallel gate traces, the non-display area is provided with a gate voltage detection unit in the charging compensation module on the side near the circuit board, the screen detection module and the level conversion integrated chip are fixedly arranged on the circuit board, the compensation trigger module and the voltage compensation unit in the charging compensation module are integrated in the level conversion integrated chip.

9. A display device, characterized in that, The display device includes the display panel of claim 8; or, a memory, a processor, and a panel compensation program stored in the memory and executable on the processor, wherein the processor, when executing the panel compensation program, implements the steps of the panel compensation method of any one of claims 5 to 7.

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