Display panel, driving method and display device

Abstract

Embodiments of the present application provide a display panel, a driving method and a display device, and relate to the technical field of display panels. In the display panel, a first target time interval between an end time of a bias reset stage of a pixel circuit in a first display area and a start time of a light emitting stage is different from a second target time interval between an end time of a bias reset stage of a pixel circuit in a second display area and a start time of a light emitting stage; and / or, a third target time interval between an end time of an initialization stage of the pixel circuit in the first display area and a start time of a data writing stage is different from a fourth target time interval between an end time of an initialization stage of the pixel circuit in the second display area and a start time of a data writing stage. According to the embodiments of the present application, the problem of display unevenness that occurs when different refresh rates are used in different partitions of a display screen can be fully solved, thereby effectively improving the display effect of the display screen.

Description

Technical Field

[0001] This application belongs to the field of display panel technology, and particularly relates to a display panel, driving method and display device. Background Technology

[0002] With the rapid development of display technology, new types of display panels, such as Organic Light Emitting Diode (OLED) and Micro Light Emitting Diode (micro LED), are emerging in an endless stream. Full-screen displays have become the development trend of mobile display devices such as mobile phones. Display devices, such as mobile phones, use different refresh rates in different application scenarios: for example, a high refresh rate is used in scenarios that require smooth display; while a low refresh rate can be used to reduce power consumption when displaying certain static images.

[0003] Currently, considering market demand, a dynamic partitioned refresh scheme for displays has been proposed in related technologies. This scheme divides the display screen into several partitions, and the refresh rate of each partition can be independently set according to actual display requirements. By dynamically adjusting the refresh rate of the display panel partitions using this technology, the power consumption of the display driver can be effectively reduced. However, the inventors have discovered that when different display partitions in a current display use different refresh rates, uneven brightness can easily occur. Summary of the Invention

[0004] This application provides a display panel, driving method, and display device that can effectively solve the problem of uneven display when different display zones in a display screen use different refresh rates, thereby effectively improving the display effect and competitiveness of the display panel.

[0005] In a first aspect, embodiments of this application provide a display panel, which includes at least two display areas, including a first display area and a second display area; both the first and second display areas include multiple pixel circuits; wherein the first display area displays using a first refresh rate, and the second display area displays using a second refresh rate; the first refresh rate is different from the second refresh rate;

[0006] The pixel circuits in the first and second display areas each include a non-light-emitting stage and a light-emitting stage in a frame. The non-light-emitting stage includes an initialization stage, a data writing stage, and a bias reset stage.

[0007] During operation, a first target duration is elapsed between the end of the bias reset phase of the pixel circuit in the first display area and the start of the light emission phase; a second target duration is elapsed between the end of the bias reset phase of the pixel circuit in the second display area and the start of the light emission phase; wherein the first target duration is different from the second target duration.

[0008] And / or, a third target duration is elapsed between the end of the initialization phase of the pixel circuit in the first display area and the start of the data writing phase, and a fourth target duration is elapsed between the end of the initialization phase of the pixel circuit in the second display area and the start of the data writing phase; wherein the third target duration is different from the fourth target duration.

[0009] Based on the same inventive concept, in a second aspect, embodiments of this application provide a driving method applied to the display panel of the aforementioned first aspect embodiment, the driving method comprising:

[0010] During display operation, a first target duration is controlled between the end of the bias reset phase of the pixel circuit in the first display area and the start of the light emission phase, and a second target duration is controlled between the end of the bias reset phase of the pixel circuit in the second display area and the start of the light emission phase; wherein, the first target duration is different from the second target duration.

[0011] And / or, control the interval between the end of the initialization phase of the pixel circuit in the first display area and the start of the data writing phase to be a third target duration, and control the interval between the end of the initialization phase of the pixel circuit in the second display area and the start of the data writing phase to be a fourth target duration; wherein the third target duration is different from the fourth target duration.

[0012] Based on the same inventive concept, in a third aspect, embodiments of this application provide a display device, which includes a display panel as described in the aforementioned first aspect embodiment.

[0013] As described above, the present application provides a display panel, driving method, and display device. The display panel includes a first display area and a second display area that display at different refresh rates. In the display panel, a first target duration is set between the end time of the bias reset phase of the pixel circuit in the first display area and the start time of the light emission phase, which is different from the second target duration between the end time of the bias reset phase of the pixel circuit in the second display area and the start time of the light emission phase. And / or, a third target duration is set between the end time of the initialization phase of the pixel circuit in the first display area and the start time of the data writing phase, which is different from the fourth target duration between the end time of the initialization phase of the pixel circuit in the second display area and the start time of the data writing phase. Compared to existing technologies, the display panel, driving method, and display device of this application embodiment, for display zones in the display panel that use different refresh rates, adjust the degree of influence of bias stress on the driving transistors by setting different driving timing sequences for the pixel circuits under each display zone, so as to fully solve the problem of uneven display when different display zones in the display screen use different refresh rates, thereby improving the brightness uniformity of the display panel and enhancing the competitiveness of the display panel. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0016] Figure 2 This is a timing diagram of a display panel provided in an embodiment of this application;

[0017] Figure 3 This is a schematic diagram of another display panel structure provided in an embodiment of this application;

[0018] Figure 4 This is a timing diagram of another display panel provided in an embodiment of this application;

[0019] Figure 5 This is a timing diagram of another display panel provided in an embodiment of this application;

[0020] Figure 6 This is a schematic diagram of a pixel circuit provided in an embodiment of this application;

[0021] Figure 7This is a timing diagram of another display panel provided in an embodiment of this application;

[0022] Figure 8 This is a timing diagram of another display panel provided in an embodiment of this application;

[0023] Figure 9 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this application;

[0024] Figure 10 This is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0025] Figure 11 This is a timing diagram of another display panel provided in an embodiment of this application;

[0026] Figure 12 This is a timing diagram of another display panel provided in an embodiment of this application;

[0027] Figure 13 This is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0028] Figure 14 This is a timing diagram of another display panel provided in an embodiment of this application;

[0029] Figure 15 This is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0030] Figure 16 This is a schematic diagram of the structure of another display panel provided in the embodiments of this application;

[0031] Figure 17 This is a schematic diagram of the structure of another display panel provided in the embodiments of this application;

[0032] Figure 18 This is a timing diagram of another display panel provided in an embodiment of this application;

[0033] Figure 19 This is a flowchart illustrating a driving method provided in an embodiment of this application;

[0034] Figure 20 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0035] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0036] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0037] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0038] It should be noted that the transistors in the embodiments of this application can be either N-type or P-type transistors. For N-type transistors, the on-state level is high and the off-state level is low. That is, when the gate of an N-type transistor is high, its first and second terminals are connected; when the gate of an N-type transistor is low, its first and second terminals are off. For P-type transistors, the on-state level is low and the off-state level is high. That is, when the control terminal of a P-type transistor is low, its first and second terminals are connected; when the control terminal of a P-type transistor is high, its first and second terminals are off. In specific implementations, the gate of each transistor is used as its control terminal. Furthermore, depending on the signal and type of the gate of each transistor, its first terminal can be used as the source and its second terminal as the drain, or vice versa. No distinction is made here. Additionally, the on-state and off-state levels in the embodiments of this invention are general terms. The on-state level refers to any level that enables the transistor to conduct, and the off-state level refers to any level that enables the transistor to turn off / become off.

[0039] In the embodiments of this application, the term "electrical connection" can refer to a direct electrical connection between two components, or it can refer to an electrical connection between two components via one or more other components.

[0040] In the embodiments of this application, the first node, the second node, and the third node are defined only for the convenience of describing the circuit structure, and the first node, the second node, and the third node are not actual circuit units.

[0041] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0042] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies:

[0043] As mentioned above, the inventors of this application have discovered that, with the rapid development of display technology, a dynamic partitioned refresh scheme for a display screen has been proposed in related technologies. This scheme divides the display screen into several partitions, and the refresh rate of each partition can be independently set according to actual display requirements. By using this technology to dynamically adjust the refresh rate of the display panel partitions, the power consumption of the display screen driver can be effectively reduced.

[0044] For example, in practical applications, a lower refresh rate can be used to reduce power consumption for areas of the display screen that need to display slow-motion images or static images; while for sections of the display screen that need to display audio-visual playback or game scenes, a higher refresh rate is required to avoid flicker and improve the display effect.

[0045] However, further research by the inventors of this application revealed that when different display zones in a current display screen employ different refresh rates, uneven brightness can easily occur. Specifically, the brightness of display zones with lower refresh rates gradually decreases during frame holding, creating a difference in brightness compared to zones with higher refresh rates, thus causing overall uneven brightness across the display panel. The reason for this is that when the display zones are driven at low frequencies, the image remains / holds for a longer period, causing the driving transistors to experience prolonged voltage stress, resulting in a threshold voltage shift. This alters the current flowing through the driving transistors, leading to variations in the brightness of the display panel and consequently, uneven display brightness.

[0046] In view of the above research findings, the embodiments of this application provide a display panel, a driving method, and a display device, which can solve the problem of uneven display brightness caused by different refresh rates used in different zones of the display panel in the related art.

[0047] It should be noted that the embodiments provided in this application are not intended to limit the scope of this application.

[0048] The technical concept of this application embodiment is as follows: for display zones in a display panel that use different refresh rates for display, by setting different driving timing sequences for the pixel circuits under each display zone, the degree of influence of bias stress on the driving transistors can be adjusted, so as to improve the brightness uniformity of the display panel and enhance the competitiveness of the display panel.

[0049] The display panel provided in the embodiments of this application will be described first. The display panel provided in the embodiments of this application can be an organic light-emitting diode (OLED) display panel or other types, without specific limitations. Those skilled in the art should understand that in other implementations of this application, the display panel can also be a micro LED display panel, a quantum dot display panel, etc.

[0050] Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of this application is shown. Figure 1As shown in the illustration, a display panel 100 provided in this application embodiment includes at least two display areas, including a first display area A1 and a second display area A2. In some cases, the number of display areas divided in the display panel can be set according to actual display requirements.

[0051] Both the first display area A1 and the second display area A2 include multiple pixel circuits. The first display area A1 uses a first refresh rate F1, while the second display area A2 uses a second refresh rate F2; the first refresh rate F1 is different from the second refresh rate F2. For example, the first refresh rate F1 of the first display area A1 may be 60Hz, and the second refresh rate F2 of the second display area A2 may be 120Hz, where F1 ≠ F2. This is just an example; in other cases, the data refresh rates of the first display area A1 and the second display area A2 can be set according to actual needs.

[0052] To facilitate the subsequent development of the solution, the definition of the refresh rate used in each display area mentioned in this application will be explained below. In the field of display panel technology, frame refresh frequency and data refresh frequency are usually distinguished. The refresh rate mentioned in this application refers to the data refresh rate frequency. Generally, the frame refresh frequency is the frequency of change of the smallest unit of screen refresh, the subframe, which is calculated by taking the minimum cycle of one light-emitting stage. The data refresh frequency refers to the frequency at which data voltage is written to the gate of the driving transistor. The data refresh cycle corresponds to the data refresh frequency. For example, if the data refresh frequency is 120Hz, then the data refresh cycle is 1 / 120 of a second. A data refresh cycle usually includes one data write frame and several hold frames. A data write frame refers to a subframe in which data voltage is written to the gate of the driving transistor, and a hold frame refers to a subframe in which no data signal is written to the gate of the driving transistor.

[0053] Taking a display panel with a frame refresh rate of 120Hz as an example, a data refresh rate of 60Hz means that one data refresh cycle includes one data write frame and one hold frame; when the data refresh rate is 30Hz, it means that one data refresh cycle includes one data write frame and three hold frames, and so on.

[0054] The pixel circuits in the first display area A1 and the second display area A2 mentioned above each include a non-light-emitting stage and a light-emitting stage in one frame. The non-light-emitting stage includes an initialization stage, a data writing stage, and a bias reset stage. In the initialization stage, an initialization signal is transmitted to the control terminal of the driving module to eliminate residual charge from the previous display frame, thereby preventing residual charge from the previous frame from affecting the next frame. In the data writing stage, a data voltage is written to the control terminal of the driving module in the pixel circuit; different written data voltages result in different brightness levels of the subsequent light-emitting elements. In the bias reset stage, a bias voltage is written to the first or second terminal of the driving module to reset the first and second terminals, thereby adjusting the bias state of the driving module. In the light-emitting stage, the driving module provides a driving current based on the data voltage written in the previous data writing stage to drive the light-emitting elements to emit light. Specifically, the driving module may include a driving transistor, which can be a PMOS transistor or an NMOS transistor.

[0055] Please see Figure 2 , Figure 2 This is a timing diagram of a display panel provided in an embodiment of this application. It should be noted that... Figure 2 The enable level of the stage control signal corresponding to the initialization stage shown is high, while the enable level for the other stages is low. For example... Figure 2 As shown, during operation, the time interval between the end of the bias reset phase of the pixel circuit in the first display area A1 and the start of the light emission phase is a first target duration T1. The time interval between the end of the bias reset phase of the pixel circuit in the second display area A2 and the start of the light emission phase is a second target duration T2.

[0056] The interval between the end of the initialization phase of the pixel circuit in the first display area A1 and the start of the data writing phase is a third target duration T3, and the interval between the end of the initialization phase of the pixel circuit in the second display area A2 and the start of the data writing phase is a fourth target duration T4. Wherein, the first target duration T1 differs from the second target duration T2, and / or, the third target duration T3 differs from the fourth target duration T4.

[0057] In other words, by setting the interval duration between the pixel circuit initialization stage and the data writing stage in the first display area A1 to be different from that in the second display area A2, and / or setting the interval duration between the pixel circuit bias reset stage and the light emitting stage in the first display area A1 to be different from that in the second display area A2, the degree of voltage stress on the pixel circuits in the display areas with different refresh rates is adjusted针对性调节,进而改善不同显示区域显示亮度不一致的问题。

[0058] From the above description, it can be seen that a display panel 100 provided by an embodiment of the present application includes a first display area A1 and a second display area A2 that display at different refresh rates. In this display panel, the first target duration T1 between the end moment of the bias reset stage and the start moment of the light emitting stage of the pixel circuit in the first display area A1 is different from the second target duration T2 between the end moment of the bias reset stage and the start moment of the light emitting stage of the pixel circuit in the second display area A2, and / or the third target duration T3 between the end moment of the initialization stage and the start moment of the data writing stage of the pixel circuit in the first display area A1 is different from the fourth target duration T4 between the end moment of the initialization stage and the start moment of the data writing stage of the pixel circuit in the second display area A2. That is: T1≠T2, and / or, T3≠T4.

[0059] Compared with the prior art, a display panel 100 provided by an embodiment of the present application, for the first display area and the second display area that display at different refresh frequencies in the display panel, by setting different driving timings for the pixel circuits in each display area to adjust the degree of influence of the bias voltage stress on the driving transistors, it can fully solve the problem of uneven display when different refresh rates are used in different display partitions of the display screen, and achieve the purpose of improving the brightness uniformity of the display panel and enhancing the competitiveness of the display panel.

[0060] According to some embodiments of the present application, optionally, more specifically, if the first refresh rate F1 is lower than the second refresh rate F2, for example, the first refresh rate F1 adopted by the first display area A1 is 60Hz, and the second refresh rate F2 of the second display area A2 is 120Hz, F1 < F2. In such a case, the above first target duration T1 is less than the second target duration T2; and / or, the third target duration T3 is less than the fourth target duration T4.

[0061] Please refer to Figure 3 , Figure 3 is a schematic structural diagram of another display panel provided by an embodiment of the present application. According to some embodiments of the present application, optionally, as Figure 3 In the illustrated display panel, the first display area A1 may include a first pixel circuit 10, and the second display area A2 may include a second pixel circuit 20. The circuit structures of the first pixel circuit 10 and the second pixel circuit can be identical, differing only in aspects such as the relevant control timing. Alternatively, in some other feasible embodiments, the circuit structure of the first pixel circuit 10 may differ from that of the second pixel circuit 20, and this application does not impose specific limitations on this.

[0062] The following description, in conjunction with specific illustrations, explains the following in the above embodiment: if the first refresh rate F1 is lower than the second refresh rate F2, then the first target duration T1 is less than the second target duration T2; and / or, the third target duration T3 is less than the fourth target duration T4.

[0063] Please see Figure 4 , Figure 4 This is a timing diagram of another display panel provided in an embodiment of this application. Figure 4 Taking the data writing frame as an example, in the same frame, the start time of the light emission stage of the first pixel circuit 10 and the second pixel circuit 20 is the same, and the end time of the bias reset stage of the first pixel circuit 10 is earlier than the end time of the bias reset stage of the second pixel circuit 20.

[0064] For example, in the field of display panel technology, cascaded shift registers are typically used to provide light-emitting control signals to each row of pixel circuits to control the specific time period of the light-emitting phase of each row of pixel circuits. In this context, the start times of the light-emitting phases of the first pixel circuit 10 and the second pixel circuit 20 are the same, which can be understood as the first pixel circuit 10 and the second pixel circuit 20 being pixel circuits in the same row of the display panel 10.

[0065] When the first refresh rate F1 is less than the second refresh rate F2 and the start time of the light emission phase of the first pixel circuit 10 and the second pixel circuit 20 is the same, the first target duration T1 is less than the second target duration T2 by setting the end time of the bias reset phase of the first pixel circuit 10 earlier than the end time of the bias reset phase of the second pixel circuit 20.

[0066] That is, by controlling the specific occurrence time of the pixel circuit bias reset phase in different display areas to be different, the interval between the bias reset phase and the light emission phase of the pixel circuit in the first display area A1 is less than the interval between the bias reset phase and the light emission phase of the pixel circuit in the second display area A2, thereby improving the brightness uniformity of display zones at different refresh rates.

[0067] For example, the first display area A1 is a low refresh rate area, and the second display area A2 is a high refresh rate area. High refresh rate areas typically do not have holding frames, and their brightness decays less during a single frame display time; low refresh rate areas have longer holding frames, and their brightness decays significantly during a single frame display time. In this embodiment, the second pixel circuit 20 in the second display area A2 is configured to reach the light-emitting stage only after a relatively long reset time following a bias reset. This changes the stress level of the driving module in the pixel circuit of the high refresh rate area, causing the brightness of the high refresh rate area A2 to decrease during the light-emitting stage of the data writing frame. This reduces the brightness difference between the high refresh rate area A2 and the low refresh rate area A1, helping to improve the brightness uniformity of the display panel.

[0068] Please see Figure 5 , Figure 5 This is a timing diagram of another display panel provided in an embodiment of this application. According to some embodiments of this application, optionally, the first display area A1 may include a first pixel circuit 10, and the second display area A2 may include a second pixel circuit 20.

[0069] Figure 5 Taking the data writing frame as an example again, in the same frame, the start time of the data writing phase of the first pixel circuit 10 and the second pixel circuit 20 is the same. The end time of the initialization phase of the first pixel circuit 10 is later than the end time of the initialization phase of the second pixel circuit 20.

[0070] For example, in the field of display panel technology, cascaded gate drive circuits are typically used to provide gate drive signals to each row of pixel circuits to control the specific time periods of multiple stages, including the data writing stage, in each row of pixel circuits. In this context, the start times of the data writing stages of the first pixel circuit 10 and the second pixel circuit 20 are consistent, which can be understood as the first pixel circuit 10 and the second pixel circuit 20 being pixel circuits in the same pixel scan row of the display panel 10.

[0071] When the first refresh rate F1 is less than the second refresh rate F2, and the start time of the data writing phase of the first pixel circuit 10 and the second pixel circuit 20 is the same, the third target duration T3 is less than the fourth target duration T4 by setting the end time of the initialization phase of the first pixel circuit 10 to be later than the end time of the initialization phase of the second pixel circuit 20.

[0072] That is, by controlling the specific timing of the pixel circuit initialization phase in different display areas, the interval between the initialization phase and the data writing phase of the pixel circuit in the first display area A1 is made shorter than the interval between the initialization phase and the data writing phase of the pixel circuit in the second display area A2, thereby improving the brightness uniformity of display zones at different refresh rates.

[0073] For example, assume a first refresh rate F1 = 1Hz and a second refresh rate F2 = 120Hz. In this case, the first display area A1 is a low refresh rate area, and the second display area A2 is a high refresh rate area. High refresh rate areas typically do not have hold frames, resulting in less brightness decay within a single frame display time; low refresh rate areas have longer hold frames, leading to significant brightness decay within a single frame display time. In this embodiment, the first pixel circuit 10 in the first display area A1 is configured to perform data writing shortly after initialization and reset. This changes the stress level of the driving module in the pixel circuit within the low refresh rate area from a temporal perspective, enhancing the reset capability of the data writing frame in the low refresh rate area. This facilitates better data voltage writing during the data writing phase, thereby increasing the display brightness of the low refresh rate area, reducing the brightness difference with the low-frequency area A1, and contributing to improved brightness uniformity of the display panel.

[0074] According to some embodiments of this application, optionally, and considering the actual pixel circuit structure, please refer to the following... Figure 6 , Figure 6 This is a schematic diagram of a pixel circuit provided in an embodiment of this application. Figure 6 As shown, the pixel circuits in both the first display area A1 and the second display area A2 may include a driving module 101, a data writing module 102, a threshold compensation module 103, and an initialization module 104. It should be noted that... Figure 6 The pixel circuit in the middle reuses the data writing module 102 as a bias reset module. The data writing module 102 implements the data writing function and the bias reset function in a time-division multiplexing manner.

[0075] Specifically, the control terminal of the initialization module 104 is electrically connected to the first scan signal line S1, the first terminal of the initialization module 104 is electrically connected to the first reference level voltage terminal Vref1, and the second terminal of the initialization module 104 is electrically connected to the control terminal of the drive module 101. The control terminal of the data writing module 102 is electrically connected to the second scan signal line S2, the first terminal of the data writing module 102 is electrically connected to the data voltage signal line Data, and the second terminal of the data writing module 102 is electrically connected to the first terminal of the drive module 101. The control terminal of the threshold compensation module 103 is electrically connected to the third scan signal line S3, the first terminal of the threshold compensation module 103 is electrically connected to the control terminal of the drive module 101, and the second terminal of the threshold compensation module 103 is electrically connected to the second terminal of the drive module 101.

[0076] and Figure 6 For the pixel circuit structure shown, please refer to [link / reference]. Figure 7 , Figure 7 This is a timing diagram of another display panel provided in the embodiments of this application. The following is in conjunction with... Figure 7The timing diagram illustrates the pixel circuitry for the first refresh rate F1 and the second refresh rate F2. In this embodiment, the enable levels output by the first scan signal line S1 and the third scan signal line S3 are high, while the others are low.

[0077] like Figure 7 As shown, when the display panel 100 is working, during the initialization phase, the first scan signal line S1 outputs an enable level. Under the control of the initialization module 104, the first scan signal line S1 is turned on, and the initialization signal provided by the first reference level voltage terminal Vref1 is transmitted to the control terminal of the drive module 101 to initialize the drive module 101.

[0078] During the data writing phase, the second scan signal line S2 outputs an enable level, the third scan signal line S3 outputs an enable level, and the data writing module 102 transmits the data voltage provided by the data voltage signal line Data to the first terminal of the drive module 101. The data voltage at the first terminal of the drive module 101 is written to the control terminal of the drive module 101 via the activated drive module 101 and the threshold compensation module 103.

[0079] During the bias reset phase, the second scan signal line S2 outputs an enable level, and the data writing module 102 transmits the bias voltage provided by the data voltage signal line Data to the first terminal of the drive module 101.

[0080] According to some embodiments of this application, in order to further adjust the display brightness of display zones in the display panel that display at different refresh rates, so as to improve the overall brightness uniformity of the display panel, improve the display effect of the display panel, and enhance product competitiveness, please refer to the following... Figure 8 , Figure 8 This is a timing diagram of another display panel provided in an embodiment of this application. For example... Figure 8 As shown, the first refresh rate F1 is less than the second refresh rate F2, and the first display area A1 is a low refresh rate area. During display operation, the first display area A1 can include data write frames and hold frames.

[0081] In the holding frame of the first display area A1, the bias voltage provided by the data voltage signal line Data during the bias reset phase is the first bias voltage. In the data writing frame of the first display area A1, the bias voltage provided by the data voltage signal line Data during the bias reset phase is the second bias voltage. The first bias voltage is greater than the second bias voltage.

[0082] In practice, the bias state of the driving module in the pixel circuit is adjusted by different bias voltages. The magnitude of the bias voltage affects the adjustment process of the driving module's bias state. When the first display area and the second display area have different refresh rates to achieve different display functions, the requirements for the pixel circuit are different, resulting in different bias states of the driving module. In this case, the bias voltage of the pixel circuit in the low refresh rate area A1 during the hold frame can be increased to compensate for the characteristic shift caused by the driving module maintaining the same working state for a long time at low frequency, thereby improving the driving performance of the driving module, and thus improving the display brightness of the first display area A1 in the hold frame. This further reduces the phenomenon of uneven display brightness in the display panel, improves the display effect and competitiveness of the display panel.

[0083] It should be understood that the voltage values ​​of the first bias voltage and the second bias voltage can be designed according to the actual situation such as the size of the display area, the refresh rate of the display area, and the luminous brightness of the light-emitting element. This embodiment of the invention does not limit this.

[0084] According to some embodiments of this application, optionally, please continue to refer to... Figure 8 . Figure 8 In the illustrated display panel 100, the first refresh rate F1 of the first display area A1 is less than the second refresh rate F2 of the second display area A2. For example, the first refresh rate F1 = 1Hz and the second refresh rate F2 = 120Hz. The first display area A1 is a low refresh rate area, and the second display area A2 is a high refresh rate area. The second display area A2 may include a data write frame during display operation. In the data write frame of the first display area A1, the bias voltage provided by the data voltage signal line Data during the bias reset phase is consistent with the data voltage provided during the data write phase.

[0085] In the data write frame of the second display area A2, the bias voltage provided by the data voltage signal line Data during the bias reset phase is consistent with the data voltage provided during the data write phase. This consistency between the bias voltage and the data voltage helps reduce the signal modulation frequency and signal complexity in the data voltage signal line Data, thus enhancing the competitiveness of the display panel.

[0086] According to some embodiments of this application, optionally, for reasons similar to those in the foregoing embodiments, in order to more fully adjust the display brightness of different display zones corresponding to different refresh rates in the display panel, so as to further improve the overall brightness uniformity of the display panel, during the initialization phase, the voltage value of the initialization signal provided by the first reference level voltage terminal Vref1 in the first display area A1 is less than the voltage value of the initialization signal provided by the first reference level voltage terminal Vref1 in the second display area A2.

[0087] In practice, the initialization level of the drive module control terminal in the pixel circuit is adjusted by varying the voltage values ​​of different initialization signals. The voltage of the initialization signal is closely related to the initialization reset level, which in turn affects the completeness of the elimination of residual charge from the previous frame on the drive module control terminal. The initialization reset level also affects the subsequent drive current. When the first display area and the second display area have different refresh rates to achieve different display functions, the requirements for the pixel circuits differ, resulting in different device characteristics for the drive modules of each pixel circuit. In this case, the voltage value of the initialization signal provided by the first reference level voltage terminal Vref1 in the second display area A2 can be increased. This ensures that when the same data voltage is written to the first display area A1 and the second display area A2, the drive current of the second pixel circuit 20 in the second display area A2 will be smaller during the light-emitting stage, resulting in lower brightness in the second display area A2 and reducing the brightness difference between the first display area A1 and the second display area A2.

[0088] Of course, in some other feasible implementations, the voltage value of the initialization signal provided by the first reference level voltage terminal Vref1 in the first display area A1 can be lowered to perform more thorough initialization of the drive module control terminal, which is conducive to increasing the drive current in the light emission stage, thereby increasing the display brightness of the first display area A1 and improving the brightness uniformity of the display panel. This application does not impose specific limitations on this.

[0089] It should be understood that the voltage values ​​of the initialization signals in the first display area A1 and the second display area A2 can be designed according to the actual situation such as the size of the display area, the refresh rate of the display area, and the brightness of the light-emitting element. This embodiment of the invention does not limit this.

[0090] According to some embodiments of this application, more specifically, please refer to Figure 9 , Figure 9 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this application. For example... Figure 9As shown, in a display panel 100 provided in this application, the pixel circuits in the first display area A1 and the second display area A2 may further include a first light-emitting control module 105, a second light-emitting control module 106, a storage module 107, and an anode reset module 108. Specifically, the control terminal of the first light-emitting control module 105 is electrically connected to the light-emitting control signal line EM, the first end of the first light-emitting control module 105 is electrically connected to the first power supply voltage signal terminal PVDD, and the second end of the first light-emitting control module 105 is electrically connected to the first end of the driving module 101. The control terminal of the second light-emitting control module 106 is electrically connected to the light-emitting control signal line EM, the first end of the second light-emitting control module 106 is electrically connected to the second end of the driving module 101, and the second end of the second light-emitting control module 106 is electrically connected to the anode of the light-emitting element. The first end of the storage module 107 is electrically connected to the first power supply voltage signal terminal PVDD, and the second end of the storage module 107 is electrically connected to the control terminal of the driving module 101. The control terminal of the anode reset module 108 is electrically connected to the fourth scan signal line S4, the first terminal of the anode reset module 108 is electrically connected to the second reference level voltage terminal Vref2, and the second terminal of the anode reset module 108 is electrically connected to the anode of the light-emitting element. The light-emitting element can be an LED (Light-Emitting Diode), an OLED (Organic Electroluminescence Display), or others.

[0091] To facilitate understanding of the pixel circuit provided in this application, the following description is provided in conjunction with some specific application embodiments.

[0092] Please see below. Figure 10 , Figure 10 This is a schematic diagram of another pixel circuit provided in an embodiment of this application. Figure 10As shown, according to some embodiments of this application, optionally, the first light-emitting control module 105 may include a first transistor M1, the data writing module 102 may include a second transistor M2, the driving module 101 may include a third transistor M3, the threshold compensation module 103 may include a fourth transistor M4, the initialization module 104 may include a fifth transistor M5, the second light-emitting control module 106 may include a sixth transistor M6, the anode reset module 108 may include a seventh transistor M7, and the storage module 107 may include a storage capacitor Cst. The control terminal of the first transistor M1 is electrically connected to the light-emitting control signal line EM, the first terminal of the first transistor M1 is electrically connected to the first power supply voltage signal terminal PVDD, and the second terminal of the first transistor M1 is electrically connected to the first node N1. The control terminal of the second transistor M2 is electrically connected to the second scan signal terminal, the first terminal of the second transistor M2 is electrically connected to the data voltage signal line Data, and the second terminal of the second transistor M2 is electrically connected to the first node N1. The control terminal of the third transistor M3 is electrically connected to the second node N2, and the first terminal of the third transistor M3 is electrically connected to the first node N1. The control terminal of the fourth transistor M4 is electrically connected to the third scan signal line S3. The first terminal of the fourth transistor M4 is electrically connected to the second node N2, and the second terminal of the fourth transistor M4 is electrically connected to the second terminal of the third transistor M3. The control terminal of the fifth transistor M5 is electrically connected to the first scan signal line S1. The first terminal of the fifth transistor M5 is electrically connected to the first reference level voltage terminal Vref1, and the second terminal of the fifth transistor M5 is electrically connected to the second node N2. The control terminal of the sixth transistor M6 is electrically connected to the light-emitting control signal line EM. The first terminal of the sixth transistor M6 is electrically connected to the second terminal of the third transistor M3, and the second terminal of the sixth transistor M6 is electrically connected to the anode of the light-emitting element. The control terminal of the seventh transistor M7 is electrically connected to the fourth scan signal line S4. The first terminal of the seventh transistor M7 is electrically connected to the second reference level voltage terminal Vref2, and the second terminal of the seventh transistor M7 is electrically connected to the anode of the light-emitting element. The first terminal of the storage capacitor Cst is electrically connected to the first power supply voltage signal terminal PVDD, and the second terminal of the storage capacitor Cst is electrically connected to the second node N2. The aforementioned third transistor M3 (driving transistor) can be an oxide semiconductor transistor, specifically an IGZO (Indium Gallium Zinc Oxide) transistor, or a silicon transistor, specifically an LTPS (Low Temperature Poly-Silicon) transistor, or others.

[0093] It should be understood that, in order to reduce leakage current and thus further ensure the display effect of the display panel 100, the aforementioned fourth transistor M4 and fifth transistor M5 may specifically be dual-gate thin-film transistors. Alternatively, in some other feasible embodiments, the fourth transistor M4 and fifth transistor M5 may also be IGZO (Indium Gallium Zinc Oxide) transistors, and this application does not impose specific limitations on this.

[0094] and Figure 10 For the pixel circuit structure shown, please refer to [link / reference]. Figure 11 , Figure 11 This is a timing diagram of another pixel circuit provided in an embodiment of this application. It is understood that, considering the widespread application of the 7T1C structure in the panel industry, for the sake of brevity, this embodiment uses... Figure 10 The specific working process of the 7T1C pixel circuit shown is not described in detail here; its specific working process can be found in conjunction with... Figure 11 The timing pairs shown Figure 10 The pixel circuit shown.

[0095] However, it should be noted that, Figure 11 If the first refresh rate F1 is lower than the second refresh rate F2, for example, the first refresh rate F1 used by the first display area A1 is 60Hz and the second refresh rate F2 used by the second display area A2 is 120Hz, then the first target duration T1 is less than the second target duration T2; and / or, the third target duration T3 is less than the fourth target duration T4.

[0096] According to some embodiments of this application, optionally, in order to further improve the display brightness of the low refresh rate area in the display panel, so as to fully improve the overall brightness uniformity of the display panel, please refer to the following... Figure 12 , Figure 12 This is a timing diagram of another display panel provided in an embodiment of this application. For example... Figure 12 As shown, if the first display area A1 is a low refresh rate area, the first display area A1 can include a data write frame and a hold frame during display operation. The duration d2 of the bias reset phase in the hold frame of the first display area A1 is greater than the duration d1 of the bias reset phase in the data write frame of the first display area A1, thereby enabling the pixel circuit of the first display area A1 to perform a more thorough bias reset on the driving transistor (third transistor M3) during the hold frame. This helps to increase the driving current provided by the third transistor M3 during the light emission phase in the hold frame, thereby improving the display brightness of the low refresh rate area in the hold frame, delaying the brightness decay phenomenon of the low refresh rate area in the hold frame, and thus significantly improving the overall brightness uniformity of the display panel.

[0097] It should be added that, in some other feasible implementations, the pixel circuits included in the first display area and the second display area in this application are not limited to the 7T1C shown in the foregoing embodiments. Optionally, please refer to... Figure 13 , Figure 13 This is a schematic diagram of another pixel circuit provided in an embodiment of this application. Figure 13 In the 8T1C pixel circuit shown, an eighth transistor M8 is added to implement the bias reset function. The gate of the eighth transistor M8 is electrically connected to the scan signal line S22. When the scan signal line S22 provides an enable level, it transmits the bias voltage to the first terminal of the third transistor M3 to achieve the bias reset of the driving transistor M3. The gate of the second transistor M2, which is used to implement data writing, is electrically connected to the scan signal line S21. The operation of this pixel circuit can be specifically combined with... Figure 14 As shown in the timing diagram, this application will not elaborate further here.

[0098] Optional, Figure 15 This is a schematic diagram of another pixel circuit provided in an embodiment of this application. Figure 15 and Figure 13 The difference is: Figure 15 The first terminal of the eighth transistor is electrically connected to the second terminal of the driving transistor M3, and is used to transmit the bias voltage to the second terminal of the third transistor M3 when the scan signal line S22 provides an enable level. And, for brevity, Figure 15 The working process of the pixel circuit shown can also be specifically combined with Figure 14 As shown in the timing diagram, this application will not elaborate further here.

[0099] Please see below. Figure 16 , Figure 16 This is a schematic diagram of another pixel circuit provided in an embodiment of this application. Figure 16 As shown, according to some embodiments of this application, optionally, and considering actual display needs, the display panel 100 may include at least two first display areas A1 and one second display area A2. The two first display areas A1 are separated by the second display area A2.

[0100] Please see below. Figure 17 , Figure 17 This is a schematic diagram of another pixel circuit provided in an embodiment of this application. Figure 17 As shown, according to some embodiments of this application, further considering the multi-refresh-rate zone display requirements of the display panel, the above-mentioned display panel 100 may also include a third display area A3. It is worth noting that... Figure 16 and Figure 17The display areas shown are horizontally divided, but this application is not limited thereto. In some other embodiments, the display areas in the display panel may also be vertically divided, or divided according to irregular shapes, and this application does not impose strict limitations on this.

[0101] Please see below. Figure 18 , Figure 18 This is a schematic diagram of another pixel circuit provided in an embodiment of this application. Figure 18 As shown, the third display area A3 adopts a third refresh rate F3, which is different from the first refresh rate F1 and the second refresh rate F2. When the display panel 100 is performing display operations, the interval between the end of the bias reset phase of the pixel circuit in the third display area A3 and the start of the light emission phase is a fifth target duration T5. This fifth target duration T5 is different from the first target duration T1 and the second target duration T2.

[0102] And / or, the interval between the end of the initialization phase of the pixel circuit in the third display area A3 and the start of the data writing phase is a sixth target duration T6. The sixth target duration T6 is different from the third target duration T3 and different from the fourth target duration T4.

[0103] Please continue reading Figure 18 According to some embodiments of this application, more specifically, the first refresh rate F1 is lower than the second refresh rate F2, and the second refresh rate F2 is lower than the third refresh rate F3. The aforementioned first target duration T1 is less than the second target duration T2, and the second target duration T2 is less than the fifth target duration T5.

[0104] And / or, the duration of the third objective T3 is less than the duration of the fourth objective T4, and the duration of the fourth objective T4 is less than the duration of the sixth objective T6.

[0105] Taking a display panel with a frame refresh rate of 120Hz as an example, let's assume the first refresh rate F1 = 30Hz, the first refresh rate F2 = 60Hz, and the third refresh rate F3 = 120Hz. Combined with... Figure 18 As shown, the first refresh rate F1 is 30Hz, so one data refresh cycle of the pixel circuit in the first display area A1 includes one data write frame and three hold frames (the complete data refresh cycle is not shown in the figure). The second refresh rate F2 is 60Hz, so one data refresh cycle of the pixel circuit in the second display area A2 includes one data write frame and one hold frame. The third refresh rate F3 is 120Hz, so one data refresh cycle of the pixel circuit in the first display area A1 includes one data write frame.

[0106] In this embodiment, by setting different driving timings for the pixel circuits in each display area: T1 < T2 < T5, and / or, T3 < T4 < T6, the problem of uneven display that occurs when different refresh rates are used in different display partitions of the display screen can be fully solved, achieving the purpose of improving the brightness uniformity of the display panel and enhancing the competitiveness of the display panel.

[0107] Based on the display panel provided in the above embodiment, correspondingly, an embodiment of the present application further provides a driving method. A driving method according to an embodiment of the present application can be applied to the display panel provided in any of the foregoing embodiments.

[0108] Figure 19 It is a schematic flowchart of a driving method provided in an embodiment of the present application. As Figure 19 shown, a driving method according to an embodiment of the present application may include the following steps:

[0109] S1901, during the display operation, control the interval between the end moment of the bias reset stage and the start moment of the light-emitting stage of the pixel circuit in the first display area to be a first target duration, and control the interval between the end moment of the bias reset stage and the start moment of the light-emitting stage of the pixel circuit in the second display area to be a second target duration; wherein, the first target duration is different from the second target duration;

[0110] S1902, and / or, control the interval between the end moment of the initialization stage and the start moment of the data writing stage of the pixel circuit in the first display area to be a third target duration, and control the interval between the end moment of the initialization stage and the start moment of the data writing stage of the pixel circuit in the second display area to be a fourth target duration; wherein, the third target duration is different from the fourth target duration.

[0111] It should be understood that, for the sake of brevity, the specific implementation processes of S1901 and S1902 can refer to the corresponding description parts in the foregoing text, and will not be elaborated here.

[0112] In this embodiment, by controlling the first target duration between the end moment of the bias reset stage and the start moment of the light-emitting stage of the pixel circuit in the first display area, which is different from the second target duration between the end moment of the bias reset stage and the start moment of the light-emitting stage of the pixel circuit in the second display area, and / or, controlling the third target duration between the end moment of the initialization stage and the start moment of the data writing stage of the pixel circuit in the first display area, which is different from the fourth target duration between the end moment of the initialization stage and the start moment of the data writing stage of the pixel circuit in the second display area, to improve the brightness uniformity.

[0113] Specifically, one driving method in this application embodiment, for display zones in a display panel that use different refresh rates, sets different driving timing sequences for the pixel circuits under each display zone to adjust the degree of influence of bias stress on the driving transistors, so as to fully solve the problem of uneven display when different display zones in the display screen use different refresh rates, thereby improving the brightness uniformity of the display panel and enhancing the competitiveness of the display panel.

[0114] Based on the display panel provided in the above embodiments, this application also provides a display device, including the display panel provided in this application. Please refer to... Figure 20 , Figure 20 This is a schematic diagram of a display device provided in an embodiment of this application. Figure 20 The provided display device 1000 includes the display panel 100 provided in any of the above embodiments of this application. Figure 20 The embodiments use a mobile phone as an example to describe the display device 1000. It is understood that the display device provided in the embodiments of this application can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices. This application does not impose specific limitations on these. The display device provided in the embodiments of this application has the beneficial effects of the display panel 100 provided in the embodiments of this application. For details, please refer to the specific descriptions of the display panel 100 in the above embodiments. These descriptions will not be repeated here.

[0115] It should be understood that the specific circuit structures and cross-sectional structures of the display panels provided in the accompanying drawings of the embodiments of this application are merely examples and are not intended to limit this application. Furthermore, the above embodiments provided in this application can be combined with each other unless there is contradiction.

[0116] It should be clarified that the various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. According to the embodiments described above, these embodiments do not exhaustively describe all details, nor do they limit this application to only the specific embodiments described. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to make good use of this application and modifications based on it. This application is limited only by the claims and their full scope and equivalents.

[0117] Those skilled in the art will understand that the above embodiments are exemplary and not restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Based on a study of the drawings, specification, and claims, those skilled in the art should be able to understand and implement other variations of the disclosed embodiments. In the claims, the term "comprising" does not exclude other structures; the quantity refers to "one" but does not exclude multiple; the terms "first" and "second" are used to identify names and not to indicate any particular order. Any reference numerals in the claims should not be construed as limiting the scope of protection. The appearance of certain technical features in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

Claims

1. A display panel, characterized in that, The display panel includes at least two display areas, including a first display area and a second display area; both the first display area and the second display area include multiple pixel circuits; wherein the first display area uses a first refresh rate for display, and the second display area uses a second refresh rate for display; the first refresh rate is different from the second refresh rate; The pixel circuits in the first display area and the second display area each include a non-light-emitting stage and a light-emitting stage in one frame. The non-light-emitting stage includes an initialization stage, a data writing stage, and a bias reset stage. During display operation, a first target duration is elapsed between the end of the bias reset phase of the pixel circuit in the first display area and the start of the light emission phase; a second target duration is elapsed between the end of the bias reset phase of the pixel circuit in the second display area and the start of the light emission phase; wherein, the first target duration is different from the second target duration. And / or, a third target duration is elapsed between the end of the initialization phase of the pixel circuit in the first display area and the start of the data writing phase, and a fourth target duration is elapsed between the end of the initialization phase of the pixel circuit in the second display area and the start of the data writing phase; wherein the third target duration is different from the fourth target duration; The first refresh rate is lower than the second refresh rate; the first target duration is less than the second target duration; and / or, the third target duration is less than the fourth target duration.

2. The display panel according to claim 1, characterized in that, The first display area includes a first pixel circuit, and the second display area includes a second pixel circuit; In the same frame, the start time of the light emission phase of the first pixel circuit and the second pixel circuit is the same; The end time of the bias reset phase of the first pixel circuit is earlier than the end time of the bias reset phase of the second pixel circuit.

3. The display panel according to claim 1, characterized in that, The first display area includes a first pixel circuit, and the second display area includes a second pixel circuit; Within the same frame, the start times of the data writing phase for the first pixel circuit and the second pixel circuit are the same; The initialization phase of the first pixel circuit ends later than the initialization phase of the second pixel circuit.

4. The display panel according to claim 2 or 3, characterized in that, The pixel circuits in the first display area and the second display area include a driving module, a data writing module, a threshold compensation module, and an initialization module; The control terminal of the initialization module is electrically connected to the first scan signal line, the first terminal of the initialization module is electrically connected to the first reference level voltage terminal, and the second terminal of the initialization module is electrically connected to the control terminal of the drive module. The control terminal of the data writing module is electrically connected to the second scan signal line, the first terminal of the data writing module is electrically connected to the data voltage signal line, and the second terminal of the data writing module is electrically connected to the first terminal of the drive module. The control terminal of the threshold compensation module is electrically connected to the third scan signal line, the first terminal of the threshold compensation module is electrically connected to the control terminal of the drive module, and the second terminal of the threshold compensation module is electrically connected to the second terminal of the drive module. During the initialization phase, the first scan signal line outputs an enable level, and the initialization module transmits the initialization signal provided by the first reference level voltage terminal to the control terminal of the drive module to initialize the drive module. During the data writing phase, the second scan signal line outputs an enable level, the third scan signal line outputs an enable level, and the data writing module transmits the data voltage provided by the data voltage signal line to the first terminal of the driving module. The data voltage at the first end of the driving module is written to the control terminal of the driving module via the turned-on driving module and the threshold compensation module; During the bias reset phase, the second scan signal line outputs an enable level, and the data writing module transmits the bias voltage provided by the data voltage signal line to the first terminal of the drive module.

5. The display panel according to claim 4, characterized in that, The first display area includes data write frames and hold frames during display operation; In the hold frame of the first display area, the bias voltage provided by the data voltage signal line during the bias reset phase is the first bias voltage; In the data writing frame of the first display area, the bias voltage provided by the data voltage signal line during the bias reset phase is the second bias voltage; Wherein, the first bias voltage is greater than the second bias voltage.

6. The display panel according to claim 5, characterized in that, The second display area includes data writing frames during display operation; In the data writing frame of the first display area, the bias voltage provided by the data voltage signal line during the bias reset phase is consistent with the data voltage provided during the data writing phase; In the data write frame of the second display area, the bias voltage provided by the data voltage signal line during the bias reset phase is the same as the data voltage provided during the data write phase.

7. The display panel according to claim 1, characterized in that, The first display area includes data write frames and hold frames during display operation; The duration of the bias reset phase in the hold frame of the first display area is greater than the duration of the bias reset phase in the data write frame of the first display area.

8. The display panel according to claim 1, characterized in that, include: During the initialization phase, the voltage value of the initialization signal provided by the first reference level voltage terminal in the first display area is less than the voltage value of the initialization signal provided by the first reference level voltage terminal in the second display area.

9. The display panel according to claim 1, characterized in that, The display panel includes at least two first display areas and one second display area; The two first display areas are separated by a second display area.

10. The display panel according to claim 1, characterized in that, The display panel also includes a third display area; the third display area adopts a third refresh rate, which is different from the first refresh rate and different from the second refresh rate; During operation, the interval between the end of the bias reset phase of the pixel circuit in the third display area and the start of the light emission phase is a fifth target duration; wherein, the fifth target duration is different from the first target duration and different from the second target duration; And / or, the interval between the end of the initialization phase of the pixel circuit in the third display area and the start of the data writing phase is a sixth target duration; wherein the sixth target duration is different from the third target duration and different from the fourth target duration.

11. The display panel according to claim 10, characterized in that, The first refresh rate is lower than the second refresh rate, and the second refresh rate is lower than the third refresh rate; The first target duration is less than the second target duration, and the second target duration is less than the fifth target duration; And / or, the duration of the third target is less than the duration of the fourth target, and the duration of the fourth target is less than the duration of the sixth target.

12. The display panel according to claim 4, characterized in that, The pixel circuits in the first display area and the second display area further include a first light emission control module, a second light emission control module, a storage module, and an anode reset module; The control terminal of the first light-emitting control module is electrically connected to the light-emitting control signal line, the first terminal of the first light-emitting control module is electrically connected to the first power supply voltage signal terminal, and the second terminal of the first light-emitting control module is electrically connected to the first terminal of the driving module. The control terminal of the second light-emitting control module is electrically connected to the light-emitting control signal line, the first terminal of the second light-emitting control module is electrically connected to the second terminal of the driving module, and the second terminal of the second light-emitting control module is electrically connected to the anode of the light-emitting element. The first end of the storage module is electrically connected to the first power supply voltage signal terminal, and the second end of the storage module is electrically connected to the control terminal of the drive module. The control terminal of the anode reset module is electrically connected to the fourth scan signal line, the first terminal of the anode reset module is electrically connected to the second reference level voltage terminal, and the second terminal of the anode reset module is electrically connected to the anode of the light-emitting element.

13. The display panel according to claim 12, characterized in that, The first light-emitting control module includes a first transistor, the data writing module includes a second transistor, the driving module includes a third transistor, the threshold compensation module includes a fourth transistor, the initialization module includes a fifth transistor, the second light-emitting control module includes a sixth transistor, the anode reset module includes a seventh transistor, and the storage module includes a storage capacitor. The control terminal of the first transistor is electrically connected to the light emission control signal line, the first terminal of the first transistor is electrically connected to the first power supply voltage signal terminal, and the second terminal of the first transistor is electrically connected to the first node. The control terminal of the second transistor is electrically connected to the second scan signal line, the first terminal of the second transistor is electrically connected to the data voltage signal line, and the second terminal of the second transistor is electrically connected to the first node. The control terminal of the third transistor is electrically connected to the second node, and the first terminal of the third transistor is electrically connected to the first node; The control terminal of the fourth transistor is electrically connected to the third scan signal line, the first terminal of the fourth transistor is electrically connected to the second node, and the second terminal of the fourth transistor is electrically connected to the second terminal of the third transistor. The control terminal of the fifth transistor is electrically connected to the first scan signal line, the first terminal of the fifth transistor is electrically connected to the first reference level voltage terminal, and the second terminal of the fifth transistor is electrically connected to the second node. The control terminal of the sixth transistor is electrically connected to the light-emitting control signal line, the first terminal of the sixth transistor is electrically connected to the second terminal of the third transistor, and the second terminal of the sixth transistor is electrically connected to the anode of the light-emitting element. The control terminal of the seventh transistor is electrically connected to the fourth scan signal line, the first terminal of the seventh transistor is electrically connected to the second reference level voltage terminal, and the second terminal of the seventh transistor is electrically connected to the anode of the light-emitting element. The first terminal of the storage capacitor is electrically connected to the first power supply voltage signal terminal, and the second terminal of the storage capacitor is electrically connected to the second node.

14. A driving method, characterized in that, Applied to a display panel as described in any one of claims 1-13, the driving method includes: During display operation, a first target duration is controlled between the end of the bias reset phase of the pixel circuit in the first display area and the start of the light emission phase, and a second target duration is controlled between the end of the bias reset phase of the pixel circuit in the second display area and the start of the light emission phase; wherein, the first target duration is different from the second target duration. And / or, control the interval between the end of the initialization phase of the pixel circuit in the first display area and the start of the data writing phase to be a third target duration, and control the interval between the end of the initialization phase of the pixel circuit in the second display area and the start of the data writing phase to be a fourth target duration; wherein the third target duration is different from the fourth target duration; The first refresh rate is lower than the second refresh rate; the first target duration is less than the second target duration; and / or, the third target duration is less than the fourth target duration.

15. A display device, characterized in that, The display device includes a display panel as described in any one of claims 1-13.

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