Memory and operating method of memory

Abstract

The embodiment of the invention relates to the field of memories, and provides a memory, which comprises an address transmission circuit, and the address transmission circuit comprises a plurality of address latch circuits and a plurality of address transmission paths. Wherein the plurality of address latch circuits receive multi-bit address signals, each address latch circuit comprises an input end, an output end and a reset end, the input end of each address latch circuit receives one bit of address signal, and the output end of each address latch circuit outputs one bit of address signal to a corresponding address transmission path; the reset ends of the plurality of address latch circuits receive reset signals; and after the memory executes a pre-charging operation, the reset signal is in an effective level, so that the output ends of the plurality of address latch circuits output a preset level.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of memory, in particular to a semiconductor memory. BACKGROUND

[0002] In the working process of a semiconductor memory, a data read / write operation is performed on a specified memory cell according to an input address signal. To achieve this process, the prior art usually adopts the following procedure: first, an address latch circuit is used to sample and latch an externally input address signal, and then the latched address is transmitted to an address decoding circuit and a failed address comparison circuit (such as a redundancy repair circuit) to complete key operations such as address decoding and failed address matching. It is worth noting that the memory will perform a global reset operation in the power-on initialization stage, which will reset the address latch circuit synchronously; however, in the subsequent normal working state, the newly input address signal will no longer trigger the reset mechanism of the latch circuit.

[0003] Due to the switching between the logic high level ("1") and the logic low level ("0") of the address signal in the transmission process, the parasitic capacitance coupling effect between the signal lines will cause level distortion. This distortion will directly affect the level recognition accuracy of the address decoding circuit and interfere with the matching judgment accuracy in the failed address comparison circuit, ultimately causing an increase in the row-to-column delay (tRCD). As a key timing parameter that determines the access speed of the memory, the abnormal increase of tRCD will significantly restrict the overall performance of the memory. Although the existing scheme ensures the stability of the initial state through power-on reset, it lacks a dynamic suppression mechanism for the address signal coupling problem in the continuous working state, and an innovative design is urgently needed to solve the timing deterioration problem caused by the coupling effect. SUMMARY

[0004] Embodiments of the present application provide a memory, which at least advantageously solves the problem of tRCD increase.

[0005] According to some embodiments of the present application, the embodiments of the present application provide a memory, comprising an address transmission circuit, the address transmission circuit comprising a plurality of address latch circuits and a plurality of address transmission paths; wherein,

[0006] The plurality of address latch circuits receive a plurality of address signals, each address latch circuit comprising an input end, an output end and a reset end, the input end of each address latch circuit receiving an address signal, the output end of each address latch circuit outputting an address signal to a corresponding address transmission path, and the reset end of the plurality of address latch circuits receiving a reset signal;

[0007] After the memory performs the pre-charge operation, the reset signal is at an active level, so that the output ends of the plurality of address latching circuits output a preset level.

[0008] In some embodiments, the preset level is a high level.

[0009] In some embodiments, the plurality of address transmission paths are adjacent to each other, and no shielding path is arranged between two adjacent address transmission paths.

[0010] In some embodiments, each address transmission path comprises a plurality of first inverters and a plurality of second inverters connected alternately, an input end of a first first inverter being connected to the output end of the address latching circuit; wherein the driving capabilities of the PMOS transistor and the NMOS transistor in the first inverter are different.

[0011] In some embodiments, the driving capability of the PMOS transistor in the first inverter is greater than that of the NMOS transistor.

[0012] In some embodiments, the driving capabilities of the PMOS transistor and the NMOS transistor in the second inverter are different.

[0013] In some embodiments, the driving capability of the PMOS transistor in the second inverter is less than that of the NMOS transistor.

[0014] In some embodiments, the memory performs the pre-charge operation based on a pre-charge flag signal, and the reset signal is a delayed signal of the pre-charge flag signal.

[0015] In some embodiments, the memory further comprises an address decoding circuit and a failed address comparison circuit, the address transmission circuit is connected to the address decoding circuit and the failed address comparison circuit, and outputs an address signal to the address decoding circuit and the failed address comparison circuit.

[0016] According to some embodiments of the present application, another aspect of the embodiments of the present application further provides an operation method of a memory, the memory comprising an address transmission circuit, the address transmission circuit comprising a plurality of address latching circuits and a plurality of address transmission paths; wherein the plurality of address latching circuits receive a plurality of address signals, and the output end of each address latching circuit outputs an address signal to a corresponding address transmission path;

[0017] The operation method comprises:

[0018] performing a pre-charge operation on the memory;

[0019] resetting the output ends of the plurality of address latching circuits to a preset level.

[0020] The technical scheme provided by the embodiment of the application has at least the following advantages.

[0021] First, after the pre-charge operation is completed, the output ends of all address latching circuits are forced to reset to a preset level by applying a valid level reset signal to the reset end of the plurality of address latching circuits, which eliminates the bidirectional level jump phenomenon (i.e., part of the address bits are switched from low level to high level, while another part of the address bits are switched from high level to low level) occurring in the subsequent address transmission process, thereby effectively suppressing the crosstalk noise caused by the level jump and improving the signal quality on the address transmission path. Moreover, based on the elimination of the bidirectional level jump, the address transmission path no longer needs to be provided with a shielding structure to isolate the interference between signals, thereby directly reducing the occupied area of the shielding metal layer and improving the integration density of the memory. According to the embodiment of the application, the transmission path is differentially configured according to the type of the address signal, the signal path that needs to be switched in level is designed by adjusting the driving capability of the transmission path, the driving capability of the circuit on the transmission path is adjusted to adapt to the level jump, and the transmission time of the critical path is shortened, so that the row select to column select delay (tRCD) is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0022] One or more embodiments are illustrated by way of example in the drawings that are not intended to be limiting of the application as disclosed herein, unless otherwise specifically noted, the drawings show possible embodiments of implementing the application as claimed.

[0023] Figure 1 A structure diagram of a memory provided by the embodiment of the present disclosure is provided.

[0024] Figure 2 A structure diagram of an address latching circuit provided by the embodiment of the present application is provided.

[0025] Figure 3 A structure diagram of a reset signal generation circuit provided by the embodiment of the present application is provided.

[0026] Figure 4 A reset signal generation timing diagram provided by the embodiment of the present application is provided.

[0027] Figure 5 A structure diagram of a memory provided by the embodiment of the present application is provided.

[0028] Figure 6 A structure diagram of an address transmission circuit provided by the embodiment of the present application is provided.

[0029] Figure 7 A schematic diagram of an inverter provided by the embodiment of the present application is provided. DETAILED DESCRIPTION

[0030] Hereinafter, exemplary embodiments of the present application will be described in detail with reference to the accompanying drawings so as to be easily practiced by those skilled in the art. As those skilled in the art will readily appreciate, the described embodiments can be modified in various different manners, all without departing from the spirit or scope of the application. For example, the example embodiments provided herein are considered to be able to be implemented by combining them in whole or in part with each other. In particular, one element described in a certain example embodiment, even if not described in another example embodiment, can be understood to be described in relation to the description of another example embodiment, unless a contrary or different description is provided therein.

[0031] Throughout this specification, when any portion is referred to as being "connected" with another portion, it includes both cases where the portion and another portion are "directly connected" with each other and cases where the portion and another portion are "indirectly connected" with each other via still another portion interposed therebetween. For example, it is understood that when an element is referred to as being "connected" or "coupled" with another element or "on" another element, it can be directly connected or coupled with the other element or on the other element, or there can be an intervening element. In contrast, when an element is referred to as being "directly connected" or "directly coupled" with another element or is referred to as "contacting" another element or "contacted" by another element, there is no intervening element at the point of contact.

[0032] In addition, "electrically connected" conceptually includes physical connection and physical disconnection. It is understood that when terms such as "first" and "second" are used in designating an element, the element is not limited thereto. They can be used only for the purpose of distinguishing the element from other elements, and can not limit the order or importance of the element. In some cases, a first element can be referred to as a second element without departing from the scope of the claims set forth herein. Similarly, a second element can also be referred to as a first element.

[0033] As known from the background art, the address latch circuit of the memory in the prior art performs a reset operation only once in the power-on initialization phase, and in the subsequent normal working state, the newly input address signal will no longer trigger the reset mechanism of the address latch circuit. Due to the switching of the logic high level ("1") and the logic low level ("0") of the address signal in the transmission process, the parasitic capacitance coupling effect (Coupling Effect) between the signal lines will cause level distortion. This distortion will directly affect the level recognition accuracy of the address decoding circuit, and interfere with the matching judgment accuracy in the invalid address comparison circuit, ultimately causing an increase in the row selection to column selection delay (tRCD).

[0034] Based on the above problems, the embodiment of the present application provides a memory. After a pre-charge operation is completed, a reset signal at an effective level is applied to the reset end of a plurality of address latching circuits, so that the output ends of all the address latching circuits are forced to reset to a preset level. This operation eliminates the bidirectional level jump phenomenon (i.e., part of the address bits are switched from a low level to a high level, while another part of the address bits are switched from a high level to a low level) occurring in the subsequent address transmission process, thereby effectively suppressing the crosstalk noise caused by the level jump and improving the signal quality on the address transmission path.

[0035] The embodiment of the present application will be described in more detail below with reference to the accompanying drawings.

[0036] Figure 1 A structural schematic diagram of a memory provided by the embodiment of the present application is shown in FIG. 1. Figure 1 The memory 1 comprises an address transmission circuit 11, wherein the address transmission circuit 11 comprises a plurality of address latching circuits 111 and a plurality of address transmission paths 112; wherein,

[0037] The plurality of address latching circuits 111 receive a multi-bit address signal Addr. Specifically, the address signal can be a row address signal and / or a column address signal. The row address signal and the column address signal both have a plurality of bits. For example, the row address signal can have 18 bits, i.e., RA<17:0>. Eighteen row address latching circuits are correspondingly provided for latching the row address signal, and eighteen address transmission paths are correspondingly provided for transmitting the row address. The column address signal can have 10 bits, i.e., CA<9:0>. Ten column address latching circuits are correspondingly provided for latching the column address signal, and ten address transmission paths are correspondingly provided for transmitting the column address.

[0038] Each address latching circuit 111 comprises an input end D, an output end Q and a reset end R. The input end of each address latching circuit receives one bit of the address signal. The output end of each address latching circuit 111 outputs one bit of the address signal Addr to a corresponding address transmission path 112. The reset ends of the plurality of address latching circuits receive a reset signal RST.

[0039] After the memory 1 performs a pre-charge operation, the reset signal RST is at an effective level, so that the output ends of the plurality of address latching circuits output a preset level. The preset level can be a high level "1" or a low level "0".

[0040] Thus, the memory can reset the reset signal RST to the active level after each pre-charge operation based on the pre-charge command or other flag signals of the pre-charge operation, so as to reset the plurality of address latching circuits 111, and make the output ends of the plurality of address latching circuits output a preset level (high level "1" or low level "0"), so that in each subsequent address transmission process, even in the face of multiple different addresses (both high and low levels exist), the output signal of the address latching circuit will only jump in one direction. Specifically, if the preset level is high, then in each subsequent address transmission process, there will only be a jump process from high to low; if the preset level is low, then in each subsequent address transmission process, there will only be a jump process from low to high. Thus, this operation eliminates the bidirectional level jump phenomenon (i.e., part of the address bits are switched from low to high, while another part of the address bits are switched from high to low) that occurs in the subsequent address transmission process, thereby effectively suppressing the crosstalk noise caused by level jump and improving the signal quality on the address transmission path.

[0041] Figure 2 A structural diagram of an address latching circuit provided by an embodiment of the present application is shown in FIG. 1. Referring to FIG. 1, Figure 1 and Figure 2 Taking one address latching circuit 111 as an example, the address latching circuit 111 includes an input end D, an output end Q, a reset end R, and a latch end LAT. The input end D of the address latching circuit 111 receives one bit of address signal (such as one bit of row address signal RA<0>). The output end Q of the address latching circuit 111 outputs one bit of address signal (such as one bit of row address signal RA<0>) to a corresponding address transmission path 112. The reset end R of the address latching circuit 111 receives a reset signal RST.

[0042] Specifically, the address latch circuit 111 includes a first gated inverter GI1, a second gated inverter GI2, and a first NOR gate NOR1. An input terminal of the first gated inverter GI1 is configured as an input terminal D of the address latch circuit 111 and receives an input address signal. An output terminal of the first gated inverter GI1 is connected to one input terminal of the first NOR gate NOR1. Another input terminal of the first NOR gate NOR1 is configured as a reset terminal of the address latch circuit 111 and receives a reset signal RST. An input terminal of the second gated inverter GI2 is connected to an output terminal of the address latch circuit 111. An output terminal of the second gated inverter GI2 is connected to an output terminal of the first gated inverter GI1, which is configured as an output terminal D of the address latch circuit. A non-inversion control terminal (i.e., an enable terminal) of the second gated inverter GI2 is connected to an inversion control terminal of the first gated inverter GI1, which is configured as a latch terminal LAT of the address latch circuit and receives a latch signal. The second gated inverter GI2 and the first NOR gate NOR1 latch and output an input signal under control of the latch signal.

[0043] Figure 2 The address latch circuit is shown by way of a latch, but it should be understood that, in other embodiments of the present application, the address latch circuit can also be a latch circuit such as a D flip-flop, an RS latch, or the like.

[0044] Figure 3 A structure diagram of a reset signal generation circuit is provided for an embodiment of the present application. The memory further includes a reset signal generation circuit 113 connected to the address latch circuit 111 and configured to provide a reset signal for the address latch circuit 111. Taking storage of a row address signal by the address latch circuit 111 as an example, referring to Figure 3 The reset signal generation circuit 113 receives an address flag signal SecEn, which can be an address flag signal obtained by decoding a row address and used to activate a specific memory bank in the memory. The address flag signal SecEn is at a valid level each time the memory receives a new activation command until a precharge operation is performed by the memory. That is, the address flag signal SecEn is at a valid level between a rising edge of an activation command and a rising edge of a precharge command. The address flag signal SecEn can also be a precharge command or a flag signal related to a precharge operation. The address flag signal SecEn is at a valid level each time a precharge operation is performed by the memory. The reset signal generation circuit 113 further receives a test mode signal TM. When a function of resetting the address latch circuit according to a precharge operation is enabled, the test mode signal TM is at a valid level. When the function of resetting the address latch circuit according to a precharge operation is not enabled, the test mode signal TM is at an invalid level.

[0045] The memory 1 includes two working modes, power-on reset mode and pre-charge reset mode, distinguished by the test mode signal TM. TM is high level, indicating that the current is in the pre-charge reset mode, and the output signal of the address latch circuit 111 is reset each time the pre-charge is performed; TM is low level, indicating that the current is in the power-on reset mode, and the output signal of the address latch circuit 111 is reset only after power-on. In the pre-charge reset mode, the reset signal is at an active level each time the memory performs a pre-charge operation, so that the output end of the plurality of address latch circuits outputs a preset level.

[0046] The reset signal generation circuit 113 includes a first NAND gate NAND1, which receives the address flag signal SecEn and the test mode signal TM, and performs NAND operation on the address flag signal SecEn; the output signal of the first NAND gate NAND1, after being inverted and delayed (by a delay unit dly), is used as one of the two input ends of a first AND gate AND1, and the output signal of the first NAND gate NAND1 is used as the other input end of the first AND gate AND1, and the output end of the first AND gate AND1 is used as the pre-charge operation flag signal PrePus, indicating that part of the circuit in the memory performs a pre-charge operation; the pre-charge flag signal PrePus is input to one input end of a first OR gate OR1, and the other input end of the first OR gate OR1 receives the global reset signal Rstbuf, which is at an active level when power-on, so that the reset signal generation circuit 113 can also retain and be compatible with the reset operation of the address latch circuit 111 when power-on in the prior art.

[0047] Figure 4 A reset signal generation timing diagram is provided for the embodiments of the present application. Figure 4 The active level of each signal is high level. Referring to Figure 4 , an active level of the address flag signal SecEn is generated, and the pulse width of the pre-charge flag signal PrePus depends on the size of the delay unit dly in the reset signal generation circuit 113, and after the logic processing and delay of the pre-charge flag signal PrePus by the first OR gate, the reset signal RST is obtained. That is, the memory performs the pre-charge operation based on the pre-charge flag signal, and the reset signal is a delayed signal of the pre-charge flag signal.

[0048] In some embodiments, the preset level outputted by the address latch circuit 111 after reset is high level "1", and the reset operation is performed after each pre-charge operation, so that the output signal of the address latch circuit 111 is high level "1". Thus, in subsequent operations, when the address signal enters the address latch circuit 111, the address signal outputted by the address latch circuit 111 either remains high level "1" or jumps from high level "1" to low level "0". Jumping from high level "1" to low level "0" will not cause interference to the signal line which always transmits high level "1", and if both of the two adjacent address signal lines jump from high level "1" to low level "0", the jumping speed of each other will be accelerated. Thus, the coupling of the address signal can be avoided, so as to improve the tRCD performance.

[0049] Thus, in some embodiments, the plurality of address transmission paths 112 can be arranged adjacent to each other, and no shielding path is arranged between the two adjacent address transmission paths. In the conventional address transmission path, there is interference of bidirectional jumping. In order to reduce the influence of address coupling, a shielding structure (such as a power line coupled to the power voltage (VDD) or ground level (GND) as a shielding line) needs to be arranged between the two address transmission paths. Based on the elimination of bidirectional level jumping, the address transmission path no longer needs to be provided with a shielding structure to isolate the interference between signals, so that the plurality of address transmission paths can be arranged adjacent to each other, and no shielding path is arranged between the two adjacent address transmission paths, thereby directly reducing the area occupied by the shielding metal line or shielding metal layer, saving area resources, and improving the integration density of the memory.

[0050] Figure 5 A structural schematic diagram of a memory provided by the embodiments of the present application is shown. In some embodiments, the memory 1 further comprises an address decoding circuit 12 and a failed address comparison circuit 13, the address transmission circuit 112 is connected to the address decoding circuit 12 and the failed address comparison circuit 13, and outputs an address signal Addr to the address decoding circuit 12 and the failed address comparison circuit 13. Among them, the address signal Addr always represents the address information, although it may be delayed and inverted, but since the information it carries has not changed, the signals inputted to the address latch circuit 111, outputted by the address latch circuit 111 and outputted by the address transmission path are all called address signals Addr.

[0051] Continuing with the example of the address latch circuit 111 latching the row address RA, the address decoding circuit 12 is a row decoder that decodes the row address to select the corresponding word line. The invalid address comparison circuit 13 compares the invalid row address with the row address output by the address latch circuit 111 to determine whether the row address corresponding to the current operation is an invalid address and whether the input row address needs to be replaced by an invalid address. In other embodiments, the address transmission circuit 11 is a first stage circuit of the row decoder and is used to latch the input row address to prepare for decoding of the row address.

[0052] Figure 6 A structure diagram of an address transmission circuit according to an embodiment of the present application. Figure 7 A schematic diagram of an inverter according to an embodiment of the present application. Referring to Figure 7 , the inverter is formed by connecting a PMOS and an NMOS with their control terminals connected as input terminals and their drain terminals connected as output terminals. Referring to Figure 6 Each address transmission path 112 includes a plurality of first inverters INV1 and a plurality of second inverters INV2 connected alternately. The output terminal of a first inverter is connected to the input terminal of a next second inverter, and the output terminal of a second inverter is connected to the input terminal of a next first inverter. The input terminal of a first inverter is connected to the output terminal of the address latch circuit. The PMOS and NMOS transistors in the first inverters INV1 have different driving capabilities.

[0053] Figure 6 The example in FIG. 2 shows two first inverters and one second inverter, but other numbers of first inverters and second inverters are also applicable in the present application. For example, when an address transmission path 112 includes three first inverters and three second inverters, the connection relationship of the inverters is: first inverter-second inverter-first inverter-second inverter-first inverter-second inverter. When an address transmission path 112 includes four first inverters and three second inverters, the connection relationship of the inverters is: first inverter-second inverter-first inverter-second inverter-first inverter-second inverter-first inverter.

[0054] When each address transmission path 112 includes a plurality of first inverters, the driving capability of the PMOS transistor and the NMOS transistor in the first inverter INV1 can be different, the driving capability of the PMOS transistor and the NMOS transistor in each first inverter INV1 of each address transmission path 112 can be different, or the driving capability of the PMOS transistor and the NMOS transistor in the first inverter INV1 at a specific position in each address transmission path 112 can be different. For example, when an address transmission path 112 has five first inverters, the driving capability of the PMOS transistor and the NMOS transistor of only the first and second first inverters can be set to be different, while the driving capability of the PMOS transistor and the NMOS transistor of the third to fifth first inverters can be set to be different. Here, the driving capability of the PMOS transistor and the NMOS transistor refers to the driving capability of the PMOS transistor and the NMOS transistor in the same inverter, i.e., the driving capability of the PMOS transistor to pull up the input level to high level "1" and the driving capability of the NMOS transistor to pull down the input level to "0" are different. That is, the driving capability refers to the comparison of the driving capability of the transistors inside the inverter, rather than the comparison of the driving capability between different inverters. That is, the pull-up capability / speed of the first inverter is greater than the pull-down capability / speed of the first inverter. In another case, the driving capability of the PMOS transistor and the NMOS transistor is only different from the conventional inverter in the prior art, rather than the comparison of the driving capability between the plurality of inverters on the address transmission path 112.

[0055] In some embodiments, the driving capability of the PMOS transistor in the first inverter is greater than the driving capability of the NMOS transistor, and the strength of the driving capability can be designed by adjusting the width-length ratio of the transistor and the like.

[0056] According to the above, the application further differentiates the configuration of the transmission path according to the type of address signal. The signal path requiring level switching adopts the transmission design of driving capacity adjustment, adapts to level jump, and adjusts the driving capacity of the circuit on the transmission path. This design shortens the transmission time of the critical path, so that the row strobe to column strobe delay (tRCD) is reduced. Specifically, after the address latch circuit 111 is reset, the address signal RAO output by the address latch circuit 111 continuously transmits a high level “1”. When the memory receives an activation command, the row address is input with the activation command. At this time, the address signal stored in the address latch circuit 111 can be high level or low level. For the case that the externally given address is high level (i.e. the address signal stored in the address latch circuit 111 is high level), the data on the address transmission path 112 will not flip due to the change of the address, so the pull-up and pull-down driving capacity and transmission speed of the first inverter and the second inverter on the address transmission path 112 have no effect on the transmission of the address signal. For the case that the externally given address is low level (i.e. the address signal stored in the address latch circuit 111 is low level), at this time, since the signal entering the first inverter of the address transmission path 112 is composed of a strong driving capacity PMOS and a weak driving capacity NMOS, at this time, since the input of the first inverter is low level “0”, the PMOS transistor starts to pull up, and the strong driving capacity PMOS can improve the pull-up speed, so that the output of the inverter is quickly pulled up to high level, thereby helping the level on the address transmission path 112 to jump quickly, improving the transmission speed, and reducing tRCD.

[0057] Figure 6 In the embodiment, an address latch circuit 111 and an address transmission path 112 are taken as an example, wherein the address transmission path 112 further includes a plurality of sub-paths (four sub-paths are taken as an example). Figure 6 For example, for a row address transmission path, it will be sent to a plurality of command decoders, row address comparators, row address decoders and the like.

[0058] With reference to the foregoing Figure 6 and Figure 7 In some embodiments, the driving capacities of the PMOS transistor and the NMOS transistor in the second inverter INV2 are different, and the driving capacity of the PMOS transistor in the second inverter INV2 is smaller than that of the NMOS transistor.

[0059] When each address transmission path 112 includes a plurality of second inverters, the driving capability of the PMOS transistor and the NMOS transistor in the second inverter INV2 can be different, that is, the driving capability of the PMOS transistor and the NMOS transistor in each second inverter INV2 of each address transmission path 112 can be different, or the driving capability of the PMOS transistor and the NMOS transistor in the second inverter INV2 at a specific position in each address transmission path 112 can be different. Here, the driving capability of the PMOS transistor and the NMOS transistor refers to the driving capability of the PMOS transistor and the NMOS transistor in the same inverter, that is, the driving capability of the PMOS transistor to pull up the input level to high level "1" and the driving capability of the NMOS transistor to pull down the input level to "0" are different. That is, the pull-up capability / speed of the second inverter is less than the pull-down capability / speed of the second inverter. In another case, the driving capability of the PMOS transistor and the NMOS transistor is different from the conventional inverter in the prior art, rather than the comparison of the driving capability between the plurality of inverters on the address transmission path 112.

[0060] In some embodiments, the driving capability of the PMOS transistor in the second inverter is less than the driving capability of the NMOS transistor, and the strength of the driving capability can be designed by adjusting the width-length ratio of the transistor and the like.

[0061] According to the above, the application further differentiates the transmission path according to the type of address signal, and adopts the transmission design of driving capacity adjustment for the signal path requiring level switching, adjusts the driving capacity of the circuit on the transmission path, and reduces the row selection to column selection delay (tRCD) by shortening the transmission time of the critical path. Specifically, after the address latch circuit 111 is reset, the address signal RAO output by the address latch circuit 111 continuously transmits a high level “1”. When the memory receives an activation command, the row address is input with the activation command, at this time, the address signal stored in the address latch circuit 111 can be high level or low level. For the case that the externally given address is high level (i.e. the address signal stored in the address latch circuit 111 is high level), the data on the address transmission path 112 will not be flipped due to the change of the address, therefore, the driving capacity, transmission speed of the pull-up and pull-down of the second inverter and the second inverter on the address transmission path 112 have no influence on the transmission of the address signal. For the case that the externally given address is low level (i.e. the address signal stored in the address latch circuit 111 is low level), at this time, the external address signal input into the second inverter has been flipped by the first inverter and is high level, since the second inverter entering this signal is composed of a weak driving capacity PMOS and a strong driving capacity NMOS, at this time, since the input of the second inverter is high level “1”, the NMOS transistor starts to pull down, and the strong driving capacity NMOS can improve the pull-down speed, so that the output of the inverter is quickly pulled down to low level, thereby helping the level on the address transmission path 112 to quickly jump, improving the transmission speed, and reducing tRCD.

[0062] In some embodiments, the driving capacity of the PMOS and NMOS in the first inverter and the second inverter on the address transmission path 112 are not the same. Specifically, the row address RA0 output by the address latch circuit 111 enters the first inverter of strong PMOS and weak NMOS, then enters the second inverter of weak PMOS and strong NMOS, and then enters the first inverter of strong PMOS and weak NMOS, and then continues to be transmitted to the next stage.

[0063] The application also provides an operation method of a memory, the memory comprising an address transmission circuit 11, the address transmission circuit 11 comprising a plurality of address latch circuits 111 and a plurality of address transmission paths 112; wherein the plurality of address latch circuits 111 receive a plurality of address signals, and the output end of each address latch circuit outputs one bit of address signal to a corresponding address transmission path;

[0064] The operation method comprises:

[0065] performing a pre-charge operation on the memory;

[0066] resetting the outputs of the plurality of address latches to a preset level.

[0067] In the above embodiments, the resetting of the outputs of the plurality of address latches to a preset level can be performed after each precharge operation of the memory. The resetting signal for resetting the outputs of the plurality of address latches can be generated based on the precharge flag signal. For example, the resetting signal can be a delayed signal of the precharge flag signal.

[0068] Thus, the memory can reset the outputs of the plurality of address latches to the preset level after each precharge operation based on the precharge flag signal, so that the outputs of the plurality of address latches output the preset level (high level "1" or low level "0"). Thus, in the subsequent address transmission process, even if multiple different addresses are faced (both high level and low level exist), the output signal of the address latch will only jump in one direction. Specifically, if the preset level is high level, only the jump process from high level to low level will occur in the subsequent address transmission process. If the preset level is low level, only the jump process from low level to high level will occur in the subsequent address transmission process. Thus, the operation eliminates the bidirectional level jump phenomenon (i.e., part of the address bits are switched from low level to high level, while another part of the address bits are switched from high level to low level) in the subsequent address transmission process, thereby effectively suppressing the crosstalk noise caused by the level jump and improving the signal quality on the address transmission path.

[0069] It is to be understood that the above-described embodiments are merely illustrative of the principles of the application, and that numerous and varied embodiments commensurate with a fair scope of the application may be made by those skilled in the art without departing from the spirit and scope of the application. Any further modifications made to the described embodiments by one of ordinary skill in the art are to be considered within the scope of the application. The scope of the application should be determined by the following claims.

Claims

1. A memory, characterized in that: It includes an address transmission circuit, wherein the address transmission circuit includes multiple address latch circuits and multiple address transmission paths; wherein, Multiple address latch circuits receive multi-bit address signals, each address latch circuit includes an input terminal, an output terminal, and a reset terminal, the input terminal of each address latch circuit receives a single-bit address signal, the output terminal of each address latch circuit outputs a single-bit address signal to a corresponding address transmission path, and the reset terminals of the multiple address latch circuits all receive a reset signal; After the memory performs a precharge operation, the reset signal is at a valid level, so that the output terminals of the plurality of address latch circuits output a preset level.

2. The memory according to claim 1, wherein The preset level is a high level.

3. The memory according to claim 1 or 2, characterized in that The multiple address transmission paths are adjacent to each other, and no shielding path is provided between two adjacent address transmission paths.

4. The memory according to claim 2, wherein: Each address transmission path includes a plurality of first inverters and a plurality of second inverters connected alternately, and an input end of a first first inverter is connected to an output end of the address latch circuit; The driving capabilities of the PMOS transistor and the NMOS transistor in the first inverter are different.

5. The memory according to claim 4, wherein: The driving capability of the PMOS transistor in the first inverter is greater than that of the NMOS transistor.

6. The memory according to claim 4, wherein: The driving capabilities of the PMOS transistor and the NMOS transistor in the second inverter are different.

7. The memory according to claim 6, wherein: The driving capability of the PMOS transistor in the second inverter is smaller than that of the NMOS transistor.

8. The memory according to claim 1, wherein: The memory performs the precharge operation based on a precharge flag signal, and the reset signal is a delayed signal of the precharge flag signal.

9. The memory according to claim 1, wherein: The memory further includes an address decoding circuit and a failed address comparison circuit. The address transmission circuit is connected to the address decoding circuit and the failed address comparison circuit and outputs an address signal to the address decoding circuit and the failed address comparison circuit.

10. A method for operating a memory, characterized in that: The memory includes an address transmission circuit, which includes a plurality of address latch circuits and a plurality of address transmission paths; wherein the plurality of address latch circuits receive multi-bit address signals, and an output end of each address latch circuit outputs a single-bit address signal to a corresponding address transmission path; The operation method includes: performing a precharge operation on the memory; The output terminals of the plurality of address latch circuits are reset to a preset level.

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