Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, in the preparation method, the height of an edge region of a substrate is lower than the height of a non-edge region of the substrate, firstly, an interlayer insulating layer is formed on the substrate; the method comprises the following steps of: forming an interlayer insulating layer on a substrate, etching a non-edge region of the interlayer insulating layer to form a first contact hole, etching an edge region of the interlayer insulating layer to form a second contact hole, forming an adhesion layer on the surface of the substrate in the second contact hole by adopting a thermal oxidation process, and finally depositing a diffusion inhibition layer in the first contact hole and the second contact hole. After the first contact hole and the second contact hole are formed, the adhesion layer is formed on the surface of the substrate in the second contact hole through the thermal oxidation process, the condition that a metal diffusion barrier layer deposited in the second contact hole formed in the edge area of the wafer is peeled off or stripped off can be avoided, and the electrical performance of the device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] In the CMP (chemical mechanical polishing) process of the interlayer insulating medium layer, the polishing amount (polishing thickness) of the interlayer insulating medium layer in the edge region of the wafer is generally greater than the polishing amount (polishing thickness) of the interlayer insulating medium layer in the middle region of the wafer, and in addition to the existence of the PH WEE (wafer edge exposure) related process and the EBR (edge bead removal) related process, the edge region of the wafer is not completely covered by the photoresist and has a certain height difference with the middle region of the wafer, that is, a gentle slope (a gentle slope with a high middle and a low edge), which leads to the fact that when the interlayer insulating medium layer is etched to form a contact hole, the etching depth of the contact hole formed in the edge region of the wafer is much greater than the etching depth of the contact hole in the middle region of the wafer, and there is a situation of silicon substrate bare leakage. Since the metal diffusion barrier layer (for example, Ti / TiN) deposited in the contact hole of the wafer edge region has poor adhesion with the silicon substrate, the metal diffusion barrier layer deposited in the contact hole of the wafer edge region is prone to peeling off / peeling off, thereby affecting the electrical performance of the device. SUMMARY

[0003] The present application provides a semiconductor device and a preparation method thereof, which can solve the problem that the metal diffusion barrier layer deposited in the contact hole formed in the edge region of the wafer is prone to peeling off / peeling off, thereby affecting the electrical performance of the device, in the case that the edge region of the wafer and the middle region of the wafer have a gentle slope with a high inside and a low outside.

[0004] In one aspect, the present application provides a preparation method of a semiconductor device, comprising:

[0005] providing a semiconductor structure, the semiconductor structure comprising at least a substrate, the height of the edge region of the substrate being lower than the height of the non-edge region of the substrate, the edge region of the substrate surrounding the non-edge region of the substrate;

[0006] forming an interlayer insulating layer, the interlayer insulating layer covering at least the edge region of the substrate and part of the non-edge region of the substrate;

[0007] etching the interlayer insulating layer to the surface of the non-edge region of the substrate to form a plurality of first contact holes, and at the same time, etching the interlayer insulating layer to the surface of part of the edge region of the substrate to form a plurality of second contact holes, wherein the depth of the second contact hole is greater than the depth of the first contact hole;

[0008] forming an adhesion layer on the surface of the edge region of the substrate in the second contact hole by using a thermal oxidation process;

[0009] A diffusion suppression layer is formed, the diffusion suppression layer covering the sidewalls and bottom wall of the first contact hole and the sidewalls and bottom wall of the second contact hole.

[0010] Optionally, in the preparation method of the semiconductor device, a thermal oxidation process is used, and in the process of forming the adhesion layer on the surface of the edge area of ​​the substrate in the second contact hole, the gas introduced into the process chamber includes at least: oxygen, the flow rate of oxygen is 100 sccm to 500 sccm; and the process temperature is 80°C.

[0011] Optionally, in the method for preparing the semiconductor device, the thickness of the adhesion layer is 10 nm to 20 nm.

[0012] Optionally, in the method for preparing the semiconductor device, a height difference between an edge region of the substrate and a non-edge region of the substrate is at least 600 nm.

[0013] Optionally, in the method for preparing the semiconductor device, the diffusion suppression layer includes: a stacked titanium layer and a titanium nitride layer, the titanium layer covers the side walls and bottom walls of the first contact hole and the side walls of the second contact hole and the adhesion layer in the second contact hole, and the titanium nitride layer covers the titanium layer.

[0014] Optionally, in the method for preparing the semiconductor device, after forming the diffusion suppression layer, the method for preparing the semiconductor device further comprises:

[0015] A metal material layer is formed, the metal material layer covering the diffusion suppression layer and filling a remaining space of the first contact hole and a remaining space of the second contact hole.

[0016] Optionally, in the method for preparing the semiconductor device, the substrate is a silicon substrate.

[0017] On the other hand, an embodiment of the present application provides a semiconductor device, including:

[0018] A semiconductor structure comprising at least a substrate, wherein a height of an edge region of the substrate is lower than a height of a non-edge region of the substrate, and the edge region of the substrate surrounds the non-edge region of the substrate;

[0019] an interlayer insulating layer, wherein the interlayer insulating layer covers at least an edge region of the substrate and a portion of a non-edge region of the substrate;

[0020] a plurality of first contact holes, wherein the first contact holes penetrate the interlayer insulating layer to the surface of the non-edge region of the substrate;

[0021] a plurality of second contact holes penetrating through the interlayer insulating layer to a surface of the edge region of the substrate, wherein a depth of the second contact holes is greater than a depth of the first contact holes;

[0022] an adhesion layer covering the surface of the edge region of the substrate in the second contact holes;

[0023] a diffusion barrier layer covering sidewalls and a bottom wall of the first contact holes and sidewalls and a bottom wall of the second contact holes.

[0024] The technical scheme of the present application has at least the following advantages:

[0025] In the present application, the height of the edge region of the substrate is lower than the height of the non-edge region of the substrate, an interlayer insulating layer is first formed on the substrate, then the non-edge region of the interlayer insulating layer is etched to form the first contact holes and the edge region of the interlayer insulating layer is etched to form the second contact holes, then a thermal oxidation process is used to form an adhesion layer on the surface of the substrate in the second contact holes, and finally a diffusion barrier layer is deposited in the first and second contact holes. After forming the first and second contact holes, the adhesion layer is formed on the surface of the substrate in the second contact holes by the thermal oxidation process, which can prevent the metal diffusion barrier layer deposited in the second contact holes formed at the edge region of the wafer from peeling off / peeling away, improve the adhesion of the diffusion barrier layer to the material of the bottom wall and sidewalls of the second contact holes, and improve the electrical performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or prior art description. Obviously, the drawings described below are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0027] Figure 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0028] Figures 2-6 is a schematic diagram of a semiconductor structure in each process step of manufacturing a semiconductor device according to an embodiment of the present application;

[0029] In the drawings, the reference signs are explained as follows:

[0030] 10-substrate, 11-non-edge region, 12-edge region, 20-interlayer insulating layer, 21-first contact hole, 22-second contact hole, 30-adhesion layer, 40-diffusion barrier layer. DETAILED DESCRIPTION

[0031] With reference to the drawings, the technical solutions in the present application will be clearly and completely described. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of the present application.

[0032] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0033] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication between two elements, it can be wireless connection, or it can be wired connection. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0034] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as there is no conflict between them.

[0035] The embodiment of the present application provides a preparation method of a semiconductor device, referring to Figure 1 , Figure 1 is a flowchart of the preparation method of the semiconductor device of the embodiment of the present application, and the preparation method of the semiconductor device comprises:

[0036] First, step S1 is performed: referring to Figure 2 , Figure 2 is a schematic diagram of a semiconductor structure provided by the embodiment of the present application, a semiconductor structure is provided, which at least comprises a substrate 10, the height of an edge region 12 of the substrate 10 is lower than the height of a non-edge region 11 of the substrate 10, and the edge region 12 of the substrate 10 surrounds the non-edge region 11 of the substrate 10.

[0037] The non-edge region 11 of the substrate 10 can include a middle region and a center region of the substrate 10, and the edge region 12 of the substrate 10 surrounds the non-edge region 11 of the substrate 10.

[0038] Preferably, the height difference between the edge region 12 of the substrate 10 and the non-edge region 11 of the substrate 10 is at least 600 nm.

[0039] In the embodiment, the substrate 10 is a silicon substrate.

[0040] Then, step S2 is performed: referring to FIG. 2, Figure 3 , Figure 3 FIG. 2 is a schematic diagram of a semiconductor structure after chemical mechanical polishing of an interlayer insulating layer according to an embodiment of the present application. An interlayer insulating layer 20 is formed, and the interlayer insulating layer 20 covers at least the edge region 12 of the substrate 10 and part of the non-edge region 11 of the substrate 10.

[0041] Further, after the interlayer insulating layer 20 is formed and before the first contact holes and the second contact holes are formed, the surface of the interlayer insulating layer 20 is polished by a chemical mechanical polishing (CMP) process to planarize the surface of the interlayer insulating layer 20.

[0042] Because the edge region 12 is originally lower than the non-edge region 11, and because of the difference in polishing between the non-edge region and the edge region in the chemical mechanical polishing (CMP) process, after the chemical mechanical polishing (CMP) process is performed, the edge region of the interlayer insulating layer 20 is still lower than the non-edge region of the interlayer insulating layer 20, so that there is a ramp at the junction between the edge region of the interlayer insulating layer 20 and the non-edge region of the interlayer insulating layer 20.

[0043] Then, step S3 is performed: referring to FIG. 3, Figure 4 , Figure 4 FIG. 3 is a schematic diagram of a semiconductor structure after formation of first contact holes and second contact holes according to an embodiment of the present application. The interlayer insulating layer 20 is etched to the surface of the non-edge region 11 of the substrate 10 to form first contact holes 21, and the interlayer insulating layer 20 is etched to the surface of part of the edge region 12 of the substrate 10 to form second contact holes 22.

[0044] The non-edge region of the interlayer insulating layer 20 cannot be completely covered by photoresist based on the principle of photoresist coating, so in the process of etching the interlayer insulating layer 20, the depth of the second contact holes 22 formed by etching is greater than the depth of the first contact holes 21 formed by etching.

[0045] Further, the lateral dimension of the second contact hole 22 near the bottom is larger than the lateral dimension of the first contact hole 21 near the bottom, and the substrate surface exposed by the bottom of the second contact hole 22 is larger than the substrate surface exposed by the bottom of the first contact hole 21.

[0046] In the embodiment, the second contact hole 22 and / or the first contact hole 21 expose the substrate surface of the source / drain region and other all ion implantation regions or metal film layers which need to be electrically connected to the chip surface.

[0047] Further, step S4 is performed: referring to Figure 5 , Figure 5 is a schematic diagram of the semiconductor structure after forming the adhesion layer in the embodiment of the present application, and the adhesion layer 30 is formed on the surface of the edge region 12 of the substrate 10 in the second contact hole 22 by using a thermal oxidation process. It is worth noting that the thermal oxidation process is to blow the edge (the position of the second contact hole 22) of the wafer with hot air containing oxygen, rotate the wafer, blow the wafer, and oxidize the wafer. Since the first contact hole 21 is not at the edge of the wafer, the inner wall of the first contact hole 21 is not blown by the hot air, and thus the inner wall of the first contact hole 21 is not oxidized.

[0048] Preferably, in the process of forming the adhesion layer 30 on the surface of the edge region 12 of the substrate 10 in the second contact hole 22 by using the thermal oxidation process, the gas flowing into the process cavity at least includes: oxygen, and the flow rate of the oxygen is 100 sccm-500 sccm; and the process temperature is 80°C.

[0049] Preferably, the thickness of the adhesion layer 30 is 10 nm-20 nm.

[0050] Finally, step S5 is performed: referring to Figure 6 , Figure 6 is a schematic diagram of the semiconductor structure after forming the diffusion inhibition layer in the embodiment of the present application, and the diffusion inhibition layer 40 is formed, which covers the side wall and bottom wall of the first contact hole 21 and the side wall and bottom wall of the second contact hole 22.

[0051] Preferably, the diffusion inhibition layer 40 includes: a titanium layer and a titanium nitride layer stacked, the titanium layer covers the side wall and bottom wall of the first contact hole 21 and the side wall of the second contact hole 22 and the adhesion layer 30 in the second contact hole 22, and the titanium nitride layer covers the titanium layer.

[0052] In the present application, after forming the first contact hole and the second contact hole, the adhesion layer is formed on the substrate surface in the second contact hole by a thermal oxidation process, which can avoid the peeling of the metal diffusion barrier layer deposited in the second contact hole formed in the wafer edge region, improve the adhesion of the diffusion barrier layer to the material of the bottom wall and the sidewall of the second contact hole, and improve the electrical performance of the device.

[0053] Further, after forming the diffusion inhibition layer 40, the preparation method of the semiconductor device further includes: forming a metal material layer (not shown), which covers the diffusion inhibition layer 30 and fills the remaining space of the first contact hole 21 and the remaining space of the second contact hole 22.

[0054] Preferably, the material of the metal material layer can be copper.

[0055] Based on the same inventive concept, the present application provides a semiconductor device, which refers to Figure 6 , the semiconductor device comprises:

[0056] a semiconductor structure, the semiconductor structure at least comprising a substrate 10, the height of an edge region 12 of the substrate 10 being lower than the height of a non-edge region 11 of the substrate 10, the edge region 12 of the substrate 10 surrounding the non-edge region 11 of the substrate 10;

[0057] an interlayer insulating layer 20, the interlayer insulating layer 20 at least covering the edge region 12 of the substrate 10 and part of the non-edge region 11 of the substrate 10;

[0058] a plurality of first contact holes 21, the first contact holes 21 penetrating through the interlayer insulating layer 20 to the surface of the non-edge region 11 of the substrate 10;

[0059] a plurality of second contact holes 22, the second contact holes 22 penetrating through the interlayer insulating layer 20 to the surface of part of the edge region 12 of the substrate 10, wherein the depth of the second contact holes 22 is greater than the depth of the first contact holes 21;

[0060] an adhesion layer 30, the adhesion layer 30 covering the surface of the edge region 11 of the substrate 10 in the second contact hole 22;

[0061] a diffusion inhibition layer 40, the diffusion inhibition layer 40 covering the sidewall and bottom wall of the first contact hole 21 and the sidewall and bottom wall of the second contact hole 22.

[0062] Obviously, the above embodiments are merely example for clearly illustrating but not limitation to the embodiments. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, all the embodiments are not required to be enumerated and it is impossible to enumerate all the embodiments. The changes or variations derived from the above are still within the protection scope of the present application.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: A semiconductor structure is provided, the semiconductor structure comprising at least a substrate, wherein a height of an edge region of the substrate is lower than a height of a non-edge region of the substrate, and the edge region of the substrate surrounds the non-edge region of the substrate; forming an interlayer insulating layer, wherein the interlayer insulating layer covers at least an edge region of the substrate and a portion of a non-edge region of the substrate; Etching the interlayer insulating layer to the surface of the non-edge region of the substrate to form a plurality of first contact holes, and at the same time, etching the interlayer insulating layer to the surface of a portion of the edge region of the substrate to form a plurality of second contact holes, wherein the depth of the second contact holes is greater than the depth of the first contact holes; forming an adhesion layer on the edge area of ​​the substrate in the second contact hole by a thermal oxidation process; A diffusion suppression layer is formed, the diffusion suppression layer covering the sidewalls and bottom wall of the first contact hole and the sidewalls and bottom wall of the second contact hole.

2. The method for preparing a semiconductor device according to claim 1, wherein: In the process of forming the adhesion layer on the edge area surface of the substrate in the second contact hole by using a thermal oxidation process, the gas introduced into the process chamber includes at least oxygen with a flow rate of 100 sccm to 500 sccm; and the process temperature is 80°C.

3. The method for preparing a semiconductor device according to claim 1, wherein: The thickness of the adhesion layer is 10 nm to 20 nm.

4. The method for preparing a semiconductor device according to claim 1, wherein: A height difference between an edge region of the substrate and a non-edge region of the substrate is at least 600 nm.

5. The method for preparing a semiconductor device according to claim 1, wherein: The diffusion suppression layer includes a stacked titanium layer and a titanium nitride layer, the titanium layer covers the sidewalls and bottom wall of the first contact hole, the sidewalls of the second contact hole, and the adhesion layer in the second contact hole, and the titanium nitride layer covers the titanium layer.

6. The method for preparing a semiconductor device according to claim 1, wherein: After forming the diffusion suppression layer, the method for preparing the semiconductor device further includes: A metal material layer is formed, the metal material layer covering the diffusion suppression layer and filling a remaining space of the first contact hole and a remaining space of the second contact hole.

7. The method for preparing a semiconductor device according to claim 1, wherein: The substrate is a silicon substrate.

8. A semiconductor device, characterized in that: include: A semiconductor structure comprising at least a substrate, wherein a height of an edge region of the substrate is lower than a height of a non-edge region of the substrate, and the edge region of the substrate surrounds the non-edge region of the substrate; an interlayer insulating layer, wherein the interlayer insulating layer covers at least an edge region of the substrate and a portion of a non-edge region of the substrate; a plurality of first contact holes, wherein the first contact holes penetrate the interlayer insulating layer to the surface of the non-edge region of the substrate; a plurality of second contact holes, wherein the second contact holes penetrate the interlayer insulating layer to a surface of a portion of an edge region of the substrate, wherein a depth of the second contact holes is greater than a depth of the first contact holes; an adhesion layer, wherein the adhesion layer covers a surface of an edge region of the substrate in the second contact hole; A diffusion suppression layer covers the sidewalls and bottom wall of the first contact hole and the sidewalls and bottom wall of the second contact hole.

Images