Method for improving step height of front film layer of interlayer dielectric CMP (chemical mechanical polishing) process

Abstract

The invention discloses a method for improving the step height of a front film layer in an interlayer dielectric CMP (chemical mechanical polishing) process, which comprises the following steps of: when an interlayer dielectric is deposited on a wafer with a groove, using a constraint process before depositing a silicon oxide film, and increasing atmosphere gas to inhibit the deposition of the silicon oxide film at a top opening of the groove; and then a repeated circulation process of silicon oxide film deposition, etching and re-deposition is carried out until the film layer filling in the groove is completed. According to the method, a filling mode of constraint process + (silicon oxide film deposition + back etching) x is adopted, the constraint process can inhibit excessive accumulation of a silicon oxide film at an opening in the top of the groove, and the circulation process of silicon oxide film deposition + back etching can ensure the filling quality of a dielectric film layer in the groove; through the process method, the height of the step formed by accumulation of the oxide film layer at the opening of the groove can be reduced, the uniformity of the CMP process can be improved in the subsequent CMP process, and the grinding amount is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor process manufacturing, and in particular to a method for improving the step height of a front film layer in an interlayer dielectric CMP process. Background Art

[0002] In semiconductor manufacturing, deep trench filling is a crucial factor in ensuring device performance. During CVD trench filling, film accumulation occurs at the trench top. This leads to large film fill volumes in subsequent high-aspect-ratio processes like HARP, complex film quality at the CMP polishing interface, W residue during CMP planarization, and high polishing volumes. This significantly limits the flexibility of device height adjustment.

[0003] like Figure 1 As shown in FIG, it is an actual micrograph of the film accumulation at the edge of the trench after the trench is filled. After the trench deposition filling process, the film layer at the trench mouth accumulates to form a step higher than the plane of the wafer itself, as shown in FIG. Figure 2 As shown, it has an adverse effect on subsequent processes, especially CMP polishing, such as polishing residues.

[0004] Top film deposition occurs during the trench filling process. Reducing the amount of top deposition during the trench filling process is an effective way to improve CMP polishing defects, polishing uniformity, and polishing amount. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method for improving the step height of the front film layer of the interlayer dielectric CMP process.

[0006] To solve the above problems, the present invention provides a method for improving the step height of the front film layer of the interlayer dielectric CMP process, comprising: After the trench etching is completed, a confinement process is used before depositing the silicon oxide film. The atmospheric gas is added to inhibit the deposition of the silicon oxide film at the top opening of the trench. The silicon oxide film deposition, etching and re-deposition process are repeated until the film layer filling in the trench is completed.

[0007] Furthermore, the confinement process uses an NH3 gas atmosphere, and the diffusion of -F ion groups in the NH3 gas creates a concentration gradient difference between the top and bottom of the trench, which inhibits the adhesion of the silicon oxide film at the top and slows down the accumulation rate of the silicon oxide film at the top of the trench.

[0008] Furthermore, when performing the etching process of the silicon oxide film, the etching process uses a mixed gas of NF3 and NH3 to perform a high-selectivity etching process on the silicon oxide film and SiN film formed in the deposition process, and etches away excess silicon oxide film in the opening area at the top of the trench.

[0009] Further, the repeated cycle process of the silicon oxide film deposition, etching and re-deposition is used, after the deposition of a certain thickness of the silicon oxide film, etching is performed to remove a certain amount of the silicon oxide film, especially the silicon oxide film accumulated at the opening of the top of the trench, and then the deposition, etching and re-deposition of the silicon oxide film are repeated until the trench is filled.

[0010] The method for improving the step height of the front film layer in the CMP process of the interlayer dielectric, when the silicon oxide film is deposited to fill the interlayer dielectric of the wafer with a trench topography, a filling method of constraint process + (silicon oxide film deposition + back etching) x is used, the constraint process can inhibit the excessive accumulation of the silicon oxide film at the opening of the top of the trench, and the cycle process of the silicon oxide film deposition + back etching can ensure the filling quality of the dielectric film layer in the trench; the step height formed by the accumulation of the oxide film layer at the opening of the trench can be improved and reduced by the above process method, and the uniformity of the CMP process can be improved and the polishing amount can be reduced in the subsequent CMP process. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a micrograph of the step formed by the accumulation of the film layer at the opening of the top of the trench after the deposition of the existing interlayer dielectric film.

[0012] Figure 2 is a schematic diagram of the step formed by the accumulation of the film layer at the opening of the top of the trench after the deposition of the existing process interlayer dielectric film.

[0013] Figure 3 is a flowchart of the process of the present application.

[0014] Figure 4 is a schematic diagram of the film layer topography and CMP polishing after the implementation of the present application and the existing process. DETAILED DESCRIPTION

[0015] The specific embodiments of the present application are described below with reference to the accompanying drawings, and the technical solutions in the present application are clearly and completely described, but the present application is not limited to the following embodiments. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The advantages and characteristics of the present application will be clearer according to the following description and claims. It should be noted that the drawings are very simplified and use non-precise ratios, which are only used for the purpose of conveniently and clearly assisting the description of the embodiments of the present application. All other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0016] The application can be implemented in different forms, and should not be interpreted as being limited to the embodiments presented here. On the contrary, these embodiments are presented in order to make the disclosure complete and full, and to fully convey the scope of the application to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions can be exaggerated for clarity, and the same reference numerals represent the same elements throughout. In the description of the present application, it should be noted that the orientations or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be interpreted as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be interpreted as limiting the present application. In addition, the terms "first", "second", "third" are only for descriptive purposes and cannot be interpreted as indicating or implying relative importance.

[0017] When depositing and filling the interlayer dielectric on the wafer with trenches, the main material of the interlayer dielectric is a silicon oxide film, which fills the trench and accumulates a certain thickness on the wafer surface. Since the reaction gas deposited at the opening of the trench top is relatively difficult to enter the inside of the trench, it tends to accumulate at the opening of the trench top, so that the silicon oxide film at the opening of the trench top is easy to accumulate. After the deposition of the interlayer dielectric is completed, a "small mountain" of silicon oxide film, i.e. a step, is formed at the opening of the trench. In some deposition processes of thicker interlayer dielectric layers, a very high step height is often formed at the opening of the trench top after deposition, and in the subsequent CMP polishing process, these high steps need to be removed by polishing. However, too high a step of silicon oxide film not only increases the polishing amount of the CMP process, but also reduces the uniformity of the CMP polishing process due to the rough surface caused by the step height.

[0018] The present application proposes a filling method of Inhibit + (Oxide Dep + Etch) x to inhibit the formation of silicon oxide at the opening of the trench top and reduce the step height formed during the gap filling process, which has a positive effect on the subsequent CMP polishing defects, polishing uniformity and polishing amount. Wherein X represents the number of cycles of deposition → etching → deposition, and the deposition and etching are repeated until the trench is filled with the desired morphology. The number of cycles needs to be determined comprehensively according to the film thickness of each deposition, the etching amount of each etching, and the final film thickness to be deposited. Generally speaking, the more the number of cycles, the better the quality of the filling in the trench and the film morphology at the opening of the trench top. However, too many cycles will affect the cost of time.

[0019] For silicon oxide films, the inhibit process uses NF3 gas. This process utilizes the diffusion of "-F" groups, creating a concentration gradient difference between the trench top opening and the bottom. This inhibits the adhesion of the SiO2 film layer at the top of the trench opening, slowing the accumulation of silicon oxide film at the trench top opening. After silicon oxide deposition, NF3+NH3 is used to etch SiO2 and SiN with high selectivity, removing excess SiO2 at the trench top opening and reducing the accumulation of silicon oxide film at the trench top opening. The NF3+NH3 etching process uses a mixed etchant gas with high selectivity for silicon oxide films, effectively removing the silicon oxide film while minimizing the impact on other film layers.

[0020] After comparative testing, the conventional direct deposition solution leaves the top of the trench opening with a thickness of 28nm, while the Inhibit + (Oxide Dep + Etch)x filling solution leaves the top with a thickness of only 13nm. Figure 4 As shown in FIG, it is a comparative diagram of the existing process before and after optimization. Under the existing process, the step height of the thin film after deposition is higher, and the grinding amount of CMP grinding is also larger. However, with the optimized process of the present invention, the step height of the thin film after deposition is lower, and the grinding amount of CMP grinding is reduced by at least 1.5 times, and the mask amount and uniformity after grinding are greatly improved.

[0021] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Those skilled in the art will appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A method for improving the step height of the front film layer of an interlayer dielectric CMP process, characterized by: When depositing an interlayer dielectric film on a wafer with grooves, a constraint process is used before depositing the interlayer dielectric film. Atmosphere gas is added to inhibit the deposition of the interlayer dielectric film at the top opening of the trench. The interlayer dielectric film deposition, back etching and re-deposition process are then repeated until the interlayer dielectric film filling in the trench and the deposition of the interlayer dielectric film on the wafer surface are completed.

2. The method for improving the step height of the front film layer of the interlayer dielectric CMP process according to claim 1, wherein: The confinement process uses a gas atmosphere to suppress the accumulation of the interlayer dielectric film at the top opening of the trench.

3. The method for improving the step height of the front layer of the interlayer dielectric CMP process according to claim 1 or 2, characterized in that: The interlayer dielectric film is a silicon oxide film.

4. The method for improving the step height of the front layer of the interlayer dielectric CMP process according to claim 3, wherein: The confinement process uses an NH3 gas atmosphere, and the diffusion of -F ion groups in the NH3 gas creates a concentration gradient difference between the top and bottom of the trench, which inhibits the adhesion of the silicon oxide film at the top and slows down the accumulation rate of the silicon oxide film at the top of the trench.

5. The method for improving the step height of the front film layer of the interlayer dielectric CMP process according to claim 2, wherein: When etching back the interlayer dielectric film, an etching process with a high etching selectivity ratio is used to reduce the loss of other film layer materials.

6. The method for improving the step height of the front film layer of the interlayer dielectric CMP process according to claim 5, characterized in that: When performing the etching process of the silicon oxide film, the etching process uses a mixed gas of NF3 and NH3 to perform a high-selectivity etching process on the silicon oxide film and SiN film formed by the deposition process, and etches away excess silicon oxide film in the opening area at the top of the trench.

7. The method for improving the step height of the front film layer of the interlayer dielectric CMP process according to claim 1, wherein: The interlayer dielectric film deposition, etch-back, and re-deposition process is repeated for a certain number of times until the interlayer dielectric film fills the trench and accumulates a certain thickness on the wafer surface.

8. The method for improving the step height of the front film layer of the interlayer dielectric in a CMP process according to claim 7, wherein: The number of cycles of the repeated cyclic process of depositing the interlayer dielectric film, etching back and then depositing is determined by the thickness of the film layer deposited each time, the etching amount of the back etching and the final thickness of the film to be deposited.

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