Packaging core component and manufacturing method

Abstract

The invention relates to a semiconductor core component and a method of forming the same. The semiconductor core components described herein may be used to form semiconductor package components, PCB components, PCB spacer components, chip carrier components, intermediate carrier components (e.g., for graphics cards), etc. In one embodiment, the silicon substrate core is constructed by direct laser patterning. One or more conductive interconnects are formed in the substrate core, and one or more redistribution layers are formed on a surface thereof. Subsequently, the silicon substrate core may be used as a core structure for semiconductor packages, PCBs, PCB spacers, chip carriers, intermediate carriers, etc.

Description

This application is a divisional application of application number 202080081984.4, filed on October 28, 2020, entitled “Packaging Core Assembly and Method of Manufacture”. BACKGROUND TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to electronic mounting structures and methods of forming the same. More particularly, embodiments described herein relate to semiconductor packages and PCB assemblies and methods of forming the same. BACKGROUND

[0002] As the demand for smaller electronic devices and components increases, the demand for faster processing power utilizing greater circuit density places corresponding demands on the materials, structures, and processes used in the manufacture of such integrated circuit chips. However, in addition to these trends toward greater integration and performance, there is an ever present pursuit of reducing manufacturing costs.

[0003] Generally, integrated circuit chips have been fabricated on organic packaging substrates coupled to circuit boards (e.g., printed circuit boards (PCBs)) due to the ease of forming features and connections in organic packaging substrates and the relatively low packaging manufacturing costs associated with organic composites. However, as circuit density increases and electronic devices are further miniaturized, the use of organic packaging substrates with conventional interconnect PCBs becomes impractical due to limitations in material structure resolution for maintaining device scale with associated performance requirements. Recently, 2.5D and 3D integrated circuits have been fabricated utilizing passive silicon interposers as redistribution layers to compensate for some of the limitations associated with organic packaging substrates. The use of silicon interposers is driven by the need for high bandwidth density, low power chip-to-chip communication, and heterogeneous integration in advanced electronic mounting and packaging applications. However, the formation of features in silicon interposers, such as through silicon vias (TSVs), is still difficult and costly. In particular, high aspect ratio TSV etching, chemical mechanical planarization, and semiconductor back end of line (BEOL) interconnects contribute to higher costs.

[0004] Accordingly, there is a need in the art for improved semiconductor packaging and PCB core assemblies having increased density and methods of forming the same. SUMMARY

[0005] The present disclosure generally relates to electronic mounting structures and methods of forming the same.

[0006] In one embodiment, a semiconductor device assembly is provided. The semiconductor device assembly includes a silicon core structure having a first surface opposite a second surface and a thickness less than about 1000 μιη. One or more electrically conductive interconnects are formed through the silicon core structure and protrude from the first surface and the second surface. The semiconductor device assembly further includes a first redistribution layer formed on the first surface and a second redistribution layer formed on the second surface. The first redistribution layer and the second redistribution layer each have one or more electrically conductive contacts formed thereon.

[0007] In one embodiment, a semiconductor device assembly is provided. The semiconductor device assembly includes a silicon core structure, a passivation layer, and a dielectric layer. The silicon core structure has a thickness less than about 1000 μιη. The passivation layer surrounds the silicon core structure and includes thermal oxide. The dielectric layer is formed on the passivation layer and includes an epoxy resin having silica particles disposed therein.

[0008] In one embodiment, a semiconductor device assembly is provided. The semiconductor device includes: a silicon core structure; a passivation layer surrounding the silicon structure and including thermal oxide; a dielectric layer surrounding the passivation layer and formed of an epoxy resin; and a redistribution layer formed on the dielectric layer. The redistribution layer further includes: an adhesion layer formed on the dielectric layer and formed of molybdenum; a copper seed layer formed on the adhesion layer; and a copper layer formed on the copper seed layer.

[0009] Embodiments of the present disclosure can further provide a semiconductor device assembly, including: a silicon core structure having a first side opposite a second side; a first redistribution layer formed on the first side; and a second redistribution layer formed on the second side. A dielectric layer including a flowable epoxy material can also be formed on the first side and the second side and have a thickness between about 5 μιη and about 50 μιη. The silicon core structure can have a thickness less than 1500 μιη; a metal cladding layer formed on the first side and the second side; and one or more electrically conductive interconnects formed in one or more through-assembly vias and having surfaces exposed at the first side and the second side. Each of the one or more through-assembly vias is defined circumferentially by the dielectric layer. The first redistribution layer and the second redistribution layer each have one or more electrically conductive contacts formed thereon. The metal cladding layer circumferentially surrounds each of the one or more electrically conductive interconnects. The metal cladding layer can have a thickness between about 100 nm and about 5 μιη on substantially all of the exposed surfaces of the silicon core. The metal cladding layer can be further electrically coupled to ground through one or more electrically conductive cladding connections disposed in the first redistribution layer and the second redistribution layer.

[0010] Embodiments of the present disclosure can further provide a semiconductor device assembly including a silicon core structure having a thickness less than 1500 pm; a metal or oxide layer formed on at least two surfaces of the silicon core structure; and a dielectric layer formed on the metal or oxide layer, the dielectric layer including an epoxy resin having silica particles. One or more vias defined circumferentially by the dielectric layer and having a diameter less than about 1500 pm are disposed through the semiconductor device assembly and are copper filled. The dielectric layer circumferentially defining the one or more vias can be further circumferentially surrounded by the metal or oxide layer. A redistribution layer having one or more redistribution connections can be formed on the dielectric layer. The redistribution connections and the copper filled vias can together form an inductive coil. The silicon core structure can further include one or more pockets containing silicon capacitors therein. A heat exchanger can be further disposed on the dielectric layer or coupled to the metal or oxide layer.

[0011] Embodiments of the present disclosure can further provide a semiconductor device assembly including a silicon core structure having a first side opposite a second side and a thickness less than 1500 pm; a nickel clad layer formed on the first side and the second side; and a dielectric layer including an epoxy resin and surrounding the nickel clad layer. An array of vias is disposed through the silicon core structure and is filled with a conductive material, each via of the array of vias being defined by the dielectric layer. A redistribution layer is formed on the dielectric layer and includes a molybdenum-containing adhesion layer formed on the dielectric layer; a copper seed layer formed on the adhesion layer; and a copper layer formed on the copper seed layer. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to enable a detailed understanding of the above-mentioned features of the present disclosure, a more particular description of the disclosure briefly described above can be obtained by reference of embodiments, some of which are illustrated in the attached drawings. However, it is to be noted that the attached drawings only illustrate exemplary embodiments and, as such, should not be considered limiting the scope thereof, and other equivalent embodiments can be allowed.

[0013] FIG. 1A A cross-sectional view schematically illustrating a semiconductor core assembly according to embodiments described herein.

[0014] FIG. 1B A cross-sectional view schematically illustrating a semiconductor core assembly according to embodiments described herein.

[0015] FIG. 1C A cross-sectional view schematically illustrating a semiconductor core assembly according to embodiments described herein.

[0016] FIG. 2 is a flowchart illustrating a process for forming a semiconductor core assembly according to embodiments described herein. FIG. 1A and FIG. 1B is a flowchart illustrating a process for forming a semiconductor core assembly according to embodiments described herein.

[0017] FIG. 3 is a flow chart illustrating a process for constructing a substrate for a semiconductor core assembly according to embodiments described herein.

[0018] FIG. 4A to FIG. 4D schematically illustrates a cross-sectional view of a core structure at different stages of the depicted process according to embodiments described herein. FIG. 3 is a cross-sectional view of a substrate at different stages of the depicted process.

[0019] FIG. 5 is a flow chart illustrating a process for forming an insulating layer on a core structure of a semiconductor core assembly according to embodiments described herein.

[0020] FIG. 6A to FIG. 6I schematically illustrates a cross-sectional view of a core structure at different stages of the depicted process according to embodiments described herein. FIG. 5 is a cross-sectional view of a core structure at different stages of the depicted process.

[0021] FIG. 7 is a flow chart illustrating a process for forming an insulating layer on a core structure of a semiconductor core assembly according to embodiments described herein.

[0022] FIG. 8A to FIG. 8E schematically illustrates a cross-sectional view of a core structure at different stages of the depicted process according to embodiments described herein. FIG. 7 is a cross-sectional view of a core structure at different stages of the depicted process.

[0023] FIG. 9 is a flow chart illustrating a process for forming an interconnect in a semiconductor core assembly according to embodiments described herein.

[0024] FIG. 10A to FIG. 10H schematically illustrates a cross-sectional view of a semiconductor core assembly at different stages of the depicted process according to embodiments described herein. FIG. 9 is a cross-sectional view of a semiconductor core assembly at different stages of the depicted process.

[0025] FIG. 11 is a flow chart illustrating a process for forming a redistribution layer on a semiconductor core assembly according to embodiments described herein.

[0026] FIG. 12A to FIG. 12L schematically illustrates a cross-sectional view of a semiconductor core assembly at different stages of the depicted process according to embodiments described herein. FIG. 11 is a cross-sectional view of a semiconductor core assembly at different stages of the depicted process.

[0027] FIG. 13A schematically illustrates a cross-sectional view of a chip carrier structure including a semiconductor core assembly according to embodiments described herein.

[0028] FIG. 13Bschematically illustrates a cross-sectional view of a PCB structure including a semiconductor core assembly according to embodiments described herein.

[0029] FIG. 13C schematically illustrates a cross-sectional view of a PCB structure including a semiconductor core assembly according to embodiments described herein.

[0030] FIG. 14A schematically illustrates a cross-sectional view of a semiconductor core assembly having one or more passive devices integrated therein according to embodiments described herein.

[0031] FIG. 14B schematically illustrates a cross-sectional view of a semiconductor core assembly having one or more passive devices integrated therein according to embodiments described herein.

[0032] FIG. 14C schematically illustrates a cross-sectional view of a semiconductor core assembly having one or more passive devices integrated therein according to embodiments described herein.

[0033] FIG. 15A schematically illustrates a cross-sectional view of a semiconductor core assembly having one or more passive devices integrated therein according to embodiments described herein.

[0034] FIG. 15B schematically illustrates a cross-sectional view of a semiconductor core assembly having one or more passive devices integrated therein according to embodiments described herein.

[0035] FIG. 15C schematically illustrates a cross-sectional view of an exemplary passive device to be integrated in a semiconductor core assembly according to embodiments described herein.

[0036] FIG. 15D schematically illustrates a cross-sectional view of a semiconductor core assembly having one or more passive devices integrated therein according to embodiments described herein. FIG. 15C

[0037] FIG. 16 schematically illustrates a cross-sectional view of a semiconductor core assembly having a bridging device integrated therein according to embodiments described herein.

[0038] To facilitate an understanding of this description, like reference characters are used throughout the disclosure. Elements and features of one embodiment are generally DETAILED DESCRIPTION

[0039] ​The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein can be used to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, interposer assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is constructed by direct laser patterning. One or more conductive interconnects are formed in the substrate core, while one or more redistribution layers are formed on a surface thereof. Subsequently, the silicon substrate core can serve as a core structure for semiconductor packages, PCBs, PCB spacers, chip carriers, interposers, and the like.

[0040] The methods and apparatus disclosed herein, including novel thin form factor semiconductor core structures, are intended to replace more conventional semiconductor package, PCB, and chip carrier structures that utilize glass fiber filled epoxy resin frames. Generally, the scalability of current semiconductor packages, PCBs, spacers, and chip carriers is limited by the rigidity and planarity deficiencies of the materials typically used to form these various structures (e.g., epoxy resin molding compounds, FR-4 and FR-5 grade glass fiber woven cloth with epoxy resin binder, etc.). The inherent properties of these materials cause difficulties in patterning and utilizing fine (e.g., micron scale) features formed therein. Moreover, as a result of the properties (e.g., insulative) of the materials currently used, mismatches in the coefficient of thermal expansion (CTE) can occur between the glass fiber frames, boards, molding compounds, and any chips disposed adjacent thereto. Thus, current package, PCB, spacer, and carrier structures require larger solder bumps having larger pitch to mitigate the effects of any warping caused by the CTE mismatch. Accordingly, conventional semiconductor package, PCB, spacer, and carrier frames are characterized by low electrical bandwidth throughout the structure, resulting in reduced overall power efficiency. The methods and apparatus described herein provide semiconductor core structures for overcoming many of the shortcomings associated with the aforementioned conventional semiconductor package, PCB, spacer, and carrier structures.

[0041] FIG. 1A to FIG. 1C A cross-sectional view of a thin form factor semiconductor core assembly 100 is illustrated in accordance with some embodiments. The semiconductor core assembly 100 can be used for structural support and electrical interconnection of semiconductor packages mounted thereon. In further examples, the semiconductor core assembly 100 can serve as a carrier structure for surface mount devices, such as chips or graphics cards. The semiconductor core assembly 100 generally includes a core structure 102, an optional passivation layer 104 (shown) or metal cladding layer 114 (shown) and an insulating layer 118. FIG. 1A and FIG. 1B FIG. 1C

[0042] ​​In one embodiment, the core structure 102 includes a patterned (e.g., structured) substrate formed of any suitable substrate material. For example, the core structure 102 includes a substrate formed of a Group III-V compound semiconductor material, silicon (e.g., having a resistivity of between about 1 and about 10 Ohm-com or a conductivity of about 100 W / mK), crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, silicon germanium, doped or undoped silicon, undoped high resistivity silicon (e.g., float zone silicon having a lower dissolved oxygen content and a resistivity of between about 5000 and about 10000 ohm-cm), doped or undoped polysilicon, silicon nitride, silicon carbide (e.g., having a conductivity of about 500 W / mK), quartz, glass (e.g., borosilicate glass), sapphire, aluminum oxide, and / or a ceramic material. In one embodiment, the core structure 102 includes a single crystalline p-type or n-type silicon substrate. In one embodiment, the core structure 102 includes a polycrystalline p-type or n-type silicon substrate. In another embodiment, the core structure 102 includes a p-type or n-type silicon solar substrate. In general, the substrate used to form the core structure 102 can have a polygonal or circular shape. For example, the core structure 102 can include a substantially square silicon substrate with or without beveled edges, the silicon substrate having a lateral dimension of between about 120 mm and about 180 mm, such as about 150 mm, or between about 156 mm and about 166 mm. In another example, the core structure 102 can include a circular silicon-containing wafer, the wafer having a diameter of between about 20 mm and about 700 mm, such as between about 100 mm and about 500 mm, for example about 200 mm or about 300 mm.

[0043] The thickness T1 of the core structure 102 is between about 50 pm and about 1500 pm, such as a thickness T1 of between about 90 pm and about 780 pm. For example, the thickness T1 of the core structure 102 is between about 100 pm and about 300 pm, such as a thickness T1 of between about 110 pm and about 200 pm. In another example, the thickness T1 of the core structure 102 is between about 70 pm and about 150 pm, such as a thickness T1 of between about 100 pm and about 130 pm. In another example, the thickness T1 of the core structure 102 is between about 700 pm and about 800 pm, such as a thickness T1 of between about 725 pm and about 775 pm.

[0044] The core structure 102 further includes one or more holes or core vias 103 (hereinafter referred to as "core vias") formed therein to enable conductive interconnects to be routed through the core structure 102. Generally, the one or more core vias 103 are substantially cylindrical in shape. However, other suitable shapes of core vias 103 are contemplated. The core vias 103 can be formed as individual and separate core vias 103 through the core structure 102, or formed in one or more groups or arrays. In one embodiment, a minimum pitch PI between each core via 103 is less than about 1000 μιη, such as between about 25 μιη and about 200 μιη. For example, the pitch PI is between about 40 μιη and about 150 μιη, such as between about 100 μιη and about 140 μιη, for example about 120 μιη. In one embodiment, a diameter VI of the one or more core vias 103 is less than about 500 μιη, such as the diameter VI is less than about 250 μιη. For example, the diameter VI of the core vias 103 is between about 25 μιη and about 100 μιη, such as the diameter VI is between about 30 μιη and about 60 μιη. In one embodiment, the diameter VI of the core vias 103 is about 40 μιη.

[0045] FIG. 1A and FIG. 1B An optional passivation layer 104 can be formed on one or more surfaces of the core structure 102, including the first surface 106, the second surface 108, and one or more sidewalls of the core vias 103. In one embodiment, the passivation layer 104 is formed on substantially all of the external surfaces of the core structure 102, such that the passivation layer 104 substantially surrounds the core structure 102. Thus, the passivation layer 104 provides a protective outer barrier for the core structure 102 against corrosion and other forms of damage. In one embodiment, the passivation layer 104 is formed from an oxide film or layer, such as a thermal oxide layer. In some examples, the passivation layer 104 has a thickness between about 100 nm and about 3 μιη, such as a thickness between about 200 nm and about 2.5 μιη. In one example, the passivation layer 104 has a thickness between about 300 nm and about 2 μιη, such as a thickness of about 1.5 μιη.

[0046] In FIG. 1CIn the illustrated embodiment, the core structure 102 includes a metal cladding layer 114, which replaces the passivation layer 104 and is formed on one or more surfaces of the core structure 102 (including the first surface 106, the second surface 108, and one or more sidewalls of the core via 103). In one embodiment, the metal cladding layer 114 is formed on substantially all exterior surfaces of the core structure 102, such that the metal cladding layer 114 substantially surrounds the core structure 102. The metal cladding layer 114 serves as a reference layer (e.g., a ground layer or a voltage supply layer) and is disposed on the substrate 302 to protect subsequently formed connections from electromagnetic interference and shield semiconductor signals from the semiconductor material (Si) used to form the core structure 102. In one embodiment, the metal cladding layer 114 comprises a conductive metal layer (including nickel, aluminum, gold, cobalt, silver, palladium, tin, etc.). In another embodiment, the metal cladding layer 114 comprises a metal layer (including an alloy or a pure metal (including nickel, aluminum, gold, cobalt, silver, palladium, tin, etc.)). The thickness of the metal cladding layer 114 is typically between about 50 nm and about 10 μm, such as between about 100 nm and about 5 μm.

[0047] The insulating layer 118 is formed on one or more surfaces of the core structure 102, the passivation layer 104, or the metal cladding layer 114 and may substantially cover the passivation layer 104, the metal cladding layer 114, and / or the core structure 102. FIG. 1A As depicted, insulating layer 118 may extend into core via 103 and coat the passivation layer 104 or metal cladding 114 formed on the sidewalls of core via 103, or directly coat core structure 102, thereby defining a diameter V2. In one embodiment, insulating layer 118 has a thickness T2 of less than about 50 μm, such as a thickness T2 of less than about 20 μm, from an outer surface of core structure 102, passivation layer 114, or metal cladding 114 to an adjacent outer surface of insulating layer 118 (e.g., major surfaces 105, 107). For example, thickness T2 of insulating layer 118 is between about 5 μm and about 10 μm.

[0048] In one embodiment, the insulating layer 118 is formed of a polymer-based dielectric material. For example, the insulating layer 118 is formed of a flowable buildup material. Therefore, although referred to below as an "insulating layer," the insulating layer 118 may also be described as a dielectric layer. In a further embodiment, the insulating layer 118 is formed of an epoxy material with a ceramic filler, such as silicon dioxide (SiO2) particles. Other examples of ceramic fillers that may be used to form the insulating layer 118 include aluminum nitride (AlN), aluminum oxide (Al2O3), silicon carbide (SiC), silicon nitride (Si3N4), Sr2Ce2Ti5O 16zirconium silicate (ZrSi04), wollastonite (CaSi03), beryllium oxide (BeO), cerium dioxide (Ce02), boron nitride (BN), calcium copper titanium oxide (CaCu3Ti40 12 In some examples, the particles of the ceramic filler used to form the insulating layer 118 have a size in a range between about 40 nm and about 1.5 pm, such as between about 80 nm and about 1 pm. For example, the particles of the ceramic filler have a size in a range between about 200 nm and about 800 nm, such as between about 300 nm and about 600 nm. In some embodiments, the particles included by the ceramic filler have a size that is less than about 10% of the width or diameter of an adjacent core via 103 in the core structure 102, such as a size that is less than about 5% of the width or diameter of the core via 103.

[0049] One or more through-component holes or vias 113 (hereinafter referred to as “through-component vias”) are formed through the insulating layer 118, where the insulating layer 118 extends into the core via 103. For example, the through-component via 113 can be formed centrally within the core via 103, which has the insulating layer 118 disposed therein. Thus, the insulating layer 118 forms one or more sidewalls of the through-component via 113, where a diameter V2 of the through-component via 113 is less than a diameter VI of the core via 103. In one embodiment, the diameter V2 of the through-component via 113 is less than about 100 pm, such as less than about 75 pm. For example, the diameter V2 of the through-component via 113 is less than about 50 pm, such as less than about 35 pm. In one embodiment, the diameter of the through-component via 113 is between about 25 pm and about 50 pm, such as a diameter between about 35 pm and about 40 pm.

[0050] The through-component via 113 provides a passage through which one or more electrical interconnects 144 are formed in the semiconductor core assembly 100. In one embodiment, the electrical interconnect 144 is formed through an entire thickness of the semiconductor core assembly 100 (i.e., from the first major surface 105 to the second major surface 107 of the semiconductor core assembly 100). For example, a longitudinal length of the electrical interconnect 144 corresponding to the total thickness of the semiconductor core assembly 100 is between about 50 pm and about 1000 pm, such as a longitudinal length between about 200 pm and about 800 pm. In one example, the longitudinal length of the electrical interconnect 144 is between about 400 pm and about 600 pm, such as a longitudinal length of about 500 pm. In another embodiment, the electrical interconnect 144 is formed through only a portion of the thickness of the semiconductor core assembly 100. In further embodiments, the electrical interconnect 144 can extend from a major surface (such as the first major surface 105 or the second major surface 107) of the semiconductor core assembly 100 to a depth that is less than the total thickness of the semiconductor core assembly 100. FIG. 1AThe depicted major surfaces 105, 107) protrude. The electrical interconnects 144 can be formed of any electrically conductive material used in the field of integrated circuits, circuit boards, chip carriers, etc. For example, the electrical interconnects 144 are formed of a metallic material such as copper, aluminum, gold, nickel, silver, palladium, tin, etc.

[0051] In FIG. 1A In the depicted embodiment, the lateral thickness of the electrical interconnects 144 is equal to the diameter V2 of the through-component via 113 in which the electrical interconnects 144 are formed. In another embodiment, such as the depicted FIG. 1B As depicted, the semiconductor core assembly 100 further includes an adhesion layer 140 and / or a seed layer 142 formed thereon for electrical isolation of the electrical interconnects 144. In one embodiment, the adhesion layer 140 is formed on a surface of the insulating layer 118 adjacent to the electrical interconnects 144, including the sidewalls of the through-component via 113. Thus, as depicted, the adhesion layer 140 is formed on the sidewalls of the through-component via 113 and on the top surface of the insulating layer 118. FIG. 1B As depicted, the lateral thickness of the electrical interconnects 144 is less than the diameter V2 of the through-component via 113 in which the electrical interconnects 144 are formed. In yet another embodiment, the electrical interconnects 144 only cover the surface of the sidewalls of the through-component via 113 and thus can have a hollow core therethrough.

[0052] The adhesion layer 140 can be formed of any suitable material including, but not limited to, titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, etc. In one embodiment, the thickness B1 of the adhesion layer 140 is between about 10 nm and about 300 nm, such as between about 50 nm and about 150 nm. For example, the thickness B1 of the adhesion layer 140 is between about 75 nm and about 125 nm, such as about 100 nm.

[0053] The optional seed layer 142 comprises an electrically conductive material including, but not limited to, copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof. The seed layer 142 can be formed on the adhesion layer 140 or directly on the sidewalls of the through-component via 113 (e.g., on the insulating layer 118 without an adhesion layer therebetween). In one embodiment, the thickness of the seed layer 142 is between about 50 nm and about 500 nm, such as between about 100 nm and about 300 nm. For example, the thickness of the seed layer 142 is between about 150 nm and about 250 nm, such as about 200 nm.

[0054] In some embodiments, such as the depicted FIG. 1B As depicted, the semiconductor core assembly 100 further includes one or more redistribution layers 150 formed on the first side 175 and / or the second side 177 of the semiconductor core assembly 100. The redistribution layers 150 are formed on the top surface of the insulating layer 118 and / or on the top surface of the adhesion layer 140 and / or the seed layer 142. FIG. 1BThe redistribution layer 150 can include one or more redistribution connections 154 formed through the redistribution vias 153 to reposition the contact points of the electrical interconnects 144 to desired locations on the surface of the semiconductor core assembly 100, such as the major surfaces 105, 107. In some embodiments, the redistribution layer 150 can further include one or more external electrical connections (not shown) formed on the major surfaces 105, 107, such as a ball grid array or solder balls. In general, the redistribution vias 153 and the redistribution connections 154 have substantially similar or smaller lateral dimensions relative to the through-assembly vias 113 and the electrical interconnects 144, respectively. For example, the redistribution vias 153 have a diameter V3 between about 2 pm and about 50 pm, such as a diameter V3 between about 10 pm and about 40 pm, such as a diameter V3 between about 20 pm and about 30 pm. Further, the redistribution layer 150 can include the adhesion layer 140 and the seed layer 142 formed on the surface adjacent to the redistribution connections 154, including the sidewalls of the redistribution vias 153.

[0055] The redistribution layer 150 can include one or more redistribution connections 154 formed through the redistribution vias 153 to reposition the contact points of the electrical interconnects 144 to desired locations on the surface of the semiconductor core assembly 100, such as the major surfaces 105, 107. In some embodiments, the redistribution layer 150 can further include one or more external electrical connections (not shown) formed on the major surfaces 105, 107, such as a ball grid array or solder balls. In general, the redistribution vias 153 and the redistribution connections 154 have substantially similar or smaller lateral dimensions relative to the through-assembly vias 113 and the electrical interconnects 144, respectively. For example, the redistribution vias 153 have a diameter V3 between about 2 pm and about 50 pm, such as a diameter V3 between about 10 pm and about 40 pm, such as a diameter V3 between about 20 pm and about 30 pm. Further, the redistribution layer 150 can include the adhesion layer 140 and the seed layer 142 formed on the surface adjacent to the redistribution connections 154, including the sidewalls of the redistribution vias 153.

[0056] In embodiments where the core structure 102 includes the metal cladding layer 114, such as the embodiment shown in FIG. 1, the redistribution layer 150 can be formed on the metal cladding layer 114. In some embodiments, the redistribution layer 150 can be formed on the metal cladding layer 114 by a process that is substantially similar to the process used to form the redistribution layer 150 on the dielectric layer 118. For example, the redistribution layer 150 can be formed on the metal cladding layer 114 by a process that is substantially similar to the process used to form the redistribution layer 150 on the dielectric layer 118, such as a process that includes forming the adhesion layer 140 on the metal cladding layer 114, forming the seed layer 142 on the adhesion layer 140, and forming the redistribution connections 154 through the seed layer 142 and the adhesion layer 140. FIG. 1C), the metal cladding layer 114 is further coupled to at least one cladding connection 116, forming a connection point on at least one side of the semiconductor core assembly 100. In certain embodiments, the metal cladding layer 114 is coupled to two cladding connections 116 formed on opposite sides of the semiconductor core assembly 100. The cladding connections 116 can be connected to a common ground (such as exemplary ground 119) used by one or more semiconductor devices stacked (e.g., above or below) the semiconductor core assembly 100. Alternatively, the cladding connections 116 are connected to a reference voltage (such as a power voltage). As shown, the cladding connections 116 are formed in the insulating layer 118 and connect the metal cladding layer 114 to a connection end of the cladding connection 116 disposed on or at a surface (such as the major surfaces 107 and 105) of the semiconductor core assembly 100, such that the metal cladding layer 114 can be connected to an external common ground or reference voltage (in FIG. 1C exemplary connection to ground 119 is illustrated in FIG. 1).

[0057] The metal cladding layer 114 can be electrically coupled to the external ground 119 via the cladding connection 116 with any other suitable coupling member. For example, the cladding connection 116 can be indirectly coupled to the external ground 119 through solder bumps on opposite sides of the semiconductor core assembly 100. In certain embodiments, the cladding connection 116 can first pass through separate electronic system or device wiring before being coupled to the external ground 119. The utilization of a ground path between the metal cladding layer 114 and the external ground 119 reduces or eliminates interference between the interconnects 144 and / or the redistribution connections 154 and prevents shorting of the integrated circuits coupled thereto, which can damage the semiconductor core assembly 100 as well as any systems or devices integrated or stacked therewith.

[0058] Similar to the electrical interconnects 144 and the redistribution connections 154, the cladding connections 116 are formed of any suitable conductive material, including but not limited to nickel, copper, aluminum, gold, cobalt, silver, palladium, tin, and the like. The cladding connections 116 are deposited or plated through a cladding via 123, which is substantially similar to the through-assembly via 113 or the redistribution via 153, but only traverses a portion of the semiconductor core assembly 100 (e.g., from a surface thereof to the core structure 102). Thus, the cladding via 123 can be formed through the insulating layer 118, directly above or below the core structure 102 having the metal cladding layer 114 formed thereon. Further, similar to the electrical interconnects 144 and the redistribution connections 154, the cladding connections 116 can completely fill the cladding via 123 or line the inner peripheral wall thereof, thereby having a hollow core.

[0059] In certain embodiments, the lateral dimensions (e.g., diameter and lateral thickness, respectively) of the overcoat via 123 and the overcoat connection 116 are substantially similar to the diameter V2. In certain embodiments, the adhesion layer 140 and the seed layer 142 are formed in the overcoat via 123, so the diameter of the overcoat via 123 can be substantially similar to the diameter V2, and the lateral thickness of the overcoat connection 116 can be less than the diameter V2, such as a lateral thickness substantially similar to the diameter V3. In certain embodiments, the diameter of the overcoat via 123 is about 5 μιη.

[0060] FIG. 2 A flowchart illustrating a representative method 200 of forming a semiconductor core assembly is shown. The method 200 has a plurality of operations 210, 220, 230, and 240. Each operation is described in more detail below with reference to FIG. 3 to FIG. 12L The method can include one or more additional operations performed before any defined operation, between two defined operations, or after all defined operations (unless the context excludes the possibility).

[0061] Generally, the method 200 includes, at operation 210, constructing a substrate for use as a core structure (e.g., a frame), described in more detail below with reference to FIG. 3 and FIG. 4A to FIG. 4D Further described in more detail below. At operation 220, an insulating layer is formed on the core structure 102, and described in more detail below with reference to FIG. 5 , FIG. 6A to FIG. 6I , FIG. 7 and FIG. 8A to FIG. 8E Further described in more detail below. At operation 230, one or more interconnects are formed through the core structure 102 and the insulating layer, and described in more detail below with reference to FIG. 9 and FIG. 10A to FIG. 10H Further described in more detail below. At operation 240, a redistribution layer is formed on the insulating layer to reposition contact points of the interconnects to desired locations on a surface of the assembled core assembly, and subsequently the core assembly is diced into individual dies. In some embodiments, one or more additional redistribution layers can be formed in addition to the first redistribution layer, described in more detail below with reference to FIG. 11 and FIG. 12A to FIG. 12L Further described in more detail below.

[0062] FIG. 3 A flowchart illustrating a representative method 300 of constructing a substrate for use as a core structure is shown. FIG. 4A to FIG. 4D A cross-sectional view of the substrate 400 at various stages of the substrate structuring process 300 is schematically illustrated. FIG. 3 Thus, for clarity, the substrate 400 at various stages of the substrate structuring process 300 is described herein together with FIG. 3 and FIG. 4A to FIG. 4D .

[0063] The method 300 begins at operation 310 and corresponds to FIG. 4A As described above with reference to the core structure 102, the substrate 400 is formed of any suitable substrate material, including but not limited to, a III-V compound semiconductor material, silicon, crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, silicon germanium, doped or undoped silicon, undoped high resistivity silicon, doped or undoped polysilicon, silicon nitride, silicon carbide, quartz, a glass material (e.g., borosilicate glass), sapphire, aluminum oxide, and / or a ceramic material. In one embodiment, the substrate 400 is a single crystalline p-type or n-type silicon substrate. In one embodiment, the substrate 400 is a polysilicon p-type or n-type silicon substrate. In another embodiment, the substrate 400 is a p-type or n-type silicon solar substrate. The substrate 400 can further have a polygonal or circular shape. For example, the substrate 400 can include a substantially square silicon substrate with or without beveled edges having lateral dimensions between about 120 mm and about 180 mm. In another example, the substrate 400 can include a circular silicon-containing wafer having a diameter between about 20 mm and about 700 mm, such as between about 100 mm and about 500 mm, for example about 200 mm or about 300 mm. Unless otherwise specified, the embodiments and examples described herein are performed on substrates having a thickness between about 50 pm and about 1500 pm, such as a thickness between about 90 pm and about 780 pm. For example, the substrate 400 has a thickness between about 100 pm and about 300 pm, such as a thickness between about 110 pm and about 200 pm.

[0064] Prior to operation 310, the substrate 400 can be sliced and separated from bulk material by a wire saw, scribe and break, mechanical abrasive saw, or laser cutting. Slicing often results in mechanical defects or irregularities in the surface of the substrate formed from the slicing, such as scratches, microcracks, chipping, and other mechanical defects. Accordingly, at operation 310, the substrate 400 is exposed to a first damage removal process to smooth and planarize its surface and remove the mechanical defects in preparation for subsequent structuring operations. In some embodiments, the substrate 400 can be further thinned by adjusting process parameters of the first damage process. For example, as exposure to the first damage removal process increases, the thickness of the substrate 400 can be reduced.

[0065] At operation 310, the first damage removal process includes exposing the substrate 400 to a substrate polishing process and / or an etching process, followed by exposure to a rinsing and drying process. In some embodiments, operation 310 includes a chemical mechanical polishing (CMP) process. In one embodiment, the etching process is a wet etching process that includes a buffered etching process that selectively removes desired materials (e.g., contaminants and other undesired compounds). In other embodiments, the etching process is a wet etching process that utilizes an isotropic aqueous etching process. Any suitable wet etchant or combination of wet etchants can be used for the wet etching process. In one embodiment, the substrate 400 is immersed in an aqueous HF etching solution to perform the etching. In another embodiment, the substrate 400 is immersed in an aqueous KOH etching solution to perform the etching.

[0066] In some embodiments, during the etching process, the etching solution is heated to a temperature between about 30 °C and about 100 °C (such as between about 40 °C and 90 °C). For example, the etching solution is heated to a temperature of about 70 °C. In other embodiments, at operation 310, the etching process is a dry etching process. Examples of dry etching processes include plasma-based dry etching processes. The thickness of the substrate 400 is adjusted by controlling the time the substrate 400 is exposed to the etchant (e.g., etching solution) used during the etching process. For example, as the exposure to the etchant increases, the final thickness of the substrate 400 decreases. Alternatively, as the exposure to the etchant decreases, the substrate 400 can have a greater final thickness.

[0067] At operation 320, the now planarized and substantially defect-free substrate 400 is patterned to form one or more core vias 403 therein (depicted in FIG. 4B as four core vias 403 in a cross-section of the substrate 400). The core vias 403 are used to form direct contact electrical interconnections through the substrate 400. FIG. 4B

[0068] ​Generally, the one or more core vias 403 can be formed by laser ablation (e.g., direct laser patterning). Any suitable laser ablation system can be utilized to form the one or more core vias 403. In some examples, the laser ablation system utilizes an infrared (IR) laser source. In some examples, the laser source is a picosecond ultraviolet (UV) laser. In other examples, the laser is a femtosecond UV laser. In yet other examples, the laser source is a femtosecond green laser. The laser source of the laser ablation system generates a continuous laser beam or a pulsed laser beam for patterning of the substrate 400. For example, the laser source can generate a pulsed laser beam having a frequency between 5 kHz and 500 kHz, such as between 10 kHz and about 200 kHz. In one example, the laser source is configured to deliver a pulsed laser beam with an output power between about 10 Watts and about 100 Watts at a wavelength between about 200 nm and about 1200 nm and a pulse duration between about 10 ns and about 5000 ns. The laser source is configured to form any desired pattern of features (including the core vias 403) in the substrate 400.

[0069] In some embodiments, the substrate 400 is optionally coupled to a carrier plate (not shown) prior to being patterned. The optional carrier plate can provide mechanical support for the substrate 400 during patterning of the substrate 400 and can prevent the substrate 400 from breaking. The carrier plate can be formed of any suitable chemically and thermally stable rigid material, including but not limited to glass, ceramic, metal, and the like. In some examples, the carrier plate has a thickness between about 1 mm and about 10 mm, such as between about 2 mm and about 5 mm. In one embodiment, the carrier plate has a textured surface. In other embodiments, the carrier plate has a polished or smoothed surface. The substrate 400 can be coupled to the carrier plate with any suitable temporary adhesive material, including but not limited to wax, glue, or similar adhesive materials.

[0070] In some embodiments, patterning the substrate 400 can cause unwanted mechanical defects on the surface of the substrate 400, including chipping, cracking, and / or warping. Accordingly, after performing operation 320 to form the core vias 403 in the substrate 400, at operation 330, the substrate 400 is exposed to a second damage removal and cleaning process (substantially similar to the first damage removal process at operation 310) to smooth the surface of the substrate 400 and remove unwanted debris. As described above, the second damage removal process includes exposing the substrate 400 to a wet or dry etching process, followed by rinsing and drying. The etching process is performed for a predetermined duration to smooth the surface of the substrate 400 and, in particular, the surface exposed to the laser patterning operation. In another aspect, the etching process is used to remove any unwanted debris remaining on the substrate 400 from the patterning process.

[0071] After removing the mechanical defects in the substrate 400 at operation 330, the substrate 400 is exposed to a passivation or metallization process at operations 340 and FIG. 4D to grow or deposit a passivation layer (such as an oxide layer 404) or a metal layer (e.g., a metal cladding layer 414) on a desired surface of the substrate 400 (e.g., all surfaces of the substrate 400). In one embodiment, the passivation process is a thermal oxidation process. The thermal oxidation process is performed at a temperature between about 800 °C and about 1200 °C (e.g., between about 850 °C and about 1150 °C). For example, the thermal oxidation process is performed at a temperature between about 900 °C and about 1100 °C (e.g., a temperature between about 950 °C and about 1050 °C). In one embodiment, the thermal oxidation process is a wet oxidation process that utilizes water vapor as the oxidizing agent. In one embodiment, the thermal oxidation process is a dry oxidation process that utilizes molecular oxygen as the oxidizing agent. It is contemplated that at operation 340, the substrate 400 can be exposed to any suitable passivation process to form an oxide layer 404 or any other suitable passivation layer thereon. The resulting oxide layer 404 is typically between about 100 nm and about 3 pm in thickness, such as between about 200 nm and about 2.5 pm. For example, the oxide layer 404 is between about 300 nm and about 2 pm in thickness, such as about 1.5 pm. Alternatively, the metallization process can be any suitable metal deposition process (including a chemical deposition process, an electroplating process, a chemical vapor deposition process, an evaporation deposition process, and / or an atomic layer deposition process). In certain embodiments, at least a portion of the metal cladding layer 414 includes a deposited nickel (Ni) layer formed by direct displacement or displacement plating on the surface of the substrate 400 (e.g., an n-Si substrate or a p-Si substrate). For example, the substrate 400 is exposed to a nickel displacement plating bath having a composition including 0.5 M of NiS04and NH4OH at a temperature between about 60 °C and about 95 °C and a pH of about 11 for a period of time between about 2 minutes and about 4 minutes. Exposure of the silicon substrate 400 to the aqueous electrolyte having nickel ions in the absence of a reducing agent causes a local oxidation / reduction reaction at the surface of the substrate 400, thereby resulting in a metal nickel plating thereon. Thus, the nickel displacement plating enables the selective formation of a thin and pure nickel layer on the silicon material of the substrate 400 using a stable solution. Moreover, the process is self-limiting, thus the reaction stops once all surfaces of the substrate 400 are plated (e.g., there is no remaining silicon on which nickel can be formed). In certain embodiments, the nickel metal cladding layer 414 can be used as a seed layer for plating additional metal layers, such as for plating nickel or copper by a chemical plating and / or electrolytic plating method. In further embodiments, the substrate 400 is exposed to a SC-1 pre-clean solution and an HF oxide etch solution prior to the nickel displacement plating bath to promote adhesion of the nickel metal cladding layer 414 to the substrate 400.

[0072] After passivation or metallization, substrate 400 is ready for use as a core structure 402 for the formation of a core assembly, such as semiconductor core assembly 100 . FIG. 5 and FIG. 7 Flowcharts are shown of representative methods 500 and 700 , respectively, for forming insulating layer 618 on core structure 402 . FIG. 6A to FIG. 6I Schematically illustrated FIG. 5 Cross-sectional views of the core structure 402 at different stages of the depicted method 500, and FIG. 8A to FIG. 8E Schematically illustrated FIG. 7 Cross-sectional views of the core structure 402 at different stages of the depicted method 700. For clarity, the following are described together. FIG. 5 and FIG. 6A to FIG. 6I , and this article describes FIG. 7 and FIG. 8A to FIG. 8E .

[0073] Generally speaking, method 500 begins at operation 502 and FIG. 6A , wherein the first surface 406 of the core structure 402 at the first side 475 (now having the core through-hole 403 formed therein and the oxide layer 404 formed thereon) is placed and fixed on the first insulating film 616a. In one embodiment, the first insulating film 616a includes one or more layers formed of a polymer-based dielectric material. For example, the first insulating film 616a includes one or more layers formed of a flowable buildup material. In one embodiment, the first insulating film 616a includes a flowable epoxy layer 618a. Generally speaking, the thickness of the epoxy layer 618a is less than about 60 μm, such as between about 5 μm and about 50 μm. For example, the thickness of the epoxy layer 618a is between about 10 μm and about 25 μm.

[0074] The epoxy layer 618a may be formed of an epoxy containing a ceramic filler, such as an epoxy filled with (e.g., containing) silicon dioxide (SiO2) particles. Other examples of ceramic fillers that may be used to form the epoxy layer 618a and other layers of the insulating film 616a include aluminum nitride (AlN), aluminum oxide (Al2O3), silicon carbide (SiC), silicon nitride (Si3N4), Sr2Ce2Ti5O 16 , zirconium silicate (ZrSiO4), wollastonite (CaSiO3), beryllium oxide (BeO), cerium dioxide (CeO2), boron nitride (BN), calcium copper titanium oxide (CaCu3Ti4O 12), magnesium oxide (MgO), titanium dioxide (TiO2), zinc oxide (ZnO), and the like. In some examples, the ceramic filler used to form the epoxy layer 618a has a size of particles in a range between about 40 nm and about 1.5 pm, such as between about 80 nm and about 1 pm. For example, the ceramic filler used to form the epoxy layer 618a has a size of particles in a range between about 200 nm and about 800 nm, such as between about 300 nm and about 600 nm.

[0075] In some embodiments, the first insulating film 616a further includes one or more protective layers. For example, the first insulating film 616a includes a polyethylene terephthalate (PET) protective layer 622a, such as a biaxial PET protective layer 622a. However, any suitable number and combination of layers and materials are contemplated for the first insulating film 616a. In some embodiments, the entire insulating film 616a has a thickness less than about 120 pm, such as a thickness less than about 90 pm.

[0076] In some embodiments, after the core structure 402 is secured to the first insulating film 616a, the core structure 402 can then be placed on a carrier 624 adjacent to the first side 475 thereof for additional mechanical stabilization during later processing operations. Generally, the carrier 624 is formed of any suitable mechanically and thermally stable material capable of withstanding temperatures above 100 °C. For example, in one embodiment, the carrier 624 includes polytetrafluoroethylene (PTFE). In another example, the carrier 624 is formed of polyethylene terephthalate (PET).

[0077] At operation 504 and FIG. 6B At operation 504 and

[0078] At operation 506, the core structure 402 (now affixed to the insulating film 616a at the first side 475 and to the protective film 660 at the second side 477) is exposed to a first lamination process. During the lamination process, the core structure 402 is exposed to an elevated temperature, causing the epoxy layer 618a of the insulating film 616a to soften and flow into the open voids or volumes between the insulating film 616a and the protective film 660, such as into the core via 403. Thus, as FIG. 6C depicted, the core via 403 is at least partially filled (e.g., occupied) by the insulating material of the epoxy layer 618a. Further, the core structure 402 is partially surrounded by the insulating material of the epoxy layer 618a.

[0079] In one embodiment, the lamination process is a vacuum lamination process that can be performed in an autoclave or other suitable device. In one embodiment, the lamination process is performed by using a hot press process. In one embodiment, the lamination process is performed at a temperature between about 80 °C and about 140 °C and for a time period between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes the application of a pressure between about 1 pound per square inch and about 150 pounds per square inch while applying a temperature between about 80 °C and about 140 °C to the core structure 402 and the insulating film 616a for a time period between about 1 minute and about 30 minutes. For example, the lamination process is performed by applying a pressure between about 10 pounds per square inch and about 100 pounds per square inch and a temperature between about 100 °C and about 120 °C for a time period between about 2 minutes and 10 minutes. For example, the lamination process is performed at a temperature of about 110 °C for a time period of about 5 minutes.

[0080] At operation 508, the protective film 660 is removed, and the core structure 402 (now having the laminated insulating material of the epoxy layer 618a at least partially surrounding the core structure 402 and partially filling the core via 403) is placed on a second protective film 662. As FIG. 6DAs depicted, the second protective film 662 is coupled to the core structure 402 adjacent to the first side 475, such that the second protective film 662 is disposed against (e.g., proximate to) the protective layer 622a of the insulating film 616a. In some embodiments, the core structure 402 (now coupled to the protective film 662) can optionally be placed on the carrier 624 for additional mechanical support on the first side 475. In some embodiments, the protective film 662 is placed on the carrier 624 prior to coupling the protective film 662 to the core structure 402. In general, the protective film 662 is substantially similar in composition to the protective film 660. For example, the protective film 662 can be formed of PET (such as biaxial PET). However, the protective film 662 can be formed of any suitable protective material. In some embodiments, the thickness of the protective film 662 is between about 50 pm and about 150 pm.

[0081] After coupling the core structure 402 to the second protective film 662, at operation 510 and FIG. 6E placement of the second insulating film 616b on the second side 477, thereby replacing the protective film 660. In one embodiment, the second insulating film 616b is positioned on the second side 477 of the core structure 402 such that the epoxy layer 618b of the second insulating film 616b covers the core via 403. In one embodiment, the placement of the second insulating film 616b on the core structure 402 can form one or more voids between the laminated insulating material of the insulating film 616b and the epoxy layer 618a (partially surrounding the core structure 402 and partially filling the core via 403). Similar to the insulating film 616a, the second insulating film 616b can include one or more layers formed of polymer-based dielectric material. As FIG. 6E depicted, the second insulating film 616b includes an epoxy layer 618b that is substantially similar to the epoxy layer 618a as described above. The second insulating film 616b can further include a protective layer 622b formed of a material similar to the protective layer 622a, such as PET.

[0082] At operation 512, as FIG. 6F depicted, a third protective film 664 is placed on the second insulating film 616b. In general, the protective film 664 is substantially similar in composition to the protective films 660, 662. For example, the protective film 664 is formed of PET (such as biaxial PET). However, the protective film 664 can be formed of any suitable protective material. In some embodiments, the thickness of the protective film 664 is between about 50 pm and about 150 pm.

[0083] At operation 514 and FIG. 6GAt operation 514, the core structure 402 (now affixed to the insulation film 616b and the protective film 664 on the second side 477 and to the protective film 662 and the optional carrier 624 on the first side 475) is exposed to a second lamination process. Similar to the lamination process at operation 504, the core structure 402 is exposed to elevated temperatures, causing the epoxy layer 618b of the insulation film 616b to soften and flow into any open voids or volumes between the laminated insulation material of the insulation film 616b and the epoxy layer 618a, thereby integrating itself with the insulation material of the epoxy layer 618a. As a result, the core via 403 becomes completely filled (e.g., encapsulated, sealed) with the insulation material of both epoxy layers 618a, 618b.

[0084] In one embodiment, the second lamination process is a vacuum lamination process that can be performed in an autoclave or other suitable device. In one embodiment, the lamination process is performed by using a hot press process. In one embodiment, the lamination process is performed at a temperature between about 80 °C and about 140 °C and for a time period between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes the application of a pressure between about 1 pound per square inch and about 150 pounds per square inch while applying a temperature between about 80 °C and about 140 °C to the core structure 402 and the insulation film 616a for a time period between about 1 minute and about 30 minutes. For example, the lamination process is performed by applying a pressure between about 10 pounds per square inch and about 100 pounds per square inch and a temperature between about 100 °C and about 120 °C for a time period between about 2 minutes and 10 minutes. For example, the lamination process is performed at a temperature of about 110 °C for a time period of about 5 minutes.

[0085] After lamination, at operation 516, the core structure 402 is detached from the carrier 624 and the protective films 662, 664 are removed, resulting in the laminated intermediate core assembly 602. As FIG. 6H depicted, the intermediate core assembly 602 includes the core structure 402 having one or more core vias 403 formed therethrough and filled with the insulating dielectric material of the insulation films 616a, 616b. The insulating dielectric material of the epoxy layers 618a, 618b further coats the core structure 402 having the oxide layer 404 formed thereon such that the insulation material covers at least two surfaces or sides (e.g., surfaces 406, 408) of the core structure 402. In some examples, the protective layers 622a, 622b are also removed from the intermediate core assembly 602 at operation 516. Generally, the protective layers 622a and 622b, the carrier 624, and the protective films 662 and 664 are removed from the intermediate core assembly 602 by any suitable mechanical process (e.g., peeling from the intermediate core assembly 602).

[0086] After removal of the protective layers 622a, 622b and the protective films 662, 664, the intermediate core assembly 602 is exposed to a curing process to fully cure (i.e., harden by chemical reaction and cross-linking) the insulating dielectric material of the epoxy layers 618a, 618b, thereby forming the insulating layer 618. The insulating layer 618 substantially surrounds the core structure 402 and fills the core via 403. For example, the insulating layer 618 at least contacts or encapsulates 107, 477 (including the surfaces 406, 408) of the core structure 402.

[0087] In one embodiment, the curing process is performed at an elevated temperature to fully cure the intermediate core assembly 602. For example, the curing process is performed at a temperature between about 140 °C and about 220 °C and for a time period between about 15 minutes and about 45 minutes, such as at a temperature between about 160 °C and about 200 °C and for a time period between about 25 minutes and about 35 minutes. For example, the curing process is performed at a temperature of about 180 °C and for a time period of about 30 minutes. In further embodiments, the curing process at operation 516 is performed at or near ambient (e.g., atmospheric) pressure conditions.

[0088] After curing, at operation 518, one or more through-assembly vias 613 are drilled through the intermediate core assembly 602, thereby forming a passage through the entire thickness of the intermediate core assembly 602 for subsequent interconnect formation. In some embodiments, the intermediate core assembly 602 can be placed on a carrier, such as the carrier 624, for mechanical support during formation of the through-assembly vias 613. The through-assembly vias 613 are drilled through the core via 403 formed in the core structure 402 and subsequently filled by the insulating layer 618. Thus, the insulating layer 618 filled within the core via 403 can circumferentially surround the through-assembly via 613. By having the epoxy material of the insulating layer 618 with ceramic fillers lining the walls of the core via 403, the completed (e.g., final) semiconductor core assembly 1270 (refer to FIG. 10G 、 FIG. 11 and FIG. 12K and FIG. 12L described) has significantly reduced capacitive coupling between the conductive silicon-based core structure 402 and the interconnects 1044 (refer to FIG. 9 and FIG. 10A to FIG. 10H described). Moreover, the flowable nature of the epoxy material of the insulating layer 618 enables more consistent and reliable encapsulation and insulation, thereby enhancing electrical performance by minimizing leakage current of the completed semiconductor core assembly 1270.

[0089] In one embodiment, the diameter of the through-assembly via 613 is less than about 100 pm, such as less than about 75 pm. For example, the diameter of the through-assembly via 613 is less than about 50 pm, such as less than about 35 pm. In some embodiments, the diameter of the through-assembly via 613 is between about 25 pm and about 50 pm, such as a diameter between about 35 pm and about 40 pm. In one embodiment, the through-assembly via 613 is formed using any suitable mechanical process. For example, the through-assembly via 613 is formed using a mechanical drilling process. In one embodiment, the through-assembly via 613 is formed through the intermediate core assembly 602 by laser ablation. For example, the through-assembly via 613 is formed using an ultraviolet laser. In one embodiment, the frequency of the laser source used for laser ablation is between about 5 kHz and about 500 kHz. In one embodiment, the laser source is configured to deliver a pulsed laser beam with a pulse energy between about 50 microjoules (pm) and about 500 pm with a pulse duration between about 10 ns and about 100 ns. The use of an epoxy material containing small ceramic filler particles further facilitates more precise and accurate laser patterning of small diameter vias, such as the through-assembly via 613, as the small ceramic filler particles in the epoxy material exhibit reduced laser reflection, scattering, diffraction, and transmission of the laser light away from the region where the via is to be formed during the laser ablation process.

[0090] In some embodiments, the through-assembly via 613 is formed within (e.g., through) the core via 403 such that the average thickness of the remaining ceramic filler-containing epoxy material (e.g., dielectric insulating material) on the sidewalls of the core via 403 is between about 1 pm and about 50 pm. For example, the average thickness of the remaining ceramic filler-containing epoxy material on the sidewalls of the core via 403 is between about 5 pm and about 40 pm, such as between about 10 pm and about 30 pm. Thus, the resulting structure after the through-assembly via 613 is formed can be described as a “via-in-a-via” (e.g., a via formed centrally within a dielectric material of a core structure). In certain embodiments, the via-in-a-via structure includes a dielectric sidewall passivation consisting of ceramic particle-filled epoxy material disposed on a thin layer of thermal oxide formed on the sidewalls of the core via 403.

[0091] In embodiments where the metal cladding layer 114, 414 is formed over the core structure 102, one or more cladding vias 123 can also be formed at operation 518 to provide a passageway for the cladding connection 116 (e.g., a via-in-a-via structure). In one embodiment, the cladding via 123 is formed through the core structure 102 and the intermediate core assembly 602 using a mechanical drilling process. In one embodiment, the cladding via 123 is formed through the core structure 102 and the intermediate core assembly 602 by laser ablation. For example, the cladding via 123 is formed using an ultraviolet laser. In one embodiment, the frequency of the laser source used for laser ablation is between about 5 kHz and about 500 kHz. In one embodiment, the laser source is configured to deliver a pulsed laser beam with a pulse energy between about 50 microjoules (pm) and about 500 pm with a pulse duration between about 10 ns and about 100 ns. FIG. 1CAs described above, the clad vias 123 are formed in the insulating layer 118 above and / or below the core structure 102 to enable the metal cladding 114, 414 to be coupled to the clad connection 116 so that the metal cladding 114, 414 can be connected to an external common ground or reference voltage. In one embodiment, the diameter of the clad via 123 is less than about 100 μm, such as less than about 75 μm. For example, the diameter of the clad via 123 is less than about 50 μm, such as less than about 35 μm. In some embodiments, the diameter of the clad via 123 is between about 5 μm and about 25 μm, such as between about 10 μm and about 20 μm.

[0092] When forming the through-component through-hole 613 and / or the covering through-hole 123 (such as FIG. 1C ), the intermediate core assembly 602 is exposed to a decontamination process. During the decontamination process, any undesirable residues and / or debris caused by laser ablation during the formation of the through-assembly vias 613 and / or the cladding vias 123 are removed from the intermediate core assembly 602. Thus, the decontamination process cleans the vias for subsequent metallization. In one embodiment, the decontamination process is a wet decontamination process. Any suitable solvent, etchant, and / or combination thereof can be used for the wet decontamination process. In one example, methanol can be used as a solvent and copper (II) chloride dihydrate (CuCl2·H2O) can be used as an etchant. Depending on the thickness of the residue, the duration of exposure of the intermediate core assembly 602 to the wet decontamination process can be different. In another embodiment, the decontamination process is a dry decontamination process. For example, the decontamination process can be a plasma decontamination process using an O2 / CF4 gas mixture. The plasma decontamination process may include generating a plasma by applying a power of about 700 W and flowing O2:CF4 at a ratio of about 10:1 (e.g., 100:10 sccm) for a period of time between about 60 seconds and about 120 seconds. In further embodiments, the decontamination process is a combination of wet and dry processes.

[0093] After the desmear process at operation 518, the intermediate core assembly 602 is ready for forming interconnect paths therein, as described below with reference to FIG. 9 and FIG. 10A to FIG. 10H Provide a description.

[0094] As mentioned above, FIG. 5 and FIG. 6A to FIG. 6I A representative method 500 for forming an intermediate core assembly 602 is illustrated. FIG. 7 and FIG. 8A to FIG. 8EAn alternative method 700 is illustrated that is substantially similar to the method 500 but with fewer operations. Generally, the method 700 includes five operations 710-750. However, the operations 710, 740, and 750 of the method 700 are substantially similar to the operations 502, 516, and 518 of the method 500, respectively. Therefore, for the sake of clarity, only the operations 720, 730, and 740 of the method 700 are described herein, respectively. FIG. 8B , FIG. 8C and FIG. 8D The operation 720, 730, and 740 are depicted as follows.

[0095] At operation 720 and FIG. 8B , after the first insulating film 616a is secured to the first surface 406 on the first side 475 of the core structure 402, the second insulating film 616b is coupled to the second surface 408 on the opposite side 477. In some embodiments, the second insulating film 616b is positioned on the surface 408 of the core structure 402 such that the epoxy layer 618b of the second insulating film 616b covers all of the core vias 403. As FIG. 8B depicted, the core vias 403 form one or more voids or gaps between the insulating films 616a and 616b. In some embodiments, a second carrier 625 is secured to the protective layer 622b of the second insulating film 616b for additional mechanical support during later processing operations.

[0096] At operation 730 and FIG. 8C , the core structure 402 (now secured to the insulating films 616a and 616b on opposite sides of the core structure 402) is exposed to a single lamination process. During the single lamination process, the core structure 402 is exposed to elevated temperatures, which causes the epoxy layers 618a and 618b of the two insulating films 616a, 616b to soften and flow into the open voids or volumes created by the core vias 403 between the insulating films 616a, 616b. As a result, the core vias 403 are filled with the insulating material of the epoxy layers 618a and 618b.

[0097] Similar to the description of FIG. 5 and FIG. 6A to FIG. 6IThe described lamination process, at operation 730, can be a vacuum lamination process that can be performed in an autoclave or other suitable device. In another embodiment, the lamination process is performed by using a hot press process. In one embodiment, the lamination process is performed at a temperature between about 80 °C and about 140 °C and for a time period between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes the application of a pressure between about 1 pound per square inch and about 150 pounds per square inch while applying a temperature between about 80 °C and about 140 °C to the core structure 402 and the insulating films 616a, 616b for a time period between about 1 minute and about 30 minutes. For example, the lamination process is performed at a pressure between about 10 pounds per square inch and about 100 pounds per square inch and a temperature between about 100 °C and about 120 °C and for a time period between about 2 minutes and 10 minutes. For example, the lamination process at operation 730 is performed at a temperature of about 110 °C for a time period of about 5 minutes.

[0098] At operation 740, one or more protective layers of the insulating films 616a, 616b are removed from the core structure 402, resulting in a laminated intermediate core assembly 602. In one example, the protective layers 622a, 622b are removed from the core structure 402, and thus the intermediate core assembly 602 is also separated from the first carrier 624 and the second carrier 625. Generally, the protective layers 622a, 622b and the carriers 624, 625 are removed by any suitable mechanical process, such as peeling therefrom. As FIG. 8D As depicted, the intermediate core assembly 602 includes the core structure 402 having one or more core vias 403 formed therein and filled with the insulating dielectric material of the epoxy layers 618a and 618b. The insulating material further coats the core structure 402 such that the insulating material covers at least two surfaces or sides (e.g., surfaces 406, 408) of the core structure 402.

[0099] After the protective layers 622a, 622b are removed, the intermediate core assembly 602 is exposed to a curing process to fully cure the insulating dielectric material of the epoxy layers 618a, 618b. The curing of the insulating material results in the formation of the insulating layer 618. As FIG. 8D As depicted and similar to the FIG. 6H Corresponding to operation 516, the insulating layer 618 substantially surrounds the core structure 402 and fills the core vias 403.

[0100] In one embodiment, the curing process is performed at an elevated temperature to fully cure the intermediate core assembly 602. For example, the curing process is performed at a temperature between about 140 °C and about 220 °C and for a time period between about 15 minutes and about 45 minutes, such as at a temperature between about 160 °C and about 200 °C and for a time period between about 25 minutes and about 35 minutes. For example, the curing process is performed at a temperature of about 180 °C and for a time period of about 30 minutes. In further embodiments, the curing process at operation 740 is performed at or near ambient (e.g., atmospheric) pressure conditions.

[0101] After curing at operation 740, the method 700 is substantially similar to operation 518 of the method 500. Thus, one or more through-assembly vias 613 and / or overcoat vias 123 (as shown) are drilled through the intermediate core assembly 602, which is then exposed to a decontamination process. After completion of the decontamination process, the intermediate core assembly 602 is ready for formation of interconnect paths therein, as described below. FIG. 1C

[0102] FIG. 9 A flowchart illustrating a representative method 900 for forming electrical interconnects through an intermediate core assembly 602. FIG. 10A to FIG. 10H A cross-sectional view of the intermediate core assembly 602 at different stages of the processes of the depicted method 900 is schematically illustrated. FIG. 9 Thus, for clarity, the intermediate core assembly 602 at different stages of the processes of the depicted method 900 are described herein together. FIG. 9 and FIG. 10A to FIG. 10H .

[0103] In one embodiment, the electrical interconnects formed through the intermediate core assembly 602 are formed of copper. Thus, the method 900 generally begins at operations 910 and FIG. 10A wherein the intermediate core assembly 602 having the through-assembly vias 613 formed therein has a barrier or adhesion layer 1040 and / or a seed layer 1042 formed thereon. In FIG. 10H a partial magnified view of the adhesion layer 1040 and the seed layer 1042 formed on the intermediate core assembly 602 is depicted for reference. The adhesion layer 1040 can be formed on desired surfaces of the insulating layer 618, such as surfaces corresponding to the major surfaces 1005, 1007 of the intermediate core assembly 602 and sidewalls of the through-assembly vias 613 and / or overcoat vias 123, to assist in promoting adhesion and preventing diffusion of the subsequently formed seed layer 1042, electrical interconnects 1044, and / or overcoat connections 116 (as shown). FIG. 1C Thus, in one embodiment, the adhesion layer 1040 acts as an adhesion layer; in another embodiment, the adhesion layer 1040 acts as a barrier layer. However, in both embodiments, the adhesion layer 1040 is described below as an “adhesion layer.”​

[0104] In one embodiment, adhesion layer 1040 is formed of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, or any other suitable material or combination thereof. In one embodiment, adhesion layer 1040 has a thickness between about 10 nm and about 300 nm, such as between about 50 nm and about 150 nm. For example, adhesion layer 1040 has a thickness between about 75 nm and about 125 nm, such as about 100 nm. Adhesion layer 1040 is formed by any suitable deposition process, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), etc.

[0105] Seed layer 1042 may be formed on adhesion layer 1040 or directly on insulating layer 618 (e.g., without adhesion layer 1040). In some embodiments, seed layer 1042 is formed on all surfaces of insulating layer 618, while adhesion layer 1040 is formed only on desired surfaces or desired portions of the surfaces of insulating layer 618. For example, adhesion layer 1040 may be formed on major surfaces 1005, 1007 and not on through-device vias 613 and / or cladding vias 123 (e.g., FIG. 1C 1005 and 1007 and the sidewalls of the through-hole. Seed layer 1042 is formed on the main surfaces 1005 and 1007 and the sidewalls of the through-hole. Seed layer 1042 is formed of a conductive material (such as copper, tungsten, aluminum, silver, gold) or any other suitable material or combination thereof. In one embodiment, the thickness of seed layer 1042 is between about 0.05 μm and about 0.5 μm, such as between about 0.1 μm and about 0.3 μm. For example, the thickness of seed layer 1042 is between about 0.15 μm and about 0.25 μm, such as about 0.2 μm. In one embodiment, the thickness of seed layer 1042 is between about 0.1 μm and about 1.5 μm. Similar to adhesion layer 1040, seed layer 1042 is formed by any suitable deposition process (such as CVD, PVD, PECVD, ALD dry process, wet chemical plating process, etc.). In one embodiment, a copper seed layer 1042 may be formed on the molybdenum adhesion layer 1040 on the intermediate core assembly 602. The combination of the molybdenum adhesion and copper seed layers enables improved adhesion to the surface of the insulating layer 618 and reduces undercutting of the conductive interconnects during the subsequent seed layer etching process at operation 970.

[0106] At operations 920 and 930 (respectively FIG. 10B and FIG. 10CA spin-on / spray-on or dry resist film 1050, such as photoresist, is applied to both major surfaces 1005, 1007 of the intermediate core assembly 602 and subsequently patterned. In one embodiment, the resist film 1050 is patterned via selective exposure to UV radiation. In one embodiment, a adhesion promoter (not shown) is applied to the intermediate core assembly 602 prior to forming the resist film 1050. The adhesion promoter improves adhesion of the resist film 1050 to the intermediate core assembly 602 by creating an interfacial adhesion layer for the resist film 1050 and by removing any moisture from the surfaces of the intermediate core assembly 602. In some embodiments, the adhesion promoter is formed from bis(trimethylsilyl)amine or hexamethyldisilazane (HMDS) and propylene glycol methyl ether acetate (PGMEA).

[0107] At operation 940, the intermediate core assembly 602 is exposed to a resist film development process. As FIG. 10D depicted, development of the resist film 1050 results in exposure of the through-assembly via 613 and / or the cladding via 123 (as FIG. 1C shown) (which can now have an adhesion layer 1040 and / or a seed layer 1042 formed thereon) throughout. In one embodiment, the film development process is a wet process, such as a wet process that includes exposing the resist film 1050 to a solvent. In one embodiment, the film development process is a wet etch process that utilizes an aqueous etch process. For example, the film development process is a wet etch process that utilizes a buffered etch process that is selective to the desired material. Any suitable combination of wet solvents or wet etchants can be used for the resist film development process.

[0108] At operations 950 and 960 (corresponding to FIG. 10E and FIG. 10F respectively), an electrical interconnect 1044 is formed through the exposed through-assembly via 613, and the resist film 1050 is removed thereafter. In embodiments where the core structure 102 has a metal cladding layer 114, 414 formed thereon, at operation 950, a cladding connection 116 (as FIG. 1C shown) can also be formed through the exposed cladding via 123 (as FIG. 1C shown). The interconnect 1044 and / or the cladding connection 116 are formed by any suitable method, including electroplating and electroless plating. In one embodiment, the resist film 1050 is removed via a wet process. As FIG. 10E and FIG. 10FAs depicted, after removal of the resist film 1050, the electrical interconnects 1044 can completely fill the through-assembly via 613 (and the wrap-around connections 116 can also completely fill the wrap-around via 123) and protrude from the surfaces 1005, 1007 of the intermediate core assembly 602. In some embodiments, the electrical interconnects 1044 and / or the wrap-around connections 116 can only line the sidewalls of the vias without completely filling the vias. In one embodiment, the electrical interconnects 1044 and / or the wrap-around connections 116 are formed of copper. In other embodiments, the electrical interconnects 1044 and / or the wrap-around connections 116 can be formed of any suitable conductive material including, but not limited to, aluminum, gold, nickel, silver, palladium, tin, etc.

[0109] At operation 970 and FIG. 10G the intermediate core assembly 602 with the electrical interconnects 1044 and / or the wrap-around connections 116 formed therein is exposed to a seed layer etch process to remove the exposed adhesive layer 1040 and the seed layer 1042 (e.g., surfaces 1005, 1007) on the outer surfaces thereof. In some embodiments, after the seed layer etch process, the adhesive layer 1040 and / or the seed layer 1042 formed between the interconnects and the sidewalls of the vias can be retained. In one embodiment, the seed layer etch is a wet etch process that includes rinsing and drying the intermediate core assembly 602. In one embodiment, the seed layer etch process is a buffered etch process that is selective to a desired material such as copper, tungsten, aluminum, silver, or gold. In other embodiments, the etch process is an aqueous etch process. Any suitable wet etchant or combination of wet etchants can be used for the seed layer etch process.

[0110] After the seed layer etch process at operation 970, one or more semiconductor core assemblies can be singulated from the intermediate core assembly 602 and used as a functionally complete semiconductor core assembly 1270 (e.g., an electronic mounting or packaging structure). For example, one or more semiconductor core assemblies can be singulated and used as a circuit board structure, a chip carrier structure, an integrated circuit package, etc. Alternatively, the intermediate core assembly 602 can have one or more redistribution layers 1260 FIG. 12J and FIG. 12K formed thereon to rewire the external contact points of the electrical interconnects 1044 to desired locations on the surface of the final semiconductor core assembly as shown.

[0111] FIG. 11 A flowchart of a representative method 1100 for forming a redistribution layer 1260 on the intermediate core assembly 602 (which has not yet been singulated into a semiconductor core assembly 1270) is illustrated. FIG. 12A to FIG. 12K A representative semiconductor core assembly 1270 is schematically illustrated FIG. 11Cross-sectional views of the intermediate core assembly 602 at different stages of the depicted method 1100. Therefore, for clarity, the following are described together herein. FIG. 11 and FIG. 12A to FIG. 12K .

[0112] Method 1100 is substantially similar to methods 500, 700, and 900 described above. Generally speaking, method 1100 begins with operations 1102 and FIG. 12A wherein the insulating film 1216 is fixed to the intermediate core assembly 602 and thereafter laminated. The insulating film 1216 is substantially similar to the insulating films 616a, 616b. In one embodiment, as FIG. 12A As depicted, insulating film 1216 includes an epoxy layer 1218 and one or more protective layers. For example, insulating film 1216 may include protective layer 1222. Any suitable combination of layers and insulating materials is contemplated for insulating film 1216. In some embodiments, an optional carrier 1224 is coupled to insulating film 1216 for added support. In some embodiments, a protective film (not shown) may be coupled to insulating film 1216.

[0113] In general, the thickness of epoxy layer 1218 is less than about 60 μm, such as between about 5 μm and about 50 μm. For example, the thickness of epoxy layer 1218 is between about 10 μm and about 25 μm. In one embodiment, the combined thickness of epoxy layer 1218 and PET protective layer 1222 is less than about 120 μm, such as less than about 90 μm. Insulating film 1216, and in particular epoxy layer 1218, is secured to a surface of intermediate core assembly 602 (such as major surface 1005) having exposed electrical interconnects 1044.

[0114] After placing the insulating film 1216, the intermediate core assembly 602 is exposed to a lamination process (substantially similar to the lamination process described with respect to operations 506, 514, and 730). The intermediate core assembly 602 is exposed to an elevated temperature to soften the epoxy layer 1218 of the insulating film 1216, which is then bonded to the insulating layer 618. Thus, the epoxy layer 1218 is integrated with the insulating layer 618 and forms an extension of the insulating layer 618, and is therefore hereinafter described as a single insulating layer 618. The integration of the epoxy layer 1218 with the insulating layer 618 further results in an expanded insulating layer 618 surrounding the previously exposed electrical interconnects 1044.

[0115] In operation 1104 and FIG. 12BAt 740, protective layer 1222 and carrier 1224 are removed from intermediate core assembly 602 by mechanical means, and intermediate core assembly 602 is exposed to a curing process to fully harden the newly expanded insulating layer 618. In one embodiment, the curing process is substantially similar to the curing process described with reference to operations 516 and 740. For example, the curing process is performed at a temperature between about 140° C. and about 220° C. and for a period of time between about 15 minutes and about 45 minutes.

[0116] Then, in operation 1106 and FIG. 12C At 1106, the intermediate core component 602 is selectively patterned by laser ablation. The laser ablation process at operation 1106 forms one or more redistribution vias 1253 in the newly expanded insulating layer 618, and exposes the desired electrical interconnects 1044 for redistribution of their contact points. In one embodiment, the diameter of the redistribution vias 1253 is substantially similar to or smaller than the diameter of the through-component vias 613. For example, the diameter of the redistribution vias 1253 is between about 5 μm and about 600 μm, such as between about 10 μm and about 50 μm, such as between about 20 μm and about 30 μm. In one embodiment, the laser ablation process at operation 1106 is performed using a CO2 laser. In one embodiment, the laser ablation process at operation 1106 is performed using a UV laser. In another embodiment, the laser ablation process at operation 1106 is performed using a green laser. In one example, the laser source can generate a pulsed laser beam having a frequency between about 100 kHz and about 1000 kHz. In one example, the laser source is configured to deliver a pulsed laser beam at a wavelength between about 100 nm and about 2000 nm, a pulse duration between about 10E-4 ns and about 10E-2 ns, and with a pulse energy between about 10 μJ and about 300 μJ.

[0117] In embodiments where the metal cladding layer 114, 414 is formed on the core structure 102 (e.g. FIG. 1C ), the intermediate core component 602 may also be patterned at operation 1106 to form one or more wrapping vias 123 through the extended insulating layer 618. Thus, for a semiconductor core component having one or more redistribution layers, wrapping vias 123 and redistribution vias 1253 may be formed simultaneously at operation 518 or 750, rather than forming wrapping vias 123 and through-component vias 613. However, in certain other embodiments, wrapping vias 123 may be patterned first at operation 518 or 750, then metallized with wrapping connections 116, and then extended or extended through the extended insulating layer 618 at operation 1106.

[0118] In operation 1108 and FIG. 12DAt operation 1120, an adhesion layer 1240 and / or a seed layer 1242 are optionally formed on one or more surfaces of the insulating layer 618. In one embodiment, the adhesion layer 1240 and the seed layer 1242 are substantially similar to the adhesion layer 1040 and the seed layer 1042, respectively. For example, the adhesion layer 1240 is formed of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, or any other suitable material or combination thereof. In one embodiment, the adhesion layer 1240 has a thickness between about 10 nm and about 300 nm, such as a thickness between about 50 nm and about 150 nm. For example, the adhesion layer 1240 has a thickness between about 75 nm and about 125 nm, such as about 100 nm. The adhesion layer 1240 can be formed by any suitable deposition process, including but not limited to CVD, PVD, PECVD, ALD, and the like.

[0119] The seed layer 1242 is formed of a conductive material, such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof. In one embodiment, the seed layer 1242 has a thickness between about 0.05 pm and about 0.5 pm, such as between about 0.1 pm and about 0.3 pm. For example, the seed layer 1242 has a thickness between about 0.15 pm and about 0.25 pm, such as about 0.2 pm. Similar to the adhesion layer 1240, the seed layer 1242 can be formed by any suitable deposition process, such as CVD, PVD, PECVD, ALD dry process, wet electroless plating process, and the like. In one embodiment, a molybdenum adhesion layer 1240 and a copper seed layer 1242 are formed on the intermediate core assembly 602 to reduce the formation of undercut during a subsequent seed layer etch process at operation 1122.

[0120] At operations 1110, 1112, and 1114 (respectively, and FIG. 12E , FIG. 12F and FIG. 12GCorrespondingly), a spin-on / spray-on or dry resist film 1250, such as photoresist, is applied over the seed surface of the intermediate core assembly 602 and is subsequently patterned and developed. In one embodiment, a adhesion promoter (not shown) is applied to the intermediate core assembly 602 prior to placement of the resist film 1250. Exposure and development of the resist film 1250 results in the opening of the redistribution via 1253 and, in certain embodiments, the opening of the wrap via 123. Accordingly, the patterning of the resist film 1250 can be performed by selectively exposing portions of the resist film 1250 to UV radiation and subsequent development of the resist film 1250 by a wet process, such as a wet etch process. In one embodiment, the resist film development process is a wet etch process utilizing a buffered etch process selective to the desired material. In other embodiments, the resist film development process is a wet etch process utilizing an aqueous etch process. Any suitable wet etchant or combination of wet etchants can be used for the resist film development process.

[0121] At operations 1116 and 1118 (correspondingly), FIG. 12H and FIG. 12I At operation 1116, the redistribution connection 1244 is formed through the exposed redistribution via 1253 and, in certain embodiments, the wrap connection 116 is also formed through the exposed wrap via 123. In one embodiment, the resist film 1250 is removed via a wet process. As FIG. 12H and FIG. 12I depicted, after removal of the resist film 1250, the redistribution connection 1244 fills the redistribution via 1253 and protrudes from the surface of the intermediate core assembly 602. In one embodiment, the redistribution connection 1244 is formed from copper. In other embodiments, the redistribution connection 1244 is formed from any suitable conductive material, including but not limited to aluminum, gold, nickel, silver, palladium, tin, and the like. Any suitable method can be used to form the redistribution connection 1244, including electroplating and electroless plating deposition.

[0122] At operations 1120 and FIG. 12J the intermediate core assembly 602 having the redistribution connection 1244 formed thereon is exposed to a seed layer etch process substantially similar to operation 970. In one embodiment, the seed layer etch is a wet etch process including rinsing and drying the intermediate core assembly 602. In one embodiment, the seed layer etch process is a wet etch process utilizing a buffered etch process selective to the desired material of the seed layer 1242. In other embodiments, the etch process is a wet etch process utilizing an aqueous etch process. Any suitable wet etchant or combination of wet etchants can be used for the seed layer etch process.

[0123] After completing the seed layer etch process at operation 1120, one or more additional redistribution layers 1260 can be formed on the intermediate core assembly 602 using the sequences and processes described above. For example, one or more additional redistribution layers 1260 can be formed on the first redistribution layer 1260 and / or on an opposite surface (such as the major surface 1007) of the intermediate core assembly 602. In one embodiment, the one or more additional redistribution layers 1260 can be formed from a polymer-based dielectric material (such as a flowable build-up material) that is different from the material of the first redistribution layer 1260 and / or the insulating layer 618. For example, in some embodiments, the insulating layer 618 can be formed from an epoxy filled with ceramic fibers, while the first and / or any additional redistribution layers 1260 are formed from polyimide, BCB, and / or PBO. Alternatively, at operation 1122 and FIG. 12K after forming the desired number of redistribution layers 1260, one or more completed semiconductor core assemblies 1270 can be cut from the intermediate core assembly 602.

[0124] The completed semiconductor core assembly 1270 formed at operation 1120 can be used in any suitable package-on-package assembly, PCB assembly, PCB spacer assembly, chip carrier assembly, interposer assembly, etc. In FIG. 13A In the depicted example embodiment, a single semiconductor core assembly 1270 is used as a carrier for a chip 1360 in a chip carrier assembly 1300. The chip 1360 can be any suitable type of chip (including a memory chip, microprocessor, complex system-on-chip (SoC), or standard chip). Suitable types of memory chips include DRAM chips or NAND flash chips. In some further examples, the chip 1360 is a digital chip, an analog chip, or a hybrid chip. The chip 1360 is disposed adjacent to one of the major surfaces 1005, 1007 of the semiconductor core assembly 1270. In some embodiments, two or more chips 1360 can be disposed adjacent to a single major surface 1005, 1007. In another embodiment, one or additional devices and / or structures (such as one or more components of a PCB or package substrate) can be disposed adjacent to the chip 1360. For example, one or more passive elements (such as capacitors, resistors, inductors, etc.) can be disposed adjacent to the chip 1360. In another example, one or more connectors can be disposed adjacent to the chip 1360.

[0125] Chip 1360 includes one or more contacts 1348 formed on an active surface 1352 thereof. As shown, contacts 1348 are conductively coupled to one or more redistribution connections 1244 of semiconductor core assembly 1270 through one or more solder bumps 1346 disposed between active surface 1352 and major surface 1005. In some embodiments, contacts 1348 can be conductively coupled to one or more interconnects 1044 through one or more solder bumps 1346. In one embodiment, contacts 1348 and / or solder bumps 1346 are formed of substantially similar materials as interconnects 1044 and redistribution connections 1244. For example, contacts 1348 and solder bumps 1346 can be formed of conductive materials such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof.

[0126] In one embodiment, solder bumps 1346 include C4 solder bumps. In one embodiment, solder bumps 1346 include C2 (copper pillar with solder cap) solder bumps. Utilization of C2 solder bumps can enable smaller pitch lengths and improved thermal and / or electrical properties of chip carrier assembly 1300. Solder bumps 1346 can be formed by any suitable die bumping process including, but not limited to, electrochemical deposition (ECD) and electroplating.

[0127] In FIG. 13B In another example embodiment depicted, semiconductor core assembly 1270 is utilized in a PCB assembly 1302. Accordingly, semiconductor core assembly 1270 is configured to function as a PCB structure for supporting (e.g., carrying) a package assembly 1310. The structure and materials of package assembly 1310 can be substantially similar to semiconductor core assembly 1270, but package assembly 1310 includes an embedded die 1326 disposed within a cavity 1320 formed within core structure 402 (substantially surrounded by insulating layer 618). Embedded die 1326 can further include an active surface 1328 having one or more contacts 1330 formed thereon and coupled with interconnects 1342 and / or redistribution connections 1344 of package assembly 1310. Similar to FIG. 13A chip carrier assembly 1300, contacts 1330 and / or interconnects 1342 and / or redistribution connections 1344 of package assembly 1310 are conductively coupled to one or more redistribution connections 1244 of semiconductor core assembly 1270 through one or more solder bumps 1346 disposed between active surface 1328 and major surface 1005. In some embodiments, contacts 1330 can be conductively coupled to one or more interconnects 1044 through one or more solder bumps 1346.

[0128] FIG. 13CThe figure illustrates yet another exemplary embodiment utilizing a semiconductor core assembly 1270 as a PCB spacer structure within a PCB assembly 1304. As shown, the semiconductor core assembly 1270 is disposed between two PCBs 1362a and 1362b and is configured to position the first PCB 1362a relative to the second PCB 1362b such that a physical space remains between the first PCB 1362a and the second PCB 1362b when they are conductively connected. Accordingly, the PCBs 1362a and 1362b include one or more conductive pads 1368 formed on their major surfaces 1364a and 1364b, respectively. The one or more conductive pads 1368 are conductively coupled to the redistribution connections 1244 and / or the interconnects 1044 of the semiconductor core assembly 1270 via one or more solder bumps 1346. Similar to contacts 1330 and 1348, conductive pad 1368 is formed of a material substantially similar to solder bump 1346, interconnect 1044, and redistribution connection 1244 to enable electrical conductivity therethrough. For example, conductive pad 1368 may be formed of a conductive material such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof.

[0129] FIG. 14A to FIG. 14C The diagram shows the configuration of a semiconductor core assembly 1270 in which one or more passive components or devices are integrated. FIG. 14A As shown, in certain embodiments, the semiconductor core component 1270 may include one or more capacitors 1410a and / or 1410b within the bag portion 1420 integrated in the core structure 402 to achieve more stable power delivery across the semiconductor core component 1270. Therefore, in certain embodiments, capacitors 1410a, 1410b can be used as decoupling capacitors. In certain embodiments, capacitors 1410a, 1410b are trench capacitors or planar capacitors. Capacitors 1410a, 1410b are formed by any suitable dielectric material (including but not limited to ceramic or silicon). In certain embodiments, capacitors 1410a, 1410b are formed by a silicon wafer cut into a single piece, and after the silicon wafer is ground to a desired thickness, the silicon wafer can be cut into separate capacitors. In such an embodiment, before being cut into a single piece, the silicon wafer can be ground to a thickness substantially similar to that of the core structure 402.

[0130] Generally, the lateral dimension of the capacitors 1410a, 1410b is between about 750 pm and about 175 mm, such as between about 1 mm and about 1.5 mm. Further, the thickness of the capacitors 1410a, 1410b is substantially equal to or less than the thickness of the core structure 402, such as less than about 1500 pm, such as less than about 780 pm, such as less than about 300 pm or about 200 pm. For example, the thickness of the capacitors 1410a, 1410b can be less than about 150 pm or about 120 pm. In certain embodiments, the capacitors integrated within the semiconductor core assembly 1270 are standalone devices (such as capacitor 1410a) having a thickness substantially similar to the thickness of the core structure 402. In certain embodiments, the capacitors are pedestal devices (such as capacitor 1410b) coupled to the thin substrate 1402 and thus have a thickness less than the thickness of the core structure 402. Prior to integration into the semiconductor core assembly 1270, the capacitors 1410b can be adhered to the substrate 1402 with an adhesive 1404. For example, a plurality of capacitors 1410 can be adhered to a bulk substrate 1402 and then diced into pedestal devices having a desired size for integration with the semiconductor core assembly 1270.

[0131] Capacitors 1410a, 1410b can be integrated within semiconductor core assembly 1270 using the above-described methods. Generally, at operation 320 of method 300, pocket 1420 is patterned into core structure 402 along with core via 403. In certain embodiments, pocket 1420 has a lateral dimension between about 10 pm and about 250 pm, greater (e.g., longer) than the lateral dimension of a capacitor 1410a or 1410b to be embedded therein, such as greater between about 20 pm and about 150 pm, or greater between about 30 pm and about 100 pm. For example, the lateral dimension of pocket 1420 can be sized to achieve a 50 pm gap between the surface of capacitor 1410a and / or 1410b and the sidewalls of pocket 1420. Then, in one embodiment utilizing method 500, capacitor 1410a and / or 1410b is placed within pocket 1420 after operation 504 (in which patterned core structure 402 is secured to first insulating film 616a) but before operation 506 (in which first protective film 660 is placed over core structure 402). Alternatively, in another embodiment utilizing method 700, capacitor 1410a and / or 1410b is placed within pocket 1420 after operation 710 (in which patterned core structure 402 is secured to first insulating film 616a) but before operation 720 (in which second insulating film 616b is secured to core substrate 402). In either embodiment, capacitor 1410a, 1410b is embedded within pocket 1420 by insulating layer 618, which is formed after lamination of both insulating films 616a and 616b.

[0132] Thereafter, as described with reference to operations 518 and 750, through-assembly via 613 and / or redistribution via 1253 is drilled through insulating layer 618 directly above or below the contacts of capacitor 1410a, 1410b to expose the contacts. Through-assembly via 613 and / or redistribution via 1253 can then be metallized to enable capacitor 1410a, 1410b to be electrically coupled to other devices (e.g., power and ground) stacked with semiconductor core assembly 1270. For example, one or more interconnects 1044 and / or redistribution connections 1244 can be formed according to methods 900 and / or 1100.

[0133] FIG. 14B and FIG. 14C An exemplary configuration of semiconductor core assembly 1270 with one or more inductors 1450a and / or 1450b integrated therein is illustrated. FIG. 14B is a cross-sectional view of semiconductor core assembly 1270, while FIG. 14Cis a top view thereof. As shown, the interconnects 1044 are electrically coupled with the redistribution connections 1244 in a coil-like arrangement, where the redistribution connections 1244 are metallized in a non-linear pattern or connect non-adjacent interconnects 1044. Thus, this coil-like arrangement forms inductors 1450a, 1450b embedded within (rather than disposed on the surface of) the semiconductor core assembly 1270, thereby saving surface area for the stacking of other components or devices on the semiconductor core assembly 1270. Moreover, the electrical connections of the semiconductor core assembly 1270 forming the coil-like shape enable its overall reduced profile without the need to utilize additional resources or operations to incorporate inductive devices.

[0134] In certain embodiments, inductors integrated into the semiconductor core assembly 1270 include a coil-like arrangement of interconnects 1044 and redistribution connections 1244 formed around the core structure 402 and the insulating layers 618 without the need to utilize a magnetic core (e.g., inductor 1450a). In certain other embodiments, the inductors further include a magnetic core 1460 (e.g., inductor 1450b) embedded within the pocket 1420 of the core structure 402 and surrounded by the coil-like arrangement of interconnects 1044 and redistribution connections 1244. The magnetic core 1460 can be formed of a ferrite-based material or a metal-polymer composition (typically including a polymer matrix having metal particles dispersed therein).

[0135] Similar to the capacitors of FIG. 14A , the inductors 1450a, 1450b can be integrated within the semiconductor core assembly 1270 using the methods described above. For example, as described with reference to the methods 500 and 700, the magnetic core 1460 can be placed within the patterned pocket 1420 of the core structure 402 and then embedded after lamination with one or more insulating films (e.g., insulating films 616a, 616b). Moreover, the drilling of the vias 403, through-assembly vias 613, and redistribution vias 1253 and the metallization of the interconnects 1044 and redistribution connections 1244 (e.g., including the patterning of the resist 1250) can be performed using the manner in which the coil-like arrangement of interconnects 1044 and redistribution connections 1244 is established within the semiconductor core assembly 1270.

[0136] FIG. 15A to FIG. 15D Other configurations of the semiconductor core assembly 1270 are illustrated integrating other types of passive devices. As FIG. 15A to FIG. 15BAs shown, the semiconductor core assembly 1270 includes heat exchangers 1510a-c integrated at various locations. The integration of the heat exchangers 1510a-c, such as heat sinks, improves the heat dissipation and thermal characteristics of the semiconductor core assembly 1270 by transferring heat conducted by the silicon core structure 402. This arrangement is particularly advantageous compared to conventional PCBs formed of glass-reinforced epoxy laminates, which have low thermal conductivity for which the addition of heat exchangers is of little value. Suitable types of heat exchangers 1510a-c include pin fins, straight fins, torch fins, and the like, which can be formed of any suitable material, such as aluminum or copper. In certain embodiments, the heat exchangers 1510a-c are formed of extruded aluminum.

[0137] In general, heat exchangers 1510a-c can be added to one or both sides of the semiconductor core assembly 1270. In certain embodiments, each of the heat exchangers 1510a-c is placed directly on or under the core structure 402 without an intervening insulating layer 618 (as shown for heat exchanger 1510a). To achieve this configuration, laser ablation can be performed for the desired area of the insulating layer 618 of the completed semiconductor core assembly 1270 to form a pocket, and then the heat exchanger 1510a can be mounted on the core structure 402. For example, the area of the insulating layer 618 having lateral dimensions corresponding to the lateral dimensions of the heat exchanger 1510a can be removed by a CO2, UV, or IR laser configured to ablate only the dielectric material of the insulating layer 618 and leave the core structure 402 intact. The heat exchanger 1510a can then be placed within the opening and mounted on the core structure 402 (which can include an oxide layer or a metal clad layer) via any suitable mounting method. In certain embodiments, an interface layer 1520 is formed between the heat exchanger 1510a and the core structure 402. For example, the interface layer 1520 can be formed of a thermal interface material (TIM), such as a thermal adhesive or a potting compound. In certain embodiments, the interface layer 1520 is a thin layer of a flowable dielectric material substantially similar to the insulating layer 618.

[0138] In certain embodiments, heat exchangers 1510a-c are placed directly on the insulating layer 618 of the semiconductor core assembly 1270 (as shown in heat exchanger 1510b). In such an example, laser ablation of the insulating layer 618 is not required. In order to optimize the heat transfer between the core substrate 402 and the heat exchanger 1510b, the semiconductor core assembly 1270 may include one or more thermal connections 1544 for thermally coupling the core structure 402 to the heat exchanger 1510b. Unlike the interconnect 1044 and the redistribution connection 1244, the thermal connection 1544 does not have any electrical function and only provides a path for conducting heat to the heat exchanger 1510b. In certain embodiments, the thermal connection 1544 is formed in a through hole substantially similar to the above-mentioned through-assembly through hole 613 and the redistribution through hole 1253. Generally speaking, the thermal connection 1544 is formed by a metal material (such as copper, aluminum, gold, nickel, silver, palladium, tin, etc.).

[0139] In certain embodiments, the heat exchangers 1510a-c are placed adjacent to active devices and components stacked with the semiconductor core assembly 1270. In general, the heat exchangers 1510a-c can be arranged in any configuration relative to the active devices or components attached to the semiconductor core assembly 1270. FIG. 15A to FIG. 15B , heat exchanger 1510c is positioned above active devices 1550 and 1560, and heat exchanger 1510b is positioned to the sides of active devices 1550, 1560 (e.g., in a transverse arrangement). The placement of heat exchangers above and to the sides of active devices 1550, 1560 increases heat conduction away from the active devices. In some embodiments, additional heat exchangers may be positioned on a side of semiconductor core assembly 1270 opposite any active devices or components (such as depicted with heat exchanger 1510a). In some embodiments, thermal connections 1544 may also be formed between core structure 402 and active devices 1550, 1560 to thermally connect active devices 1550, 1560 to core structure 402 and facilitate heat conduction from the active devices to the core.

[0140] like FIG. 15B As shown, the heat exchangers 1510a-c can be further coupled to one or more fans 1570 that assist in heat dissipation by providing additional fluid flow for convection. Although depicted as being directly mounted to the heat exchangers 1510a-c, the fans 1570 can be attached and oriented in any suitable position along the semiconductor core assembly 1270 for optimized fluid flow and thermal regulation. In examples where the semiconductor core assembly 1270 is stacked with other packaging structures (such as PCBs 1362a, 1362b), a cavity 1580 can be formed in the additional structure just above or below the heat exchangers 1510a-c to enable placement of one or more fans 1570 and / or to facilitate heat dissipation therefrom.

[0141] Alternatively or in addition to the heat exchangers described above, the semiconductor core assembly 1270 can also have one or more heat pipes or heat spreaders 1590 integrated thereon in various locations to improve heat dissipation and thermal modulation. FIG. 15C and FIG. 15D An exemplary heat spreader 1590 is illustrated, as well as an exemplary arrangement of heat spreaders 1590 on the semiconductor core assembly 1270. Similar to the heat exchangers described above, the heat spreader 1590 transfers heat conducted by the silicon core structure 402. However, the heat spreader 1590 is implemented using a phase change of a liquid contained within its plenum 1593. For example, as shown, the heat spreader 1590 includes a hot interface or evaporator 1591 at which the contained liquid changes to vapor 1594 by absorbing heat therefrom. In certain embodiments, the liquid is in contact with the evaporator 1591 via a wick 1592 disposed within the plenum 1593. After vaporization, the vapor 1594 travels within the heat spreader 1590 to a cold surface or condenser 1596 at which the vapor 1584 condenses to liquid condensate 1595 and releases latent heat, thereby spreading the heat. The liquid condensate 1595 then returns to the evaporator 1591 by capillary action (as shown by reference numeral 1597) through the wick 1592, and this cycle can be repeated for further heat transfer. This principle enables efficient lateral transfer of heat away from the core structure 402 of the semiconductor core assembly 1270 and, for example, toward other heat dissipation devices. FIG. 15C

[0142] Similar to the heat exchangers described above, the heat spreader 1590 can be placed directly on or under the core structure 402 without the need for an intervening insulating layer 618. As shown in FIG. 15D In certain embodiments, the heat spreader 1590 is placed directly on the insulating layer 618 with one or more thermal connections 1544 thermally coupling the heat spreader 1590 to the core structure 402. In general, the heat spreader 1590 is oriented such that the "hot side" or side containing the evaporator of the heat spreader 1590 is disposed closest to the core structure 402, while the "cold side" or side containing the condenser is disposed away from the core structure 402 (such as adjacent to the heat exchanger 1510c in FIG. 15D In some examples, the heat spreader 1590 can also be used in combination with one or more fans 1570 disposed in the vicinity of the heat spreader 1590 and / or other heat dissipation devices for additional heat dissipation by air convection.

[0143] FIG. 16 ​An exemplary arrangement 1600 of the semiconductor core assembly 1270 is illustrated, in which the semiconductor core assembly 1270 facilitates a variable density of interconnects 1044 and redistribution connections 1244 for bridging two active devices 1650 and 1660 having active layers 1652 and 1662, respectively. As shown, the semiconductor core assembly 1270 includes a bridge 1610 embedded within the pocket 1420 of the core structure 402, and through the bridge 1610, the active devices 1650 and 1660 are partially interconnected via their bridging redistribution layers 1620. The bridge 1610 is disposed under adjacent ends of the active layers 1652, 1662 and provides a high density and short distance interconnection of active device connections disposed at or near these ends, thereby enabling a local high density interconnection. However, active device connections disposed at distal ends of the active layers 1652, 1662 can be interconnected via lower density but higher range signal paths formed through the interconnects 1044 and redistribution connections 1244 of the semiconductor core assembly 1270, which can have reduced crosstalk compared to the high density and short distance interconnection.

[0144] Generally, the bridge 1610 includes a silicon-containing base 1630 having a thickness substantially equal to or less than the thickness of the core structure 402. For example, the thickness of the base 1630 is between about 80 pm and about 775 pm, such as between about 100 pm and about 400 pm, or between about 110 pm and about 300 pm. In certain embodiments, the base 1630 is a high density substrate, such as a high density fan-out substrate including silicon dioxide, and the redistribution layer 1620 is a back end of line (BEOL) redistribution layer. In certain embodiments, the base 1630 is a high density silicon interposer, and the redistribution layer 1620 is a dual damascene BEOL redistribution layer. The base 1630 supports the redistribution layer 1620 having a thickness up to about 1 pm. In certain embodiments, the base 1630 supports a connection pitch in a range of between about 0.3 pm and about 2 pm, such as between about 0.5 pm and about 1.5 pm. To take advantage of the relatively small pitch of the bridge 1610, the active devices 1650, 1660 can be soldered to the semiconductor core assembly 1270 via micro-bumps 1646 having a width or diameter of between about 20 pm and about 150 pm, or between about 30 pm and about 80 pm, thereby enabling a higher density interconnection therebetween. The micro-bumps 1646 are formed of a material substantially similar to that of the interconnects 1044, redistribution connections 1244, or solder bumps 1346, such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof. Similar to the redistribution connections 1244, the micro-bumps 1646 can be formed of a material having a higher melting point than the solder bumps 1346, such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof. FIG. 14A to FIG. 14CPassive devices, the bridge 1610 can be integrated into the semiconductor core assembly 1270 using any of the methods described above. For example, in accordance with methods 500 and 700, the bridge 1610, on which the redistribution layer 1620 has been formed, can be placed within the patterned pockets 1420 of the core structure 402 and then embedded after lamination against one or more insulating films (e.g., insulating films 616a, 616b). Further, the through-assembly via 613 can be drilled through the insulating layer 618 directly above the contacts of the redistribution layer 1620 and then metallized to form the interconnects 1044 and 1244, thereby enabling subsequent connection of the bridge 1610 to the active devices 1650 and 1660.

[0145] In the embodiments shown above, the utilization of the semiconductor core assembly 1270 provides a number of advantages over conventional packages, PCBs, PCB spacers, and chip carrier structures. Such benefits include a thin form factor and a high chip or die to package volume ratio, which enables greater I / O scaling to meet the increasing bandwidth and power efficiency demands of artificial intelligence (AI) and high performance computing (HPC). The utilization of a structured silicon frame provides optimal material stiffness and thermal conductivity for improved electrical performance, thermal management, and reliability of 3-dimensional integrated circuit (3DIC) architectures. Further, the manufacturing methods of through-assembly vias and structures of vias described herein provide high performance and flexibility for 3D integration with relatively lower manufacturing costs compared to conventional TSV technology.

[0146] By utilizing the methods described above, high aspect ratio features can be formed on glass and / or silicon core structures, thereby enabling thinner and narrower circuit boards, chip carriers, integrated circuit packages, etc. to be economically formed. The semiconductor core assemblies manufactured using the methods described above not only provide the benefits of high I / O density and improved bandwidth and power, but also the benefit of higher reliability due to reduced weight / inertia-induced stress and the component architecture that allows for flexible solder ball placement. Further advantages of the methods described above include economic manufacturing with bi- side metallization capability and high production rates. Further, the utilization of silicon cores reduces or eliminates the mismatch of coefficient of thermal expansion (CTE) between the core assembly and any chips connected thereto, enabling smaller solder pitch and increased device density.

[0147] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure can be devised without departing from the basic scope thereof, and the scope of the present disclosure is determined by the following claims.

Claims

1. A semiconductor device assembly comprising: A core structure, comprising: a first side opposite the second side; as well as a conductive interconnect formed through the core structure, wherein the conductive interconnect has a first surface exposed at the first side, a second surface exposed at the second side, and a third surface disposed between the first surface and the second surface; an insulating layer disposed on the first side and the second side and between the third surface of the conductive interconnect and the core structure; as well as A heat exchanger is coupled to the core structure.

2. The semiconductor device assembly of claim 1 , further comprising: An oxide layer is formed between the core structure and the insulating layer.

3. The semiconductor device assembly of claim 2, wherein the oxide layer comprises thermal oxide.

4. The semiconductor device assembly of claim 1, wherein the heat exchanger is a heat sink comprising copper or aluminum. The semiconductor device assembly of claim 1 , wherein the heat exchanger is a heat pipe. 6 . The semiconductor device assembly of claim 1 , wherein the heat exchanger is disposed within a pocket formed in the insulating layer and is directly coupled to the core structure. 7 . The semiconductor device assembly of claim 1 , wherein the heat exchanger is disposed within a pocket formed in the insulating layer and coupled to the core structure via an interface layer.

8. The semiconductor device assembly of claim 7, wherein the interface layer is a thermal adhesive or a thermal potting compound.

9. The semiconductor device assembly of claim 1, wherein the heat exchanger is coupled to the core structure via one or more electrically conductive thermal connections formed in the insulating layer.

10. The semiconductor device assembly of claim 1, further comprising: A fan is attached to the semiconductor device assembly and is disposed adjacent to the heat exchanger.

11. A semiconductor device assembly comprising: A core structure, comprising: a first side opposite the second side; a through-hole comprising a through-hole surface defining an opening extending through the core structure from the first side to the second side; and a pocket formed in the core structure; a first conductive interconnect formed in the through-hole and having surfaces exposed at the first side and the second side; a capacitor disposed in the pocket and coupled to a second conductive interconnect exposed at the first side or the second side; as well as An insulating layer is disposed on the first and second sides and within the through-hole and the pocket, the insulating layer embedding the capacitor in the pocket and forming an intermediate layer between the first conductive interconnect and the core structure. 12 . The semiconductor device assembly of claim 11 , further comprising an oxide layer formed between the core structure and the insulating layer.

13. The semiconductor device assembly of claim 12, wherein the oxide layer comprises thermal oxide.

14. The semiconductor device assembly of claim 11, wherein the oxide layer comprises silicon or ceramic.

15. The semiconductor device assembly of claim 11, wherein a thickness of the capacitor is substantially equal to a thickness of the core structure.

16. The semiconductor device assembly of claim 11, wherein the capacitor is a decoupling capacitor.

17. The semiconductor device assembly of claim 11, wherein the capacitor is a trench capacitor.

18. The semiconductor device assembly of claim 11, wherein the insulating layer comprises an epoxy material.

19. The semiconductor device assembly of claim 18, wherein the epoxy material comprises silicon dioxide particles having a size between about 80 nm and about 1 μm.

20. A semiconductor device assembly comprising: A core structure, comprising: a first side opposite the second side; a through hole comprising a through hole surface defining an opening extending through the core structure from the first side to the second side; a pocket formed in the core structure and extending through the core structure from the first side to the second side; as well as a passivation layer formed on all surfaces of the core structure; a first conductive interconnect formed in the through-hole and having surfaces exposed at the first side and the second side; a capacitor disposed in the pocket and coupled to a second conductive interconnect exposed at the first side or the second side; as well as an insulating layer disposed on the first and second sides and within the through-hole and the pocket, the insulating layer embedding the capacitor within the pocket and forming an intermediate layer between the first conductive interconnect and the core structure, the insulating layer comprising an epoxy resin having silicon dioxide particles disposed therein.

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